A novel three-stage operational amplifier indirect frequency compensation circuit

Abstract

The application discloses a novel three-stage operational amplifier indirect frequency compensation circuit and belongs to the electronic circuit field. A , a second resistor R B , a first capacitor C C1 , a second capacitor C C2 , NMOS tubes MN1-MN8 and PMOS tubes MP1-PMOS tubes MP6; the NMOS tubes MN1-MN5 and the PMOS tubes MP1-PMOS tubes MP2 are a first gain stage of an operational amplifier; the NMOS tubes MN6-MN7 and the PMOS tubes MP3-PMOS tubes MP5 are a second gain stage of the operational amplifier; the NMOS tube MN8 and the PMOS tube MP6 are a third gain stage; the second resistor R B and the first capacitor C C1 , the first resistor R A and the second capacitor C C2 are an indirect frequency compensation network. The application can greatly improve the loop phase margin and the circuit transient stability under the condition of using a smaller compensation capacitor by generating a zero point located in the left half plane to offset a sub-pole in the operational amplifier loop.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a novel three-stage operational amplifier indirect frequency compensation circuit. Background Technology

[0002] Operational amplifiers are a fundamental unit in analog and mixed-signal systems, widely used in circuit designs such as high-speed ADCs / DACs, analog data sampling filters, and voltage reference sources. With the advancement of integrated circuit design technology, CMOS process feature sizes are continuously decreasing. While smaller feature sizes can improve circuit operating speed, they also lead to a decrease in the intrinsic gain of MOSFETs, significantly increasing the difficulty of designing high-performance analog circuits.

[0003] In modern circuit design, the power supply voltage drops at a much faster rate than the threshold voltage of a MOSFET, making leakage current difficult to control. Therefore, traditional gain enhancement schemes based on cascode and common-source architectures are no longer suitable for small-size circuit designs. In small-size processes, multi-stage operational amplifiers (op-amps) are required to meet application gain requirements. Considering loop stability and circuit feasibility, op-amp designs are typically based on a three-stage structure and direct Miller compensation.

[0004] The small-signal model of a traditional op-amp with direct Miller compensation is shown in the appendix. Figure 1 As shown, the compensation capacitor C C This will generate a zero point z1 in the right half plane as shown in equation (1). z1 will reduce the phase margin of the op-amp loop and reduce the stability of the op-amp.

[0005] Summary of the Invention

[0006] The purpose of this invention is to provide a novel three-stage operational amplifier indirect frequency compensation circuit to solve the problems of reduced circuit phase margin and decreased stability caused by traditional three-stage operational amplifier direct Miller compensation.

[0007] To solve the above-mentioned technical problems, the present invention provides a novel three-stage operational amplifier indirect frequency compensation circuit, including a first resistor R. A Second resistor R B First capacitor C C1 Second capacitor C C2 NMOS transistors MN1 to MN8 and PMOS transistors MP1 to MP6;

[0008] NMOS transistors MN1-MN5 and PMOS transistors MP1-MP2 form the first gain stage of the operational amplifier; NMOS transistors MN6-MN7 and PMOS transistors MP3-MP5 form the second gain stage; NMOS transistor MN8 and PMOS transistor MP6 form the third gain stage; and the second resistor R...B and the first capacitor C C1 First resistor R A Second capacitor C C2 It is an indirect frequency compensation network.

[0009] In one embodiment, the first resistor R A The upper end is connected to node A, and the lower end is connected to the second capacitor C. C2 The upper end; the second resistor R B The upper end is connected to node B, and the lower end is connected to the first capacitor C. C1 The upper end; the first capacitor C C1 The upper end is connected to the second resistor R B The lower end is connected to both the drain of PMOS transistor MP5 and the drain of NMOS transistor MN7; the second capacitor C C2 The upper end is connected to the first resistor R A The lower end is connected to both the drain of PMOS transistor MP6 and the drain of NMOS transistor MN8.

[0010] In one embodiment, the drain of the NMOS transistor MN1 is connected to node B, and the gate is connected to the negative input signal V of the operational amplifier. IN_N The source terminal is connected to the drain terminal of NMOS transistor MN5; the drain terminal of NMOS transistor MN2 is connected to node A, and the gate terminal is connected to the positive input signal V of the operational amplifier. IN_P The source terminal is connected to the drain terminal of NMOS transistor MN5; the drain terminal of NMOS transistor MN3 is connected to the gate terminal of PMOS transistor MP5, and the gate terminal is connected to the negative input signal V of the operational amplifier. IN_N The source terminal is connected to node B; the drain terminal of NMOS transistor MN4 is connected to the gate terminal of PMOS transistor MP4, and the gate terminal is connected to the positive input signal V of the operational amplifier. IN_P The source terminal is connected to node A; the drain terminal of NMOS transistor MN5 is connected to the source terminal of both NMOS transistor MN1 and NMOS transistor MN2, and the gate terminal of NMOS transistor MN5 is connected to the NMOS transistor bias voltage signal V. bias_N The source terminal of NMOS transistor MN6 is connected to GND; the drain terminal of NMOS transistor MN6 is connected to the drain terminal of PMOS transistor MP4, and the gate terminal is connected to the gate terminal of NMOS transistor MN7, with the source terminal connected to GND; the drain terminal of NMOS transistor MN7 is connected to the drain terminal of PMOS transistor MP5, and the gate terminal is connected to the drain terminal of NMOS transistor MN6, with the source terminal connected to GND; the drain terminal of NMOS transistor MN8 is connected to the op-amp output V. OUT The gate is connected to the drain of NMOS transistor MN7, and the source is connected to GND.

[0011] In one embodiment, the drain terminal of the PMOS transistor MP1 is connected to the drain terminal of the NMOS transistor MN3, the gate terminal is connected to its own drain terminal, and the source terminal is connected to the power supply V. DD The drain of PMOS transistor MP2 is connected to the drain of NMOS transistor MN4, the gate is connected to the gate of PMOS transistor MP1, and the source is connected to V.DD The drain of PMOS transistor MP3 is connected to the source of both PMOS transistors MP4 and MP5, and the gate is connected to the PMOS transistor bias voltage signal V. bias_P Source end connected to V DD The drain of PMOS transistor MP4 is connected to the drain of NMOS transistor MN6, its gate is connected to the drain of PMOS transistor MP2, and its source is connected to the drain of PMOS transistor MP3; the drain of PMOS transistor MP5 is connected to the drain of NMOS transistor MN7, its gate is connected to the drain of PMOS transistor MP1, and its source is connected to the drain of PMOS transistor MP3; the drain of PMOS transistor MP6 is connected to V... OUT The gate terminal is connected to the drain terminal of PMOS transistor MP2, and the source terminal is connected to V. DD .

[0012] In the novel three-stage operational amplifier indirect frequency compensation circuit provided by this invention, by generating a zero point located in the left half-plane to cancel the secondary pole in the operational amplifier loop, the loop phase margin and circuit transient stability can be significantly improved with a smaller compensation capacitor. Attached Figure Description

[0013] Figure 1 This is a small-signal model diagram of a traditional direct Miller compensation circuit.

[0014] Figure 2 This invention provides a structural diagram of a novel three-stage operational amplifier indirect frequency compensation circuit.

[0015] Figure 3 This invention provides a small-signal model diagram of a novel three-stage operational amplifier indirect frequency compensation circuit. Detailed Implementation

[0016] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a novel three-stage operational amplifier indirect frequency compensation circuit proposed in this invention. The advantages and features of this invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0017] This invention provides a novel three-stage operational amplifier indirect frequency compensation circuit, the specific structure of which is as follows: Figure 2 As shown, it includes a first resistor R. A Second resistor R B First capacitor C C1 Second capacitor C C2The operational amplifier consists of NMOS transistors MN1-MN8 and PMOS transistors MP1-MP6. NMOS transistors MN1-MN5 and PMOS transistors MP1-MP2 form the first gain stage; NMOS transistors MN6-MN7 and PMOS transistors MP3-MP5 form the second gain stage; NMOS transistor MN8 and PMOS transistor MP6 form the third gain stage. The second resistor R... B and the first capacitor C C1 First resistor R A Second capacitor C C2 It is an indirect frequency compensation network.

[0018] Please continue reading. Figure 2 The first resistor R A The upper end is connected to node A, and the lower end is connected to the second capacitor C. C2 The upper end; the second resistor R B The upper end is connected to node B, and the lower end is connected to the first capacitor C. C1 The upper end; the first capacitor C C1 The upper end is connected to the second resistor R B The lower end is connected to both the drain of PMOS transistor MP5 and the drain of NMOS transistor MN7; the second capacitor C C2 The upper end is connected to the first resistor R A The lower end is connected to both the drain of PMOS transistor MP6 and the drain of NMOS transistor MN8.

[0019] The drain of NMOS transistor MN1 is connected to node B, and its gate is connected to the negative input signal V of the operational amplifier. IN_N The source terminal is connected to the drain terminal of NMOS transistor MN5; the drain terminal of NMOS transistor MN2 is connected to node A, and the gate terminal is connected to the positive input signal V of the operational amplifier. IN_P The source terminal is connected to the drain terminal of NMOS transistor MN5; the drain terminal of NMOS transistor MN3 is connected to the gate terminal of PMOS transistor MP5, and the gate terminal is connected to the negative input signal V of the operational amplifier. IN_N The source terminal is connected to node B; the drain terminal of NMOS transistor MN4 is connected to the gate terminal of PMOS transistor MP4, and the gate terminal is connected to the positive input signal V of the operational amplifier. IN_P The source terminal is connected to node A; the drain terminal of NMOS transistor MN5 is connected to the source terminal of both NMOS transistor MN1 and NMOS transistor MN2, and the gate terminal of NMOS transistor MN5 is connected to the NMOS transistor bias voltage signal V. bias_N The source terminal of NMOS transistor MN6 is connected to GND; the drain terminal of NMOS transistor MN6 is connected to the drain terminal of PMOS transistor MP4, and the gate terminal is connected to the gate terminal of NMOS transistor MN7, with the source terminal connected to GND; the drain terminal of NMOS transistor MN7 is connected to the drain terminal of PMOS transistor MP5, and the gate terminal is connected to the drain terminal of NMOS transistor MN6, with the source terminal connected to GND; the drain terminal of NMOS transistor MN8 is connected to the op-amp output V. OUTThe gate is connected to the drain of NMOS transistor MN7, and the source is connected to GND.

[0020] The drain of PMOS transistor MP1 is connected to the drain of NMOS transistor MN3, the gate is connected to its own drain, and the source is connected to the power supply V. DD The drain of PMOS transistor MP2 is connected to the drain of NMOS transistor MN4, the gate is connected to the gate of PMOS transistor MP1, and the source is connected to V. DD The drain of PMOS transistor MP3 is connected to the source of both PMOS transistors MP4 and MP5, and the gate is connected to the PMOS transistor bias voltage signal V. bias_P Source end connected to V DD The drain of PMOS transistor MP4 is connected to the drain of NMOS transistor MN6, its gate is connected to the drain of PMOS transistor MP2, and its source is connected to the drain of PMOS transistor MP3; the drain of PMOS transistor MP5 is connected to the drain of NMOS transistor MN7, its gate is connected to the drain of PMOS transistor MP1, and its source is connected to the drain of PMOS transistor MP3; the drain of PMOS transistor MP6 is connected to V... OUT The gate terminal is connected to the drain terminal of PMOS transistor MP2, and the source terminal is connected to V. DD .

[0021] The working principle of this invention is as follows:

[0022] (1) Compensation network analysis:

[0023] In this invention, indirect frequency compensation is implemented based on low-impedance nodes in the circuit, specifically as follows: Figure 2 By splitting the MOS transistors at the positive and negative input terminals of the operational amplifier into NMOS transistors MN1 and MN3 and NMOS transistors MN2 and MN4 connected in series, a low-impedance node required for compensation is formed at the source terminals of the common-source and common-gate transistors MN3 and MN4. The first capacitor C... C1 To compensate for the capacitor, a second resistor R, which serves as the zero-adjustment resistor, is used. B The second capacitor C is connected to the low-impedance node B. C2 To compensate for the capacitor, the first resistor R, which serves as the zero-adjustment resistor, is connected. A When connected to the low-impedance node A, two zeros (z1, z2) in the left half-plane can be generated in the loop to offset the effect of the secondary poles (p1, p2) on the loop phase margin.

[0024] (2) Frequency response analysis

[0025] like Figure 3 In the small-signal model diagram of the novel three-stage operational amplifier indirect frequency compensation circuit shown, g m1 ~g m3R1 to R3 are the equivalent transconductances of the first to third gain stages, and R1 to R3 are the equivalent output impedances of the first to third gain stages. The loop transfer function is shown in equation (2), where a0, a1, a2, a3, a4, a5, b0, b1, b2, and b3 are process-independent constants.

[0026]

[0027] The zeros z1 and z2 generated by the indirect frequency compensation network in the left half-plane are shown in equation (3):

[0028]

[0029] The parasitic zero z3 located at high frequencies is shown in equation (4):

[0030]

[0031] The principal pole p1 is shown in equation (5):

[0032]

[0033] The secondary poles p2 and p3 are shown in equations (6) and (7):

[0034]

[0035]

[0036] Properly configure the resistors and capacitors (R) in the circuit compensation network. A R B C C1 C C2 When equations (9) and (11) are true, the zeros and secondary poles in the loop can cancel each other out, and the phase margin and stability of the circuit can be greatly improved.

[0037]

[0038]

[0039]

[0040]

[0041] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A novel three-stage operational amplifier indirect frequency compensation circuit, characterized in that, Including the first resistor R A Second resistor R B First capacitor C C1 Second capacitor C C2 NMOS transistors MN1 to MN8 and PMOS transistors MP1 to MP6; NMOS transistors MN1~MN5 and PMOS transistors MP1~MP2 form the first gain stage of the operational amplifier; NMOS transistors MN6~MN7 and PMOS transistors MP3~MP5 form the second gain stage; NMOS transistor MN8 and PMOS transistor MP6 form the third gain stage; and the second resistor R... B and the first capacitor C C1 First resistor R A Second capacitor C C2 For indirect frequency compensation networks; The first resistor R A The upper end is connected to node A, and the lower end is connected to the second capacitor C. C2 The upper end; the second resistor R B The upper end is connected to node B, and the lower end is connected to the first capacitor C. C1 The upper end; the first capacitor C C1 The upper end is connected to the second resistor R B The lower end is connected to both the drain of PMOS transistor MP5 and the drain of NMOS transistor MN7; the second capacitor C C2 The upper end is connected to the first resistor R A The lower end is connected to both the drain of PMOS transistor MP6 and the drain of NMOS transistor MN8. The drain of the NMOS transistor MN1 is connected to node B, and its gate is connected to the negative input signal V of the operational amplifier. IN_N The source terminal is connected to the drain terminal of NMOS transistor MN5; the drain terminal of NMOS transistor MN2 is connected to node A, and the gate terminal is connected to the positive input signal V of the operational amplifier. IN_P The source terminal is connected to the drain terminal of NMOS transistor MN5; the drain terminal of NMOS transistor MN3 is connected to the gate terminal of PMOS transistor MP5, and the gate terminal is connected to the negative input signal V of the operational amplifier. IN_N The source terminal is connected to node B; the drain terminal of NMOS transistor MN4 is connected to the gate terminal of PMOS transistor MP4, and the gate terminal is connected to the positive input signal V of the operational amplifier. IN_P The source terminal is connected to node A; the drain terminal of NMOS transistor MN5 is connected to the source terminal of both NMOS transistor MN1 and NMOS transistor MN2, and the gate terminal of NMOS transistor MN5 is connected to the NMOS transistor bias voltage signal V. bias_N The source terminal of NMOS transistor MN6 is connected to GND; the drain terminal of NMOS transistor MN6 is connected to the drain terminal of PMOS transistor MP4, and the gate terminal is connected to the gate terminal of NMOS transistor MN7, with the source terminal connected to GND; the drain terminal of NMOS transistor MN7 is connected to the drain terminal of PMOS transistor MP5, and the gate terminal is connected to the drain terminal of NMOS transistor MN6, with the source terminal connected to GND; the drain terminal of NMOS transistor MN8 is connected to the op-amp output V. OUT The gate terminal is connected to the drain terminal of NMOS transistor MN7, and the source terminal is connected to GND; The drain of the PMOS transistor MP1 is connected to the drain of the NMOS transistor MN3, the gate is connected to its own drain, and the source is connected to the power supply V. DD The drain of PMOS transistor MP2 is connected to the drain of NMOS transistor MN4, the gate is connected to the gate of PMOS transistor MP1, and the source is connected to V. DD The drain of PMOS transistor MP3 is connected to the source of both PMOS transistors MP4 and MP5, and the gate is connected to the PMOS transistor bias voltage signal V. bias_P Source end connected to V DD The drain of PMOS transistor MP4 is connected to the drain of NMOS transistor MN6, its gate is connected to the drain of PMOS transistor MP2, and its source is connected to the drain of PMOS transistor MP3; the drain of PMOS transistor MP5 is connected to the drain of NMOS transistor MN7, its gate is connected to the drain of PMOS transistor MP1, and its source is connected to the drain of PMOS transistor MP3; the drain of PMOS transistor MP6 is connected to V... OUT The gate terminal is connected to the drain terminal of PMOS transistor MP2, and the source terminal is connected to V. DD .

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