High-dropout linear regulator

Abstract

The invention discloses a high dropout linear regulator. According to the high-voltage-difference linear voltage regulator, the second end of a power tube is connected with the first end of a zero point compensation module, and a zero point generated by the zero point compensation module compensates a pole of the output end of the high-voltage-difference linear voltage regulator. The offset voltage calibration module samples the current of the power tube and generates a calibration current according to the sampled current so as to calibrate the feedback voltage. The output voltage feedback module generates feedback voltage according to the output voltage of the power tube to the inverted input end of the error amplification module, reference voltage is connected to the in-phase input end of the error amplification module, and the error amplification module adjusts the control end voltage of the power tube according to the reference voltage and the feedback voltage so as to adjust the output voltage of the power tube. According to the technical scheme, the application range of the load capacitor is widened, the application flexibility of the high-voltage-difference linear voltage regulator is improved, and the precision of the output voltage of the high-voltage-difference linear voltage regulator is improved.

Description

A high differential linear regulator Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a high-voltage differential linear regulator. Background Technology

[0002] With the rapid development of automotive electronics and industrial control, electronic devices are placing higher demands on the stability, reliability, and adaptability of power supply systems. Linear regulators are widely used in the power supply links of various electronic systems to convert unstable input voltages into stable output voltages, providing reliable power to sensitive electronic components such as chips, sensors, and processors.

[0003] Existing linear regulators operating under high-voltage input conditions work by comparing the difference between the reference voltage and the output feedback voltage using an internal error amplifier. This difference drives the power transistor to dynamically adjust its voltage drop, thereby maintaining a stable output voltage. To improve output voltage stability and transient response performance, a load capacitor is typically connected in parallel at the output of the linear regulator. The energy storage and filtering characteristics of the load capacitor suppress output voltage ripple and fluctuations, mitigating the impact of sudden load current changes on the output voltage. Currently, some mainstream high-voltage linear regulators require a load capacitor of specific specifications at the output to ensure stable operation.

[0004] However, the load capacitor configuration of the aforementioned high differential linear regulator is limited in flexibility and the output voltage accuracy is low. Summary of the Invention

[0005] This invention provides a high differential voltage linear regulator to broaden the applicable range of the load capacitor of the high differential voltage linear regulator, improve the design flexibility of the high differential voltage linear regulator, and enhance the output voltage accuracy of the high differential voltage linear regulator.

[0006] According to one aspect of the present invention, a high differential voltage linear regulator is provided. The high differential voltage linear regulator of this embodiment includes an error amplification module, a power transistor, a zero-point compensation module, an output voltage feedback module, and an offset voltage calibration module. The first terminal of the power transistor is connected to the input voltage, the control terminal of the power transistor is connected to the output terminal of the error amplification module, and the second terminal of the power transistor is connected to the first terminal of the zero-point compensation module. The second terminal of the zero-point compensation module serves as the output terminal of the high differential voltage linear regulator, and the zero point generated by the zero-point compensation module is used to compensate for the poles of the output terminal of the load high differential voltage linear regulator. The input terminal of the output voltage feedback module is connected to the second terminal of the power transistor and is used to generate an offset voltage feedback module based on the output voltage of the power transistor. The output voltage feedback module's output terminal is connected to the inverting input terminal of the error amplifier module, and the fixed potential terminal of the output voltage feedback module is grounded. The non-inverting input terminal of the error amplifier module is connected to the reference voltage, and the error amplifier module is used to adjust the control terminal voltage of the power transistor according to the reference voltage and the feedback voltage. The first input terminal of the offset voltage calibration module is connected to the control terminal of the power transistor, the second input terminal of the offset voltage calibration module is connected to the second terminal of the power transistor, and the output terminal of the offset voltage calibration module is connected to the inverting input terminal of the error amplifier module. The offset voltage calibration module is used to sample the current of the power transistor and generate a calibration current based on the sampled current. The calibration current is used to calibrate the feedback voltage.

[0007] Optionally, the zero-point compensation module includes a compensation resistor; the first end of the compensation resistor is connected to the second end of the power transistor, and the second end of the compensation resistor serves as the output terminal of the high-voltage differential linear regulator.

[0008] Optionally, the offset voltage calibration module includes a current sampling unit, a current adjustment unit, and a calibration current generation unit. The first input terminal of the current sampling unit is connected to the control terminal of the power transistor, and the second input terminal is connected to the second terminal of the power transistor. The current sampling unit samples the current of the power transistor and generates a sampling current. The input terminal of the current adjustment unit is connected to the output terminal of the current sampling unit, and the power supply terminal of the current adjustment unit is connected to the power supply voltage. The current adjustment unit generates an adjustment current based on the sampling current; wherein the adjustment current is linearly related to the sampling current. The input terminal of the calibration current generation unit is connected to the output terminal of the current adjustment unit, and the fixed potential terminal of the calibration current generation unit is grounded. The calibration current generation unit generates a calibration current based on the adjustment current; wherein the calibration current is proportional to the adjustment current.

[0009] Optionally, the current sampling unit includes a first transistor; the control terminal of the first transistor is connected to the control terminal of the power transistor, the second terminal of the first transistor is connected to the second terminal of the power transistor, and the first terminal of the first transistor is connected to the input terminal of the current adjustment unit.

[0010] Optionally, the current regulation unit includes a second transistor and a third transistor; the first terminal of the second transistor is connected to the output terminal of the current sampling unit, the second terminal of the second transistor is connected to the power supply voltage, and the first terminal of the second transistor is connected to the control terminal of the second transistor; the second terminal of the third transistor is connected to the second terminal of the second transistor, the control terminal of the third transistor is connected to the control terminal of the second transistor, and the first terminal of the third transistor is connected to the input terminal of the calibration current generation unit.

[0011] Optionally, the current regulation unit further includes a first modulation resistor and a second modulation resistor; the first end of the first modulation resistor is connected to the second end of the second transistor, the second end of the first modulation resistor is connected to the control terminal of the second transistor, and the first end of the second transistor is connected to the control terminal of the second transistor through the second modulation resistor; the first end of the second modulation resistor is connected to the second end of the first modulation resistor, and the second end of the second modulation resistor is connected to the control terminal of the third transistor.

[0012] Optionally, the calibration current generation unit includes a fourth transistor and a fifth transistor; the first terminal of the fourth transistor is connected to the output terminal of the current regulation unit, the first terminal of the fourth transistor is connected to the control terminal of the fourth transistor, and the second terminal of the fourth transistor is grounded; the control terminal of the fifth transistor is connected to the control terminal of the fourth transistor, the second terminal of the fifth transistor is connected to the second terminal of the fourth transistor, and the first terminal of the fifth transistor is the output terminal of the calibration current generation unit.

[0013] Optionally, the high differential linear regulator of this invention further includes a pre-regulator module; the input terminal of the pre-regulator module is connected to the input voltage, and the output terminal of the pre-regulator module is connected to the power supply terminal of the error amplifier module. The pre-regulator module is used to regulate the input voltage and output a power supply voltage, which is used to power the error amplifier module.

[0014] Optionally, the pre-regulation module includes a current-limiting resistor, a current source unit, a voltage generation unit, a super source follower, and a Zener transistor. The first terminal of the current-limiting resistor and the first terminal of the Zener transistor are both connected to the input voltage. The second terminal of the current-limiting resistor, the first power supply terminal of the current source unit, the first input terminal of the voltage generation unit, the first input terminal of the super source follower, and the control terminal of the Zener transistor are all connected to the first node. The second power supply terminal of the current source unit is grounded. The first output terminal of the current source unit is connected to the control terminal of the voltage generation unit, the second output terminal of the current source unit is connected to the first control terminal of the super source follower, and the output terminal of the voltage generation unit is connected to the second control terminal of the super source follower. The current source unit outputs a first current based on the voltage of the first node, the voltage generation unit outputs a first voltage based on the first current, the super source follower regulates the voltage of the first node based on the first voltage, and the second terminal of the Zener transistor is the output terminal of the pre-regulation module.

[0015] Optionally, the current source unit includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a first resistor; the second terminals of the sixth, seventh, and eighth transistors are all connected to the first node; the first terminal of the sixth transistor is connected to the control terminal of the sixth transistor, the control terminal of the sixth transistor is connected to the control terminal of the seventh transistor, and the control terminal of the eighth transistor is connected to the control terminal of the seventh transistor; the first terminal of the ninth transistor is connected to the first terminal of the sixth transistor, the control terminal of the ninth transistor is connected to the control terminal of the tenth transistor, and the second terminal of the ninth transistor is connected to the first terminal of the first resistor; the first terminal of the tenth transistor is connected to the first terminal of the seventh transistor, the first terminal of the tenth transistor is connected to the control terminal of the tenth transistor, and the second terminal of the tenth transistor is grounded; the first terminal of the eleventh transistor is connected to the first terminal of the eighth transistor, and the control terminal of the eleventh transistor is connected to the tenth transistor. The control terminal of the eleventh transistor is connected to the second terminal of the first resistor, and the second terminal of the first resistor is grounded. The voltage generation unit includes a twelfth transistor and a second resistor. The second terminal of the twelfth transistor is connected to the first node, the control terminal of the twelfth transistor is connected to the control terminal of the eighth transistor, the first terminal of the twelfth transistor is connected to the second resistor, and the second terminal of the second resistor is grounded. The super source follower includes a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor. The second terminal of the thirteenth transistor and the first terminal of the fourteenth transistor are connected to the first node, the control terminal of the thirteenth transistor is connected to the first terminal of the twelfth transistor, the control terminal of the fourteenth transistor is connected to the first terminal of the thirteenth transistor, the first terminal of the fifteenth transistor is connected to the first terminal of the thirteenth transistor, the control terminal of the fifteenth transistor is connected to the control terminal of the eleventh transistor, and the second terminals of the fourteenth transistor and the fifteenth transistor are grounded.

[0016] The technical solution of this invention, by setting a zero-point compensation module, adaptively generates a zero that matches the output pole of the high-dropout linear regulator when the capacitance range of the load capacitor is increased. This does not affect the zero-point and pole matching of the output port of the high-dropout linear regulator, improves the phase margin, and enhances the design flexibility of the high-dropout linear regulator. However, the zero-point compensation module has an offset voltage at its terminals, which reduces the output accuracy of the high-dropout linear regulator. By adding an offset voltage calibration module, the current of the power transistor is sampled, and a calibration current proportional to the sampled current is generated. After the output voltage feedback module samples the output voltage of the power transistor to form a feedback voltage, the calibration current calibrates the feedback voltage, and the calibrated feedback voltage is output to the error amplification module. The error amplification module controls the gate voltage of the power transistor according to the calibrated feedback voltage, so that the output voltage of the power transistor can compensate for the offset voltage. Therefore, while widening the capacitance range of the load capacitor, the accuracy of the output voltage of the high-dropout linear regulator can be guaranteed, thereby achieving output voltage stability of the power transistor. In summary, the technical solution of this invention broadens the applicable range of load capacitors, improves the application flexibility of high differential linear regulators, and improves the accuracy of the output voltage of high differential linear regulators.

[0017] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 is a schematic diagram of a high-voltage differential linear regulator provided in an embodiment of the present invention; Figure 2 is a schematic diagram of another high-voltage differential linear regulator provided in an embodiment of the present invention; Figure 3 is a circuit diagram of an offset voltage calibration module provided in an embodiment of the present invention; Figure 4 is a circuit diagram of another offset voltage calibration module provided in an embodiment of the present invention; Figure 5 is a schematic diagram of yet another high-voltage differential linear regulator provided in an embodiment of the present invention; Figure 6 is a circuit diagram of a pre-regulation module provided in an embodiment of the present invention; Figure 7 is a circuit diagram of an error amplification module provided in an embodiment of the present invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0021] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0022] Figure 1 is a schematic diagram of a high-dropout linear regulator provided in an embodiment of the present invention. This embodiment is applicable to fields requiring stable output voltage under conditions of large input-output voltage differences, such as automotive power supply systems, industrial control systems, and aerospace. This embodiment does not impose specific limitations. As shown in Figure 1, the high-dropout linear regulator provided in this embodiment includes an error amplification module 110, a power transistor 120, a zero-point compensation module 130, an output voltage feedback module 140, and an offset voltage calibration module 150. The first terminal of the power transistor 120 is connected to the input voltage VIN, and the control terminal of the power transistor 120 is connected to the output terminal of the error amplification module 110. The second terminal of the power transistor 120 is connected to the first terminal of the zero-point compensation module 130, which serves as the output terminal of the high-dropout linear regulator. The zeros generated by the zero-point compensation module 130 are used to compensate for the poles of the output terminal of the high-dropout linear regulator. The input terminal of the output voltage feedback module 140 is connected to the second terminal of the power transistor 120 and is used to generate a feedback voltage based on the output voltage VCC of the power transistor 120. The output terminal of the feedback module 140 is connected to the inverting input terminal of the error amplifier module 110, and the fixed potential terminal of the output voltage feedback module 140 is grounded. The non-inverting input terminal of the error amplifier module 110 is connected to the reference voltage VREF. The error amplifier module 110 is used to adjust the control terminal voltage of the power transistor 120 according to the reference voltage VREF and the feedback voltage. The first input terminal of the offset voltage calibration module 150 is connected to the control terminal of the power transistor 120, the second input terminal of the offset voltage calibration module 150 is connected to the second terminal of the power transistor 120, and the output terminal of the offset voltage calibration module 150 is connected to the inverting input terminal of the error amplifier module 110. The offset voltage calibration module 150 is used to sample the current of the power transistor 120 and generate a calibration current according to the sampled current. The calibration current is used to calibrate the feedback voltage.

[0023] In this embodiment, power transistor 120 is a device in a high-dropout linear regulator that converts an unstable input voltage VIN into a stable output voltage VCC. The input voltage VIN can be high voltage, for example, less than or equal to 100V. Power transistor 120 can also be a device in a high-dropout linear regulator that carries load current. Power transistor 120 can be an N-type MOSFET, with its first terminal being the drain of the N-type MOSFET, its second terminal being the source of the N-type MOSFET, and its control terminal being the gate of the N-type MOSFET. The drain of power transistor 120 can have high voltage withstand capability.

[0024] The zero-point compensation module 130 has impedance characteristics and can adjust the output impedance of the power transistor 120 and the zero point formed by the load capacitor. This can increase the capacitance range of the load capacitor without affecting the matching between the output pole and the zero point of the high-dropout linear regulator, thereby improving the stability of the output voltage VOUT of the high-dropout linear regulator.

[0025] The output voltage feedback module 140 can generate a feedback voltage based on the output voltage VCC of the power transistor 120. The feedback voltage has a linear relationship with the output voltage VCC, so the feedback voltage can characterize the output voltage VCC. The fixed point terminal of the output voltage feedback module 140 is grounded, and GND indicates grounding.

[0026] The offset voltage calibration module 150 can sample the current of the power transistor 120 and output a calibration current that is linearly or proportionally related to the current of the power transistor 120. The calibration current calibrates the feedback voltage of the output voltage feedback module 140, and the calibrated feedback voltage is input to the error amplifier module 110.

[0027] The error amplifier module 110 can adjust the voltage at the control terminal of the power transistor 120 to maintain a stable output voltage of the power transistor 120. The input terminals of the error amplifier module 110 can be connected to a reference voltage VREF and a feedback voltage. For example, the non-inverting input terminal of the error amplifier module 110 can be connected to the reference voltage VREF, and the inverting input terminal can be connected to the feedback voltage. When the feedback voltage is too high, the output voltage of the error amplifier module 110 decreases to reduce the conduction level of the power transistor 120, thereby reducing the output voltage of the power transistor 120. When the feedback voltage is too low, the output voltage of the error amplifier module 110 increases to increase the conduction level of the power transistor 120, thereby increasing the output voltage of the power transistor 120.

[0028] Specifically, when the feedback voltage is greater than the reference voltage VREF, the gate voltage of the power transistor 120 output by the error amplifier module 110 is relatively small. When the gate voltage is small, the conduction level of the power transistor 120 decreases, its on-resistance increases, its gate-source voltage drop increases, and its output voltage VCC decreases. When the feedback voltage is less than the reference voltage VREF, the gate voltage of the power transistor 120 output by the error amplifier module 110 is relatively large. When the gate voltage is large, the conduction level of the power transistor 120 increases, its on-resistance decreases, its gate-source voltage drop decreases, and its output voltage VCC increases. Simultaneously, the current in the power transistor 120 passing through the zero-point compensation module 130 generates a voltage drop, causing the output voltage VOUT of the high-dropout linear regulator to be less than the output voltage VCC of the power transistor 120. The offset voltage calibration module 150 can sample the current of the power transistor 120 and output a calibration current. The calibration current calibrates the feedback voltage output by the output voltage feedback module 140. The calibrated feedback voltage is output to the error amplification module 110. After adjustment by the error amplification module 110, the output voltage VCC of the power transistor 120 can compensate for the voltage offset generated by the zero-point compensation module 130, so that the output voltage VOUT of the high-voltage differential linear regulator reaches the voltage value of the high-voltage differential linear regulator under the target state.

[0029] According to the technical solution of this embodiment of the invention, by setting a zero-point compensation module, when the capacitance range of the load capacitor is increased, the zero-point compensation module can adaptively generate a zero that matches the output pole of the high-dropout linear regulator based on the capacitance value of the load capacitor. This does not affect the zero-point and pole matching of the output port of the high-dropout linear regulator, improves the phase margin, broadens the applicable range of the load capacitor, and enhances the design flexibility of the high-dropout linear regulator. At this time, there is an offset voltage across the zero-point compensation module, which will reduce the output accuracy of the high-dropout linear regulator. By adding an offset voltage calibration module, the current of the power transistor is sampled, and a calibration current proportional to the sampling current is generated. After the output voltage feedback module samples the output voltage of the power transistor to form a feedback voltage, the feedback voltage is calibrated by the calibration current, and the calibrated feedback voltage is output to the error amplification module. The error amplification module controls the gate voltage of the power transistor according to the calibrated feedback voltage, so that the output voltage of the power transistor can compensate for the offset voltage. Thus, the accuracy of the output voltage of the high-dropout linear regulator can be guaranteed while broadening the capacitance range of the load capacitor, thereby achieving output voltage stability of the power transistor. In summary, the technical solution of this invention broadens the applicable range of load capacitors, improves the application flexibility of high differential linear regulators, and improves the accuracy of the output voltage of high differential linear regulators.

[0030] Based on the above embodiments, Figure 2 is a schematic diagram of another high-voltage differential linear regulator provided by the present invention. As shown in Figure 2, optionally, the zero-point compensation module 130 includes a compensation resistor RM; the first end of the compensation resistor RM is connected to the second end of the power transistor 120, and the second end of the compensation resistor RM serves as the output terminal of the high-voltage differential linear regulator.

[0031] The compensation resistor RM has impedance characteristics. When connected between the output terminal of power transistor 120 and the output terminal of the high-dropout linear regulator, it can adjust the output impedance of power transistor 120 and the pole of the load capacitor. When the capacitance of the load capacitor changes, the output pole of the high-dropout linear regulator is the ratio of the equivalent small-signal transconductance of power transistor 120 to the capacitance of the load capacitor. The zero point compensated by the zero-point compensation module 130 is the reciprocal of the product of the compensation resistor RM and the capacitance of the load capacitor. The zero point formed by the zero-point compensation module 130 can change with the capacitance of the load capacitor. Therefore, when the capacitance of the load capacitor changes, the zero point compensated by the zero-point compensation module 130 can dynamically track the output pole of the high-dropout linear regulator.

[0032] A zero point can be generated by the compensation resistor RM, which matches the equivalent output impedance of the power transistor 120 and the pole of the load capacitor. This improves the phase margin and system stability of the high-dropout linear regulator loop under different load capacitors, thus effectively broadening the applicable range of the load capacitor of the high-dropout linear regulator and improving the flexibility of the high-dropout linear regulator in practical applications.

[0033] Figure 3 is a circuit structure diagram of an offset voltage calibration module provided in an embodiment of the present invention. As shown in Figure 3, in some embodiments, the offset voltage calibration module includes a current sampling unit 151, a current adjustment unit 152, and a calibration current generation unit 153. The first input terminal of the current sampling unit 151 is connected to the control terminal of the power transistor, and the second input terminal of the current sampling unit 151 is connected to the second terminal of the power transistor. The current sampling unit 151 is used to sample the current of the power transistor and generate a sampling current. The input terminal of the current adjustment unit 152 is connected to the output terminal of the current sampling unit 151, and the power supply terminal of the current adjustment unit 152 is connected to the power supply voltage. The current adjustment unit 152 is used to generate an adjustment current according to the sampling current. The adjustment current is linearly related to the sampling current. The input terminal of the calibration current generation unit 153 is connected to the output terminal of the current adjustment unit 152, and the fixed potential terminal of the calibration current generation unit 153 is grounded. The calibration current generation unit 153 is used to generate a calibration current according to the adjustment current. The calibration current is proportional to the adjustment current.

[0034] The current sampling unit 151 samples the current of the power transistor, and the output current of the current sampling unit 151 is proportional to the current of the power transistor. The current adjustment unit 152 outputs an adjustment current that is linearly related to the sampling current generated by the current sampling unit 151. The calibration current generation unit 153 generates a calibration current that is proportional to the adjustment current. Finally, the calibration current output by the calibration current generation unit 153 is proportional to the sampling current. By setting an appropriate ratio, the calibration current calibrates the feedback voltage generated by the voltage feedback module. The calibrated feedback voltage is output to the error amplification module, so that the output voltage of the power transistor can compensate for the offset voltage caused by the zero-point compensation module, thereby calibrating the accuracy of the output voltage of the high-dropout linear regulator.

[0035] Referring again to Figure 3, in some embodiments, the current sampling unit 151 includes a first transistor NC1; the control terminal of the first transistor NC1 is connected to the control terminal of the power transistor, the second terminal of the first transistor NC1 is connected to the second terminal of the power transistor, and the first terminal of the first transistor NC1 is connected to the input terminal of the current adjustment unit 152.

[0036] In this design, the first transistor NC1 can be an N-type MOS transistor. The first terminal of the first transistor NC1 is the drain of the N-type MOS transistor, the second terminal of the first transistor NC1 is the source of the N-type MOS transistor, and the control terminal of the first transistor NC1 is the gate of the N-type MOS transistor. The drain of the first transistor NC1 is the output terminal of the current sampling unit 151.

[0037] Specifically, the gate of the first transistor NC1 is connected to the gate of the power transistor and connected to the gate voltage VG of the power transistor. The source of the first transistor NC1 is connected to the source of the power transistor and connected to the output voltage VCC of the power transistor. The first transistor NC1 and the power transistor can be MOS transistors of the same type and process. The gate-source voltage and threshold voltage of the first transistor NC1 and the power transistor are the same. By selecting the first transistor NC1 which is proportional to the channel width-to-length ratio of the power transistor, a sampling current proportional to the current of the power transistor can be output.

[0038] Referring again to Figure 3, optionally, the current regulation unit 152 includes a second transistor PC1 and a third transistor PC2; the first terminal of the second transistor PC1 is connected to the output terminal of the current sampling unit 151, the second terminal of the second transistor PC1 is connected to the power supply voltage, and the first terminal of the second transistor PC1 is connected to the control terminal of the second transistor PC1; the second terminal of the third transistor PC2 is connected to the second terminal of the second transistor PC1, the control terminal of the third transistor PC2 is connected to the control terminal of the second transistor PC1, and the first terminal of the third transistor PC2 is connected to the input terminal of the calibration current generation unit 153.

[0039] In this configuration, the second transistor PC1 and the third transistor PC2 can be P-type MOSFETs. The first terminals of the second transistor PC1 and the third transistor PC2 are the drains of the P-type MOSFETs, and the second terminals of the second transistor PC1 and the third transistor PC2 are the sources of the P-type MOSFETs. The control terminals of the second transistor PC1 and the third transistor PC2 are the gates of the P-type MOSFETs. The drain of the second transistor PC1 is the input terminal of the current adjustment unit 152, and the drain of the third transistor PC2 is the output terminal of the current adjustment unit 152.

[0040] Specifically, the sources of the second transistor PC1 and the third transistor PC2 are connected to the power supply voltage. The drain of the second transistor PC1 is connected to the output terminal of the current sampling unit 151. The second transistor PC1 and the first transistor NC1 in the current sampling unit 151 are in the same current branch, and the current of the second transistor PC1 is the same as that of the first transistor NC1, i.e., the same as the sampling current. The second transistor PC1 and the third transistor PC2 form a first current mirror. The third transistor PC2 can proportionally replicate the current of the second transistor PC1. Therefore, the current adjustment unit 152 can generate an adjustment current that is linearly related to the sampling current. In addition, the PMOS current mirror formed by the current adjustment unit 152 realizes the replication of the power transistor's current from the power supply voltage domain to the analog power supply voltage domain. The voltage of the power supply is higher than that of the analog power supply, ensuring that the gate voltage of the power transistor matches the gate voltage of the first transistor NC1.

[0041] Referring again to Figure 3, optionally, the calibration current generation unit 153 includes a fourth transistor NC2 and a fifth transistor NC3; the first terminal of the fourth transistor NC2 is connected to the output terminal of the current adjustment unit 152, the first terminal of the fourth transistor NC2 is connected to the control terminal of the fourth transistor NC2, and the second terminal of the fourth transistor NC2 is grounded; the control terminal of the fifth transistor NC3 is connected to the control terminal of the fourth transistor NC2, the second terminal of the fifth transistor NC3 is connected to the second terminal of the fourth transistor NC2, and the first terminal of the fifth transistor NC3 is the output terminal of the calibration current generation unit 153.

[0042] In this configuration, the fourth transistor NC2 and the fifth transistor NC3 can be N-type MOSFETs. The first terminals of the fourth transistor NC2 and the fifth transistor NC3 are the drains of the N-type MOSFETs, and the second terminals of the fourth transistor NC2 and the fifth transistor NC3 are the sources of the N-type MOSFETs. The control terminals of the fourth transistor NC2 and the fifth transistor NC3 are the gates of the N-type MOSFETs. The drain of the fourth transistor NC2 is the input terminal of the current adjustment unit 152, and the drain of the fifth transistor NC3 is the output terminal of the calibration current generation unit 153.

[0043] Specifically, the sources of the fourth transistor NC2 and the fifth transistor NC3 are grounded. The drain of the fourth transistor NC2 is connected to the output of the current adjustment unit 152. The fourth transistor NC2 and the third transistor PC2 in the current adjustment unit 152 are on the same current branch, and the current of the fourth transistor NC2 and the third transistor PC2 is the same, that is, the same as the adjustment current. The fourth transistor NC2 and the fifth transistor NC3 form a second current mirror. The fifth transistor NC3 can proportionally replicate the current of the fourth transistor NC2 to generate a calibration current IS that is proportional to the adjustment current. Finally, the calibration current IS is proportional to the sampling current.

[0044] By selecting power transistors with appropriate channel width-to-length ratios, and transistors NC1, PC1, PC2, NC2, and NC3, the calibration current IS can be made proportional to the current of the power transistor. The offset voltage is the voltage drop caused by the current of the power transistor passing through the zero-point compensation module. Therefore, when the calibration current IS is in an appropriate proportion to the current of the power transistor, the output voltage of the power transistor can compensate for the offset voltage caused by the zero-point compensation module after the calibration current IS calibrates the feedback voltage.

[0045] Based on any of the above embodiments, Figure 4 is a circuit structure diagram of another offset voltage calibration module provided by the embodiment of the present invention. As shown in Figure 4, optionally, the current adjustment unit 152 further includes a first modulation resistor RC1 and a second modulation resistor RC2; the first end of the first modulation resistor RC1 is connected to the second end of the second transistor PC1, the second end of the first modulation resistor RC1 is connected to the control terminal of the second transistor PC1, and the first end of the second transistor PC1 is connected to the control terminal of the second transistor PC1 through the second modulation resistor RC2; the first end of the second modulation resistor RC2 is connected to the second end of the first modulation resistor RC1, and the second end of the second modulation resistor RC2 is connected to the control terminal of the third transistor PC2.

[0046] In this circuit, the drain-source voltage of the first transistor NC1 differs from that of the power transistor. The drain voltage of the power transistor is typically connected to a power supply voltage, which can be high. To save area, the power transistor usually uses the smallest channel size, resulting in a significant channel modulation effect between the power transistor and the first transistor NC1. This reduces the accuracy of current sampling of the power transistor through the first transistor NC1. By adding a first modulation resistor RC1 and a second modulation resistor RC2 as shown in Figure 4, the gate voltage of the third transistor PC2 is adjusted to be linearly proportional to the gate voltage of the second transistor PC1. The gate-source voltage of the third transistor PC2 is slightly higher than that of the second transistor PC1, making the relationship between the regulating current output by the third transistor PC2 and the sampling current more linear and improving the sampling accuracy of the sampling current.

[0047] By selecting power transistors with appropriate channel width-to-length ratios, first transistor NC1, second transistor PC1, third transistor PC2, fourth transistor NC2, and fifth transistor NC3, and by selecting first modulation resistor RC1 and second modulation resistor RC2 with appropriate resistance values, the calibration current IS can be made to have a certain proportional relationship with the current of the power transistor. This allows the calibration current IS to be calibrated to the feedback voltage, so that the output voltage of the power transistor can compensate for the offset voltage caused by the zero-point compensation module.

[0048] Based on any of the above embodiments, Figure 5 is a structural schematic diagram of another high differential linear regulator provided by the present invention. As shown in Figure 5, optionally, the high differential linear regulator of the present invention further includes a pre-regulator module 160; the input terminal of the pre-regulator module 160 is connected to the input voltage VIN, and the output terminal of the pre-regulator module 160 is connected to the power supply terminal of the error amplifier module 110. The pre-regulator module 160 is used to regulate the input voltage VIN and output a power supply voltage VREG, which is used to power the error amplifier module 110.

[0049] The pre-regulator module 160 regulates the input voltage VIN to generate a stable supply voltage VREG. The supply voltage VREG generated by the pre-regulator module 160 can provide operating power to other circuit modules within the high-dropout linear regulator. For example, the output terminal of the pre-regulator module 160 is connected to the power supply terminal of the error amplifier module 110, and the supply voltage VREG output by the pre-regulator module 160 provides the operating voltage for the error amplifier module 110.

[0050] Optionally, the output voltage feedback module 140 may include a first feedback resistor RF1 and a second feedback resistor RF2. The first terminal of the first feedback resistor RF1 is connected to the second terminal of the power transistor 120, and the second terminal of the first feedback resistor RF1 is connected to the first terminal of the second feedback resistor RF2. The second terminal of the first feedback resistor RF1 serves as a feedback node, and the second terminal of the second feedback resistor RF2 is grounded. RF1 can also be the resistance value of the first feedback resistor, and RF2 can be the resistance value of the second feedback resistor.

[0051] The offset voltage calibration module 150 can calibrate the voltage offset caused by the zero-point compensation module 130. For example, the offset voltage V caused by the compensation resistor RM... OS for: The calibration current generated by the offset voltage calibration module 150 for ,in, The calibration current output by the offset voltage calibration module 150 The proportionality factor with the current of power transistor 120, This is the load current, i.e., the current of power transistor 120. At the feedback node, Kirchhoff's current law equation is: Where VFB is the feedback voltage and VCC is the output voltage of power transistor 120, VCC can be further derived as follows: By selecting a power transistor 120 with an appropriate channel width-to-length ratio, a transistor with an appropriate channel width-to-length ratio in the offset voltage calibration module 150, and a first modulation resistor and a second modulation resistor with appropriate resistance values, the calibration current is adjusted. The proportionality factor with the current of power transistor 120 satisfy: ,but Calibrated current After calibration, the output voltage VCC of power transistor 120, after being output through the compensation resistor RM, compensates for the voltage offset caused by the compensation resistor RM, ensuring that the output voltage VOUT of the high-dropout linear regulator reaches the target output voltage. Compensating for the voltage offset caused by the compensation resistor RM reduces the load regulation of the high-dropout linear regulator, ensuring good output accuracy under different load current conditions.

[0052] For example, within a load capacitance range of 100nF to 100uF, the system phase margin is above 50°, achieving system stability over a wide load capacitance range. Before adding the offset voltage calibration module 150, a 20mA load change results in a 75mV change in the output voltage VOUT of the high-dropout linear regulator. After adding the offset voltage calibration module 150, a 20mA load change results in a 6mV change in the output voltage VOUT of the high-dropout linear regulator.

[0053] Optionally, the high-dropout linear regulator may further include a bandgap reference source 170. The input of the bandgap reference source 170 is connected to the output of the pre-regulation module 160. The supply voltage VREG generated by the pre-regulation module 160 provides the operating voltage for the bandgap reference source 170. The output of the bandgap reference source 170 is connected to the non-inverting input of the error amplifier module 140. The bandgap reference source 170 is used to generate a reference voltage VREF. The bandgap reference source 170 can be integrated onto the high-dropout linear regulator chip. The high-dropout linear regulator may also include an over-temperature protection module and an under-voltage lockout module. The over-temperature protection module triggers a protection mechanism when the temperature of the high-dropout linear regulator chip exceeds a safe threshold, limiting the conduction of the power transistor 120 or even turning it off to prevent the chip from burning out due to overheating. The undervoltage lockout module is used to forcibly shut down the power transistor 120 and part of the internal circuit when the input voltage VIN of the high differential linear regulator is lower than the minimum operating threshold, so as to prevent problems such as unstable output voltage or abnormal operation of the power transistor 120 when the input voltage is insufficient.

[0054] Figure 6 is a circuit structure diagram of a pre-regulator module provided in an embodiment of the present invention. Optionally, the pre-regulator module includes a current-limiting resistor RD, a current source unit 161, a voltage generation unit 162, a super source follower 163, and a Zener transistor NB6. The first terminal of the current-limiting resistor RD and the first terminal of the Zener transistor NB6 are both connected to the input voltage VIN. The second terminal of the current-limiting resistor RD, the first power supply terminal of the current source unit 161, the first input terminal of the voltage generation unit 162, the first input terminal of the super source follower 163, and the control terminal of the Zener transistor NB6 are all connected to the first node D. The two power supply terminals are grounded. The first output terminal of the current source unit 161 is connected to the control terminal of the voltage generation unit 162, and the second output terminal of the current source unit 161 is connected to the first control terminal of the super source follower 163. The output terminal of the voltage generation unit 162 is connected to the second control terminal of the super source follower 163. The current source unit 161 is used to output a first current according to the voltage of the first node D, the voltage generation unit 162 is used to output a first voltage according to the first current, the super source follower 163 is used to regulate the voltage of the first node D according to the first voltage, and the second terminal of the Zener transistor NB6 is the output terminal of the pre-regulator module.

[0055] The current-limiting resistor RD limits the maximum current in the input circuit of the high-dropout linear regulator. RD can be positioned between the input terminal of the high-dropout linear regulator and the Zener transistor NB6 to protect the high-dropout linear regulator chip and its front-end circuitry. The current source unit 161 provides a bias current to the pre-regulator module, for example, by generating a stable first current based on the voltage at the first node D, thus providing a stable operating current and improving the voltage regulation accuracy and anti-interference capability of the pre-regulator module. The voltage generation unit 162 outputs a stable first voltage, for example, by generating a stable first voltage under the influence of the first current. The super source follower 163 follows the first voltage output by the voltage generation unit 162 and generates a stable voltage at the first node D. The super source follower 163 has low output impedance characteristics, providing a stable voltage at the first node D while also exhibiting good anti-interference performance.

[0056] Specifically, the input voltage VIN, after passing through the current-limiting resistor RD, forms the first node D. The first power supply terminal of the current source unit 161 is connected to the first node D, generating a stable first current based on the voltage of the first node D. This first current can be a small current in the nanoamp range, significantly reducing the power consumption of the pre-regulator module. The first output terminal of the current source unit 161 is connected to the voltage generation unit 162, and the second output terminal of the current source unit 161 is connected to the super source follower 163, providing bias current for both the voltage generation unit 162 and the super source follower 163. The output terminal of the voltage generation unit 162 is connected to the super source follower 163, which generates a stable voltage at the first node D based on the first voltage output by the voltage generation unit 162. Through the current source unit 161, the voltage generation unit 162, and the super source follower 163, the voltage at the first node D is stabilized, thereby stabilizing the gate voltage of the voltage regulator transistor NB6. The voltage regulator transistor NB6 then outputs a stable supply voltage VREG.

[0057] Referring again to Figure 6, optionally, the current source unit 161 includes a sixth transistor PB1, a seventh transistor PB2, an eighth transistor PB3, a ninth transistor NB1, a tenth transistor NB2, an eleventh transistor NB3, and a first resistor RB1; the second terminals of the sixth transistor PB1, the seventh transistor PB2, and the eighth transistor PB3 are all connected to the first node D; the first terminal of the sixth transistor PB1 is connected to the control terminal of the sixth transistor PB1; the control terminal of the sixth transistor PB1 is connected to the control terminal of the seventh transistor PB2; the control terminal of the eighth transistor PB3 is connected to the control terminal of the seventh transistor PB2; the first terminal of the ninth transistor NB1 is connected to the sixth transistor PB1. The first terminal of transistor B1 is connected to the control terminal of the ninth transistor NB1, which is connected to the control terminal of the tenth transistor NB2. The second terminal of the ninth transistor NB1 is connected to the first terminal of the first resistor RB1. The first terminal of the tenth transistor NB2 is connected to the first terminal of the seventh transistor PB2, which is connected to the control terminal of the tenth transistor NB2. The second terminal of the tenth transistor NB2 is grounded. The first terminal of the eleventh transistor NB3 is connected to the first terminal of the eighth transistor PB3, which is connected to the control terminal of the tenth transistor NB2. The second terminal of the eleventh transistor NB3 is connected to the first terminal of the first resistor RB1, which is grounded.

[0058] Among them, the sixth transistor PB1, the seventh transistor PB2, and the eighth transistor PB3 can be P-type MOS transistors. The first terminal of the sixth transistor PB1, the first terminal of the seventh transistor PB2, and the first terminal of the eighth transistor PB3 are the drains of the P-type MOS transistors. The second terminal of the sixth transistor PB1, the second terminal of the seventh transistor PB2, and the second terminal of the eighth transistor PB3 are the sources of the P-type MOS transistors. The control terminals of the sixth transistor PB1, the seventh transistor PB2, and the eighth transistor PB3 are the gates of the P-type MOS transistors. The sixth transistor PB1, the seventh transistor PB2, and the eighth transistor PB3 constitute a PMOS current mirror. The ninth transistor NB1, the tenth transistor NB2, and the eleventh transistor NB3 can be N-type MOSFETs. The first terminal of the ninth transistor NB1, the first terminal of the tenth transistor NB2, and the first terminal of the eleventh transistor NB3 can be the drain of the N-type MOSFETs, and the second terminal of the ninth transistor NB1, the second terminal of the tenth transistor NB2, and the second terminal of the eleventh transistor NB3 can be the source of the N-type MOSFETs. The control terminals of the ninth transistor NB1, the control terminals of the tenth transistor NB2, and the control terminals of the eleventh transistor NB3 can be the gates of the N-type MOSFETs. The ninth transistor NB1, the tenth transistor NB2, and the eleventh transistor NB3 constitute an NMOS current mirror. The sixth transistor PB1, the seventh transistor PB2, the eighth transistor PB3, the ninth transistor NB1, the tenth transistor NB2, the eleventh transistor NB3, and the first resistor RB1 constitute a self-biased subthreshold current source, outputting a stable nanoampere-level reference current to provide a stable bias current for driving the voltage generation unit 162 and the super source follower 163 in the pre-regulation module.

[0059] The voltage generation unit 162 includes a twelfth transistor PB4 and a second resistor RB2; the second terminal of the twelfth transistor PB4 is connected to the first node D, the control terminal of the twelfth transistor PB4 is connected to the control terminal of the eighth transistor PB3, the first terminal of the twelfth transistor PB4 is connected to the second resistor RB2, and the second terminal of the second resistor RB2 is grounded.

[0060] In this transistor configuration, the twelfth transistor PB4 can be a P-type MOSFET. Its first terminal can be the drain, its second terminal can be the source, and its control terminal can be the gate. The gate of PB4 is connected to the gate of the eighth transistor PB3. PB4 replicates the current of the eighth transistor PB3, and based on the channel width-to-length ratio of PB4 and PB3, it can proportionally replicate the current of PB3. When PB4 is turned on, its current generates a first voltage through the second resistor RB2.

[0061] The super source follower 163 includes a thirteenth transistor PB5, a fourteenth transistor NB5, and a fifteenth transistor NB4; the second terminal of the thirteenth transistor PB5 and the first terminal of the fourteenth transistor NB5 are connected to the first node D; the control terminal of the thirteenth transistor PB5 is connected to the first terminal of the twelfth transistor PB4; the control terminal of the fourteenth transistor NB5 is connected to the first terminal of the thirteenth transistor PB5; the first terminal of the fifteenth transistor NB4 is connected to the first terminal of the thirteenth transistor PB5; the control terminal of the fifteenth transistor NB4 is connected to the control terminal of the eleventh transistor NB3; and the second terminals of the fourteenth transistor NB5 and the fifteenth transistor NB4 are grounded.

[0062] Among them, the thirteenth transistor PB5 can be a P-type MOSFET. The first terminal of the thirteenth transistor PB5 can be the drain of the P-type MOSFET, the second terminal of the thirteenth transistor PB5 can be the source of the P-type MOSFET, and the control terminal of the thirteenth transistor PB5 can be the gate of the P-type MOSFET. The fourteenth transistor NB5 and the fifteenth transistor NB4 can be N-type MOSFETs. The first terminal of the fourteenth transistor NB5 and the first terminal of the fifteenth transistor NB4 can be the drain of the N-type MOSFET, the second terminal of the fourteenth transistor NB5 and the second terminal of the fifteenth transistor NB4 can be the source of the N-type MOSFET, and the control terminal of the fourteenth transistor NB5 and the control terminal of the fifteenth transistor NB4 can be the gate of the N-type MOSFET.

[0063] The gate of the thirteenth transistor PB5 is connected to the drain of the twelfth transistor PB4, and the drain of the thirteenth transistor PB5 is connected to the drain of the fifteenth transistor NB4. The gate of the fifteenth transistor NB4 is connected to the gate of the eleventh transistor NB3, and the fifteenth transistor NB4 replicates the gate current of the eleventh transistor NB3. When the thirteenth transistor PB5 and the fifteenth transistor NB4 are turned on, the source voltage of the thirteenth transistor PB5 is the sum of the first voltage output by the voltage generation unit 162 and the gate-source voltage of the thirteenth transistor PB5, thereby forming the voltage of the first node D. When the fourteenth transistor NB5 is turned on, excess current in the first node D can be discharged through the discharge path.

[0064] The current-limiting resistor RD of the pre-regulator module affects the overall power consumption of the pre-regulator module. By adjusting the resistance value of the current-limiting resistor RD, the low current consumption of the pre-regulator module can be achieved. The pre-regulator module uses CMOS devices to achieve pre-regulation of the input voltage and generate a stable supply voltage VREG. Compared with the traditional Zener diode breakdown regulation scheme, the high-dropout linear regulator chip significantly reduces the layout area and power consumption.

[0065] Figure 7 is a circuit diagram of an error amplification module provided in an embodiment of the present invention. As shown in Figure 7, the error amplification module includes a sixteenth transistor NA2, a seventeenth transistor NA1, an eighteenth transistor PA1, a nineteenth transistor PA2, and a bias current source IB. The base of the sixteenth transistor NA2 is connected to a reference voltage VREF, the base of the seventeenth transistor NA1 is connected to a feedback voltage VFB, the emitters of the sixteenth transistor NA2 and the seventeenth transistor NA1 are connected to the first terminal of the bias current source IB, and the second terminal of the bias current source IB is grounded. The sources of the eighteenth transistor PA1 and the nineteenth transistor PA2 are connected to a power supply voltage, the gate of the eighteenth transistor PA1 is connected to the gate of the nineteenth transistor PA2, the drain of the eighteenth transistor PA1 is connected to the gate of the eighteenth transistor PA1, the drain of the eighteenth transistor PA1 is connected to the collector of the sixteenth transistor NA2, and the drain of the nineteenth transistor PA2 is connected to the collector of the seventeenth transistor NA1.

[0066] The power supply voltage connected to the source of the eighteenth transistor PA1 and the source of the nineteenth transistor PA2 can be the power supply voltage VREG output by the pre-regulator module. Based on the relationship between the reference voltage VREF and the feedback voltage VFB, the error amplifier module can adjust the gate voltage VG of the power transistor.

[0067] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0068] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A high-differential linear voltage regulator, characterized in that, The system includes an error amplification module, a power transistor, a zero-point compensation module, an output voltage feedback module, and an offset voltage calibration module. The first terminal of the power transistor is connected to the input voltage, and its control terminal is connected to the output terminal of the error amplification module. The second terminal of the power transistor is connected to the first terminal of the zero-point compensation module, which serves as the output terminal of the high-voltage differential linear regulator. The zero point generated by the zero-point compensation module is used to compensate for the poles of the output terminal of the high-voltage differential linear regulator. The input terminal of the output voltage feedback module is connected to the second terminal of the power transistor and is used to generate a feedback voltage based on the output voltage of the power transistor. The output terminal of the output voltage feedback module is connected to the inverting input terminal of the error amplification module, and its fixed potential terminal is grounded. The non-inverting input terminal of the error amplification module is connected to a reference voltage, and the error amplification module is used to adjust the control terminal voltage of the power transistor based on the reference voltage and the feedback voltage. The first input terminal of the offset voltage calibration module is connected to the control terminal of the power transistor, the second input terminal of the offset voltage calibration module is connected to the second terminal of the power transistor, and the output terminal of the offset voltage calibration module is connected to the inverting input terminal of the error amplification module. The offset voltage calibration module is used to sample the current of the power transistor and generate a calibration current based on the sampled current. The calibration current is used to calibrate the feedback voltage.

2. The high differential linear voltage regulator according to claim 1, characterized in that, The zero-point compensation module includes a compensation resistor; the first end of the compensation resistor is connected to the second end of the power transistor, and the second end of the compensation resistor serves as the output terminal of the high-voltage differential linear regulator.

3. The high differential linear voltage regulator according to claim 1, characterized in that, The offset voltage calibration module includes a current sampling unit, a current adjustment unit, and a calibration current generation unit. The first input terminal of the current sampling unit is connected to the control terminal of the power transistor, and the second input terminal is connected to the second terminal of the power transistor. The current sampling unit samples the current of the power transistor and generates the sampled current. The input terminal of the current adjustment unit is connected to the output terminal of the current sampling unit, and the power supply terminal of the current adjustment unit is connected to the power supply voltage. The current adjustment unit generates an adjustment current based on the sampled current; wherein the adjustment current is linearly related to the sampled current. The input terminal of the calibration current generation unit is connected to the output terminal of the current adjustment unit, and the fixed potential terminal of the calibration current generation unit is grounded. The calibration current generation unit generates a calibration current based on the adjustment current; wherein the calibration current is proportional to the adjustment current.

4. The high differential linear regulator according to claim 3, characterized in that, The current sampling unit includes a first transistor; the control terminal of the first transistor is connected to the control terminal of the power transistor, the second terminal of the first transistor is connected to the second terminal of the power transistor, and the first terminal of the first transistor is connected to the input terminal of the current regulation unit.

5. The high differential linear regulator according to claim 3, characterized in that, The current regulation unit includes a second transistor and a third transistor; the first terminal of the second transistor is connected to the output terminal of the current sampling unit, the second terminal of the second transistor is connected to the power supply voltage, and the first terminal of the second transistor is connected to the control terminal of the second transistor; the second terminal of the third transistor is connected to the second terminal of the second transistor, the control terminal of the third transistor is connected to the control terminal of the second transistor, and the first terminal of the third transistor is connected to the input terminal of the calibration current generation unit.

6. The high differential linear regulator according to claim 5, characterized in that, The current regulation unit further includes a first modulation resistor and a second modulation resistor; a first end of the first modulation resistor is connected to a second end of the second transistor, a second end of the first modulation resistor is connected to a control terminal of the second transistor, and a first end of the second transistor is connected to a control terminal of the second transistor through the second modulation resistor; a first end of the second modulation resistor is connected to a second end of the first modulation resistor, and a second end of the second modulation resistor is connected to a control terminal of the third transistor.

7. The high differential linear regulator according to claim 3, characterized in that, The calibration current generation unit includes a fourth transistor and a fifth transistor; the first terminal of the fourth transistor is connected to the output terminal of the current adjustment unit, the first terminal of the fourth transistor is connected to the control terminal of the fourth transistor, and the second terminal of the fourth transistor is grounded; the control terminal of the fifth transistor is connected to the control terminal of the fourth transistor, the second terminal of the fifth transistor is connected to the second terminal of the fourth transistor, and the first terminal of the fifth transistor is the output terminal of the calibration current generation unit.

8. The high differential linear regulator according to claim 1, characterized in that, It also includes a pre-regulator module; the input terminal of the pre-regulator module is connected to the input voltage, and the output terminal of the pre-regulator module is connected to the power supply terminal of the error amplifier module. The pre-regulator module is used to regulate the input voltage and output a power supply voltage, which is used to power the error amplifier module.

9. The high differential linear regulator according to claim 8, characterized in that, The pre-regulation module includes a current-limiting resistor, a current source unit, a voltage generation unit, a super source follower, and a Zener transistor. The first terminal of the current-limiting resistor and the first terminal of the Zener transistor are both connected to the input voltage. The second terminal of the current-limiting resistor, the first power supply terminal of the current source unit, the first input terminal of the voltage generation unit, the first input terminal of the super source follower, and the control terminal of the Zener transistor are all connected to a first node. The second power supply terminal of the current source unit is grounded. The first output terminal of the current source unit is connected to the control terminal of the voltage generation unit. The second output terminal of the current source unit is connected to the first control terminal of the super source follower. The output terminal of the voltage generation unit is connected to the second control terminal of the super source follower. The current source unit is used to output a first current based on the voltage of the first node, the voltage generation unit is used to output a first voltage based on the first current, the super source follower is used to regulate the voltage of the first node based on the first voltage, and the second terminal of the Zener transistor is the output terminal of the pre-regulator module.

10. The high differential linear regulator according to claim 9, characterized in that, The current source unit includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a first resistor. The second terminals of the sixth, seventh, and eighth transistors are all connected to the first node. The first terminal of the sixth transistor is connected to its control terminal, which is also connected to the control terminal of the seventh transistor. The control terminal of the eighth transistor is connected to the control terminal of the seventh transistor. The first terminal of the ninth transistor is connected to the first terminal of the sixth transistor, and its control terminal is connected to the control terminal of the tenth transistor. The second terminal of the ninth transistor is connected to the first terminal of the first resistor. The first terminal of the tenth transistor is connected to the first terminal of the seventh transistor. The first terminal of the tenth transistor is connected to the control terminal of the tenth transistor, and the second terminal of the tenth transistor is grounded; the first terminal of the eleventh transistor is connected to the first terminal of the eighth transistor, the control terminal of the eleventh transistor is connected to the control terminal of the tenth transistor, and the second terminal of the eleventh transistor is connected to the first terminal of the first resistor, the second terminal of the first resistor is grounded; the voltage generation unit includes a twelfth transistor and a second resistor; the second terminal of the twelfth transistor is connected to the first node, the control terminal of the twelfth transistor is connected to the control terminal of the eighth transistor, the first terminal of the twelfth transistor is connected to the second resistor, and the second terminal of the second resistor is grounded; the super source follower includes a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor; The second terminal of the thirteenth transistor and the first terminal of the fourteenth transistor are connected to the first node. The control terminal of the thirteenth transistor is connected to the first terminal of the twelfth transistor. The control terminal of the fourteenth transistor is connected to the first terminal of the thirteenth transistor. The first terminal of the fifteenth transistor is connected to the first terminal of the thirteenth transistor. The control terminal of the fifteenth transistor is connected to the control terminal of the eleventh transistor. The second terminals of the fourteenth transistor and the fifteenth transistor are grounded.

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