Dead zone adjusting system and adjusting method of half-bridge driving chip

Abstract

The invention relates to the field of bridge driving chips, in particular to a dead zone adjusting system and adjusting method of a half-bridge driving chip, the dead zone adjusting system comprises a half-bridge driving module, a dead zone protection module, a dead zone automatic adjusting module and a dead zone reference setting module, the dead zone automatic adjusting module comprises a dead zone signal acquisition unit, a digital-to-analog conversion unit and a comparison amplification unit; the dead zone signal acquisition unit acquires a half-bridge driving signal VH and a half-bridge driving signal VL, the half-bridge driving signal VH and the half-bridge driving signal VL are complementary pulse waveforms, the dead zone signal acquisition unit carries out XNOR logic conversion to generate a dead zone pulse signal VC1 recording dead zone information, and the dead zone pulse signal VC1 is used for outputting the dead zone information. A dead-zone pulse signal VC1 is converted into an analog voltage signal VC2 through an analog-to-digital conversion module, the analog voltage signal VC2 and a dead-zone reference voltage VREF are compared through a comparison amplification unit, then a dead-zone adjusting voltage VS is output, the resistance value of a voltage-controlled adjusting device is controlled, and dead-zone delay is regulated and controlled in real time.

Description

Technical Field

[0001] This invention relates to the field of bridge driver chips, and more specifically to a dead-time adjustment system and method for a half-bridge driver chip. Background Technology

[0002] A half-bridge driver chip is an integrated circuit chip used to enhance the gate control signal of a controller and control the conduction and cutoff of power semiconductor devices, playing a core role in the field of power conversion and control. It significantly improves the switching speed of power devices (such as MOSFETs and IGBTs) and reduces losses by converting low-voltage signals into high-voltage or high-current drive signals. It also integrates key functions such as high / low-side drive, level shifting, dead-time control, and bootstrap power supply design, ensuring stable operation of power devices in complex circuits. Its core working principle involves processing external input signals (such as PWM signals) through internal logic circuits, achieving floating power supply for the high-side drive signal via a level shifting module, and finally providing a fast, high-current switching signal to the power devices through an output drive module.

[0003] The existing dead-time protection method for power transistor half-bridge driver chips is to set the dead-time parameter and interlock it with the half-bridge power transistor drive signal. However, the dead-time protection parameter is a fixed value after being set. When the chip's operating temperature and other external conditions change, it will cause the delay RC circuit parameter in the dead-time protection circuit to shift, thereby causing the dead-time protection parameter to shift. This will lead to a decrease in the operating stability of the half-bridge power transistor and prevent the power transistor from burning out due to an excessively small dead time. Summary of the Invention

[0004] The purpose of this invention is to provide a dead-time adjustment system and method for a half-bridge driver chip, aiming to improve the problem that conventional dead-time protection parameters are set to fixed values. When external conditions such as chip operating temperature change, the parameters of the delay RC circuit in the dead-time protection circuit will shift, resulting in a shift in the dead-time protection parameters, which leads to a decrease in the operating stability of the half-bridge power transistor and avoids the problem of the power transistor burning out due to an excessively small dead time.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: A dead-time adjustment system and method for a half-bridge driver chip, characterized in that it includes a half-bridge driver module, a dead-time protection module, a dead-time automatic adjustment module, and a dead-time reference setting module, wherein the dead-time automatic adjustment module includes a dead-time signal acquisition unit, a digital-to-analog conversion unit, and a comparison amplification unit; The half-bridge drive control signal VPWM is input to the dead-time protection module. The dead-time protection module includes a voltage-controlled adjustment device and is connected to the input terminal of the half-bridge drive module. The dead-time signal acquisition unit is connected to the output terminal of the half-bridge drive module. The digital-to-analog converter is connected to the output terminal of the dead-time signal acquisition unit. The output terminal of the digital-to-analog converter and the output terminal of the dead-time reference setting module are respectively connected to the inverting input terminal and the non-inverting input terminal of the comparator amplification unit. The output terminal of the comparator amplification unit is electrically connected to the control terminal of the voltage-controlled adjustment device.

[0006] Furthermore, the half-bridge driver module includes NOT5, NOT6, NOT7, and NOT8 gates; The output terminal of the dead-time protection module is electrically connected to the input terminal of NOT gate 5 and NOT gate 7. The output terminal of NOT gate 5 is electrically connected to the input terminal of NOT gate 6. The output terminal of NOT gate 7 is electrically connected to the input terminal of NOT gate 8. The output terminal of NOT gate 6 outputs VH to the dead-time signal acquisition unit, and the output terminal of NOT gate 8 outputs VL to the dead-time signal acquisition unit.

[0007] Furthermore, the half-bridge drive module also includes MOSFET N1 and MOSFET N2; The drain of the MOS transistor N1 is electrically connected to the external power supply VCC. The output terminal of NOT6 is electrically connected to the gate of MOSFET N1, the output terminal of NOT8 is electrically connected to the gate of MOSFET N2, and the source of MOSFET N1 and the drain of MOSFET N2 serve as output terminals to output VOUT. The source of the MOS transistor N2 is grounded.

[0008] Furthermore, both MOS transistors N1 and N2 are NMOS transistors.

[0009] Furthermore, the dead-zone protection module includes NOT gate NOT0, NOT gate NOT1, NOT gate NOT3, NOT gate NOT4, NOR gate NOR1, NOR gate NOR2 and capacitors C1 and C2, and the voltage-controlled adjustment device includes voltage-controlled resistor VCR1 and voltage-controlled resistor VCR2. The half-bridge drive control signal VPWM is input to the first input terminal of NOR gate NOR1 and the input terminal of NOT gate NOT0. The output terminal of NOT gate NOT0 is electrically connected to the second input terminal of NOR gate NOR2. The input terminal of NOR gate NOR1 is electrically connected to the input terminal of NOT gate NOT1. The output terminal of NOT gate NOT1 is electrically connected to one end of voltage-controlled resistor VCR1. The other end of voltage-controlled resistor VCR1 is electrically connected to one end of capacitor C1 and the input terminal of NOT gate NOT3. The output terminal of NOT gate NOT3 is electrically connected to the input terminal of NOT gate NOT5 and the first input terminal of NOR gate NOR2. The input terminal of the NOR gate NOR2 is electrically connected to the input terminal of the NOT gate NOT2, the output terminal of the NOT gate NOT2 is electrically connected to one end of the voltage-controlled resistor VCR2, the other end of the voltage-controlled resistor VCR2 is electrically connected to one end of the capacitor C2 and the input terminal of the NOT gate NOT4, and the output terminal of the NOT gate NOT4 is electrically connected to the input terminal of the NOT gate NOT7 and the second input terminal of the NOR gate NOR1. The other ends of capacitor C1 and capacitor C2 are both grounded.

[0010] Furthermore, the dead-zone reference setting module includes an adjustable resistor RREF and a resistor R1; One end of the adjustable resistor RREF is electrically connected to the external power supply VCC, and the other end of the adjustable resistor RREF is electrically connected to one end of the resistor R1, and outputs the dead zone reference voltage VREF to the non-inverting input of the comparator amplifier unit. The other end of the resistor R1 is grounded.

[0011] Furthermore, the dead-zone signal acquisition unit includes AND gate AND1, AND gate AND2, NOT gate NOT21, NOT gate NOT22, and OR gate OR1; The half-bridge driver module outputs a drive signal VH to the first input terminal of AND gate AND1 and the input terminal of NOT gate NOT21; the half-bridge driver module outputs a drive signal VL to the second input terminal of AND gate AND1 and the input terminal of NOT gate NOT22; the output terminal of NOT gate NOT21 and the output terminal of NOT gate NOT22 are electrically connected to the first and second input terminals of AND gate AND2, respectively; the output terminals of AND gate AND1 and AND gate AND2 are electrically connected to the first and second input terminals of OR gate OR1, respectively; and the output terminal of OR gate OR1 outputs a dead-time pulse signal VC1 to the digital-to-analog converter unit.

[0012] Furthermore, the digital-to-analog conversion unit includes an operational amplifier U1, resistors R5, R6, and R7, and a capacitor C3; The dead-zone signal acquisition unit outputs a dead-zone pulse signal VC1 to one end of resistor R7. The other end of resistor R7 is electrically connected to the non-inverting input of operational amplifier U1 and one end of capacitor C3. One end of resistor R5 and one end of resistor R6 are both electrically connected to the inverting input of operational amplifier U1. The output of operational amplifier U1 is electrically connected to the other end of resistor R6 and outputs an analog voltage signal VC2 to the inverting input of comparator amplifier unit.

[0013] Furthermore, the comparison amplification unit includes an operational amplifier U2, a resistor RI, and a resistor RF; The analog-to-digital converter outputs an analog voltage signal VC2 to one end of resistor RI. The other end of resistor RI and one end of resistor RF are both electrically connected to the inverting input of operational amplifier U2. The dead-time reference setting module outputs a dead-time reference voltage VREF to the non-inverting input of operational amplifier U2. The output of operational amplifier U2 is electrically connected to the other end of resistor RF and outputs a dead-time adjustment voltage VS to the control terminal of voltage-controlled adjustment device.

[0014] To achieve the above objectives, the present invention also adopts the following technical solution: An adjustment method, employing the dead-time adjustment system of the aforementioned half-bridge driver chip, includes the following steps: S01. The dead-zone signal acquisition unit acquires the drive signal VH and drive signal VL output by the half-bridge drive module; S02. The dead-zone signal acquisition unit generates a dead-zone pulse signal VC1 through XOR NOT logic transformation, and outputs the dead-zone pulse signal VC1 to the digital-to-analog conversion unit for digital-to-analog conversion; S03. The analog-to-digital converter outputs the analog voltage signal VC2 to the inverting input of the comparator amplifier unit, and the dead-zone reference setting module outputs the dead-zone reference voltage VREF to the non-inverting input of the comparator amplifier unit. S04. The dead-time adjustment voltage VS of the comparator amplifier unit is output to the control terminal of the voltage-controlled regulator; S05. The voltage-controlled adjustment device changes its own resistance to change the dead zone and extend the time.

[0015] By adopting the above technical solution, the present invention has the following advantages compared with the prior art: The dead-time signal acquisition unit acquires the half-bridge drive signals VH and VL, which are complementary pulse waveforms. The dead-time signal acquisition unit performs an XOR NOT logic transformation to generate a dead-time pulse signal VC1 that records dead-time information. The dead-time pulse signal VC1 is converted into an analog voltage signal VC2 by the analog-to-digital converter module. The analog voltage signal VC2 and the dead-time reference voltage VREF are compared by the comparator amplification unit to output the dead-time adjustment voltage VS. The dead-time adjustment voltage VS controls the resistance value of the voltage-controlled adjustment device to achieve real-time adjustment of the dead-time delay. Attached Figure Description

[0016] Figure 1 This is a block diagram of the adjustment method for the half-bridge driver chip described in this invention; Figure 2 This is a circuit diagram of the dead-time adjustment system of the half-bridge driver chip described in this invention. Figure 3 This is a circuit diagram of the dead-time signal acquisition unit of the dead-time adjustment system of the half-bridge driver chip described in this invention. Figure 4 This is a circuit diagram of the digital-to-analog converter unit of the dead-time adjustment system of the half-bridge driver chip described in this invention; Figure 5 This is a circuit diagram of the comparison amplification unit of the dead-time adjustment system of the half-bridge driver chip described in this invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0018] Additionally, it should be noted that the terms "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" are all based on the orientation or positional relationship shown in the accompanying drawings. They are merely for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element of the present invention must have a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0019] When an element is referred to as being "fixed to," "set on," or "contained on" another element, it can be directly on or indirectly on that other element. When an element is referred to as being "connected to," it can be directly connected to or indirectly connected to that other element.

[0020] Unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances. Example

[0021] Please refer to Figure 1-5 As shown, this embodiment provides a dead-time adjustment system for a half-bridge driver chip, including a half-bridge driver module, a dead-time protection module, a dead-time automatic adjustment module, and a dead-time reference setting module. The dead-time automatic adjustment module includes a dead-time signal acquisition unit, a digital-to-analog conversion unit, and a comparison amplification unit.

[0022] Please refer to Figure 2 As shown, the half-bridge drive control signal VPWM is input to the dead-time protection module. The dead-time protection module includes a voltage-controlled regulator (VCD) connected to the input of the half-bridge drive module. The dead-time signal acquisition unit is connected to the output of the half-bridge drive module. The digital-to-analog converter (DAC) is connected to the output of the dead-time signal acquisition unit. The output of the DAC and the output of the dead-time reference setting module are respectively connected to the inverting and non-inverting inputs of the comparator amplifier unit. The output of the comparator amplifier unit is electrically connected to the control terminal of the VCD.

[0023] Please refer to Figure 1 As shown, this embodiment further discloses an adjustment method, which applies the above-mentioned adjustment system and specifically includes the following steps: S01. The dead-zone signal acquisition unit acquires the drive signal VH and drive signal VL output by the half-bridge drive module; S02. The dead-zone signal acquisition unit generates a dead-zone pulse signal VC1 through XOR NOT logic transformation, and outputs the dead-zone pulse signal VC1 to the digital-to-analog conversion unit for digital-to-analog conversion; S03. The analog-to-digital converter outputs the analog voltage signal VC2 to the inverting input of the comparator amplifier unit, and the dead-zone reference setting module outputs the dead-zone reference voltage VREF to the non-inverting input of the comparator amplifier unit. S04. The dead-time adjustment voltage VS of the comparator amplifier unit is output to the control terminal of the voltage-controlled regulator; S05. The voltage-controlled adjustment device changes its own resistance to change the dead zone and extend the time.

[0024] The dead-time signal acquisition unit acquires the half-bridge drive signals VH and VL, which are complementary pulse waveforms. The dead-time signal acquisition unit performs an XOR NOT logic transformation to generate a dead-time pulse signal VC1 that records dead-time information. The dead-time pulse signal VC1 is converted into an analog voltage signal VC2 by the analog-to-digital converter module. The analog voltage signal VC2 and the dead-time reference voltage VREF are compared by the comparator amplification unit to output the dead-time adjustment voltage VS. The dead-time adjustment voltage VS controls the resistance value of the voltage-controlled adjustment device to achieve real-time adjustment of the dead-time delay.

[0025] Please refer to Figure 2 As shown, specifically, the half-bridge driver module includes NOT5, NOT6, NOT7, and NOT8 gates. The output of the dead-time protection module is electrically connected to the input of NOT5 and NOT7; the output of NOT5 is electrically connected to the input of NOT6, and the output of NOT7 is electrically connected to the input of NOT8. The output of NOT6 outputs VH to the dead-time signal acquisition unit; the output of NOT8 outputs VL to the dead-time signal acquisition unit.

[0026] In this embodiment, the half-bridge driver module further includes MOSFETs N1 and N2. The drain of MOSFET N1 is electrically connected to the external power supply VCC. The output of NOT gate 6 is electrically connected to the gate of MOSFET N1, and the output of NOT gate 8 is electrically connected to the gate of MOSFET N2. The source of MOSFET N1 and the drain of MOSFET N2 serve as the output terminals VOUT, and the source of MOSFET N2 is grounded. Both MOSFETs N1 and N2 are NMOS transistors.

[0027] NOT5 and NOT6 form the upper half-bridge driver, and NOT7 and NOT8 form the lower half-bridge driver. They output drive signals VH and VL to MOSFETs N1 and N2 respectively to control the magnitude of the output voltage VOUT.

[0028] Specifically, the dead-zone protection module includes NOT gates NOT0, NOT gates NOT3, NOT gates NOT4, NOR gates NOR1 and NOR gates NOR2, and capacitors C1 and C2. The voltage-controlled adjustment device includes voltage-controlled resistors VCR1 and VCR2.

[0029] The half-bridge drive control signal VPWM is input to the first input terminal of NOR gate NOR1 and the input terminal of NOT gate NOT0. The output terminal of NOT gate NOT0 is electrically connected to the second input terminal of NOR gate NOR2, and the input terminal of NOR gate NOR1 is electrically connected to the input terminal of NOT gate NOT1. The output terminal of NOT gate NOT1 is electrically connected to one end of voltage-controlled resistor VCR1, the other end of voltage-controlled resistor VCR1 is electrically connected to one end of capacitor C1 and the input terminal of NOT gate NOT3, and the output terminal of NOT gate NOT3 is electrically connected to the input terminal of NOT gate NOT5 and the first input terminal of NOR gate NOR2. The input of NOR2 is electrically connected to the input of NOT2. The output of NOT2 is electrically connected to one end of VCR2. The other end of VCR2 is electrically connected to one end of capacitor C2 and the input of NOT4. The output of NOT4 is electrically connected to the input of NOT7 and the second input of NOR1. The other ends of capacitors C1 and C2 are both grounded. In this embodiment, the capacitance values ​​of capacitors C1 and C2 are equal, and the resistance values ​​of VCR1 and VCR2 are equal.

[0030] The half-bridge drive control signal VPWM serves as the drive signal VPH for the upper power transistor. VPWM, after passing through NOT gate 0, generates the drive signal VPL for the lower power transistor. The upper power transistor drive signal VPH, after passing through NOR gate NOR1, NOT gate NOT1, voltage-controlled resistor VCR1, and NOT gate NOT3, generates the drive signal VH1, which is then output to drive the upper half-bridge transistor. The lower power transistor drive signal VPL, after passing through NOR gate NOR2, NOT gate NOT2, voltage-controlled resistor VCR2, and NOT gate NOT4, generates the drive signal VL1, which is then output to drive the lower half-bridge transistor. Drive signal VH1 is further enhanced by NOT gate NOT5 and NOT gate NOT6, and drive signal VL1 is further enhanced by NOT gate NOT7 and NOT gate NOT8, driving MOSFETs N1 and N2 respectively.

[0031] The drive signals VPH and VL1 of the upper power transistor, and VPL and VH1 of the lower power transistor, are interlocked via an NOR gate to prevent dead time in drive signals VH1 and VL1 and avoid overlapping of in-phase signals. Voltage-controlled resistors VCR1 and C1, and VCR2 and C2, are combined to form RC delay circuits to generate dead time delays.

[0032] Specifically, the dead-time reference setting module includes an adjustable resistor RREF and a resistor R1. One end of the adjustable resistor RREF is electrically connected to the external power supply VCC, and the other end of the adjustable resistor RREF is electrically connected to one end of the resistor R1, outputting the dead-time reference voltage VREF to the non-inverting input of the comparator amplifier unit. The other end of the resistor R1 is grounded. The dead-time reference voltage VREF is adjusted by the adjustable resistor RREF to set the dead-time parameters. The analog voltage signal VC2 and the dead-time reference voltage VREF are compared by the comparator amplifier unit to output a dead-time adjustment voltage VS. The dead-time adjustment voltage VS controls the resistance value of the voltage-controlled adjustment device, enabling real-time adjustment of the dead-time delay. When the dead-zone non-overlap time of drive signals VH and VL decreases, the duty cycle of the dead-zone pulse signal VC1 generated by the dead-zone signal acquisition unit decreases synchronously. The analog voltage signal VC2 output by the digital-to-analog converter of the dead-zone pulse signal VC1 also decreases accordingly. The decreasing analog voltage signal VC2 and the dead-zone reference voltage VREF output by the comparator amplification unit increase the dead-zone adjustment voltage VS. As the dead-zone adjustment voltage VS increases, the resistance values ​​of the voltage-controlled resistors VCR1 and VCR2 controlled by it also increase, thereby increasing the dead-zone delay and thus increasing the dead-zone non-overlap time of drive signals VH and VL.

[0033] When the dead-time non-overlapping time of drive signals VH and VL increases, the duty cycle of the dead-time pulse signal VC1 generated by the dead-time signal acquisition unit increases synchronously. The analog voltage signal VC2 output from the digital-to-analog converter of the dead-time pulse signal VC1 also increases accordingly. The increased analog voltage signal VC2 and the dead-time reference voltage VREF, output from the comparator amplification unit, decrease. As the dead-time adjustment voltage VS decreases, the resistance values ​​of the voltage-controlled resistors VCR1 and VCR2, which it controls, also decrease, thereby reducing the dead-time delay and, consequently, the dead-time non-overlapping time of drive signals VH and VL. The automatic dead-time adjustment module achieves negative feedback in the half-bridge drive circuit, automatically controlling the stability of the dead-time.

[0034] Please refer to Figure 3As shown, the dead-time signal acquisition unit includes AND gate AND1, AND gate AND2, NOT gate NOT21, NOT gate NOT22, and OR gate OR1; the half-bridge driver module outputs a drive signal VH to the first input terminal of AND gate AND1 and the input terminal of NOT gate NOT21; the half-bridge driver module outputs a drive signal VL to the second input terminal of AND gate AND1 and the input terminal of NOT gate NOT22; the output terminal of NOT gate NOT21 and the output terminal of NOT gate NOT22 are electrically connected to the first and second input terminals of AND gate AND2, respectively; the output terminals of AND gate AND1 and AND gate AND2 are electrically connected to the first and second input terminals of OR gate OR1, respectively; and the output terminal of OR gate OR1 outputs a dead-time pulse signal VC1 to the digital-to-analog converter unit.

[0035] Please refer to Figure 4 As shown, the digital-to-analog conversion unit includes an operational amplifier U1, resistors R5, R6, and R7, and a capacitor C3. The dead-time signal acquisition unit outputs a dead-time pulse signal VC1 to one end of resistor R7. The other end of resistor R7 is electrically connected to the non-inverting input of operational amplifier U1 and one end of capacitor C3. One end of resistor R5 and one end of resistor R6 are both electrically connected to the inverting input of operational amplifier U1. The output of operational amplifier U1 is electrically connected to the other end of resistor R6 and outputs an analog voltage signal VC2 to the inverting input of the comparator amplifier unit.

[0036] Please refer to Figure 5 As shown, the comparison amplification unit includes operational amplifier U2, resistor RI, and resistor RF; the digital-to-analog converter outputs an analog voltage signal VC2 to one end of resistor RI, and the other end of resistor RI and one end of resistor RF are electrically connected to the inverting input of operational amplifier U2; the dead-time reference setting module outputs a dead-time reference voltage VREF to the non-inverting input of operational amplifier U2, and the output of operational amplifier U2 is electrically connected to the other end of resistor RF, and outputs a dead-time adjustment voltage VS to the control terminal of the voltage-controlled adjustment device.

[0037] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A dead-time adjustment system for a half-bridge driver chip, characterized in that, It includes a half-bridge drive module, a dead-time protection module, a dead-time automatic adjustment module, and a dead-time reference setting module. The dead-time automatic adjustment module includes a dead-time signal acquisition unit, a digital-to-analog conversion unit, and a comparison amplification unit. The half-bridge drive control signal VPWM is input to the dead-time protection module. The dead-time protection module includes a voltage-controlled adjustment device and is connected to the input terminal of the half-bridge drive module. The dead-time signal acquisition unit is connected to the output terminal of the half-bridge drive module. The digital-to-analog converter is connected to the output terminal of the dead-time signal acquisition unit. The output terminal of the digital-to-analog converter and the output terminal of the dead-time reference setting module are respectively connected to the inverting input terminal and the non-inverting input terminal of the comparator amplification unit. The output terminal of the comparator amplification unit is electrically connected to the control terminal of the voltage-controlled adjustment device.

2. The dead-time adjustment system for a half-bridge driver chip according to claim 1, characterized in that: The half-bridge driver module includes NOT5, NOT6, NOT7, and NOT8 gates; The output terminal of the dead-time protection module is electrically connected to the input terminal of NOT gate 5 and NOT gate 7. The output terminal of NOT gate 5 is electrically connected to the input terminal of NOT gate 6. The output terminal of NOT gate 7 is electrically connected to the input terminal of NOT gate 8. The output terminal of NOT gate 6 outputs VH to the dead-time signal acquisition unit, and the output terminal of NOT gate 8 outputs VL to the dead-time signal acquisition unit.

3. The dead-time adjustment system for a half-bridge driver chip according to claim 2, characterized in that: The half-bridge drive module also includes MOSFET N1 and MOSFET N2; The drain of the MOSFET N1 is electrically connected to the external power supply VCC; the output of the NOT gate NOT6 is electrically connected to the gate of the MOSFET N1; the output of the NOT gate NOT8 is electrically connected to the gate of the MOSFET N2; and the source of the MOSFET N1 and the drain of the MOSFET N2 serve as the output terminals VOUT. The source of the MOS transistor N2 is grounded.

4. The dead-time adjustment system for a half-bridge driver chip according to claim 3, characterized in that: Both MOS transistors N1 and N2 are NMOS transistors.

5. The dead-time adjustment system for a half-bridge driver chip according to claim 2, characterized in that: The dead zone protection module includes NOT0, NOT1, NOT3, NOT4, NOR1, NOR2 and capacitors C1 and C2. The voltage-controlled adjustment device includes voltage-controlled resistors VCR1 and VCR2. The half-bridge drive control signal VPWM is input to the first input terminal of NOR gate NOR1 and the input terminal of NOT gate NOT0. The output terminal of NOT gate NOT0 is electrically connected to the second input terminal of NOR gate NOR2. The input terminal of NOR gate NOR1 is electrically connected to the input terminal of NOT gate NOT1. The output terminal of NOT gate NOT1 is electrically connected to one end of voltage-controlled resistor VCR1. The other end of voltage-controlled resistor VCR1 is electrically connected to one end of capacitor C1 and the input terminal of NOT gate NOT3. The output terminal of NOT gate NOT3 is electrically connected to the input terminal of NOT gate NOT5 and the first input terminal of NOR gate NOR2. The input terminal of the NOR gate NOR2 is electrically connected to the input terminal of the NOT gate NOT2, the output terminal of the NOT gate NOT2 is electrically connected to one end of the voltage-controlled resistor VCR2, the other end of the voltage-controlled resistor VCR2 is electrically connected to one end of the capacitor C2 and the input terminal of the NOT gate NOT4, and the output terminal of the NOT gate NOT4 is electrically connected to the input terminal of the NOT gate NOT7 and the second input terminal of the NOR gate NOR1. The other ends of capacitor C1 and capacitor C2 are both grounded.

6. The dead-time adjustment system for a half-bridge driver chip according to claim 1, characterized in that: The dead zone reference setting module includes an adjustable resistor RREF and a resistor R1; One end of the adjustable resistor RREF is electrically connected to the external power supply VCC, and the other end of the adjustable resistor RREF is electrically connected to one end of the resistor R1, and outputs the dead zone reference voltage VREF to the non-inverting input of the comparator amplifier unit. The other end of the resistor R1 is grounded.

7. The dead-time adjustment system for a half-bridge driver chip according to claim 1, characterized in that: The dead zone signal acquisition unit includes AND gate AND1, AND gate AND2, NOT gate NOT21, NOT gate NOT22, and OR gate OR1; The half-bridge driver module outputs a drive signal VH to the first input terminal of AND gate AND1 and the input terminal of NOT gate NOT21; the half-bridge driver module outputs a drive signal VL to the second input terminal of AND gate AND1 and the input terminal of NOT gate NOT22; the output terminal of NOT gate NOT21 and the output terminal of NOT gate NOT22 are electrically connected to the first and second input terminals of AND gate AND2, respectively; the output terminals of AND gate AND1 and AND gate AND2 are electrically connected to the first and second input terminals of OR gate OR1, respectively; and the output terminal of OR gate OR1 outputs a dead-time pulse signal VC1 to the digital-to-analog converter unit.

8. The dead-time adjustment system for a half-bridge driver chip according to claim 1, characterized in that: The digital-to-analog conversion unit includes an operational amplifier U1, resistors R5, R6, and R7, and a capacitor C3; The dead-zone signal acquisition unit outputs a dead-zone pulse signal VC1 to one end of resistor R7. The other end of resistor R7 is electrically connected to the non-inverting input of operational amplifier U1 and one end of capacitor C3. One end of resistor R5 and one end of resistor R6 are both electrically connected to the inverting input of operational amplifier U1. The output of operational amplifier U1 is electrically connected to the other end of resistor R6 and outputs an analog voltage signal VC2 to the inverting input of comparator amplifier unit.

9. The dead-time adjustment system for a half-bridge driver chip according to claim 1, characterized in that: The comparison amplification unit includes an operational amplifier U2, a resistor RI, and a resistor RF; The analog-to-digital converter outputs an analog voltage signal VC2 to one end of resistor RI. The other end of resistor RI and one end of resistor RF are both electrically connected to the inverting input of operational amplifier U2. The dead-time reference setting module outputs a dead-time reference voltage VREF to the non-inverting input of operational amplifier U2. The output of operational amplifier U2 is electrically connected to the other end of resistor RF and outputs a dead-time adjustment voltage VS to the control terminal of voltage-controlled adjustment device.

10. An adjustment method, characterized in that, The dead-time adjustment system of the half-bridge driver chip according to any one of claims 1-9 includes the following steps: S01. The dead-zone signal acquisition unit acquires the drive signal VH and drive signal VL output by the half-bridge drive module; S02. The dead-zone signal acquisition unit generates a dead-zone pulse signal VC1 through XOR NOT logic transformation, and outputs the dead-zone pulse signal VC1 to the digital-to-analog conversion unit for digital-to-analog conversion; S03. The analog-to-digital converter outputs the analog voltage signal VC2 to the inverting input of the comparator amplifier unit, and the dead-zone reference setting module outputs the dead-zone reference voltage VREF to the non-inverting input of the comparator amplifier unit. S04. The dead-time adjustment voltage VS of the comparator amplifier unit is output to the control terminal of the voltage-controlled regulator; S05. The voltage-controlled adjustment device changes its own resistance to change the dead zone and extend the time.

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