Method and device for controlling three-level power converter and power conversion system

Abstract

The embodiment of the invention provides a method and device for controlling a three-level power converter, control equipment and a power conversion system. The method comprises the following steps: acquiring an alternating current side current of a three-level power converter, wherein the three-level power converter is configured to perform power conversion between direct current power and alternating current power; in response to determining the flow direction of the acquired AC-side current and determining the power switch group currently performing level switching, the power switch group is switched on the basis of the voltage or potential information of the three-level power converter and time information related to the switching operation of the three-level power converter. Determining a compensation duty ratio for compensating a dead zone of the power switch group; and adjusting the duty cycle of at least one power switch of the power switch group based on the compensation duty cycle; and transmitting a signal for controlling the at least one power switch based on the adjusted duty cycle. The embodiment of the invention can relieve or eliminate the defects of distortion, harmonic waves and the like caused by the dead time period.

Description

Technical Field

[0001] This disclosure relates to the field of power electronics technology, and more specifically, to methods and apparatuses, control devices, and power conversion systems for controlling three-level power converters. Background Technology

[0002] Power converters convert input power into appropriate output power to supply a load by controlling the on / off state of power switches. For example, an inverter for driving an AC motor can convert DC power into the AC power required by the motor. Currently, multilevel technology is widely used in power converters to reduce harmonics and switching losses.

[0003] During the operation of a power converter, the power switch may experience switching delay. Therefore, to avoid short circuits between the positive and negative terminals of the power supply caused by the switching delay, a dead time is typically set during the switching process of the power converter. However, the presence of a dead time can lead to problems such as current distortion, increased harmonics, and output torque pulses. Currently, there is a lack of precise and effective methods to eliminate the adverse effects of dead time on the operation of power converters, especially three-level power converters. Summary of the Invention

[0004] To at least partially address the above and other potential problems, embodiments of this disclosure provide methods and apparatus for controlling a three-level power converter, control devices, and power conversion systems.

[0005] In a first aspect of this disclosure, a method for controlling a three-level power converter is provided, the method comprising: acquiring an AC-side current of the three-level power converter, the three-level power converter being configured to perform power conversion between DC power and AC power; in response to determining the flow direction of the acquired AC-side current and determining a power switch group currently performing level switching, determining a compensation duty cycle for compensating the dead time of the power switch group based on voltage or potential information of the three-level power converter and time information related to the switching operation of the three-level power converter; adjusting the duty cycle of at least one power switch of the power switch group based on the compensation duty cycle; and transmitting a signal for controlling at least one power switch based on the adjusted duty cycle.

[0006] In some embodiments of this disclosure, the method further includes: acquiring the neutral point voltage of a three-level power converter, the neutral point voltage including at least one of the voltage between the neutral point and the DC-side positive bus and the voltage between the neutral point and the DC-side negative bus, wherein the voltage or potential information includes the acquired neutral point voltage.

[0007] In some embodiments of this disclosure, the method further includes: determining the turn-on transition duration and turn-off transition duration of at least one power switch in the power switch group based on the magnitude of the acquired AC side current, wherein the time information includes the turn-on transition duration and the turn-off transition duration.

[0008] In some embodiments of this disclosure, the turn-on transition time and turn-off transition time of the power switch adjacent to the DC positive bus or the DC negative bus are different from the turn-on transition time and turn-off transition time of the power switch not adjacent to the DC positive bus or the DC negative bus.

[0009] In some embodiments of this disclosure, the three-level power converter includes: a first power switch, a second power switch, a third power switch, and a fourth power switch connected in series between a DC-side positive bus and a DC-side negative bus; a first freewheeling diode connected in parallel with the first power switch, a second freewheeling diode connected in parallel with the second power switch, a third freewheeling diode connected in parallel with the third power switch, and a fourth freewheeling diode connected in parallel with the fourth power switch; a first clamping diode coupled to a neutral point at its anode and coupled to a node between the first and second power switches at its cathode; and a second clamping diode coupled to a neutral point at its cathode and coupled to a node between the third and fourth power switches at its anode.

[0010] In some embodiments of this disclosure, when the acquired AC side current flows out of the three-level power converter and the power switch group currently performing level switching is the first power switch and the third power switch, the voltage or potential information further includes at least one of the following: the voltage between the DC side positive bus and the DC side negative bus, the on-state voltage drop of the first power switch, the on-state voltage drop of the second power switch, and the on-state voltage drop of the first clamping diode, and the time information further includes at least one of the following: the duty cycle before adjustment of the first power switch, and the carrier period duration.

[0011] In some embodiments of this disclosure, when the acquired AC side current flows into the three-level power converter and the power switch group currently performing level switching is the first power switch and the third power switch, the voltage or potential information further includes at least one of the following: the voltage between the DC side positive bus and the DC side negative bus, the on-state voltage drop of the first power switch, the on-state voltage drop of the second power switch, the on-state voltage drop of the third power switch, the on-state voltage drop of the first freewheeling diode, and the on-state voltage drop of the second clamping diode, and the time information further includes at least one of the following: the duty cycle before adjustment for the first power switch, the dead time for the first power switch, the dead time for the third power switch, and the carrier period duration.

[0012] In some embodiments of this disclosure, when the acquired AC side current flows out of the three-level power converter and the power switch group currently performing level switching is the second power switch and the fourth power switch, the voltage or potential information further includes at least one of the following: the voltage between the DC side positive bus and the DC side negative bus, the on-state voltage drop of the second power switch, the on-state voltage drop of the third power switch, the on-state voltage drop of the fourth power switch, the on-state voltage drop of the fourth freewheeling current tube, and the on-state voltage drop of the first clamping diode, and the time information further includes at least one of the following: the duty cycle before adjustment for the second power switch, the dead time for the second power switch, the dead time for the fourth power switch, and the carrier period duration.

[0013] In some embodiments of this disclosure, when the acquired AC side current flows into the three-level power converter and the power switch group currently performing level switching is the second power switch and the fourth power switch, the voltage or potential information further includes at least one of the following: the voltage between the DC side positive bus and the DC side negative bus, the on-state voltage drop of the third power switch, the on-state voltage drop of the fourth power switch, and the on-state voltage drop of the second clamping diode, and the time information further includes at least one of the following: the duty cycle before adjustment for the second power switch, the dead time for the second power switch, the dead time for the fourth power switch, and the carrier period duration.

[0014] In some embodiments of this disclosure, the dead time for the corresponding power switch is greater than or equal to the maximum turn-off transition time of the corresponding power switch.

[0015] In some embodiments of this disclosure, determining the compensation duty cycle for compensating the dead zone of the power switch group includes: when the deviation between the phase angle of the acquired AC side current and the zero-crossing point exceeds a predetermined threshold and the AC side current flows out of the three-level power converter, calculating the difference between the expected output voltage and the actual output voltage of the three-level power converter on the AC side, and determining a first compensation value as the compensation duty cycle based on the calculated difference; when the deviation between the phase angle of the acquired AC side current and the zero-crossing point exceeds a predetermined threshold and the AC side current flows into the three-level power converter, calculating the difference between the expected output voltage and the actual output voltage of the three-level power converter on the AC side, and determining a second compensation value as the compensation duty cycle based on the calculated difference; and when the deviation between the phase angle of the acquired AC side current and the zero-crossing point is lower than a predetermined threshold, determining the compensation duty cycle by linear interpolation between the first compensation value and the second compensation value.

[0016] In some embodiments of this disclosure, the three-level power converter includes a three-phase three-level inverter.

[0017] In a second aspect of this disclosure, a control device is provided that is coupled to a three-level power converter and configured to perform the method according to the first aspect.

[0018] In a third aspect of this disclosure, an apparatus for controlling a three-level power converter is provided, the apparatus comprising: an acquisition unit configured to acquire an AC side current of the three-level power converter; a determination unit configured to, in response to determining the flow direction of the acquired AC side current and determining a power switch group currently performing level switching, determine a compensation duty cycle for compensating the dead time of the power switch group based on voltage or potential information of the three-level power converter and time information related to the switching operation of the three-level power converter; an adjustment unit configured to adjust the duty cycle of at least one power switch of the power switch group based on the compensation duty cycle; and a transmission unit configured to transmit a signal for controlling at least one power switch based on the adjusted duty cycle.

[0019] In a fourth aspect of this disclosure, a power conversion system is provided, comprising: a three-level power converter; and a control device according to the second aspect, coupled to the three-level power converter.

[0020] The summary section is provided to present the chosen concepts in a simplified form, which will be further described in the detailed description below. The summary section is not intended to identify key or principal features of this disclosure, nor is it intended to limit the scope of this disclosure. Attached Figure Description

[0021] The above and other objects, features and advantages of this disclosure will become more apparent from the accompanying drawings, in which like reference numerals generally denote like parts.

[0022] Figure 1 A schematic circuit diagram of a power conversion system according to an embodiment of the present disclosure is shown.

[0023] Figure 2A and Figure 2B A schematic waveform diagram of the drive signal and desired phase voltage of a power switch for one phase of a three-level power converter without dead time, according to an embodiment of the present disclosure, is shown.

[0024] Figure 3A and Figure 3B A schematic waveform diagram of the drive signal for the power switch of one phase of a three-level power converter with a dead zone is shown according to an embodiment of the present disclosure.

[0025] Figure 4A schematic flowchart of a method for controlling a three-level power converter according to an embodiment of the present disclosure is shown.

[0026] Figure 5A and Figure 5B The switching characteristic curves of the power switch of a three-level power converter according to an embodiment of the present disclosure are shown.

[0027] Figure 6 A schematic circuit diagram is shown of the current flow path of one phase of a three-level power converter with a dead zone according to an embodiment of the present disclosure.

[0028] Figure 7 A schematic waveform diagram of the drive signal, actual phase voltage, desired phase voltage, and voltage error of one phase of a three-level power converter with a dead zone is shown according to an embodiment of the present disclosure.

[0029] Figure 8 A schematic circuit diagram is shown of the current flow path of one phase of a three-level power converter with a dead zone according to an embodiment of the present disclosure.

[0030] Figure 9 A schematic waveform diagram of the drive signal, actual phase voltage, desired phase voltage, and voltage error of one phase of a three-level power converter with a dead zone is shown according to an embodiment of the present disclosure.

[0031] Figure 10 A schematic circuit diagram is shown of the current flow path of one phase of a three-level power converter with a dead zone according to an embodiment of the present disclosure.

[0032] Figure 11 A schematic waveform diagram of the drive signal, actual phase voltage, desired phase voltage, and voltage error of one phase of a three-level power converter with a dead zone is shown according to an embodiment of the present disclosure.

[0033] Figure 12 A schematic circuit diagram is shown of the current flow path of one phase of a three-level power converter with a dead zone according to an embodiment of the present disclosure.

[0034] Figure 13 A schematic waveform diagram of the drive signal, actual phase voltage, desired phase voltage, and voltage error of one phase of a three-level power converter with a dead zone is shown according to an embodiment of the present disclosure.

[0035] Figure 14 A schematic block diagram of a process 1400 for determining a compensation duty cycle according to an embodiment of the present disclosure is shown.

[0036] Figure 15A schematic graph showing the compensation duty cycle versus the phase angle of the phase current before and after linearization near the zero crossing is shown.

[0037] Figure 16A and Figure 16B The waveforms and frequency analysis diagrams of the phase currents before and after dead-zone compensation are shown.

[0038] Figure 17 A schematic block diagram of an apparatus for controlling a power converter according to an embodiment of the present disclosure is shown. Detailed Implementation

[0039] Embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Those skilled in the art can derive alternative technical solutions from the following description without departing from the spirit and scope of the present disclosure.

[0040] The term “comprising” and its variations as used herein signify open inclusion, i.e., “including but not limited to”. Unless otherwise stated, the term “or” means “and / or”. The term “based on” means “at least partially based on”. The term “one embodiment” means “at least one embodiment”. Other explicit and implicit definitions may also be included below.

[0041] As mentioned earlier, power switches in power converters may experience switching delays. For example, if two power switches on the same bridge arm of a power converter are switched on and off in a complementary manner, and one power switch experiences a delay during its turn-off process, the switch that should be turned off may remain on while the other power switch, operating in a complementary manner, is also turned on. This can lead to shoot-through and short circuits caused by multiple power switches connected in series, potentially damaging the power switches and other components in the power converter. To avoid shoot-through and short circuits caused by switching delays, a dead time can be incorporated into the operation of the power switches. For example, a certain dead time period can be added after a power switch is turned off, and another power switch can be turned on only after the dead time period has elapsed to ensure no shoot-through occurs. Although the dead time period is short and only occupies a small portion of the switching cycle, the accumulated voltage error can still lead to increased current distortion and harmonics. When the load is a motor, the dead time can also cause output torque pulsation and increase motor losses. Currently, although some schemes exist to compensate for the dead time, their effectiveness is unsatisfactory. Especially for three-level power converters, currently only a rough compensation can be made for the dead time of the three-level power converter, and it is not possible to accurately eliminate and compensate for the adverse effects caused by the dead time.

[0042] This disclosure provides an improved control scheme for a three-level power converter. In the improved scheme, the current flow path can be determined by identifying the direction of AC current flow and the current level switching method. Furthermore, by combining the voltage or potential information of the three-level power converter with time information related to switching operation, the compensation duty cycle for dead-time compensation can be accurately determined using equivalent voltage, thereby reducing or eliminating output voltage deviations caused by dead-time and thus reducing or eliminating defects such as harmonics, current distortion, and torque pulses. In some embodiments, the neutral point voltage of the three-level power converter can also be acquired in real time. Since the neutral point voltage is prone to drift and is an important state parameter in determining the compensation duty cycle using equivalent voltage, acquiring a more accurate neutral point voltage can effectively improve the accuracy of voltage or potential information, thereby improving the dead-time compensation effect. In some embodiments, the on-time and off-time of the power switch can be determined in real time by acquiring the magnitude of the AC current, and the differences in dead-time characteristics between the internal and external switches can be considered, thus avoiding the influence of current variations and differences between internal and external switches on the compensation accuracy, thereby improving the dead-time compensation effect. In some embodiments, the compensation duty cycle can be linearized near the current zero-crossing point, which can effectively eliminate the step phenomenon that occurs when the current crosses zero, thereby suppressing current harmonics and distortion.

[0043] Figure 1A schematic circuit diagram of a power conversion system 10 according to an embodiment of the present disclosure is shown. Figure 1 As shown, the power conversion system 10 includes a three-level power converter 100. As an example, the three-level power converter 100 may be a three-level three-phase inverter connected to a power source on its DC side and to a load on its AC side, thereby converting DC power from the power source into AC power suitable for driving the load. In one example, the power source may be an energy storage device such as a battery, and the load may be a motor. However, it is understood that the power converter 100 may be other types of power conversion devices, including but not limited to rectifiers, AC-DC-AC converters, etc., the power source supplying the three-level power converter 100 may be any other type of DC power source, and the load driven by the three-level power converter 100 may be other types of loads and electrical equipment.

[0044] The three-level power converter 100 includes a DC-side positive bus 101 and a DC-side negative bus 102 on its DC side, and includes one or more bridge arms connected between the DC-side positive bus 101 and the DC-side negative bus 102. When the three-level power converter 100 is a three-phase converter, it includes three bridge arms, and each bridge arm has a first power switch T1, a second power switch T2, a third power switch T3, and a fourth power switch T4 connected in series between the DC-side positive bus 101 and the DC-side negative bus 102. Power switches can be implemented using, but are not limited to, insulated-gate bipolar transistors (IGBTs), junction field-effect transistors (JFETs), bipolar junction transistors (BJTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), gate-turn-off thyristors (GTOs), MOS-controlled thyristors (MCTs), integrated gate-commutated thyristors (IGCTs), silicon carbide (SiC) switching devices, or gallium nitride (GaN) switching devices. For some or all of the power switches in the three-level power converter 100, anti-parallel freewheeling diodes may be provided. For example, the first power switch T1, the second power switch T2, the third power switch T3, and the fourth power switch T4 can each be equipped with freewheeling diodes D1, D2, D3, and D4, respectively. The anti-parallel freewheeling diodes can be parasitic diodes of the controllable switching device or additional diodes.

[0045] The three-level power converter 100 also includes bus capacitors C1 and C2 connected in series between the DC-side positive bus 101 and the DC-side negative bus 102. A neutral point O is located at the node between bus capacitors C1 and C2 to provide the intermediate level in the three-level configuration. Furthermore, for each of the multiple bridge arms, the three-level power converter 100 is provided with a first clamping diode D5 and a second clamping diode D6. The first clamping diode D5 is coupled at its anode to the neutral point O and at its cathode to the node between the first power switch T1 and the second power switch T2 of the corresponding bridge arm, while the second clamping diode D6 is coupled at its cathode to the neutral point O and at its anode to the node between the third power switch T3 and the fourth power switch T4 of the corresponding bridge arm. A phase line 103 is connected at the node between the second power switch T2 and the third power switch T3 of each bridge arm to transmit the AC voltage V. a V b and V c and alternating current I a I b and I c Apply to the load.

[0046] According to embodiments of this disclosure, the power conversion system 10 further includes a control device 200. The control device 200 is configured to control the three-level power converter 100. For example, the control device 200 may receive sensing information related to the operation of the three-level power converter 100, and control the power switches in the three-level power converter 100 to perform on and off operations based on the received sensing information, thereby achieving the desired power conversion. The control device 200 may be implemented in various ways. For example, the control device 200 may be implemented as a controller with computing and processing capabilities, as a circuit of analog and / or digital circuitry, or as a combination of the above.

[0047] It is understood that the power conversion system 10 may also include other devices or components not shown in the figures. For example, the power conversion system 10 may also include voltage and / or current sensing devices, which may be separate from the power converter 100 and the control device 200, or may be integrated with the power converter 100 or the control device 200 to provide sensing information to the control device 200 to achieve the desired control.

[0048] Figure 2A and Figure 2B The drive signals for the power switches T1, T2, T3, and T4 of phase A of the three-level power converter 100 without dead time, and the desired phase voltage U are shown. AO_REF A schematic waveform diagram. Figure 2A and Figure 2BThe waveform conditions within a single carrier cycle under different modes are described. When the carrier frequency of the three-level power converter 100 is frqSwt, the carrier cycle of the three-level power converter 100 can be expressed as Ts = 1 / frqSwt. In other words, the durations of times t0 to t9 and t0' to t9' are both 1 / frqSwt. For ease of explanation only, the power switches T1 to T4 in the following description are exemplarily described as being turned on under a high-level drive signal and turned off under a low-level drive signal. However, the power switches in the three-level power converter 100 can also be power switches of other trigger types, such as power switches being turned on by a low-level drive signal and turned off by a high-level drive signal, and this disclosure does not limit this.

[0049] exist Figure 2A During the time periods t0 to t9, which have a single carrier cycle, the drive signal for power switch T1 is maintained at a low level suitable for turning off power switch T1 from t0 to t3, at a high level suitable for turning on power switch T1 from t3 to t5, and at a low level suitable for turning off power switch T1 from t5 to t9. The drive signal for power switch T3 is provided in a complementary manner to the drive signal for power switch T1, thereby maintaining a high level suitable for turning on power switch T3 from t0 to t3, a low level suitable for turning off power switch T3 from t3 to t5, and a high level suitable for turning on power switch T3 from t5 to t9. Additionally, the drive signal for power switch T2 is maintained at a high level suitable for turning on power switch T2, while the drive signal for power switch T4 is maintained at a low level suitable for turning off power switch T4. Figure 2A During the carrier cycle shown, when T1 and T2 are on and T3 and T4 are off (e.g., from time t3 to t5), node A between power switches T2 and T3 is directly connected to the DC-side positive bus 101 to ensure that the phase voltage U under ideal conditions is... AO_REF This refers to the voltage between the DC-side positive bus 101 and the neutral point O, i.e., the bus voltage V. DC Half of the phase voltage U is connected to the neutral point O when T2 and T3 are on and T1 and T4 are off (e.g., from time t0 to t3 and from time t5 to t9). AO_REF The value is 0. Therefore, level switching, i.e., phase voltage U, can be achieved by alternately turning power switches T1 and T3 on and off. AO_REF It is expected to be in 0 and 1 / 2*V DC Switching between them, and by controlling the duty cycle of power switch T1, it is expected that U AO_REF The equivalent voltage between times t0 and t9 is controlled to be 0 to 1 / 2*V. DC Any voltage between.

[0050] exist Figure 2B During the time periods t0' to t9' with a single carrier cycle, the drive signal for power switch T2 remains low for turning off power switch T2 from t0' to t3', high for turning on power switch T2 from t3' to t5', and low for turning off power switch T2 from t5' to t9'. The drive signal for power switch T4 is provided complementary to the drive signal for power switch T2; therefore, the drive signal for power switch T4 remains high for turning on power switch T2 from t0' to t3', low for turning off power switch T4 from t3' to t5', and high for turning on power switch T4 from t5' to t9'. Additionally, the drive signal for power switch T3 remains high for turning on power switch T3, while the drive signal for power switch T1 remains low for turning off power switch T1. Figure 2B During the carrier cycle shown, when T2 and T3 are on and T1 and T4 are off (e.g., from time t3' to t5'), node A between power switches T2 and T3 is directly connected to the neutral point O to ensure that the phase voltage U under ideal conditions is... AO_REF The value is 0, and when T3 and T4 are turned on and T1 and T2 are turned off (e.g., from time t0' to t3' and from time t5' to t9'), node A is directly connected to the DC side negative bus 102 to make the phase voltage U under ideal conditions 0. AO_REF This is the voltage between the DC-side negative busbar 102 and the neutral point O, i.e., the negative 1 / 2 busbar voltage V. DC Therefore, level switching, i.e., phase voltage U, can be achieved by alternately turning power switches T2 and T4 on and off. AO_REF The expected value is in -1 / 2*V DC Switching between 0 and 0, and by controlling the duty cycle of power switch T2, it is expected that U AO_REF The equivalent voltage between times t0' and t9' is controlled to be -1 / 2*V. DC Any voltage between 0 and 0.

[0051] Power switches, such as IGBTs, have specific turn-off and turn-on transition times. The turn-off transition time is the time required for the power switch to transition from the on state to the off state after receiving a turn-off drive signal. During this time, although the drive signal has switched to the turn-off level, the power switch is not actually turned off. The turn-on transition time is the time required for the power switch to transition from the off state to the on state after receiving an on drive signal. During this time, although the drive signal has switched to the on level, the power switch is not actually turned on. This transition time may pose a risk of power converter short circuits and damage during operation. For example, as... Figure 2A As shown, at time t3, the drive signal of power switch T1 goes high to turn on power switch T1, and simultaneously the drive signal of power switch T3 goes low to turn off power switch T3. However, the turn-off transition time of power switch T3 causes power switch T3 to remain on after the drive signal goes low, while power switch T1 is turned on. This results in a shoot-through state where power switches T1, T2, and T3 are all on, which causes the DC positive bus 101 to be short-circuited to the neutral point O. Similarly, Figure 2A At time t5, it is also possible that the DC-side positive bus 101 will be short-circuited and connected to the neutral point O. Figure 2B At times t3' and t5', the neutral point O is short-circuited and connected to the DC side negative bus 102. This short circuit may cause excessive current to flow through the power switch and other circuit components, resulting in damage to the power converter.

[0052] Figure 3A and Figure 3B A schematic waveform diagram of the drive signals for the power switches T1, T2, T3, and T4 of phase A of a three-level power converter 100 with a dead time is shown. Similar to... Figure 2A and Figure 2B , Figure 3A and Figure 3B This involves the waveform conditions within a single carrier cycle under different modes, with the durations from t0 to t9 and from t0' to t9' both being the carrier cycle Ts = 1 / frqSwt. Figure 2A and Figure 2B The difference is that, Figure 3A and Figure 3B Deadtimes T1deadoff, T2deadoff, T3deadoff, and T4deadoff are respectively set between the drive signals of power switches T1, T2, T3, and T4. Furthermore, Figure 3A and Figure 3BThe instruction specifies the on-state transition time T1on and off-state transition time T1off for power switch T1, the on-state transition time T3on and off-state transition time T3off for power switch T3, the on-state transition time T2on and off-state transition time T2off for power switch T2, and the on-state transition time T4on and off-state transition time T4off for power switch T4. By setting a dead time period, shoot-through short circuit problems caused by transition time during switch operation can be avoided.

[0053] exist Figure 3A During the time periods t0 to t9, which have a single carrier cycle, the drive signal for power switch T1 remains low (suitable for turning off power switch T1) from t0 to t3, high (suitable for turning on power switch T1) from t3 to t5, and low (suitable for turning off power switch T1) from t5 to t9. Similarly, the drive signal for power switch T3 remains high (suitable for turning on power switch T3) from t0 to t1, low (suitable for turning off power switch T3) from t1 to t7, and high (suitable for turning on power switch T3) from t7 to t9. Furthermore, the drive signal for power switch T2 remains high (suitable for turning on power switch T2), while the drive signal for power switch T4 remains low (suitable for turning off power switch T4).

[0054] It can be seen that the drive signal of power switch T3 transitions from high to low level ahead of time t1, and delays its transition from low to high level at time t7. Therefore, a dead time T3deadoff for turning off power switch T3 is provided between the falling edge of the drive signal of power switch T3 and the rising edge of the drive signal of power switch T1, while a dead time T1deadoff for turning off power switch T1 is provided between the falling edge of the drive signal of power switch T1 and the rising edge of the drive signal of power switch T3. By providing T3deadoff, the drive signal of power switch T1 is ensured to transition from low to high level only after the turn-off transition time T3off of power switch T3 has elapsed, eliminating the possibility of T1, T2, and T3 being turned on simultaneously. Similarly, by providing T1deadoff, the drive signal of power switch T3 is ensured to transition from low to high level only after the turn-off transition time T1off of power switch T1 has elapsed, thereby eliminating the possibility of power switches T1, T2, and T3 being turned on simultaneously.

[0055] exist Figure 3BDuring the time periods t0' to t9' with a single carrier cycle, the drive signal for power switch T2 remains low for turning off power switch T2 from t0' to t3', high for turning on power switch T2 from t3' to t5', and low for turning off power switch T2 from t5' to t9'. The drive signal for power switch T4 remains high for turning on power switch T4 from t0' to t1', low for turning off power switch T4 from t1' to t7', and high for turning on power switch T4 from t7' to t9'. Additionally, the drive signal for power switch T3 remains high for turning on power switch T3, while the drive signal for power switch T1 remains low for turning off power switch T1.

[0056] It can be seen that the drive signal of power switch T4 transitions from high to low level ahead of time t1', and delays its transition from low to high level at time t7'. Therefore, a dead time T4deadoff for turning off power switch T4 is provided between the falling edge of the drive signal of power switch T4 and the rising edge of the drive signal of power switch T2, while a dead time T2deadoff for turning off power switch T2 is provided between the falling edge of the drive signal of power switch T2 and the rising edge of the drive signal of power switch T4. By providing T4deadoff, the drive signal of power switch T2 is ensured to transition from low to high level only after the turn-off transition time T4off of power switch T4 has elapsed, eliminating the possibility of T2, T3, and T4 being turned on simultaneously. Similarly, by providing T2deadoff, the drive signal of power switch T4 is ensured to transition from low to high level only after the turn-off transition time T2off of power switch T2 has elapsed, thereby eliminating the possibility of T2, T3, and T4 being turned on simultaneously.

[0057] By setting dead zones T1deadoff, T2deadoff, T3deadoff, and T4deadoff, short circuits can be prevented from occurring through the power switch, improving the safety of the three-level power converter. However, dead zones also lead to problems such as reduced effective transmission time, low voltage utilization during modulation, current distortion, output torque pulses, and increased harmonics, which may cause instability in load systems such as motors.

[0058] Figure 4 A schematic flowchart of a method 400 for controlling a three-level power converter according to an embodiment of the present disclosure is shown. Method 400 can be performed in... Figure 1 This is implemented in the scenario described above and executed by the control device 200. For the purposes of discussion, references will be made to... Figure 1 , Figure 2A , Figure 2B , Figure 3A and Figure 3B To describe method 400.

[0059] In block 401, control device 200 acquires the AC side current of three-level power converter 100. For example, control device 200 can receive the phase current I of the three-phase AC power converter 100 from a current sensing device. a I b and I c However, the control device 200 can also obtain the AC side current in any other way, for example, by calculating or estimating the phase current I based on electrical quantities related to the phase current. a I b and I c .

[0060] In block 402, in response to determining the direction of flow of the acquired AC side current and determining the power switch group currently performing level switching, the control device 200 determines a compensation duty cycle for compensating the dead time of the power switch group based on the voltage or potential information of the three-level power converter 100 and the timing information related to the switching operation of the three-level power converter 100.

[0061] As an example, the control device 200 can determine the direction of AC current flow based on the acquired AC side current, for example, based on the phase current I. a Is the phase current I determined by whether it is a positive or negative current? a Whether the power flow is from the three-level power converter 100 to the load or from the load to the three-level power converter 100. Furthermore, the control device 200 can determine the power switch group currently performing level switching based on the current control timing, for example, when the phase voltage U... AO It is expected to be in 0 and 1 / 2*V DC When switching between them, the power switch group that performs the level switching is power switch T1 and T3 (e.g., Figure 2A and Figure 3A As shown), when the phase voltage U AO The expected value is in -1 / 2*V DC When switching between 0 and 0, the power switch group that performs the level switching is power switch T2 and T4 (e.g., Figure 2B and Figure 3B (As shown). After determining the current direction and the power switch group that performs level switching, the control device 200 can determine or calculate the actual equivalent output voltage in the current time period, thereby determining the desired voltage (e.g., U). AO_REF ) and the current actual voltage (e.g., U) AO The error is calculated based on the error. Therefore, the control device 200 can determine the compensation duty cycle based on the error.

[0062] In block 403, control device 200 adjusts the duty cycle of at least one power switch in the power switch group based on a compensation duty cycle. As an example, control device 200 can increase or decrease the duty cycle of the corresponding power switch by using a compensation duty cycle. For instance, if the actual equivalent output voltage from time t0 to t9 is less than the desired voltage, control device 200 can increase the on-state duty cycle of power switch T1, or adjust the duty cycles of both power switches T1 and T3, thereby increasing the actual output voltage from time t0 to t9 to approach or reach the desired voltage.

[0063] In block 404, control device 200 sends a signal for controlling at least one power switch based on an adjusted duty cycle. For example, for times t0 to t9, control device 200 can add a compensation duty cycle to the original duty cycle of power switch T1 to adjust the duty cycle and output voltage, thereby reducing or eliminating voltage errors and other defects caused by dead time.

[0064] In some embodiments of this disclosure, method 400 further includes acquiring the neutral point voltage of the three-level power converter 100, which includes at least one of the voltage between neutral point O and the DC-side positive bus 101 and the voltage between neutral point O and the DC-side negative bus 102. The voltage or potential information used to determine the compensation duty cycle includes the acquired neutral point voltage. Specifically, the potential at neutral point O in the three-level power converter 100 provides the middle level of the three levels, and the potential at the neutral point is prone to fluctuations or drifts due to the charging and discharging of bus capacitors C1 and C2. Such fluctuations or drifts in the neutral point voltage can lead to deviations in the determination of the equivalent output voltage during the determination of the compensation duty cycle using voltage or level information and time information, thereby affecting the determination of the compensation duty cycle and dead-time compensation. By acquiring the voltage between neutral point O and either the positive bus 101 or the negative bus 102, the state of the neutral point voltage can be determined in real time, which significantly improves the voltage information used to determine the compensation duty cycle, thereby improving the accuracy of dead-time compensation.

[0065] In some embodiments of this disclosure, method 400 further includes determining the turn-on transition time and turn-off transition time of at least one power switch in the power switch group based on the magnitude of the acquired AC side current. Studies have shown that the turn-on transition time and turn-off transition time of the power switch are strongly correlated with the phase current of the three-level power converter. In other words, the turn-on transition time and turn-off transition time of the power switch are primarily affected by the current. For example, due to the presence of cooling water and the maximum protection temperature of the switching transistor (e.g., the maximum IGBT protection temperature does not exceed 150°C), in obtaining the transition times (e.g., T1on, T1off) of the power switch, it is only necessary to set a relationship curve between the transition time and the current without considering other factors. This relationship curve can be obtained by referencing the three-phase current curve (e.g., the characteristic curve of the switching transistor) and modifying it according to the actual situation. Therefore, after determining the current magnitude, the turn-on transition time and turn-off transition time of the corresponding power switch can be determined by querying the set relationship curve.

[0066] In some embodiments of this disclosure, the timing information used to determine the compensation duty cycle includes the turn-on transition duration and the turn-off transition duration. During the determination of the compensation duty cycle using voltage or level information and timing information, changes in the turn-on transition duration and turn-off transition duration relative to the current affect the accuracy of the timing information, leading to deviations between the determination of the actual output voltage and the determination of the compensation duty cycle. Therefore, the magnitude of the current flowing through the corresponding power switch can be determined by sensing or otherwise acquiring the magnitude of the AC side current, and the turn-on transition duration and turn-off transition duration corresponding to the current can be further determined based on, for example, the correspondence indicated by a transition duration-time curve. By determining accurate turn-on transition duration and turn-off transition duration based on the acquired AC side current, the accuracy of the timing information can be significantly improved, thereby improving the effect of dead-time compensation.

[0067] Figure 5A The switching characteristic curves of power switches T1 and T4 are shown, and Figure 5BThe switching characteristic curves of power switches T2 and T3 are shown. In some embodiments, the turn-on transition time and turn-off transition time of the power switch adjacent to the DC-side positive bus 101 or DC-side negative bus 102 are different from those of the power switch not adjacent to the DC-side positive bus 101 or DC-side negative bus 102. Specifically, in a three-level power converter, the power switch adjacent to the DC-side positive bus 101 or DC-side negative bus 102 can also be referred to as the external switch, while the power switch not adjacent to the DC-side positive bus 101 or DC-side negative bus 102 can also be referred to as the internal switch. External and internal switches generally have different switching characteristics because external switches (e.g., power switches T1 and T4) remain in the off state for a longer period and undergo more frequent turn-on and turn-off operations, while internal switches (e.g., power switches T2 and T3) remain in the on state for a longer period. Therefore, external switches are selected for lower switching losses and the ability to withstand higher turn-off voltages, while internal switches are selected for lower conduction losses. When determining the compensation duty cycle, the different switching characteristics of the external and internal switches need to be considered. For example, in... Figure 5A The characteristic curves of the external switch shown include the curves showing the changes in the turn-on and turn-off transition times of the external switch relative to the current. These curves can be directly used, or appropriately modified according to actual conditions, to obtain the fitting curves for the turn-on and turn-off times of the external switch. Similarly, in Figure 5B The characteristic curves of the internal switching transistors shown include the curves showing the changes in the turn-on and turn-off transition times of the internal switching transistors relative to the current. These curves can be directly used, or appropriately modified according to actual conditions, to obtain the fitted curves for the turn-on and turn-off times of the internal switching transistors. By inputting the current phase current into a function or table based on the fitted curves of the external switching transistors, the turn-on and turn-off transition times of power switches T1 and T4 (acting as external switching transistors) can be obtained. Similarly, by inputting the current phase current into a function or table based on the fitted curves of the internal switching transistors, the turn-on and turn-off transition times of power switches T2 and T3 (acting as internal switching transistors) can be obtained. Therefore, the switching transition times of power switches T1, T2, T3, and T4 can be determined more accurately, thus obtaining accurate timing information for determining the compensation duty cycle.

[0068] In some embodiments, the dead time for a given power switch is greater than or equal to the maximum turn-off transition time of that power switch. For example, the dead time for power switch T1 can be set to be greater than or equal to the maximum turn-off transition time of power switch T1 under all phase current magnitudes. This ensures that the dead time covers all possible turn-off transition times of power switch T1, thereby preventing shoot-through of multiple power switches. The dead times of power switches T2, T3, and T4 can be obtained in the same manner. Considering the difference between internal and external switches, power switch T4, as an external switch, can have the same dead time as power switch T1, while power switches T2 and T3, as internal switches, have different dead times than power switch T1. Furthermore, since the dead time of each power switch is greater than or equal to the maximum turn-off transition time of each power switch, the dead time of each power switch generally does not fluctuate with current or other factors, thus allowing it to be set or calibrated in advance before the power converter begins operation.

[0069] The following will be referenced Figures 6 to 13 A more detailed process for determining the compensated duty cycle according to embodiments of the present disclosure is described in illustrative terms. Figures 6 to 13 The description takes phase A of the three-level power converter 100 as an example, but it is understood that the described process is also applicable to other phases (such as phases B and C) or power converters with other numbers of phases (such as single-phase power converters).

[0070] Figure 6 , Figure 8 , Figure 10 and Figure 12 A schematic circuit diagram showing the current flow path of phase A of a three-level power converter 100 with a dead zone is provided. Figure 7 , Figure 9 , Figure 11 and Figure 13 A schematic waveform diagram showing the drive signal, actual phase voltage, desired phase voltage, and voltage error of phase A of a three-level power converter 100 with a dead zone is shown.

[0071] Figure 6 and Figure 7 This involves level switching performed by power switches T1 and T3 (i.e., power switches T1 and T3 generate waveforms) and phase current I a This refers to the situation during a single carrier cycle of forward current (i.e., current flowing from the three-level power converter 100 to the load). Compared to Figure 3A , Figure 6 and Figure 7 The changes in the current flow path and the output voltage are described in more detail.

[0072] like Figure 6 and Figure 7 As shown, during the period t0~t1~t2, power switches T2 and T3 are in the ON state, and power switches T1 and T4 are in the OFF state. Specifically, from t0 to t1, the drive signals for power switches T2 and T3 are high; and from t1 to t2, the drive signal for power switch T2 is high, and although the drive signal for power switch T3 is low, power switch T3 is in a transitional off state and is not turned off. Therefore, during the period t0~t1~t2, power switches T2 and T3 are actually always ON, and the current path of phase A flows from neutral point O through the first clamping diode D5, power switch T2, and node A to the load. During the period t0~t1~t2, the actual output phase voltage U AO The formula is -Ud5-Ut2, where Ud5 is the forward voltage drop of the first clamping diode D5, and Ut2 is the forward voltage drop of the power switch T2.

[0073] During the period from t2 to t3 to t4, power switch T2 is in the ON state, while power switches T1, T3, and T4 are in the OFF state. Specifically, from t2 to t3, only the drive signal of power switch T2 is high; and from t3 to t4, the drive signal of power switch T2 is high, and although the drive signal of power switch T1 is high, power switch T1 is in a transitional state and not ON. Therefore, during the period from t2 to t3 to t4, only power switch T2 is actually always ON, and the current path of phase A still flows from neutral point O through the first clamping diode D5, power switch T2, and node A to the load. During the period from t2 to t3 to t4, the actual output phase voltage U... AO It remains -Ud5-Ut2, where Ud5 is the forward voltage drop of the first clamping diode D5, and Ut2 is the forward voltage drop of the power switch T2.

[0074] During the period t4 to t5 to t6, power switches T1 and T2 are in the ON state, while power switches T3 and T4 are in the OFF state. Specifically, from t4 to t5, the drive signals for power switches T1 and T2 are high; and from t5 to t6, the drive signal for power switch T2 is high, and although the drive signal for power switch T1 is low, power switch T1 is in a transitional off state and is not actually turned off. Therefore, during the period t4 to t5 to t6, power switches T1 and T2 are actually always ON, and the current path of phase A flows from the DC positive bus 101 through power switches T1, T2, and node A to the load. During the period t4 to t5 to t6, the actual output phase voltage U... AOThe formula is Vdc-Unp-Ut1-Ut2, where Vdc is the bus voltage between the DC positive bus 101 and the DC negative bus 102, Unp is the voltage between the neutral point O and the DC negative bus 102 (also known as the neutral point voltage), Ut1 is the on-state voltage drop of power switch T1, and Ut2 is the on-state voltage drop of power switch T2.

[0075] Current path and actual output phase voltage U during t6~t7~t8 AO The current path and the actual output phase voltage U during t2~t3~t4 are the same, and the current path during t8~t9 are the same. AO The same applies to t0~t1~t2, so it will not be repeated here.

[0076] After setting the dead time, waveforms are generated at power switches T1 and T3 and the phase current I... a Under the condition of positive current, the actual output phase voltage U during the period from t0 to t9 AO The equivalent voltage U AO_DEAD This can be expressed as the following equation:

[0077] U AO_DEAD =(T1duty-T1on+T1off)*(Vdc-Unp-Ut1-Ut2)+(Ts-T1duty

[0078] +T1on-T1off)*(-Ud5-Ut2) (1)

[0080] Where T1duty is the duration of the high-level drive signal of power switch T1, T1on is the turn-on transition duration of power switch T1, T1off is the turn-off transition duration of power switch T1, Vdc is the bus voltage between the DC positive bus 101 and the DC negative bus 102, Unp is the voltage between the neutral point O and the DC negative bus 102, Ut1 is the on-state voltage drop of power switch T1, Ut2 is the on-state voltage drop of power switch T2, Ts is the carrier period, and Ud5 is the on-state voltage drop of the first clamping diode D5.

[0081] In addition, the expected output phase voltage U during the period from t0 to t9 AO The equivalent voltage U AO_REF This can be expressed as the following equation:

[0082] U AO_REF =T1duty*(1 / 2*Vdc-0) (2)

[0083] Therefore, the voltage error U between the expected output phase voltage and the actual output phase voltage AO_ERR This can be expressed as the following equation:

[0084] UAO_ERR = U AO_REF -U AO_DEAD (3)

[0085] Furthermore, after setting the dead time, waveforms are generated at power switches T1 and T3 and the phase current I... a When the current is positive, the compensation duty cycle Dcom can be expressed as the following equation:

[0086] Dcom = U AO_ERR / (Vdc-Unp-Ut1-Ut2-(-Ud5-Ut2)) / Ts (4)

[0087] Based on equations (1) to (4), the compensation duty cycle Dcom can be obtained through the following equation:

[0088] Dcom=DutyCycleT1*1 / 2*Vdc / (Vdc-Unp-Ut1-Ut2-(-Ud5-Ut2))-

[0089] (T1duty-T1on+T1off)*(Vdc-Unp-Ut1-Ut2) / (Vdc-Unp-Ut1-Ut2

[0090] -(-Ud5-Ut2)) / Ts-(-Ud5-Ut2)*(Ts-T1duty+T1on-T1off) / (Vdc-

[0091] Unp-Ut1-Ut2-(-Ud5-Ut2)) / Ts (5)

[0093] Where DutyCycleT1 is the original duty cycle of power switch T1. Therefore, according to the equivalent voltage method, by superimposing the compensation duty cycle Dcom onto the original duty cycle DutyCycleT1 of power switch T1, the voltage error can be reduced or eliminated, thereby compensating for the dead zone.

[0094] Figure 8 and Figure 9 This involves level switching performed by power switches T1 and T3 (i.e., power switches T1 and T3 generate waveforms) and phase current I a This refers to the situation during a single carrier cycle with negative current (i.e., current flowing from the load to the level-to-power converter 100). Compared to Figure 3A , Figure 8 and Figure 9 The changes in the current flow path and the output voltage are described in more detail.

[0095] like Figure 8 and Figure 9As shown, during the period t0~t1~t2, power switches T2 and T3 are in the ON state, and power switches T1 and T4 are in the OFF state. Specifically, from t0 to t1, the drive signals for power switches T2 and T3 are high; and from t1 to t2, the drive signal for power switch T2 is high, and although the drive signal for power switch T3 is low, power switch T3 is in a transitional off state and is not turned off. Therefore, during the period t0~t1~t2, power switches T2 and T3 are actually always ON, and the current path of phase A flows from the load through node A, power switch T3, and the second clamping diode D6 to the neutral point O. During the period t0~t1~t2, the actual output phase voltage U AO Let Ud6+Ut3 be the forward voltage drop of the second clamping diode D6, and Ut3 be the forward voltage drop of the power switch T3.

[0096] During the period from t2 to t3 to t4, power switch T2 is in the ON state, while power switches T1, T3, and T4 are in the OFF state. Specifically, from t2 to t3, only the drive signal of power switch T2 is high; and from t3 to t4, the drive signal of power switch T2 is high, and although the drive signal of power switch T1 is high, power switch T1 is in a transitional state and not ON. Therefore, during the period from t2 to t3 to t4, only power switch T2 is actually always ON, and the current path of phase A flows from the load through node A, the freewheeling diode D1 of power switches T2 and T1 to the DC positive bus 101. During the period from t2 to t3 to t4, the actual output phase voltage U AO It is Vdc-Unp+Ud_t1+Ut2, where Vdc is the bus voltage between the DC positive bus 101 and the DC negative bus 102, Unp is the voltage between the neutral point O and the DC negative bus 102, Ud_t1 is the forward voltage drop of the freewheeling diode D1 of power switch T1, and Ut2 is the forward voltage drop of power switch T2.

[0097] During the period from t4 to t5 to t6, power switches T1 and T2 are in the ON state, while power switches T3 and T4 are in the OFF state. Specifically, from t4 to t5, the drive signals for power switches T1 and T2 are high; and from t5 to t6, the drive signal for power switch T2 is high, and although the drive signal for power switch T1 is low, power switch T1 is in a transitional off state and is not actually turned off. Therefore, during the period from t4 to t5 to t6, power switches T1 and T2 are actually always ON, and the current path of phase A flows from the load through node A, power switch T2, and power switch T1 to the DC positive bus 101. During the period from t4 to t5 to t6, the actual output phase voltage U... AOThe formula is Vdc-Unp+Ut1+Ut2, where Vdc is the bus voltage between the DC positive bus 101 and the DC negative bus 102, Unp is the voltage between the neutral point O and the DC negative bus 102 (also known as the neutral point voltage), Ut1 is the on-state voltage drop of power switch T1, and Ut2 is the on-state voltage drop of power switch T2.

[0098] Current path and actual output phase voltage U during t6~t7~t8 AO The current path and the actual output phase voltage U during t2~t3~t4 are the same, and the current path during t8~t9 are the same. AO The same applies to t0~t1~t2, so it will not be repeated here.

[0099] After setting the dead time, waveforms are generated at power switches T1 and T3 and the phase current I... a When the current is negative, the actual output phase voltage U during the period from t0 to t9 AO The equivalent voltage U AO_DEAD This can be expressed as the following equation:

[0100] U AO_DEAD =(T1duty-T1on+T1off)*(Vdc-Unp+Ut1+Ut2)+

[0101] (T3deadoff-T3off+T1on+T1deadoff-T1off+T3on)*(Vdc-Unp+

[0102] Ud_t1+Ut2)+(Ts-T1duty-T1deadoff-T3on-(T3deadoff-T3off))*

[0103] (Ud6+Ut3) (6)

[0105] Where T1duty is the duration of the high-level drive signal of power switch T1, T1on is the turn-on transition duration of power switch T1, T1off is the turn-off transition duration of power switch T1, Vdc is the bus voltage between the DC positive bus 101 and the DC negative bus 102, Unp is the voltage between the neutral point O and the DC negative bus 102, Ut1 is the on-state voltage drop of power switch T1, Ut2 is the on-state voltage drop of power switch T2, and T3dead... T1deadoff is the preset theoretical dead time for power switch T3, T3off is the turn-off transition time of power switch T3, T1deadoff is the preset theoretical dead time for power switch T1, T3on is the turn-on transition time of power switch T3, Ud_t1 is the forward voltage drop of the freewheeling diode D1 of power switch T1, Ts is the carrier period, Ud6 is the forward voltage drop of the second clamping diode D6, and Ut3 is the forward voltage drop of power switch T3.

[0106] In addition, the expected output phase voltage U during the period from t0 to t9 AO The equivalent voltage U AO_REF Similarly, it can be expressed by equation (2).

[0107] Therefore, the voltage error U between the expected output phase voltage and the actual output phase voltage AO_ERR Similarly, it can be expressed by equation (3).

[0108] Furthermore, after setting the dead time, waveforms are generated at power switches T1 and T3 and the phase current I... a When the current is negative, the compensation duty cycle Dcom can be expressed as the following equation:

[0109] Dcom = U AO_ERR / (Vdc-Unp+Ut1+Ut2-(Ud6+Ut3)) / Ts (7)

[0110] Based on equations (2), (3), (6) and (7), the compensation duty cycle Dcom can be obtained through the following equation:

[0111] Dcom=DutyCycleT1*1 / 2Vdc / (Vdc-Unp+Ut1+Ut2-(Ud6+Ut3))-

[0112] (T1duty-T1on+T1off)*(Vdc-Unp+Ut1+Ut2) / (Vdc-Unp+Ut1+Ut2-(

[0113] Ud6+Ut3)) / Ts-(T3deadoff-T3off+T1on+T1deadoff-T1off+T3on)*(

[0114] Vdc-Unp+Ud_t1+Ut2) / (Vdc-Unp+Ut1+Ut2-(Ud6+Ut3)) / Ts-(Ts-

[0115] T1duty-T1deadoff-T3on-(T3deadoff-T3off))*(Ud6+Ut3) / (Vdc-

[0116] Unp+Ut1+Ut2-(Ud6+Ut3)) / Ts (8)

[0118] Where DutyCycleT1 is the original duty cycle of power switch T1. Therefore, according to the equivalent voltage method, by superimposing the compensation duty cycle Dcom onto the original duty cycle DutyCycleT1 of power switch T1, the voltage error can be reduced or eliminated, thereby compensating for the dead zone.

[0119] Figure 10 and Figure 11 This involves level switching performed by power switches T2 and T4 (i.e., power switches T2 and T4 generate waveforms) and phase current I a This refers to the situation during a single carrier cycle of forward current (i.e., current flowing from the level-to-power converter 100 to the load). Compared to Figure 3B , Figure 10 and Figure 11 The changes in the current flow path and the output voltage are described in more detail.

[0120] like Figure 10 and Figure 11 As shown, during the period t0'~t1'~t2', power switches T3 and T4 are in the ON state, and power switches T1 and T2 are in the OFF state. Specifically, from t0' to t1', the drive signals for power switches T3 and T4 are high; and from t1' to t2', the drive signal for power switch T3 is high, and although the drive signal for power switch T4 is low, power switch T4 is in a transitional off state and is not turned off. Therefore, during the period t0'~t1'~t2', power switches T3 and T4 are actually always ON, and the current path of phase A flows from the DC side negative bus 102 through power switch T4, power switch T3, and node A to the load. During the period t0'~t1'~t2', the actual output phase voltage U AO The formula is -Ut4-Ut3-Unp, where Ut4 is the on-state voltage drop of power switch T4, Ut3 is the on-state voltage drop of power switch T3, and Unp is the voltage between neutral point O and DC side negative bus 102.

[0121] During the period t2'~t3'~t4', power switch T3 is in the ON state, while power switches T1, T2, and T4 are in the OFF state. Specifically, from t2' to t3', only the drive signal of power switch T3 is high; and from t3' to t4', the drive signal of power switch T3 is high, and although the drive signal of power switch T2 is high, power switch T2 is in a transitional state and not ON. Therefore, during the period t2'~t3'~t4', only power switch T3 is actually always ON, and the current path of phase A flows from the DC side negative bus 102 through the freewheeling diode D4 of power switch T4, power switch T3, and node A to the load. During the period t2'~t3'~t4', the actual output phase voltage U AO It is -Ud_t4-Ut3-Unp, where Ud_t4 is the forward voltage drop of the freewheeling diode D4 of power switch T4, Ut3 is the forward voltage drop of power switch T3, and Unp is the voltage between neutral point O and DC side negative bus 102.

[0122] During the period t4'~t5'~t6', power switches T2 and T3 are in the ON state, and power switches T1 and T4 are in the OFF state. Specifically, from t4' to t5', the drive signals for power switches T2 and T3 are high; and from t5' to t6', the drive signal for power switch T3 is high, and although the drive signal for power switch T2 is low, power switch T2 is in a transitional off state and is not turned off. Therefore, during the period t4'~t5'~t6', power switches T2 and T3 are actually always ON, and the current path of phase A flows from neutral point O through the first clamping diode D5, power switch T2, and node A to the load. During the period t4'~t5'~t6', the actual output phase voltage U AO The formula is -Ud5-Ut2, where Ud5 is the forward voltage drop of the first clamping diode D5, and Ut2 is the forward voltage drop of the power switch T2.

[0123] Current path and actual output phase voltage U during t6'~t7'~t8' AO The current path and the actual output phase voltage U during t2'~t3'~t4' are the same, and the current path during t8'~t9' is the same. AO The same as t0'~t1'~t2', so it will not be described again.

[0124] After setting the dead time, waveforms are generated at power switches T2 and T4 and the phase current I... a Under the condition of positive current, the actual output phase voltage U during the period from t0' to t9' AO The equivalent voltage U AO_DEAD This can be expressed as the following equation:

[0125] U AO_DEAD =(T2duty-T2on+T2off)*(-Ud5-Ut2)+

[0126] (T4deadoff-T4off+T2on+T2deadoff-T2off+T4on)*(-Ud_t4-

[0127] Ut3-Unp)+(Ts-T2duty-T2deadoff-T4on-(T4deadoff-T4off))*

[0128] (-Ut4-Ut3-Unp) (9)

[0130] Where T2duty is the duration of the high-level drive signal of power switch T2, T2on is the turn-on transition duration of power switch T2, T2off is the turn-off transition duration of power switch T2, Ud5 is the on-state voltage drop of the first clamping diode D5, Ut2 is the on-state voltage drop of power switch T2, T4deadoff is the preset theoretical dead time for power switch T4, T4off is the turn-off transition duration of power switch T4, T2deadoff is the preset theoretical dead time for power switch T2, T4on is the turn-on transition duration of power switch T4, Ud_t4 is the on-state voltage drop of the freewheeling diode D4 of power switch T4, Ut3 is the on-state voltage drop of power switch T3, Unp is the voltage between neutral point O and DC side negative bus 102, Ts is the carrier period, and Ut4 is the on-state voltage drop of power switch T4.

[0131] Furthermore, the expected output phase voltage U during the period from t0' to t9' AO The equivalent voltage U AO_REF This can be expressed as the following equation:

[0132] U AO_REF =(Ts-T2duty)*(0-1 / 2Vdc) (10)

[0133] Therefore, the voltage error U between the expected output phase voltage and the actual output phase voltage AO_ERR It can also be expressed by equation (3).

[0134] Furthermore, after setting the dead time, waveforms are generated at power switches T2 and T4, and the phase current I... a When the current is positive, the compensation duty cycle Dcom can be expressed as the following equation:

[0135] Dcom = U AO_ERR / (-Ud5-Ut2-(-Ut4-Ut3-Unp)) / Ts (11)

[0136] Based on equations (3), (9), (10) and (11), the compensation duty cycle Dcom can be obtained through the following equation:

[0137] Dcom=(1-DutyCycleT2)*(-1 / 2Vdc) / (-Ud5-Ut2-(-Ut4-Ut3-Unp))-

[0138] (T2duty-T2on+T2off)*(-Ud5-Ut2) / (-Ud5-Ut2-(-Ut4-Ut3-Unp)) / Ts

[0139] -(T4deadoff-T4off+T2on+T2deadoff-T2off+T4on)*(-Ud_t4-Ut3-

[0140] Unp) / (-Ud5-Ut2-(-Ut4-Ut3-Unp)) / Ts-(Ts-T2duty-T2deadoff-T4on

[0141] -(T4deadoff-T4off))*(-Ut4-Ut3-Unp) / (-Ud5-Ut2-(-Ut4-Ut3-Unp)) /

[0142] Ts (12)

[0144] Where DutyCycleT2 is the original duty cycle of power switch T2. Therefore, according to the equivalent voltage method, by superimposing the compensation duty cycle Dcom onto the original duty cycle DutyCycleT2 of power switch T2, voltage error can be reduced or eliminated, thereby compensating for dead time.

[0145] Figure 12 and Figure 13 This involves level switching performed by power switches T2 and T4 (i.e., power switches T2 and T4 generate waveforms) and phase current I a This refers to the situation during a single carrier cycle with negative current (i.e., current flowing from the level power converter 100 to the load). Compared to Figure 3B , Figure 12 and Figure 13 The changes in the current flow path and the output voltage are described in more detail.

[0146] like Figure 12 and Figure 13As shown, during the period t0'~t1'~t2', power switches T3 and T4 are in the ON state, and power switches T1 and T2 are in the OFF state. Specifically, from t0' to t1', the drive signals for power switches T3 and T4 are high; and from t1' to t2', the drive signal for power switch T3 is high, and although the drive signal for power switch T4 is low, power switch T4 is in a transitional off state and is not turned off. Therefore, during the period t0'~t1'~t2', power switches T3 and T4 are actually always ON, and the current path of phase A flows from the load through node A, power switch T3, and power switch T4 to the DC side negative bus 102. During the period t0'~t1'~t2', the actual output phase voltage U AO The formula is Ut3+Ut4-Unp, where Ut3 is the on-state voltage drop of power switch T3, Ut4 is the on-state voltage drop of power switch T4, and Unp is the voltage between neutral point O and DC side negative bus 102.

[0147] During the period t2'~t3'~t4', power switch T3 is in the ON state, while power switches T1, T2, and T4 are in the OFF state. Specifically, from t2' to t3', only the drive signal of power switch T3 is high; and from t3' to t4', the drive signal of power switch T3 is high, and although the drive signal of power switch T2 is high, power switch T2 is in a transitional state and not ON. Therefore, during the period t2'~t3'~t4', only power switch T3 is actually always ON, and the current path of phase A flows from the load through node A, power switch T3, and the second clamping diode D6 to the neutral point O. During the period t2'~t3'~t4', the actual output phase voltage U AO It is Ud6+Ut3, where Ud6 is the forward voltage drop of the second clamping diode D6, and Ut3 is the forward voltage drop of the power switch T3.

[0148] During the period t4'~t5'~t6', power switches T2 and T3 are in the ON state, and power switches T1 and T4 are in the OFF state. Specifically, from t4' to t5', the drive signals for power switches T2 and T3 are high; and from t5' to t6', the drive signal for power switch T3 is high, and although the drive signal for power switch T2 is low, power switch T2 is in a transitional off state and is not turned off. Therefore, during the period t4'~t5'~t6', power switches T2 and T3 are actually always ON, and the current path of phase A flows from the load through node A, power switch T3, and the second clamping diode D6 to the neutral point O. During the period t4'~t5'~t6', the actual output phase voltage U AOIt is Ud6+Ut3, where Ud6 is the forward voltage drop of the second clamping diode D6, and Ut3 is the forward voltage drop of the power switch T3.

[0149] Current path and actual output phase voltage U during t6'~t7'~t8' AO The current path and the actual output phase voltage U during t2'~t3'~t4' are the same, and the current path during t8'~t9' is the same. AO The same as t0'~t1'~t2', so it will not be described again.

[0150] After setting the dead time, waveforms are generated at power switches T2 and T4 and the phase current I... a When the current is negative, the actual output phase voltage U during the period from t0' to t9' AO The equivalent voltage U AO_DEAD This can be expressed as the following equation:

[0151] U AO_DEAD =(T2duty+T2deadoff+T4on+T4deadoff-T4off)*(Ud6+

[0152] Ut3)+(Ts-T2duty-T2deadoff-T4on-(T4deadoff-T4off))*(Ut3+

[0153] Ut4-Unp) (13)

[0155] Where T2duty is the duration of the high-level drive signal of power switch T2, T2deadoff is the preset theoretical dead time for power switch T2, T4on is the turn-on transition time of power switch T4, T4deadoff is the preset theoretical dead time for power switch T4, T4off is the turn-off transition time of power switch T4, Ud6 is the forward voltage drop of the second clamping diode D6, Ut3 is the forward voltage drop of power switch T3, Ts is the carrier period, Ut4 is the forward voltage drop of power switch T4, and Unp is the voltage between neutral point O and DC side negative bus 102.

[0156] Furthermore, the expected output phase voltage U during the period from t0' to t9' AO The equivalent voltage U AO_REF It can be represented by equation (10).

[0157] Therefore, the voltage error U between the expected output phase voltage and the actual output phase voltage AO_ERR It can be represented by equation (3).

[0158] Furthermore, after setting the dead time, waveforms are generated at power switches T2 and T4, and the phase current I... a When the current is negative, the compensation duty cycle Dcom can be expressed as the following equation:

[0159] Dcom = U AO_ERR / (Ud6+Ut3-(Ut3+Ut4-Unp)) / Ts (14)

[0160] Based on equations (3), (10), (13) and (14), the compensation duty cycle Dcom can be obtained through the following equation:

[0161] Dcom=(1-DutyCycleT2)*(-1 / 2Vdc) / (Ud6+Ut3-(Ut3+Ut4-Unp))-

[0162] (T2duty+T2deadoff+T4on+T4deadoff-T4off)*(Ud6+Ut3) / (Ud6+

[0163] Ut3-(Ut3+Ut4-Unp)) / Ts-(Ts-T2duty-T2deadoff-T4on-(T4deadoff-

[0164] T4off))*(Ut3+Ut4-Unp) / (Ud6+Ut3-(Ut3+Ut4-Unp)) / Ts (15)

[0166] Where DutyCycleT2 is the original duty cycle of power switch T2. Therefore, according to the equivalent voltage method, by superimposing the compensation duty cycle Dcom onto the original duty cycle DutyCycleT2 of power switch T2, voltage error can be reduced or eliminated, thereby compensating for dead time.

[0167] It is understandable that, although the compensation duty cycle was determined above for different power switch groups and different current directions using equations (5), (8), (12) and (15), some voltage and time parameters can be added, omitted or replaced in the calculation process as needed, for example, to simplify the calculation and processing process or to further improve the compensation accuracy.

[0168] Figure 14 A schematic block diagram of a process 1400 for determining a compensation duty cycle in some embodiments of this disclosure is shown. Process 1400 may be implemented in block 402.

[0169] In block 1401, when the deviation between the phase angle of the acquired AC side current and the zero-crossing point exceeds a predetermined threshold and the AC side current flows out of the three-level power converter 100, the control device 200 calculates the difference between the expected output voltage and the actual output voltage of the three-level power converter 100 on the AC side based on voltage or potential information and time information, and determines a first compensation value as the compensation duty cycle Dcom based on the calculated difference. As an example, when the phase current I... a When the current is positive (i.e., the direction of the outflow from the three-level power converter 100) and power switches T1 and T3 are emitting waves, the control device 200 can determine the compensation duty cycle Dcom based on equation (5), while when the phase current I a When the three-level power converter 100 is positive (i.e., the direction of the outflow of power switches T2 and T4), the control device 200 can determine the compensation duty cycle Dcom based on equation (12).

[0170] In block 1402, if the deviation between the phase angle of the acquired AC side current and the zero-crossing point exceeds a predetermined threshold and the AC side current flows into the three-level power converter 100, the control device 200 calculates the difference between the expected output voltage and the actual output voltage of the three-level power converter 100 on the AC side based on voltage or potential information and time information, and determines a second compensation value as the compensation duty cycle Dcom based on the calculated difference. As an example, when the phase current I... a When the current is negative (i.e., the direction flowing into the three-level power converter 100) and power switches T1 and T3 are emitting waves, the control device 200 can determine the compensation duty cycle Dcom based on equation (8), while when the phase current I a When the signal is negative (i.e., the direction of the input to the three-level power converter 100) and power switches T2 and T4 are emitting waves, the control device 200 can determine the compensation duty cycle Dcom based on equation (15).

[0171] In block 1403, when the deviation between the phase angle of the acquired AC side current and the zero-crossing point is lower than a predetermined threshold, the control device 200 determines the compensation duty cycle through linear interpolation between the first compensation value and the second compensation value. Specifically, during the process of the three-level power converter 100 driving a load such as a motor, the phase current may change from positive to negative or from negative to positive, and during this change, different compensation duty cycles Dcom will be obtained based on different compensation calculation methods (e.g., equations (5), (8), (12), and (15)). As a result, the compensation duty cycle Dcom and the adjusted duty cycle will jump during the positive and negative changes of the phase current. By setting a predetermined threshold and linearizing the compensation duty cycle Dcom when the phase angle is lower than the predetermined threshold, the jump phenomenon that may occur when the phase current crosses zero can be avoided.

[0172] Figure 15 A schematic graph showing the compensation duty cycle versus the phase angle of the phase current before and after linearization at the zero crossing point is presented. Figure 15 The horizontal axis represents the phase angle of the phase current (or the actual angle of the motor load) θe, and the vertical axis represents the compensation duty cycle Dcom. Figure 15 In the upper curve of the graph, linearization is not performed at the zero-crossing point of the phase current. Therefore, when the phase current crosses zero, the compensation duty cycle Dcom changes abruptly from Dcom+ (for positive phase current) to Dcom- (for negative phase current). Figure 15 In the curve below, linearization is performed at the zero-crossing point of the phase current. Thus, outside the calibration range of the predetermined threshold Δθ near the zero-crossing point, the compensation duty cycle Dcom remains Dcom+ or Dcom-. However, within the calibration range of the predetermined threshold Δθ near the zero-crossing point, the compensation duty cycle Dcom gradually changes linearly from Dcom+ to Dcom-, thereby eliminating the step jump problem that may occur in the compensation duty cycle at the zero-crossing point of the phase current.

[0173] Figure 16A and Figure 16B The phase current I is shown before and after dead-time compensation. a The waveform and frequency analysis diagram. For example... Figure 16A and Figure 16B As shown, before applying dead-time compensation, the harmonic distortion rate (THD) of the phase current output by the three-level power converter 100 is 6.31%, while after applying the dead-time compensation scheme according to an embodiment of the present disclosure, the harmonic distortion rate (THD) of the phase current output by the three-level power converter 100 decreases to 5.12%.

[0174] Figure 17 A schematic block diagram of an apparatus 1700 for controlling a power converter 100 according to an embodiment of the present disclosure is shown. The apparatus 1700 can be implemented as follows: Figure 1 Control equipment 200. For example... Figure 17 As shown, device 1700 includes acquisition unit 1710. Acquisition unit 1710 is configured to acquire the AC side current of three-level power converter 100, such as phase current I. a I b and / or I cThe device 1700 also includes a determining unit 1720. The determining unit 1720 is configured to, in response to determining the flow direction of the acquired AC side current and determining the power switch group currently performing level switching, determine a compensation duty cycle for compensating the dead time of the power switch group based on voltage or potential information of the three-level power converter 100 and timing information related to the switching operation of the three-level power converter 100. Furthermore, the device 1700 also includes an adjusting unit 1730 and a transmitting unit 1740. The adjusting unit 1730 is configured to adjust the duty cycle of at least one power switch in the power switch group based on the compensation duty cycle, and the transmitting unit 1740 is configured to transmit a signal for controlling at least one power switch based on the adjusted duty cycle.

[0175] In some embodiments of this disclosure, the apparatus 1700 further includes another acquisition unit 1750 configured to acquire the neutral point voltage of the three-level power converter 100, the neutral point voltage including at least one of the voltage between neutral point O and the DC-side positive bus 101 and the voltage between neutral point O and the DC-side negative bus 102. Voltage or potential information used to determine the compensation duty cycle includes the acquired neutral point voltage.

[0176] In some embodiments of this disclosure, the apparatus 1700 further includes a duration determination unit 1760, which is configured to determine the turn-on transition duration and turn-off transition duration of at least one power switch in the power switch group based on the magnitude of the acquired AC side current. The timing information used to determine the compensation duty cycle includes the determined turn-on transition duration and turn-off transition duration.

[0177] Those skilled in the art will understand that the various steps of the methods disclosed above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. Optionally, they can be implemented using device-executable program code, which can then be stored in a storage device for execution by the computing device. Alternatively, they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this disclosure is not limited to any particular combination of hardware and software.

[0178] It should be understood that although several devices or sub-devices of the device have been mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more devices described above can be embodied in one device. Conversely, the features and functions of one device described above can be further divided and embodied by multiple devices.

[0179] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for controlling a three-level power converter, comprising: The AC side current of the three-level power converter is obtained, and the three-level power converter is configured to perform power conversion between DC power and AC power; In response to determining the flow direction of the acquired AC side current and identifying the power switch group currently performing level switching, a compensation duty cycle for compensating the dead zone of the power switch group is determined based on the voltage or potential information of the three-level power converter and the time information related to the switching operation of the three-level power converter. as well as The duty cycle of at least one power switch in the power switch group is adjusted based on the compensation duty cycle. as well as The signal for controlling the at least one power switch is sent based on the adjusted duty cycle.

2. The method according to claim 1, further comprising: The neutral point voltage of the three-level power converter is obtained, and the neutral point voltage includes at least one of the voltage between the neutral point and the DC-side positive bus and the voltage between the neutral point and the DC-side negative bus. The voltage or potential information mentioned therein includes the acquired neutral point voltage.

3. The method according to claim 1 or 2, further comprising: The turn-on transition time and turn-off transition time of at least one power switch in the power switch group are determined based on the magnitude of the acquired AC side current. The time information includes the connection transition duration and the shutdown transition duration.

4. The method according to claim 3, wherein the turn-on transition time and turn-off transition time of the power switch adjacent to the DC positive bus or the DC negative bus are different from the turn-on transition time and turn-off transition time of the power switch not adjacent to the DC positive bus or the DC negative bus.

5. The method according to claim 3, wherein the three-level power converter comprises: A first power switch, a second power switch, a third power switch, and a fourth power switch are sequentially connected in series between the DC-side positive bus and the DC-side negative bus; A first freewheeling diode connected in parallel with the first power switch, a second freewheeling diode connected in parallel with the second power switch, a third freewheeling diode connected in parallel with the third power switch, and a fourth freewheeling diode connected in parallel with the fourth power switch; The first clamping diode is coupled to the neutral point at its anode and to the node between the first power switch and the second power switch at its cathode; as well as The second clamping diode is coupled to the neutral point at its cathode and to the node between the third and fourth power switches at its anode.

6. The method of claim 5, wherein when the acquired AC side current flows out of the three-level power converter and the power switch group currently performing level switching is the first power switch and the third power switch, The voltage or potential information further includes at least one of the following: the voltage between the DC-side positive bus and the DC-side negative bus, the on-state voltage drop of the first power switch, the on-state voltage drop of the second power switch, and the on-state voltage drop of the first clamping diode. The timing information also includes at least one of the following: the duty cycle before adjustment of the first power switch, and the carrier period duration.

7. The method of claim 5, wherein when the acquired AC side current flows into the three-level power converter and the power switch group currently performing level switching is the first power switch and the third power switch, The voltage or potential information further includes at least one of the following: the voltage between the DC-side positive bus and the DC-side negative bus, the on-state voltage drop of the first power switch, the on-state voltage drop of the second power switch, the on-state voltage drop of the third power switch, the on-state voltage drop of the first freewheeling diode, and the on-state voltage drop of the second clamping diode. The timing information also includes at least one of the following: the duty cycle before adjustment of the first power switch, the dead time of the first power switch, the dead time of the third power switch, and the carrier period duration.

8. The method of claim 5, wherein when the acquired AC side current flows out of the three-level power converter and the power switch group currently performing level switching is the second power switch and the fourth power switch, The voltage or potential information further includes at least one of the following: the voltage between the DC-side positive bus and the DC-side negative bus, the on-state voltage drop of the second power switch, the on-state voltage drop of the third power switch, the on-state voltage drop of the fourth power switch, the on-state voltage drop of the fourth freewheeling current transistor, and the on-state voltage drop of the first clamping diode. The timing information also includes at least one of the following: the duty cycle before adjustment for the second power switch, the dead time for the second power switch, the dead time for the fourth power switch, and the carrier period duration.

9. The method of claim 5, wherein when the acquired AC side current flows into the three-level power converter and the power switch group currently performing level switching is the second power switch and the fourth power switch, The voltage or potential information further includes at least one of the following: the voltage between the DC-side positive bus and the DC-side negative bus, the on-state voltage drop of the third power switch, the on-state voltage drop of the fourth power switch, and the on-state voltage drop of the second clamping diode. The timing information also includes at least one of the following: the duty cycle before adjustment for the second power switch, the dead time for the second power switch, the dead time for the fourth power switch, and the carrier period duration.

10. The method according to any one of claims 6 to 9, wherein the dead time for the corresponding power switch is greater than or equal to the maximum turn-off transition time of the corresponding power switch.

11. The method of claim 1, wherein determining the compensation duty cycle for compensating the dead time of the power switch group comprises: If the deviation between the phase angle of the acquired AC side current and the zero crossing point exceeds a predetermined threshold and the AC side current flows out of the three-level power converter, the difference between the expected output voltage and the actual output voltage of the three-level power converter on the AC side is calculated, and a first compensation value is determined as the compensation duty cycle based on the calculated difference. If the deviation between the phase angle of the acquired AC side current and the zero crossing point exceeds a predetermined threshold and the AC side current flows into the three-level power converter, the difference between the expected output voltage and the actual output voltage of the three-level power converter on the AC side is calculated, and a second compensation value is determined as the compensation duty cycle based on the calculated difference. as well as If the deviation between the phase angle of the acquired AC side current and the zero crossing point is lower than a predetermined threshold, the compensation duty cycle is determined by linear interpolation between the first compensation value and the second compensation value.

12. The method according to claim 1, wherein the three-level power converter comprises a three-phase three-level inverter.

13. A control device adapted to be coupled to the three-level power converter and configured to perform the method according to any one of claims 1 to 12.

14. An apparatus for controlling a three-level power converter, comprising: The acquisition unit is configured to acquire the AC side current of the three-level power converter; The determining unit is configured to, in response to determining the flow direction of the acquired AC side current and determining the power switch group currently performing level switching, determine a compensation duty cycle for compensating the dead time of the power switch group based on the voltage or potential information of the three-level power converter and the time information related to the switching operation of the three-level power converter. The adjustment unit is configured to adjust the duty cycle of at least one power switch in the power switch group based on the compensation duty cycle; as well as The transmitting unit is configured to transmit a signal for controlling the at least one power switch based on an adjusted duty cycle.

15. A power conversion system, comprising: Three-level power converter; as well as The control device according to claim 13 is coupled to the three-level power converter.

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