Safety response trigger circuit and safety response system

Abstract

The invention relates to the technical field of electric driving, and provides a safety response trigger circuit and a safety response system. The safety response trigger circuit is used for a multi-drive system, and comprises a pulse conversion circuit which is configured to convert a rotating speed signal into a pulse signal; the pulse width comparison circuit is configured to generate a corresponding trigger signal according to the relationship between the frequency of the pulse signal and a frequency threshold; wherein the rotating speed signal is a rotating speed signal of a fault driving system of the multi-driving system, and the trigger signal is used for triggering the fault driving system to enter a corresponding safety state; and the signal latch circuit is configured to latch the received trigger signal and periodically output the latest trigger signal. According to the rotating speed signal of the fault driving system, the fault driving system is triggered to accurately enter the corresponding safety state, reverse torque and back electromotive force are avoided, the requirement that part of driving system faults do not affect other driving work is met, and the maximum driving advantage of the multi-driving system is brought into play.

Description

Technical Field

[0001] This invention relates to the field of electric drive technology, and more specifically, to a safety response trigger circuit and a safety response system. Background Technology

[0002] For electric vehicles equipped with multiple drive systems, the requirement that damage to one drive system does not affect the operation of other drive systems is becoming increasingly important.

[0003] In traditional electric drive technology, when part of the drive system fails, the vehicle's response is deceleration and stopping. Taking a dual-drive system as an example, when one drive system fails, its inverter disconnects the relay connected to the high-voltage battery. This relay connects the high-voltage battery to the inverters of both drive systems. When the relay disconnects, the operation of the other drive system is affected, and the vehicle decelerates and stops. During this process, because the relay is disconnected, the voltage on the high-voltage bus connecting the inverter and the high-voltage battery changes. The faulty drive system then switches between different safety states based on the voltage on the high-voltage bus. Specifically, when the voltage on the high-voltage bus is high, the faulty drive system enters a first safety state that avoids back electromotive force; when the voltage on the high-voltage bus is low, the faulty drive system enters a second safety state that avoids reverse torque.

[0004] Since the failure of some drive systems does not affect the operation of other drive systems, when a drive system fails, the relay does not disconnect so that the drive system without faults can continue to work. At this time, the voltage on the high-voltage bus does not change, so the faulty drive system cannot accurately switch between different safety states.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] In view of this, the present invention provides a safety response trigger circuit and a safety response system, which can trigger the faulty drive system to accurately enter the corresponding safety state according to the speed signal of the faulty drive system, avoid reverse torque and back electromotive force, meet the requirement that the failure of some drive systems does not affect the operation of other drives, and enable multiple drive systems to exert their maximum drive advantages.

[0007] According to one aspect of the present invention, a safety response triggering circuit is provided for a multi-drive system, comprising: a pulse conversion circuit configured to convert a rotational speed signal into a pulse signal; a pulse width comparison circuit connected to the pulse conversion circuit, the pulse width comparison circuit being configured to generate a corresponding trigger signal based on the relationship between the frequency of the pulse signal and a frequency threshold; wherein the rotational speed signal is the rotational speed signal of a fault drive system of the multi-drive system, and the trigger signal is used to trigger the fault drive system to enter a corresponding safety state; and a signal latching circuit connected to the pulse width comparison circuit, the signal latching circuit being configured to latch the received trigger signal and periodically output the latest trigger signal.

[0008] In some embodiments, the pulse conversion circuit includes: a first comparator, the two input terminals of the first comparator receiving the rotation speed signal and a first threshold signal respectively, and the output terminal of the first comparator outputting the pulse signal.

[0009] In some embodiments, the first threshold signal is determined based on the critical speed, and the relationship between the speed signal and the critical speed determines the fault drive system to enter the corresponding safe state.

[0010] In some embodiments, the first threshold signal is generated by the series node of two voltage divider resistors connected in series with the power supply.

[0011] In some embodiments, the pulse width comparison circuit includes: a first integrated circuit chip connected between the output terminal of the pulse conversion circuit and the input terminal of the signal latch circuit; when the frequency of the pulse signal is greater than and less than the frequency threshold, the first integrated circuit chip outputs a first trigger signal for triggering the fault drive system to enter a first safe state and a second trigger signal for triggering the fault drive system to enter a second safe state.

[0012] In some embodiments, the pulse width comparison circuit further includes: a first charging and discharging circuit connected between the output terminal of the pulse conversion circuit and the threshold terminal of the first integrated circuit chip; when the frequency of the pulse signal is greater than and less than the frequency threshold, the first charging and discharging circuit charges and discharges respectively, so that the voltage at the threshold terminal of the first integrated circuit chip is greater than and less than the first control voltage, so that the first integrated circuit chip outputs the first trigger signal and the second trigger signal respectively.

[0013] In some embodiments, the first charging and discharging circuit includes: a first transistor, the control terminal of which is connected to the output terminal of the pulse conversion circuit; a first capacitor, connected in parallel between the input and output terminals of the first transistor, the positive terminal of the first capacitor being connected to the threshold terminal of the first integrated circuit chip and connected to a power supply via at least one voltage divider resistor, and the negative terminal of the first capacitor being grounded; when the frequency of the pulse signal is greater than the frequency threshold, the first transistor is turned off, the first capacitor is charged, and the voltage at the threshold terminal of the first integrated circuit chip is greater than the first control voltage; when the frequency of the pulse signal is less than the frequency threshold, the first transistor is turned on, the first capacitor is discharged, and the voltage at the threshold terminal of the first integrated circuit chip is less than the first control voltage.

[0014] In some embodiments, the first integrated circuit chip is an NE555 timer integrated circuit. The trigger terminal of the NE555 timer integrated circuit is connected to the output terminal of the pulse conversion circuit, and the output terminal of the NE555 timer integrated circuit is connected to the input terminal of the signal latch circuit. The first control voltage is the voltage of the control terminal of the NE555 timer integrated circuit. When the voltage at the threshold terminal of the first integrated circuit chip is greater than the first control voltage, the first integrated circuit chip outputs the first trigger signal, which is a constant voltage. When the voltage at the threshold terminal of the first integrated circuit chip is less than the first control voltage, the first integrated circuit chip outputs the second trigger signal, which is the voltage at the trigger terminal of the NE555 timer integrated circuit.

[0015] In some embodiments, the first trigger signal is a constant voltage, and the second trigger signal is a pulse signal received by the first integrated circuit chip; the pulse width comparison circuit further includes: a constant voltage conversion circuit connected between the output terminal of the first integrated circuit chip and the input terminal of the signal latching circuit, the constant voltage conversion circuit being configured to convert the received constant voltage into a first trigger signal in a first constant voltage form, and to convert the received pulse signal into a second trigger signal in a second constant voltage form.

[0016] In some embodiments, the constant voltage conversion circuit includes: a second charge-discharge circuit connected to the output terminal of the first integrated circuit chip; a second comparator, the two input terminals of the second comparator being respectively connected to the second charge-discharge circuit and receiving a second threshold signal; when the second charge-discharge circuit receives the constant voltage and the pulse signal respectively, the voltage output by the second charge-discharge circuit to the second comparator is greater than and less than the second threshold signal respectively, so that the second comparator outputs a first trigger signal in the form of the first constant voltage and a second trigger signal in the form of the second constant voltage respectively.

[0017] In some embodiments, the second charging and discharging circuit includes: a second transistor, the control terminal of which is connected to the output terminal of the first integrated circuit chip; a second capacitor, connected in parallel between the input and output terminals of the second transistor, the positive terminal of the second capacitor being connected to the positive terminal of the second comparator and connected to a power supply via a fifth voltage divider resistor, and the negative terminal of the second capacitor being grounded; when the second charging and discharging circuit receives the constant voltage, the second transistor remains off, the second capacitor remains charging, making the voltage at the positive terminal of the second comparator greater than the second threshold signal, and the second comparator outputs a first trigger signal in the form of the first constant voltage; when the second charging and discharging circuit receives the pulse signal, the second transistor is turned on and off, the second capacitor is discharged and charged, making the voltage at the positive terminal of the second comparator less than the second threshold signal, and the second comparator outputs a second trigger signal in the form of the second constant voltage; wherein, the second constant voltage is less than the first constant voltage.

[0018] In some embodiments, a sixth voltage divider resistor is connected in series between the control terminal of the second transistor and the output terminal of the first integrated circuit chip, and / or a seventh voltage divider resistor is connected in parallel between the second capacitor and the second transistor.

[0019] In some embodiments, the signal latching circuit includes: a second integrated circuit chip connected to the output of the pulse width comparison circuit, wherein the second integrated circuit chip is configured to latch the received trigger signal and output the latest trigger signal based on periodically generated activation signals.

[0020] In some embodiments, the second integrated circuit chip is a rising edge triggered D flip-flop, the set terminal of the rising edge triggered D flip-flop is connected to the output terminal of the pulse width comparator circuit, and the clock signal input terminal of the rising edge triggered D flip-flop receives the activation signal, the activation signal being a rising edge signal.

[0021] In some embodiments, the activation signal is generated by a timing reset circuit, which includes: a third integrated circuit chip connected to the second integrated circuit chip; and a charge-discharge interlock circuit connected to the threshold terminal of the third integrated circuit chip. As the charge-discharge interlock circuit operates, the voltage at the threshold terminal of the third integrated circuit chip periodically satisfies a preset relationship with the second control voltage, causing the third integrated circuit chip to periodically output the activation signal.

[0022] In some embodiments, the charge-discharge interlock circuit includes: a third transistor, the control terminal of which is connected to the discharge terminal of the third integrated circuit chip, the input terminal of which is connected to a power supply via an eighth voltage divider resistor, and the output terminal of which is grounded; a fourth transistor, the control terminal of which is connected to the input terminal of the third transistor, and the input terminal of which is connected to the power supply; and a third capacitor, the positive terminal of which is connected to the threshold terminal of the third integrated circuit chip and the output terminal of the fourth transistor, and connected to the discharge terminal of the third integrated circuit chip via a ninth voltage divider resistor, and the negative terminal of which is grounded; wherein the third transistor and the fourth transistor are alternately turned on, so that the voltage at the threshold terminal of the third integrated circuit chip and the second control voltage periodically satisfy the preset relationship.

[0023] In some embodiments, the third integrated circuit chip is an NE555 timer integrated circuit, and the second control voltage is the voltage at the control terminal of the NE555 timer integrated circuit; when the voltage at the threshold terminal of the third integrated circuit chip is greater than the second control voltage, the third integrated circuit chip outputs the activation signal.

[0024] In some embodiments, the discharge terminal of the third integrated circuit chip is connected to the power supply via a tenth voltage divider resistor, and / or the positive terminal of the third capacitor is connected to the output terminal of the fourth transistor via an eleventh voltage divider resistor.

[0025] According to another aspect of the present invention, a safety response system is provided for use in a multi-drive system, comprising: a fault response module configured to acquire a rotational speed signal of the faulty drive system in response to a fault signal of the multi-drive system; a safety response triggering circuit as described in any of the above embodiments, wherein a pulse conversion circuit of the safety response triggering circuit is connected to the fault response module, and a trigger signal output by a signal latching circuit of the safety response triggering circuit includes a first trigger signal and a second trigger signal; and a safety strategy module configured to trigger the faulty drive system to enter a first safety state according to the first trigger signal, and to trigger the faulty drive system to enter a second safety state according to the second trigger signal.

[0026] The beneficial effects of this invention compared to the prior art include at least the following:

[0027] The speed signal of the fault-driven system is converted into a pulse signal by a pulse conversion circuit for subsequent quantification and comparison. The speed signal is determined to some extent by the voltage on the high-voltage bus connecting the inverter of the fault-driven system to the high-voltage battery. The pulse width comparison circuit compares the frequency of the pulse signal with a frequency threshold. The frequency of the pulse signal reflects the voltage on the high-voltage bus to some extent, thus enabling the generated trigger signal to accurately trigger the fault-driven system to enter the corresponding safe state, avoiding reverse torque and back electromotive force. The signal latching circuit periodically outputs the latest trigger signal to prevent frequent fluctuations in the trigger signal from causing the safety response system to enter different safe states to jam, thus keeping the trigger signal stable within a reasonable period.

[0028] Therefore, the safety response triggering circuit of the present invention, through the cooperation of pulse conversion circuit, pulse width comparison circuit and signal latching circuit, can accurately trigger the faulty drive system to enter the corresponding safety state according to the speed signal of the faulty drive system, avoid reverse torque and back electromotive force, meet the requirement that the failure of some drive systems does not affect the operation of other drives, and enable multiple drive systems to exert the maximum drive advantage.

[0029] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0030] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0031] Figure 1 A schematic diagram of the security response triggering circuit in an embodiment of the present invention is shown;

[0032] Figure 2 This diagram illustrates how the pulse conversion circuit in an embodiment of the present invention converts a speed signal into a pulse signal.

[0033] Figure 3 This diagram illustrates the latching and output trigger signal of the signal latching circuit in an embodiment of the present invention.

[0034] Figure 4 A schematic diagram of the pulse conversion circuit in an embodiment of the present invention is shown;

[0035] Figure 5 A schematic diagram of the circuit structure of the first threshold signal generation circuit in an embodiment of the present invention is shown;

[0036] Figure 6 A schematic diagram of the circuit structure of the pulse width comparison circuit in an embodiment of the present invention is shown;

[0037] Figure 7 A schematic diagram of the circuit structure of the signal latch circuit in an embodiment of the present invention is shown;

[0038] Figure 8 A schematic diagram of the security response system in an embodiment of the present invention is shown. Detailed Implementation

[0039] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to those described herein. Rather, these embodiments are provided to make the invention more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0040] The accompanying drawings are merely illustrative of the invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0041] The use of terms such as "first," "second," and similar terms in the specific description does not indicate any order, quantity, or importance, but is merely used to distinguish different components. In the description of this invention, it should be noted that when a device is said to be "connected" to another device, this includes not only direct connections but also indirect connections via other elements.

[0042] It should be noted that, unless otherwise specified, the embodiments of the present invention and the features in different embodiments can be combined with each other.

[0043] Figure 1 The main circuit modules of the safety response trigger circuit are shown in the diagram. Figure 1 As shown, the safety response triggering circuit for a multi-drive system provided in this embodiment of the invention includes a pulse conversion circuit 100, a pulse width comparison circuit 200, and a signal latching circuit 300.

[0044] A multi-drive system can be a dual-drive system, a four-drive system, or any other automotive drive system that includes two or more drive systems.

[0045] The pulse conversion circuit 100 is configured to convert the speed signal into a pulse signal. The speed signal is the speed signal of the faulty drive system in the multi-drive system. The speed signal is an analog signal; converting it into a pulse signal facilitates subsequent quantization and comparison. The speed signal is determined to some extent by the voltage on the high-voltage bus connecting the inverter of the faulty drive system to the high-voltage battery.

[0046] Figure 2 This diagram illustrates how a pulse conversion circuit converts a speed signal into a pulse signal; combined with... Figure 1 and Figure 2 As shown, the pulse conversion circuit 100 converts the sinusoidal speed signal 100a into a square wave pulse signal 100b. Figure 2 In the diagram, the horizontal axis represents time, and the vertical axis represents voltage.

[0047] The pulse width comparison circuit 200 is connected to the pulse conversion circuit 100 and is configured to generate a corresponding trigger signal based on the relationship between the frequency of the pulse signal and a frequency threshold. This trigger signal is used to trigger the fault-driven system to enter the corresponding safe state. By comparing the frequency of the pulse signal with the frequency threshold through the pulse width comparison circuit 200, the frequency of the pulse signal reflects the voltage on the high-voltage bus to a certain extent, thus enabling the generated trigger signal to accurately trigger the fault-driven system to enter the corresponding safe state, avoiding reverse torque and back electromotive force.

[0048] Specifically, by setting a frequency threshold, when the frequency of the pulse signal is relatively high (indicating a higher voltage on the high-voltage bus), the trigger signal generated by the pulse width comparison circuit 200 is used to trigger the fault drive system into a first safe state that avoids back electromotive force. Conversely, when the frequency of the pulse signal is relatively low (indicating a lower voltage on the high-voltage bus), the trigger signal generated by the pulse width comparison circuit 200 is used to trigger the fault drive system into a second safe state that avoids reverse torque. For example, when the frequency of the pulse signal is greater than the frequency threshold, the pulse width comparison circuit 200 generates a high-level trigger signal; when the frequency of the pulse signal is less than the frequency threshold, the pulse width comparison circuit 200 generates a low-level trigger signal. In this description, high and low levels, low voltage and high voltage, etc., are all relative terms.

[0049] The signal latch circuit 300 is connected to the pulse width comparison circuit 200 and is configured to latch the received trigger signal and periodically output the latest trigger signal. By periodically outputting the latest trigger signal through the signal latch circuit 300, the frequent fluctuations of the trigger signal can prevent the fault drive system / the safety response system from entering different safety states due to trigger fault drive system from getting stuck, thus keeping the trigger signal stable within a reasonable period.

[0050] Figure 3This diagram illustrates the signal latching circuit's latching and output trigger signal, where the horizontal axis represents time and the vertical axis represents voltage. (Combined with...) Figures 1 to 3 As shown, trigger signal 300a is continuously output to signal latch circuit 300. In the first cycle T1, signal latch circuit 300 outputs the newly received low-level trigger signal 300a1; in the second cycle T2, signal latch circuit 300 outputs the newly received high-level trigger signal 300a2; in the third cycle T3, signal latch circuit 300 outputs the newly received high-level trigger signal 300a3, and so on. Between two cycles, regardless of whether the received trigger signal 300a changes, the output of signal latch circuit 300 remains unchanged from the trigger signal output in the previous cycle until a new trigger signal is output in the next cycle.

[0051] The safety response triggering circuit of the present invention, through the cooperation of pulse conversion circuit 100, pulse width comparison circuit 200 and signal latching circuit 300, can accurately trigger the faulty drive system to enter the corresponding safe state according to the speed signal of the faulty drive system, avoid reverse torque and back electromotive force, meet the requirement that the failure of some drive systems does not affect the operation of other drives, and enable multiple drive systems to exert the maximum drive advantage.

[0052] Figure 4 The circuit structure of the pulse conversion circuit is illustrated; combined with Figure 1 and Figure 4 As shown, in some embodiments, the pulse conversion circuit 100 includes: a first comparator U1, the two input terminals of the first comparator U1 receiving a speed signal VRPS and a first threshold signal Vth1 respectively, and the output terminal OUT1 of the first comparator U1 outputs a pulse signal.

[0053] Specifically, the first comparator U1 can receive the speed signal VRPS through its positive input terminal and the first threshold signal Vth1 through its negative input terminal. When the voltage value of the speed signal VRPS is greater than or equal to the voltage value of the first threshold signal Vth1, the output terminal OUT1 of the first comparator U1 outputs an effective pulse width. A schematic diagram of the conversion of the speed signal into a pulse signal can be found in [reference needed]. Figure 2 As shown; however, not limited thereto, the first comparator U1 can also receive the speed signal VRPS through the negative input terminal and the first threshold signal Vth1 through the positive input terminal.

[0054] The first comparator U1 can be an LT1716 comparator, but is not limited to this. The first comparator U1 is also connected to a power supply, for example, 5V, but is not limited to this. All circuit modules of the safety response trigger circuit can be powered by this power supply.

[0055] In other embodiments, the pulse conversion circuit 100 can also be implemented by other circuit structures, such as Schmitt triggers, microcontrollers, etc.

[0056] In some embodiments, the first threshold signal Vth1 is determined based on the critical speed, and the relationship between the speed signal VRPS and the critical speed determines the corresponding safe state that the faulty drive system enters. When the motor speed of the faulty drive system, represented by the speed signal VRPS, is greater than or equal to the critical speed, the faulty drive system needs to enter a first safe state that avoids back electromotive force; when the motor speed of the faulty drive system, represented by the speed signal VRPS, is less than or equal to or less than the critical speed, the faulty drive system needs to enter a second safe state that avoids reverse torque. The critical speed can be determined based on the motor configuration of the faulty drive system or by calculation; for example, the critical speed can be 6000 rpm, but is not limited to this. The determination of the first threshold signal Vth1 requires that the pulse signals converted from the speed signals greater than and less than the critical speed have frequencies greater than and less than the frequency thresholds, respectively, so as to trigger the faulty drive system to enter the first and second safe states, respectively. When determining the first threshold signal Vth1, the corresponding frequency threshold can be determined first based on the critical speed, and then the first threshold signal Vth1 can be determined based on the frequency threshold.

[0057] In circuit design, the following formula can be used to simulate a sinusoidal speed signal: V = 2.4 + 1.5 * sin(6.283 * (Fs + (Fe - Fs) / te * time / 2) * time). Where Fs = 0, Fe = 100, and te = 10.

[0058] Figure 5 The circuit structure of the circuit that generates the first threshold signal is illustrated; combined with Figure 4 and Figure 5 As shown, in some embodiments, the first threshold signal Vth1 is generated by the series connection of two voltage-dividing resistors (including a first voltage-dividing resistor R1 and a second voltage-dividing resistor R2) connected in series with a power supply. The resistance of the first voltage-dividing resistor R1 can be 13kΩ, and the resistance of the second voltage-dividing resistor R2 can be 12kΩ. The power supply is, for example, 5V, as described above, but is not limited thereto. The first threshold signal Vth1 can be adjusted by adjusting the resistance values ​​of the first voltage-dividing resistor R1 and / or the second voltage-dividing resistor R2.

[0059] Figure 6 The circuit structure of the pulse width comparator circuit is illustrated; combined with Figure 1 , Figure 4 and Figure 6As shown, in some embodiments, the pulse width comparison circuit 200 includes: a first integrated circuit chip U2, connected between the output terminal OUT1 of the pulse conversion circuit 100 and the input terminal of the signal latch circuit 300; when the frequency of the pulse signal PWM output by the output terminal OUT1 is greater than and less than the frequency threshold, the first integrated circuit chip U2 outputs a first trigger signal for triggering the fault drive system to enter a first safe state and a second trigger signal for triggering the fault drive system to enter a second safe state.

[0060] For example, when the frequency of the pulse signal PWM is greater than the frequency threshold, the first integrated circuit chip U2 outputs a first trigger signal; when the frequency of the pulse signal PWM is less than the frequency threshold, the first integrated circuit chip U2 outputs a second trigger signal; when the frequency of the pulse signal PWM is equal to the frequency threshold, the first integrated circuit chip U2 can output either the first trigger signal or the second trigger signal according to the design requirements.

[0061] The first integrated circuit chip U2 can adopt a suitable circuit structure such as a microcontroller to generate a corresponding trigger signal based on the relationship between the frequency of the pulse signal PWM and the frequency threshold.

[0062] In some embodiments, the pulse width comparison circuit 200 further includes: a first charging and discharging circuit 210 connected between the output terminal OUT1 of the pulse conversion circuit 100 and the threshold terminal THRS of the first integrated circuit chip U2; when the frequency of the pulse signal PWM is greater than and less than the frequency threshold, the first charging and discharging circuit 210 charges and discharges respectively, so that the voltage of the threshold terminal THRS of the first integrated circuit chip U2 is greater than and less than the first control voltage, so that the first integrated circuit chip U2 outputs the first trigger signal and the second trigger signal respectively.

[0063] The first integrated circuit chip U2 is configured to output a first trigger signal or a second trigger signal based on the relationship between the voltage of its threshold terminal THRS and a first control voltage. For example, when the voltage of the threshold terminal THRS is greater than the first control voltage, the first integrated circuit chip U2 outputs the first trigger signal; when the voltage of the threshold terminal THRS is less than the first control voltage, the first integrated circuit chip U2 outputs the second trigger signal; and when the voltage of the threshold terminal THRS is equal to the first control voltage, the first integrated circuit chip U2 can output either the first trigger signal or the second trigger signal. Through the first charging and discharging circuit 210, charging and discharging are achieved according to the change in the relationship between the frequency of the pulse signal PWM and the frequency threshold, thereby changing the voltage of the threshold terminal THRS of the first integrated circuit chip U2, and thus changing the trigger signal output by the first integrated circuit chip U2.

[0064] The specific circuit structure of the first charging and discharging circuit 210 and the internal structure of the first integrated circuit chip U2 can be designed as needed. As long as the first charging and discharging circuit 210 switches the charging and discharging state according to the relationship between the frequency of the pulse signal PWM and the frequency threshold, the relationship between the voltage of the threshold terminal THRS of the first integrated circuit chip U2 and the first control voltage changes, and then the first integrated circuit chip U2 outputs the corresponding trigger signal.

[0065] In some embodiments, the first charging and discharging circuit 210 includes: a first transistor Q1, the control terminal of which is connected to the output terminal OUT1 of the pulse conversion circuit 100; a first capacitor C1, which is connected in parallel between the input and output terminals of the first transistor Q1, the positive terminal of the first capacitor C1 is connected to the threshold terminal THRS of the first integrated circuit chip U2 and connected to the power supply through at least one voltage divider resistor, and the negative terminal of the first capacitor C1 is grounded; when the frequency of the pulse signal PWM is greater than the frequency threshold, the first transistor Q1 is turned off, the first capacitor C1 is charged, and the voltage of the threshold terminal THRS of the first integrated circuit chip U2 is greater than the first control voltage; when the frequency of the pulse signal PWM is less than the frequency threshold, the first transistor Q1 is turned on, the first capacitor C1 is discharged, and the voltage of the threshold terminal THRS of the first integrated circuit chip U2 is less than the first control voltage.

[0066] The first transistor Q1 can be a suitable transistor such as a bipolar junction transistor (BJT) or a field-effect transistor (FET); for example, the first transistor Q1 can be a PNP type transistor, specifically a BC856B type transistor, but it is not limited thereto. The capacitance of the first capacitor C1 can be 100nF, but it is not limited thereto. The positive terminal of the first capacitor C1 can be connected to the power supply through the third voltage divider resistor R3 and the fourth voltage divider resistor R4. The resistance value of the third voltage divider resistor R3 can be 100kΩ, but it is not limited thereto.

[0067] In some embodiments, the first integrated circuit chip U2 is an NE555 timer integrated circuit. The trigger terminal TRIG of the NE555 timer integrated circuit is connected to the output terminal OUT1 of the pulse conversion circuit 100. The output terminal OUT of the NE555 timer integrated circuit is connected to the input terminal of the signal latch circuit 300. The first control voltage is the voltage of the control terminal CV of the NE555 timer integrated circuit. When the voltage of the threshold terminal THRS of the first integrated circuit chip U2 is greater than or equal to the first control voltage, the first integrated circuit chip U2 outputs a first trigger signal, which is a constant voltage signal Vcons. When the voltage of the threshold terminal THRS of the first integrated circuit chip U2 is less than or equal to or less than the first control voltage, the first integrated circuit chip U2 outputs a second trigger signal, which is the voltage of the trigger terminal TRIG of the NE555 timer integrated circuit, that is, the pulse signal PWM output by the output terminal OUT1 of the pulse conversion circuit 100.

[0068] Reference Figure 6 As shown, according to the configuration of the NE555 timer IC: when the voltage of the threshold terminal THRS is greater than or equal to the voltage of the control terminal CV, the output terminal OUT outputs a constant voltage signal Vcons, which is usually a constant high voltage; when the voltage of the threshold terminal THRS is less than or equal to or less than the voltage of the control terminal CV, the output terminal OUT outputs the voltage of the trigger terminal TRIG. The control terminal CV can be grounded through the fourth capacitor C4, the capacitance of which can be 10nF, but is not limited to this. Furthermore, the power supply terminal Vcc and the reset terminal RST of the NE555 timer IC are both connected to the power supply, the discharge terminal DIS is connected to the threshold terminal THRS, and the ground terminal GND is grounded.

[0069] In some embodiments, the first trigger signal is a constant voltage signal Vcons, and the second trigger signal is a pulse signal PWM received by the first integrated circuit chip U2; the pulse width comparison circuit 200 further includes a constant voltage conversion circuit 220, connected between the output terminal OUT of the first integrated circuit chip U2 and the input terminal of the signal latch circuit 300. The constant voltage conversion circuit 220 is configured to convert the received constant voltage signal Vcons into a first trigger signal Vtrig1 in a first constant voltage form, and to convert the received pulse signal PWM into a second trigger signal Vtrig2 in a second constant voltage form.

[0070] The constant voltage conversion circuit 220 converts the constant voltage signal Vcons and the pulse signal PWM output by the first integrated circuit chip U2 into a first trigger signal Vtrig1 in the form of a first constant voltage and a second trigger signal Vtrig2 in the form of a second constant voltage, respectively. The first trigger signal Vtrig1 in the form of a first constant voltage is, for example, a constant high voltage, and the second trigger signal Vtrig2 in the form of a second constant voltage is, for example, a constant low voltage. This facilitates triggering the fault drive system to enter a first safe state that can avoid back electromotive force and a second safe state that can avoid reverse torque, respectively.

[0071] The constant voltage converter circuit 220 can achieve level conversion through capacitor filtering, switching transistor circuits, etc.

[0072] In some embodiments, the constant voltage conversion circuit 220 includes: a second charging and discharging circuit 220a connected to the output terminal OUT of the first integrated circuit chip U2; a second comparator U3, the two input terminals of the second comparator U3 being connected to the second charging and discharging circuit 220a and receiving a second threshold signal Vth2, respectively; when the second charging and discharging circuit 220a receives a constant voltage signal Vcons and a pulse signal PWM, the voltage output by the second charging and discharging circuit 220a to the second comparator U3 is greater than and less than the second threshold signal Vth2, respectively, so that the second comparator U3 outputs a first trigger signal Vtrig1 in the form of a first constant voltage and a second trigger signal Vtrig2 in the form of a second constant voltage.

[0073] The specific circuit structure of the second charging / discharging circuit 220a can be designed as needed, as long as it switches the charging / discharging state according to the constant voltage signal Vcons and the pulse signal PWM, so that the voltage output to the second comparator U3 is greater than and less than the second threshold signal Vth2, respectively. The second comparator U3 can be connected to the second charging / discharging circuit 220a through its positive input terminal and receive the second threshold signal Vth2 through its negative input terminal, but this is not a limitation. By adjusting the parameters of the second charging / discharging circuit 220a, the second comparator U3, and the second threshold signal Vth2, it is ensured that when the second charging / discharging circuit 220a receives the constant voltage signal Vcons, the voltage output to the second comparator U3 is greater than or equal to the second threshold signal Vth2, so that the second comparator U3 outputs a first trigger signal Vtrig1 in the form of a first constant voltage, and that when the second charging / discharging circuit 220a receives the pulse signal PWM, the voltage output to the second comparator U3 is less than or equal to the second threshold signal Vth2, so that the second comparator U3 outputs a second trigger signal Vtrig2 in the form of a second constant voltage.

[0074] The second comparator U3 can be an LT1716 comparator, but is not limited to this.

[0075] In some embodiments, the second charging and discharging circuit 220a includes: a second transistor Q2, the control terminal of which is connected to the output terminal OUT of the first integrated circuit chip U2; a second capacitor C2, connected in parallel between the input and output terminals of the second transistor Q2, the positive terminal of the second capacitor C2 being connected to the positive terminal of the second comparator U3 and connected to the power supply via the fifth voltage divider resistor R5, and the negative terminal of the second capacitor C2 being grounded; when the second charging and discharging circuit 220a receives a constant voltage signal Vcons, the second transistor Q2 remains off, and the second capacitor C2 remains charged, making the voltage at the positive terminal of the second comparator U3 greater than the voltage at the second comparator U3. The threshold signal Vth2 and the second comparator U3 output a first trigger signal Vtrig1 in the form of a first constant voltage. When the second charging and discharging circuit 220a receives the pulse signal PWM, the second transistor Q2 is turned on and off, and the second capacitor C2 is discharged and charged, so that the voltage at the positive terminal of the second comparator U3 is less than the second threshold signal Vth2. The second comparator U3 outputs a second trigger signal Vtrig2 in the form of a second constant voltage. The second constant voltage is less than the first constant voltage. The first trigger signal Vtrig1 in the form of the first constant voltage is a constant high voltage, and the second trigger signal Vtrig2 in the form of the second constant voltage is a constant low voltage.

[0076] The second transistor Q2 can be a PNP type transistor, such as the 2N2907 type transistor, but is not limited thereto. The capacitance of the second capacitor C2 can be 10μF, and the resistance of the fifth voltage divider resistor R5 can be 100kΩ, but is not limited thereto.

[0077] Specifically, when the second charging and discharging circuit 220a receives the pulse signal PWM: if the pulse signal PWM is high, the second transistor Q2 is cut off and the second capacitor C2 is charged; if the pulse signal PWM is low, the second transistor Q2 is turned on and the second capacitor C2 is discharged. Through the design of parameters such as the second transistor Q2, the second capacitor C2, and the fifth voltage divider resistor R5, the charging voltage of the second capacitor C2 under the action of the pulse signal PWM is always less than the second threshold signal Vth2. Therefore, the second comparator U3 outputs the second trigger signal Vtrig2 in the form of a second constant voltage.

[0078] In some embodiments, a sixth voltage divider resistor R6 is connected in series between the control terminal of the second transistor Q2 and the output terminal OUT of the first integrated circuit chip U2, and / or a seventh voltage divider resistor R7 is connected in parallel between the second capacitor C2 and the second transistor Q2. The resistance value of the sixth voltage divider resistor R6 can be 100kΩ, and the resistance value of the seventh voltage divider resistor R7 can be 110kΩ, but is not limited thereto.

[0079] Figure 7 The circuit structure of the signal latch circuit is illustrated; combined with Figure 1 , Figure 6 and Figure 7As shown, in some embodiments, the signal latching circuit 300 includes: a second integrated circuit chip U4 connected to the output terminal of the pulse width comparison circuit 200. The second integrated circuit chip U4 is configured to latch the received trigger signal (including a first trigger signal Vtrig1 in the form of a first constant voltage and a second trigger signal Vtrig2 in the form of a second constant voltage) and output the latest trigger signal based on the periodically generated activation signal VCLK.

[0080] The schematic diagram of the latching and output trigger signal of the second integrated circuit chip U4 can be found in [reference]. Figure 3 As shown, the second integrated circuit chip U4 outputs a low-level trigger signal 300a1 in the first cycle T1 and the third cycle T3, which is the second trigger signal Vtrig2 in the second constant voltage form, and outputs a high-level trigger signal 300a2 in the second cycle T2, which is the first trigger signal Vtrig1 in the first constant voltage form.

[0081] In some embodiments, the second integrated circuit chip U4 is a rising edge triggered D flip-flop. The set terminal PRE of the rising edge triggered D flip-flop is connected to the output terminal of the pulse width comparator circuit 200. The clock signal input terminal CLK of the rising edge triggered D flip-flop receives the activation signal VCLK, which is a rising edge signal.

[0082] In this way, the second integrated circuit chip U4 latches the received trigger signal and periodically outputs the latest received first trigger signal Vtrig1 in the form of a first constant voltage or the second trigger signal Vtrig2 in the form of a second constant voltage based on the activation signal VCLK. This prevents the fault drive system / the safety response system that triggers the fault drive system to enter different safety states from being stuck due to frequent fluctuations in the trigger signal, and keeps the trigger signal stable within a reasonable period.

[0083] The second integrated circuit chip U4 can specifically be an SN74HCS74D type trigger. Its power supply terminal VCC and clear terminal CLR are connected to the power supply, the data terminal Data and the ground terminal GND are grounded, and the two output terminals Q_N and Q can be selected to output the first trigger signal Vtrig1 in the first constant voltage form and the second trigger signal Vtrig2 in the second constant voltage form.

[0084] The activation signal VCLK can be input periodically from an external source. In some embodiments, the activation signal VCLK is generated by a timed reset circuit. (See reference...) Figure 7As shown, the timing reset circuit includes: a third integrated circuit chip U5, connected to the second integrated circuit chip U4; a charge-discharge interlock circuit 300b, connected to the threshold terminal THRS of the third integrated circuit chip U5; as the charge-discharge interlock circuit 300b operates, the voltage of the threshold terminal THRS of the third integrated circuit chip U5 periodically satisfies the preset relationship with the second control voltage, so that the third integrated circuit chip U5 periodically outputs the activation signal VCLK.

[0085] The charge / discharge interlock circuit 300b mainly consists of a switching transistor and a capacitor. After power-on, the circuit alternately charges and discharges the capacitor by switching the transistor on and off, periodically changing the voltage at the threshold terminal THRS of the third integrated circuit chip U5. This ensures that the voltage at the threshold terminal THRS of the third integrated circuit chip U5 periodically satisfies a preset relationship with the second control voltage. The third integrated circuit chip U5 can employ a suitable circuit structure, such as a microcontroller, to output an activation signal VCLK at a set time based on the relationship between the threshold terminal THRS voltage and the second control voltage.

[0086] In some embodiments, the charge / discharge interlock circuit 300b includes: a third transistor Q3, the control terminal of the third transistor Q3 being connected to the discharge terminal DIS of the third integrated circuit chip U5, the input terminal of the third transistor Q3 being connected to a power supply via an eighth voltage divider resistor R8, and the output terminal of the third transistor Q3 being grounded; a fourth transistor M4, the control terminal of the fourth transistor M4 being connected to the input terminal of the third transistor Q3, and the input terminal of the fourth transistor M4 being connected to a power supply; a third capacitor C3, the positive terminal of the third capacitor C3 being connected to the threshold terminal THRS of the third integrated circuit chip U5 and the output terminal of the fourth transistor M4, and connected to the discharge terminal DIS of the third integrated circuit chip U5 via a ninth voltage divider resistor R9, and the negative terminal of the third capacitor C3 being grounded; wherein, the third transistor Q3 and the fourth transistor M4 are alternately turned on, so that the voltage of the threshold terminal THRS of the third integrated circuit chip U5 periodically satisfies a preset relationship with the second control voltage.

[0087] The third transistor Q3 and the fourth transistor M4 can be suitable transistors such as bipolar junction transistors (BJTs) and field-effect transistors (FETs); for example, the third transistor Q3 can be an NPN transistor, and the fourth transistor M4 can be a PMOS transistor, specifically an FDS4435A type transistor, but this is not a limitation. The resistance value of the eighth voltage divider resistor R8 can be 1kΩ, the resistance value of the ninth voltage divider resistor R9 can be 200kΩ, and the capacitance of the third capacitor C3 can be 10μF, but this is not a limitation. The preset relationship can refer to the voltage at the threshold terminal THRS of the third integrated circuit chip U5 being greater than or equal to the second control voltage, but this is not a limitation.

[0088] In one specific implementation: the initial voltage of the discharge terminal DIS of the third integrated circuit chip U5 is low; when the signal latch circuit 300 is powered on, the third transistor Q3 is cut off, the fourth transistor M4 is turned on, and the third capacitor C3 is charged, causing the voltages of the threshold terminal THRS and the discharge terminal DIS of the third integrated circuit chip U5 to rise; when the voltage of the discharge terminal DIS of the third integrated circuit chip U5 rises to the point that the third transistor Q3 is turned on, the fourth transistor M4 is cut off, and the third capacitor C3 discharges, making the voltage of the threshold terminal THRS of the third integrated circuit chip U5 greater than or equal to the second control voltage, thereby causing the third integrated circuit chip U5 to output the activation signal VCLK. The third capacitor C3 can achieve instantaneous discharge, making the activation signal VCLK appear as a rising edge. Then, the voltage of the discharge terminal DIS of the third integrated circuit chip U5 is pulled low, returning to the state where the third transistor Q3 is cut off and the fourth transistor M4 is turned on, and so on, thus realizing the periodic output of the activation signal VCLK by the third integrated circuit chip U5 through the charge and discharge interlock circuit 300b.

[0089] In some embodiments, the third integrated circuit chip U5 is an NE555 timer integrated circuit, and the second control voltage is the voltage of the control terminal CV of the NE555 timer integrated circuit; when the voltage of the threshold terminal THRS of the third integrated circuit chip U5 is greater than the second control voltage, the third integrated circuit chip U5 outputs an activation signal VCLK.

[0090] Reference Figure 7 As shown, according to the configuration of the NE555 timer IC: when the voltage of the threshold terminal THRS is greater than or equal to the voltage of the control terminal CV, the output terminal OUT outputs a rising edge signal, i.e., the activation signal VCLK; when the voltage of the threshold terminal THRS is less than or equal to or less than the voltage of the control terminal CV, the output terminal OUT outputs the voltage of the trigger terminal TRIG, and the voltage of the trigger terminal TRIG can be equal to the voltage of the threshold terminal THRS. The control terminal CV can be grounded through the fifth capacitor C5, and the capacitance of the fifth capacitor C5 can be 10nF, but is not limited to this. Furthermore, the power supply terminal Vcc and the reset terminal RST of the NE555 timer IC are both connected to the power supply, and the ground terminal GND is grounded.

[0091] In some embodiments, the discharge terminal DIS of the third integrated circuit chip U5 is connected to the power supply via the tenth voltage divider resistor R10, and / or the positive terminal of the third capacitor C3 is connected to the output terminal of the fourth transistor M4 via the eleventh voltage divider resistor R11. The resistance value of the tenth voltage divider resistor R10 can be 1kΩ, and the resistance value of the eleventh voltage divider resistor R11 can be 10Ω, but is not limited thereto.

[0092] This invention also provides a safety response system for multi-drive systems. Figure 8 The main circuit modules of the safety response system are illustrated, combined with... Figure 1 and Figure 8 As shown, the security response system provided in this embodiment of the invention includes:

[0093] The fault response module 810 is configured to acquire the speed signal of the faulty drive system in response to a fault signal of the multi-drive system.

[0094] As described in any of the above embodiments, the safety response triggering circuit, wherein the pulse conversion circuit 100 is connected to the fault response module 810, and the trigger signal output by the signal latching circuit 300 includes a first trigger signal (e.g., a first trigger signal in the form of a first constant voltage) and a second trigger signal (e.g., a second trigger signal in the form of a second constant voltage).

[0095] The safety policy module 830 is configured to trigger the fault drive system 860 to enter a first safety state based on a first trigger signal, and to trigger the fault drive system 860 to enter a second safety state based on a second trigger signal.

[0096] The safety policy module 830 can directly control the fault drive system 860 to enter the corresponding safety state; or, the safety policy module 830 can output the corresponding safety policy signal according to the trigger signal, and then the subsequent safety logic circuit can control the fault drive system 860 to enter the corresponding safety state according to the safety policy signal.

[0097] The safety response system of the present invention can automatically trigger the faulty drive system to accurately enter the corresponding safety state based on the speed signal of the faulty drive system, avoid reverse torque and back electromotive force, meet the requirement that the failure of some drive systems does not affect the operation of other drive systems, and enable multiple drive systems to exert their maximum drive advantages.

[0098] The safety response system of the present invention is particularly suitable for dual-drive systems, which can ensure that the failure of one drive system does not affect the normal operation of the other drive system, thus greatly improving the performance of dual-drive systems.

[0099] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A safety response trigger circuit for a multi-drive system, characterized in that, include: The pulse conversion circuit is configured to convert the rotation speed signal into a pulse signal; A pulse width comparison circuit is connected to the pulse conversion circuit. The pulse width comparison circuit is configured to generate a corresponding trigger signal based on the relationship between the frequency of the pulse signal and a frequency threshold. Wherein, the speed signal is the speed signal of the faulty drive system of the multi-drive system, and the trigger signal is used to trigger the faulty drive system to enter the corresponding safe state; A signal latch circuit, connected to the pulse width comparison circuit, is configured to latch the received trigger signal and periodically output the latest trigger signal.

2. The safety response trigger circuit as described in claim 1, characterized in that, The pulse conversion circuit includes: A first comparator receives the rotation speed signal and a first threshold signal at its two input terminals, and outputs the pulse signal at its output terminal.

3. The safety response trigger circuit as described in claim 2, characterized in that, The first threshold signal is determined based on the critical speed, and the relationship between the speed signal and the critical speed determines the fault drive system to enter the corresponding safe state.

4. The safety response trigger circuit as described in claim 2 or 3, characterized in that, The first threshold signal is generated by the series connection of two voltage divider resistors connected in series with the power supply.

5. The safety response trigger circuit as described in claim 1, characterized in that, The pulse width comparison circuit includes: A first integrated circuit chip is connected between the output terminal of the pulse conversion circuit and the input terminal of the signal latch circuit; When the frequency of the pulse signal is greater than and less than the frequency threshold, the first integrated circuit chip outputs a first trigger signal for triggering the fault drive system to enter a first safe state and a second trigger signal for triggering the fault drive system to enter a second safe state.

6. The safety response triggering circuit as described in claim 5, characterized in that, The pulse width comparison circuit further includes: The first charging and discharging circuit is connected between the output terminal of the pulse conversion circuit and the threshold terminal of the first integrated circuit chip. When the frequency of the pulse signal is greater than and less than the frequency threshold, the first charging and discharging circuit charges and discharges respectively, so that the voltage at the threshold terminal of the first integrated circuit chip is greater than and less than the first control voltage, so that the first integrated circuit chip outputs the first trigger signal and the second trigger signal respectively.

7. The safety response trigger circuit as described in claim 6, characterized in that, The first charging and discharging circuit includes: The first transistor, the control terminal of the first transistor is connected to the output terminal of the pulse conversion circuit; The first capacitor is connected in parallel between the input and output terminals of the first transistor. The positive terminal of the first capacitor is connected to the threshold terminal of the first integrated circuit chip and connected to the power supply through at least one voltage divider resistor. The negative terminal of the first capacitor is grounded. When the frequency of the pulse signal is greater than the frequency threshold, the first transistor is turned off, the first capacitor is charged, and the voltage at the threshold terminal of the first integrated circuit chip is greater than the first control voltage. When the frequency of the pulse signal is less than the frequency threshold, the first transistor is turned on, the first capacitor is discharged, and the voltage at the threshold terminal of the first integrated circuit chip is less than the first control voltage.

8. The safety response trigger circuit as described in claim 6, characterized in that, The first integrated circuit chip is an NE555 timer integrated circuit. The trigger terminal of the NE555 timer integrated circuit is connected to the output terminal of the pulse conversion circuit, and the output terminal of the NE555 timer integrated circuit is connected to the input terminal of the signal latch circuit. The first control voltage is the voltage of the control terminal of the NE555 timer integrated circuit. When the voltage at the threshold terminal of the first integrated circuit chip is greater than the first control voltage, the first integrated circuit chip outputs the first trigger signal, which is a constant voltage. When the voltage at the threshold terminal of the first integrated circuit chip is less than the first control voltage, the first integrated circuit chip outputs the second trigger signal, which is the voltage at the trigger terminal of the NE555 timer integrated circuit.

9. The safety response trigger circuit as described in claim 6, characterized in that, The first trigger signal is a constant voltage, and the second trigger signal is a pulse signal received by the first integrated circuit chip; The pulse width comparison circuit further includes: A constant voltage conversion circuit is connected between the output terminal of the first integrated circuit chip and the input terminal of the signal latch circuit. The constant voltage conversion circuit is configured to convert the received constant voltage into a first trigger signal in a first constant voltage form, and to convert the received pulse signal into a second trigger signal in a second constant voltage form.

10. The safety response trigger circuit as described in claim 9, characterized in that, The constant voltage conversion circuit includes: The second charging and discharging circuit is connected to the output terminal of the first integrated circuit chip; The second comparator has two input terminals connected to the second charging / discharging circuit and receiving the second threshold signal, respectively. When the second charging and discharging circuit receives the constant voltage and the pulse signal respectively, the voltage output by the second charging and discharging circuit to the second comparator is greater than and less than the second threshold signal respectively, so that the second comparator outputs the first trigger signal in the form of the first constant voltage and the second trigger signal in the form of the second constant voltage respectively.

11. The safety response trigger circuit as described in claim 10, characterized in that, The second charging and discharging circuit includes: The control terminal of the second transistor is connected to the output terminal of the first integrated circuit chip; The second capacitor is connected in parallel between the input and output terminals of the second transistor. The positive terminal of the second capacitor is connected to the positive terminal of the second comparator and connected to the power supply through the fifth voltage divider resistor. The negative terminal of the second capacitor is grounded. When the second charging and discharging circuit receives the constant voltage, the second transistor remains off, the second capacitor remains charged, making the voltage at the positive terminal of the second comparator greater than the second threshold signal, and the second comparator outputs the first trigger signal in the form of the first constant voltage. When the second charging and discharging circuit receives the pulse signal, the second transistor is turned on and off, the second capacitor is discharged and charged, so that the voltage at the positive terminal of the second comparator is less than the second threshold signal, and the second comparator outputs the second trigger signal in the form of the second constant voltage. The second constant pressure is less than the first constant pressure.

12. The safety response trigger circuit as described in claim 11, characterized in that, A sixth voltage divider resistor is connected in series between the control terminal of the second transistor and the output terminal of the first integrated circuit chip, and / or a seventh voltage divider resistor is connected in parallel between the second capacitor and the second transistor.

13. The safety response trigger circuit as described in claim 1, characterized in that, The signal latching circuit includes: The second integrated circuit chip is connected to the output of the pulse width comparison circuit. The second integrated circuit chip is configured to latch the received trigger signal and output the latest trigger signal based on the periodically generated activation signal.

14. The safety response trigger circuit as described in claim 13, characterized in that, The second integrated circuit chip is a rising edge triggered D flip-flop. The set terminal of the rising edge triggered D flip-flop is connected to the output terminal of the pulse width comparator circuit. The clock signal input terminal of the rising edge triggered D flip-flop receives the activation signal, which is a rising edge signal.

15. The safety response trigger circuit as described in claim 13, characterized in that, The activation signal is generated by a timed reset circuit, which includes: The third integrated circuit chip is connected to the second integrated circuit chip; A charge / discharge interlock circuit is connected to the threshold terminal of the third integrated circuit chip; As the charge-discharge interlock circuit operates, the voltage at the threshold terminal of the third integrated circuit chip periodically satisfies a preset relationship with the second control voltage, causing the third integrated circuit chip to periodically output the activation signal.

16. The safety response trigger circuit as described in claim 15, characterized in that, The charge / discharge interlock circuit includes: The third transistor has its control terminal connected to the discharge terminal of the third integrated circuit chip, its input terminal connected to the power supply via the eighth voltage divider resistor, and its output terminal grounded. The fourth transistor has its control terminal connected to the input terminal of the third transistor, and its input terminal connected to the power supply. The third capacitor has its positive terminal connected to the threshold terminal of the third integrated circuit chip and the output terminal of the fourth transistor, and connected to the discharge terminal of the third integrated circuit chip via the ninth voltage divider resistor. The negative terminal of the third capacitor is grounded. The third transistor and the fourth transistor are alternately turned on, so that the voltage at the threshold terminal of the third integrated circuit chip periodically satisfies the preset relationship with the second control voltage.

17. The safety response trigger circuit as described in claim 16, characterized in that, The third integrated circuit chip is an NE555 timer integrated circuit, and the second control voltage is the voltage at the control terminal of the NE555 timer integrated circuit; When the voltage at the threshold terminal of the third integrated circuit chip is greater than the second control voltage, the third integrated circuit chip outputs the activation signal.

18. The safety response trigger circuit as described in claim 16, characterized in that, The discharge terminal of the third integrated circuit chip is connected to the power supply via the tenth voltage divider resistor, and / or the positive terminal of the third capacitor is connected to the output terminal of the fourth transistor via the eleventh voltage divider resistor.

19. A safety response system applied to a multi-drive system, characterized in that, include: The fault response module is configured to acquire the speed signal of the faulty drive system in response to a fault signal from the multi-drive system. ； The safety response triggering circuit as described in any one of claims 1-18, wherein the pulse conversion circuit of the safety response triggering circuit is connected to the fault response module, and the trigger signal output by the signal latching circuit of the safety response triggering circuit includes a first trigger signal and a second trigger signal; The security policy module is configured to trigger the fault-driven system to enter a first security state based on the first trigger signal, and to trigger the fault-driven system to enter a second security state based on the second trigger signal.

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