Level shifter circuit

Abstract

The invention provides a level shifter test circuit, a method of testing the level shifter test circuit, and a semiconductor chip. The circuit includes a first level shifter for converting a signal from a first domain to a second domain. The first level shifter is configured to receive the signal from the first domain as an input and output a converted signal that has been converted by the first level shifter for the second domain, where the converted signal is divided into a first output signal and a first level shifter feedback signal. The circuit additionally includes test logic configured to receive the first level shifter feedback signal and test operation of the first level shifter.

Description

Technical Field

[0001] This disclosure relates to an apparatus and method for a level shifter circuit, the level shifter circuit including feedback for testing the performance of the level shifter. Background Technology

[0002] In existing system-on-a-chip (SoC) devices, multiple power domains may intersect. Typically, this occurs at the interface between digital synthesis logic and analog macros. These interfaces are often not structurally tested, leaving gaps in fault coverage during production testing and functional safety (ISO 26262) related self-testing. Summary of the Invention

[0003] According to a first aspect, a level shifter test circuit is provided. The circuit includes a first level shifter for converting a signal from a first domain to a second domain. The first level shifter is configured to receive the signal as input from the first domain and output a converted signal converted for the second domain by the first level shifter, wherein the converted signal is divided into a first output signal and a first level shifter feedback signal. The circuit further includes test logic configured to receive the first level shifter feedback signal and test the operation of the first level shifter.

[0004] Optionally, the level shifter test circuit further includes feedback logic functionality. Optionally, said feedback logic functionality includes XOR logic gates.

[0005] Optionally, the level shifter test circuit further includes a gate for protecting the first output signal in a safe state, the gate comprising: a protection logic gate configured to receive the first output signal and protect the first output signal in the safe state; and

[0006] The terminal gate feedback logic gate; wherein the output signal from the protection logic gate is divided into a protected first output signal and a first terminal gate feedback signal, wherein the first terminal gate feedback signal is guided to the terminal gate feedback logic gate.

[0007] Optionally, the level shifter test circuit further includes: a second level shifter for converting the second signal from the first domain to the second domain, the second level shifter being configured to receive the second signal as input from the first domain; and

[0008] The output is a second converted signal that has been converted for the second domain, wherein the second converted signal is divided into a second output signal and a second level shifter feedback signal; and wherein the test logic receives the second level shifter feedback signal. Optionally, a logic gate is further included that concatenates the first level shifter feedback signal and the second level shifter feedback signal.

[0009] Optionally, the level shifter test circuit further includes a second gate for protecting the second output signal. The second gate includes: a second protection logic gate configured to receive the second output signal and protect it in the safe state; and a second gate feedback logic gate; wherein the output from the second protection logic gate is split into a protected second output signal and a second gate feedback signal directed to the second gate feedback logic gate; and wherein the second gate feedback logic gate is configured to receive a first gate feedback signal from the first gate and concatenate this first gate feedback signal with the second gate feedback signal. Optionally, the gate is supplied with a clamping signal, wherein the clamping signal enables the safe state when set to a value of zero and disables the safe state when set to a value of one.

[0010] Optionally, the level shifter test circuit further includes a feedback circuit, which includes feedback logic gates for combining feedback signals. Optionally, it further includes: a second domain input signal for sending to the first domain; and a multiplexer for disabling the combined feedback circuit if the device is not in a safe state.

[0011] Optionally, the level shifter test circuit may further include a buffer and one or more electrostatic discharge protectors.

[0012] Optionally, the level shifter test circuit is further configured to measure the silicon processing speed based on the level shifter feedback signal.

[0013] Optionally, the test logic is a scannable register.

[0014] According to a second aspect, a method for testing a level shifter circuit is provided. The method includes: providing a first input signal to a first level shifter and converting the first input signal from a first domain to a second domain, wherein an output signal from the first level shifter is split into a first output signal in the second domain and a first level shifter feedback signal for testing the operation of the first level shifter; receiving the first level shifter feedback signal at a first test logic; and determining whether the level shifter circuit is operating based on the output of the test logic.

[0015] According to the third aspect, there exists a semiconductor chip that includes the level shifter circuit described in the first aspect. Attached Figure Description

[0016] A more complete understanding of the subject matter can be obtained by referring to the specific embodiments and claims considered in conjunction with the following figures, in which similar reference numerals refer to similar elements in each figure.

[0017] Figure 1 A schematic diagram of a level shifter test circuit including a feedback signal according to an embodiment of the present disclosure is shown.

[0018] Figure 2 A circuit diagram of a level shifter test circuit according to an embodiment of the present disclosure is shown;

[0019] Figures 3A to 3C An alternative circuit diagram of a level shifter feedback circuit according to an embodiment of the present disclosure is shown. Detailed Implementation

[0020] The following detailed description is illustrative in nature and is not intended to limit the subject matter or the application and use of such embodiments. As used herein, the terms "exemplary" and "example" mean "serving as an example, instance, or illustration." Any embodiment described herein as exemplary or illustrative should not necessarily be construed as preferred or advantageous over other embodiments. Furthermore, there is no intention to be bound by any express or implied theory presented in the foregoing technical field, background art, or the following detailed description.

[0021] This disclosure proposes a level shifter design with an incorporation feedback path. This allows for coverage of the level shifter circuitry and the receiving power domain during structural tests, such as production scan tests or logic-built-in self-test (Logic-BIST). A device is provided that acts as a level shifter between power domains while allowing structural test coverage of the structure during production testing and field logic testing. This helps reduce field returns while improving time-of-failure (FIT) detection capability.

[0022] The proposed design can implement two feedback circuits: one feedback circuit is directly after the level shifter circuit, and a second optional feedback circuit is used to provide coverage when the output signal is in a safe state.

[0023] This disclosure contributes to improved security and secure applications, where feedback signals collected from various points throughout the circuit can be used to identify unexpected or malicious input vectors. The feedback signals can be used, for example, for fault detection by examining interface signal input vectors.

[0024] Figure 1A schematic diagram of a level shifter test circuit 100 including a feedback signal according to an embodiment of the present disclosure is shown. The level shifter test circuit 100 includes a level shifter 110 and test logic 120. The level shifter 110 receives an input signal 112 from a first domain (also referred to as the primary voltage domain) and outputs a converted signal converted for a second domain (also referred to as the secondary voltage domain), wherein the output signal is split into a first output signal 114 for the second domain and a first level shifter feedback signal 116. In one example, the first domain is a low voltage domain and the second domain is a high voltage domain. In an alternative example, the first domain is a high voltage domain and the second domain is a low voltage domain. Other alternatives include where the first domain is a low voltage domain and the second domain is a low voltage domain.

[0025] A method for testing a level shifter test circuit 100 includes providing a first input signal 112 to a first level shifter 110 and converting the first input signal 112 from a first domain to a second domain, wherein an output conversion signal from the first level shifter 110 is split into a first output signal in the second domain 114 and a first level shifter feedback signal 116 for testing the operation of the first level shifter 110. The first level shifter feedback signal 116 is received at a first test logic 120. At the test logic 120, it is determined whether the level shifter circuit is operating based on the output of the test logic.

[0026] The level shifter 110 can be implemented as one of many alternative configurations. For example, when the primary voltage domain is low and the secondary voltage domain is high, the level shifter can be implemented as a latch. When the primary and secondary voltage domains are similar in voltage, the level shifter can be implemented as a buffer. Other alternatives include buffered low-to-high level shifters, buffered high-to-low level shifters, power and ground level shifter units, multi-bit level shifter units, overdriven level shifter units, enabled level shifter units, and differential level shifter units. Where clamping is required, a latch-based level shifter may be preferred (clamping is described in more detail later). Multi-bit level shifter methods can be implemented in embodiments that include multiple level shifter circuits. Using multi-bit level shifters can help save space and reduce circuit size.

[0027] Feedback signal 116 is an input signal to test logic 120. Test logic 120 is configured to receive the first level shifter feedback signal 116 to test the operation of the first level shifter 110. Test logic 120 includes components suitable for monitoring the current interface state of the signal. In one example, test logic 120 is a scannable register (e.g., a digital register such as a flip-flop) that allows real-time readback of the feedback signal value. In another example, test logic 120 is a chip-level pin that exposes the signal. In yet another example, test logic 120 is a logic gate, such as an XOR logic gate.

[0028] To test feedback signal 116, the measured signal value at the scannable register of test logic 120 is compared with the expected value. The expected value depends on the given input vector. In some examples, the input vector is bound to a static value (e.g., logic 1 or logic 0). If the feedback signal 116 received at test logic 120 does not read the expected value, a fault (e.g., a defect) can be identified.

[0029] In a scan configuration (logic-BIST or production test / ATPG), feedback signal 116 is used to derive a pass / fail signature at test logic 120. During functional testing, feedback signal 116 is actively read by the controller (e.g., CPU) at test logic 120 and compared to the expected value.

[0030] If the test is performed in the first domain, the feedback signal 116 needs to be level-shifted back to the primary voltage domain so that it is consumed there and fed back to the first domain. If a defect exists in the feedback signal, this will be detected, and it will be determined that the circuit is not working. If no defect exists, it will be determined that the circuit is working as it should.

[0031] In digital electronics, level shifters are circuits used to convert signals from one logic level or voltage domain to another, thereby allowing compatibility between integrated circuits with different voltage requirements. Level shifter designs, including test feedback logic, are used in... Figure 1 As shown in the image. Figure 1 The feedback signal 116 is directed toward the secondary power domain after the level shifting circuit 110. The feedback signal is designed to capture digital cell switching activity during structural testing, such as during production scan testing or Logic Built-in Self-Test (BIST) (where hardware and / or software are built into an integrated circuit, allowing the integrated circuit to test its own operation, as opposed to relying on external automated test equipment).

[0032] Soft defects (also known as transient defects) and latent defects can be found using a level shifter test circuit 100, where feedback signal 116 includes these defects. Soft defects are defects that may not be (fully) reproducible. For example, the logic state in a circuit may change due to radiation. Soft defects can be, for example, soft error rates caused by the effects of particle impacts in sensitive areas of submicroelectronic circuits. Latent defects are defects that were not screened out during production and may develop during the life of the device. Transition or path delay defects may be caused by bias temperature instability (BTI). If a defect is present, the test logic will detect its presence.

[0033] Figure 2 A circuit diagram of a level shifter test circuit 200 according to an embodiment of the present disclosure is shown. Figure 2 The level shifter test circuit 200 will Figure 1 The level shifter test circuit 100 is implemented in a standard cell. In addition to the level shifter 110 and feedback logic gate 122, the level shifter test circuit 200 includes a buffer 202 in the first domain and an electrostatic discharge (ESD) protector 204 in the second domain. Test logic 120 is not shown in this example. The buffer 202 replicates the digital signal and increases tolerance to degradation caused by other circuitry. The ESD protector 204 protects the transistor from damage during an ESD event. Feedback logic gate 122 is used to cascade the signal from the level shifter 110 and provides improved area coverage efficiency. Cascading the signal using logic gates allows it to avoid level-shifting every single feedback signal output from the level shifter 110 back to the first domain, which would otherwise consume chip area. Suitable logic functions include, but are not limited to, XOR, NAND, NOR, AND, and OR logic gates.

[0034] During operation, input signal 112 (signal_in) is received from domain 1 at buffer 202. The signal output from buffer 202 at domain 1 is fed to ESD protector 204, and then to level shifter 110. The output signal from level shifter 110 is split into output signal 114 (signal_out) and level shifter feedback signal 116.

[0035] The level shifter feedback signal 116 is fed to the feedback logic function (FB) 122. The feedback logic function 122 includes, but is not limited to, one of the following: XOR, NAND, NOR, AND, or OR logic gates. Also fed to the feedback logic function 122 is the second feedback signal 206, feedback_in, which is a dynamic signal (e.g., a switchable signal). If the level shifter test circuit 200 is the first level shifter test circuit 200, then signal 206 includes a static logic 0 or logic 1. If the level shifter test circuit 200 is the second level shifter test circuit 200 in a set of circuits, then signal 206 is received from the previous level shifter. The feedback signals 116 and 206 received at the feedback logic function 122 are cascaded and output from the feedback logic function 122 as feedback_out. Cascading multiple level shifters has the advantages of reducing the number of signals that need to be shifted back to the primary power domain, saving chip space, and reducing complexity. The output signal (level shifter feedback signal) from feedback logic function 122 is fed to the next level shifter in the stack, or fed to the bottom of the stack, shifted back to the primary voltage domain and consumed by detection circuitry such as a scannable register.

[0036] If the level shifter feedback signal includes a defect, then the level shifter circuit is determined to be faulty. If no defect is found, then the level shifter circuit is determined not to be faulty. Therefore, the circuit enables structural coverage of the interface during production testing, thereby increasing the ability to detect defects in the level shifter circuit.

[0037] Providing the level shifter feedback signal in the described manner allows for in-circuit testing. This is advantageous because it eliminates the need to shut down other parts of the chip during testing.

[0038] Figure 2 Includes horizontal units. Additional units can be added to the test circuit 200 above or below the circuit 200. Feedback from the additional units is cascaded between adjacent units at feedback logic function 122.

[0039] Figure 2 Alternatives to the circuit shown include the placement of buffer 202, which may be located in the first domain instead of the second domain. In other alternatives, the buffer may be another functional logic located in either the first or second domain. Another ESD protector 204 may also be present in the first domain, for example, before the signal reaches buffer 202.

[0040] Figure 3A A circuit diagram of a level shifter test circuit according to an embodiment of the present disclosure is shown. Figure 3A The embodiment shown is Figure 1 and Figure 2 An extension of the level shifter test circuit shown.

[0041] The circuit includes horizontal units C1, C2, C3, and C4. Units C1 and C2 include level shifter circuits, while units C3 and C4 include feedback circuits. Figure 3A In the illustrated embodiment, all feedback logic functions, including logic gates, are indicated by the symbol "FB". The type of feedback logic function will depend on its location in the circuit and is interchangeable.

[0042] The input signals of the level shifter circuit include the input signals In that are respectively input to cells C1 and C2 on the first domain side of the circuit. C1 and In C2 Output signal Out C1 and Out C2 Outputs are taken from units C1 and C2 respectively. Unit C3 receives the input signal In from the second domain. C3 And output Out C3 Unit C4 has only the feedback signal Out. C4 One of the output signals.

[0043] Signals are also applied to the circuitry and fed onto the cells. These signals include the power supply (SUP) signal and the dynamic feedback signal FB. D (It can be switched), clamping signal and static feedback signal FB S (It cannot be switched). The power supply signal acts as a power supply presence indicator and can be used, for example, to disable the output in the event of a power loss (e.g., Figure 3A , Figure 3B , Figure 3C Output signal Out C3 and Out C4 Feedback signal FB D FB S It can be a static connection signal, an input from an adjacent level shifter, or another logic signal whose behavior is deterministic and known. In FB... D FB S Given the signals, this can be used to determine the output signals Out from C3 and C4 respectively. C3 and Out C4 The obtained signature. The clamp signal is a control signal used to enable or disable the safety state function of the level shifter output circuit. The clamp signal enables the safety state when set to a value of zero, and disables the safety state when set to a value of one.

[0044] The first unit C1 and the second unit C2 include components for transmitting the input signal In C1 In C2Test circuit for level shifters that convert from the first domain to the second domain. Output signal Out. C1 and Out C2 Output from C1 and C2 respectively. Figure 3A The level shifter test circuit includes the circuit described above. Figure 2 Components. Besides Figure 2 In addition to the level shifter circuit, ESD protection is provided on the first domain side of the circuit before the signal reaches the buffer. Figure 3A In the embodiment shown, the buffer is located in the first domain. Buffer 202 may be placed in domain 1 and / or domain 2. In domain 2, for example, the ESD and level shifter (L / S) may be bundled together in C1, or the ESD and L / S may be placed as separate elements. Many alternative arrangements are possible and are taken into consideration by this disclosure.

[0045] Unit C1 includes a first feedback logic function, and unit C2 includes a second feedback logic function. Each of the logic functions is one of an XOR, NAND, NOR, AND, or OR logic gate. The first feedback logic function feeds back the signal FB. D The feedback signal (first level shifter feedback signal) from the first level shifter in the first unit C1 is used as input. Feedback signal FB D This includes a logic 0 or logic 1 value. The second feedback logic function takes the feedback signal FB from the first logic function of the first unit C1. D The output of the series connection of the feedback signal of the first level shifter of C1 and the feedback signal of the second level shifter from the second unit C2 (the feedback signal of the second level shifter) are used as inputs.

[0046] Figure 3A The diagram also shows end gates at the ends of units C1 and C2, which are... Figure 2 Additional features of the circuit shown. Terminal gates are used to secure the output signal from the level shifter circuit and protect the output signal from intermittent or illegal signal states. The terminal gates include protection logic gates configured to receive the output signal from the level shifter as needed and protect the output signal in a secure state. The protection logic gates receive a clamp signal and the output signal from the level shifter as inputs. The secure-state output signal is Out. C1 Out C2The protection logic gates output from the first unit C1 and the second unit C2, respectively. The terminal gate also includes a terminal gate feedback logic gate (e.g., a logic function). The output signal from the protection logic gate can be divided into the unit's output signal (the protected output signal) and the input signal to the terminal gate's feedback logic gate (the terminal gate feedback signal), the input signal being directed to the terminal gate's feedback logic gate. The feedback logic gate also receives a static feedback signal FB. S The input signal, the static feedback signal FB S This signal can be used to observe the state of the logic behind the terminal gate (protection / safety state circuit). While it's not possible to arbitrarily switch this signal, a defect can still be detected if, for example, the protection provided by the safety state fails to function properly. The terminal gate feedback logic gate outputs a terminal gate feedback signal to determine the terminal gate's performance. Therefore, in addition to the above regarding... Figure 1 and Figure 2 In addition to the first feedback circuitry of the described level shifter, the gate also provides a second feedback circuitry. This second-level feedback circuitry provides overlay when the output signal is in a safe state. Defects here will cause the second-level feedback circuitry to change its state compared to the expected state, making it possible to identify defects. Detected defects include design-for-test (DfT) defects such as bridging, disconnection, or jamming faults. If the output of C1 (due to a defect) produces a logic 1 instead of a logic 0, the second-level feedback circuitry will reflect this. Similarly, if the output of C1 (due to a defect) follows the input of C1 instead of a logic 0, the second-level feedback circuitry will also reflect this. This knowledge is used to detect defects in the gate circuitry.

[0047] To establish a safe state for the signal, a clamp signal is used. The clamp signal is input to the protection logic gate at the end gate, and the clamp signal can have a value of either "logic 0" or "logic 1". When the clamp signal equals logic 0, the signal is protected in a safe state. This safe state signal is fed back to the primary side. If safe state establishment is no longer needed, the clamp signal can be set to logic 1, and the end gate's output signal will follow the end gate's input signal, i.e., the output signal from the level shifter. The clamp signal affects all units such that if the clamp signal equals logic 0, all level shifters in the device are in a safe state (and vice versa).

[0048] The gates of unit C1 include protection logic gates as AND gates, while the gates of unit C2 include protection logic gates as OR gates, where one of the signals is inverted. A "0" in the C1 logic gate and a "1" in the C2 logic gate indicate that once the clamp signal is active (i.e., the clamp signal has a value of 0), the outputs (Out) of C1 and C2 will be... C1 Out C2 The expected safe value at )

[0049] The first terminal feedback logic gate (of unit C1) includes the feedback signal FB. S The first gate feedback signal (from the output of the protection logic gate of unit C1) serves as input to the functional logic. These signals can be cascaded and output from the first gate feedback logic gate of unit C1. The second gate feedback logic gate (of unit C2) includes functional logic that receives the second gate feedback signal (from the output of the second protection logic gate of unit C2) and the output of the first gate feedback logic gate of unit C1 as inputs. The cascaded output signal from the second gate feedback logic gate includes FB. S The first gate feedback signal (of unit C1) and the second gate feedback signal (of unit C2).

[0050] Any number of units similar to units C1 and C2, including level-shifting test circuitry, can be added above and / or below units C1 and C2. Feedback signals from each additional unit can be cascaded in the same manner as described above. However, the number of units that will affect the timing arc of the circuit should be considered, as the timing arc depends on the number of level shifters and gates present in the test circuit. For example, a timing arc includes the amount of time it takes for a signal input at unit C1 to be output at unit C4. More units will increase the duration of the timing arc, while fewer units will decrease its duration.

[0051] Unit C3 includes a first feedback unit. Signal In C3 The input is from the second domain and sent to the first domain. Feedback from the level shifter circuit and from the terminal gates of C1 and C2 are combined, for example, in series, at the feedback logic function FB in cell C3. The output of the feedback logic gate includes all the feedback signals as a whole.

[0052] A multiplexer is also used in this unit. The multiplexer receives: a series feedback signal from the feedback logic function FB, an input signal from the second domain, and a clamp signal. If the clamp signal is logic 0 (the gate is in a safe state), unit C3 acts as a feedback unit, providing the series feedback signal received from units C1 and C2 for testing. If the clamp signal is logic 1 (not in a safe state), C3 acts as a normal level shifter from domain 2 to domain 1, and outputs the signal at the Out position. C3 No feedback signal is provided.

[0053] After passing through the multiplexer, the signal passes through the ESD protector and the AND gate, and is output as the signal. C3Output. The level-shifting function for transmitting the signal from the second domain back to the first domain can be implemented by the electrical characteristics of the AND gate in domain 1 of unit C3 (and unit C4 described below). This can depend on the primary domain voltage and the secondary domain voltage, etc. In other embodiments, an alternative is to additionally include a latch in the feedback circuit. The implementation is determined by the voltages of the various circuits.

[0054] If there are defects in the feedback signal, these defects will be present in the output signal Out. C3 In production testing, deviations from the expected signature will result in test failure and can filter out defective devices. In security applications, deviations from the expected result can escalate to a security monitor, and a switch can be moved to a safe state. For fault analysis, signals can be evaluated against different input vectors to pinpoint the location of the defect. For example, individual units can be tested to determine where the faulty part of the circuit is located.

[0055] Unit C4 is also a feedback unit similar to C3. However, unit C4 does not include the input signal from the second domain. Feedback logic gates are used to combine (e.g., cascade) the feedback signals from the level shifter and the terminal gates of units C1 and C2 as the output signal Out. C4 Output. The signal passes through an ESD combiner and an AND gate, similar to unit C3.

[0056] If the feedback signal output from unit C4 is Out C4 Defects, in particular, can be detected in a manner similar to that of unit C3.

[0057] It can be connected in series at the logic gates in the signal path based on the cascade chain using the level shifter feedback path and at the signal Out. C3 Out C4 The silicon processing speed is calculated using the level shifter feedback signal output from the chip. The absolute duration of the timing arc (from the first level shifter to the point where feedback is collected) can be measured using on-chip instruments. This duration is process-dependent, temperature-dependent, and voltage-dependent, and can be used for characterization. Depending on the silicon processing speed, the duration is a measure of voltage, and this disclosure can also be used as a tamper detector to detect whether the voltage has been tampered with (for security applications).

[0058] Horizontal layers C1, C2, C3, and C4 are standard units, delivered to approved standards for all corners related to functional and test operations. This includes shielding corners such as very low voltage (VLV) and high voltage stress (HVST) tests, under which the level shifter must be fully operational.

[0059] Apart from Figure 3AIn addition to those shown, combinations of different units are also possible. For example, only one of units C3 and C4 may exist, or other units C1 and C2 may exist.

[0060] Figure 3A The units C1 and C2 shown include the same components; however, in some cases, the components may differ between the units.

[0061] Figure 3A The specific implementation depends on the technology library, where different types of gates can be more or less area- and timing-sensitive. Many implementations are possible and can be optimized based on area, speed, or other factors. Figure 3B The implementation showing all logic gates of the circuit, including the XOR gate, is shown. Figure 3A The circuit.

[0062] Figure 3C The implementation scheme is shown Figure 3A The circuit contains level shifter feedback logic gates in C1 and C2, as well as logic gates in feedback units C3 and C4, including XOR logic gates. However, the terminal feedback logic gates include an OR gate in unit C1 and an AND gate with an inverting input in unit C2. Typically, XOR gates are larger than AND, NAND, OR, and NOR gates. Figure 3C This can be particularly beneficial when optimization space is required. This particular configuration is made possible by secondary feedback with fixed and known output values ​​in a safe state (which is static and cannot be toggled).

[0063] Using different types of logic gates, and Figure 3B and Figure 3C Many different configurations are possible, as illustrated. Depending on the technology library, some doors are more area- and time-efficient than others. Different implementations are possible and can be optimized for factors such as area and speed. This paper considers all such configurations.

[0064] The apparatus shown in any of the above figures exists on a semiconductor chip and is used to produce scan tests or logic BISTs.

[0065] It will be readily understood that the components of the embodiments generally described herein and illustrated in the accompanying drawings can be arranged and designed in a wide variety of different configurations. Therefore, the detailed descriptions of the various embodiments illustrated in the figures are not intended to limit the scope of this disclosure, but merely to illustrate various embodiments. While various aspects of the embodiments are presented in the figures, the figures are not necessarily drawn to scale unless specifically indicated otherwise.

[0066] The invention may be embodied in other specific forms without departing from its essential characteristics. The described embodiments are to be regarded in all respects as illustrative rather than restrictive. Therefore, the scope of the invention is indicated by the appended claims rather than by the detailed description herein. All variations existing within the equivalent meaning and scope of the claims are to be included within the scope of the claims.

[0067] Throughout this specification, references to features, advantages, or similar language do not imply that all features and advantages achievable through the invention should be, or are present in, any single embodiment of the invention. In fact, references to such features and advantages should be understood as indicating that a specific feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the invention. Therefore, throughout this specification, discussions of features and advantages, and similar language, may, but do not necessarily refer to the same embodiment.

[0068] Furthermore, the features, advantages, and characteristics described in this invention may be combined in any suitable manner in one or more embodiments. Those skilled in the art will recognize that, in view of the description herein, this invention may be practiced without one or more specific features or advantages of a particular embodiment. In other instances, additional features and advantages in certain embodiments that may not be present in all embodiments of the invention may be appreciated.

Claims

1. A level shifter test circuit, characterized in that, include: A first level shifter, used to convert a signal from a first domain to a second domain, is configured to: Receive the signal as input from the first domain; as well as The output is a converted signal that has been converted for the second domain by the first level shifter, wherein the converted signal is divided into a first output signal and a first level shifter feedback signal; as well as The test logic is configured to receive the feedback signal from the first level shifter and test the operation of the first level shifter.

2. The level shifter test circuit according to claim 1, characterized in that, Additionally, it includes an end gate for protecting the first output signal in a safe state, the end gate comprising: A protection logic gate, configured to receive the first output signal and protect the first output signal in the safe state; and End gate feedback logic gate; The output signal from the protection logic gate is divided into a protected first output signal and a first gate feedback signal; and The first end gate feedback signal is guided to the end gate feedback logic gate.

3. The level shifter test circuit according to claim 1, characterized in that, In addition, including: A second level shifter, used to convert a second signal from the first domain to the second domain, is configured to: Receive the second signal as input from the first domain; and The output is a second converted signal that has been converted for the second domain, wherein the second converted signal is divided into a second output signal and a second level shifter feedback signal; and The test logic is configured to receive the feedback signal from the second level shifter.

4. The level shifter test circuit according to claim 3, characterized in that, Additionally, a second terminal gate is included for protecting the second output signal, the second terminal gate comprising: A second protection logic gate is configured to receive the second output signal and protect the second output signal in the safe state; and Second-end gate feedback logic gate; The output from the second protection logic gate is divided into a protected second output signal and a second terminal feedback signal guided to the second terminal feedback logic gate; and The second terminal gate feedback logic gate is configured to receive the second terminal gate feedback signal.

5. The level shifter test circuit according to claim 1, characterized in that, Additionally, a feedback circuit is included, which includes feedback logic gates for combining feedback signals.

6. The level shifter test circuit according to claim 5, characterized in that, The feedback circuit further includes: The second domain input signal is used to send to the first domain; and A multiplexer for disabling the feedback circuit when the device is not in a safe state.

7. A method for testing a level shifter circuit, characterized in that, The method includes: The first input signal is provided to the first level shifter, and the first input signal is converted from the first domain to the second domain, wherein the output conversion signal from the first level shifter is divided into a first output signal in the second domain and a first level shifter feedback signal for testing the operation of the first level shifter; The first level shifter feedback signal is received at the first test logic; and The output of the test logic is used to determine whether the level shifter circuit is working.

8. The method according to claim 7, characterized in that, Additionally, the first output signal is protected in a safe state by means of the following methods: The first output signal is received at the protection logic gate, and the first output signal is protected in the safe state. as well as The output signal from the protection logic gate is divided into a protected first output signal and a first gate feedback signal; and The first end gate feedback signal is guided to the end gate feedback logic gate.

9. The method according to claim 8, characterized in that, Additionally, it includes providing a clamp signal to the protection logic gate, whereby the clamp signal enables the security state when set to a value of zero, and disables the security state when set to a value of one.

10. A semiconductor chip including a level shifter test circuit, characterized in that, include: A first level shifter, used to convert a signal from a first domain to a second domain, is configured to: Receive the signal as input from the first domain; as well as The output is a converted signal that has been converted for the second domain by the first level shifter, wherein The conversion signal is divided into a first output signal and a first level shifter feedback signal; as well as The test logic is configured to receive the feedback signal from the first level shifter and test the operation of the first level shifter.

Images