Inverter and inverter-based ring oscillator
By using NMOS transistor inverter units and temperature compensation mechanisms, the power supply and temperature sensitivity issues of ring oscillators are solved, achieving low noise, low power consumption, and frequency stability, making it suitable for ring oscillators in phase-locked loops.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-12
- Publication Date
- 2026-03-13
AI Technical Summary
The high power supply sensitivity and high temperature sensitivity of ring oscillators lead to noise modulation of the output frequency and frequency drift, increasing system complexity and power consumption.
An inverter unit based on NMOS transistors is used to reduce power supply sensitivity and temperature sensitivity by controlling the bias voltage and capacitor. Frequency tuning and calibration are performed using a variable resistor and capacitor DAC, and the oscillation frequency is stabilized by a temperature compensation mechanism.
It achieves a low-power, low-noise ring oscillator with improved frequency stability, reduced system complexity and power consumption, and adaptability to a wide temperature range.
Smart Images
Figure CN121664176A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to inverter cells and ring oscillators based on inverter cells. More specifically, but not exclusively, this disclosure relates to inverter cells, ring oscillators, and phase-locked loops including ring oscillators that have low sensitivity to fluctuations in supply voltage. Background Technology
[0002] A problem associated with ring oscillators is their high power supply sensitivity. This can create paths for noise or ripple on the supply voltage to modulate the ring oscillator's output frequency. A common way to address this is to add a high power supply rejection ratio (PSRR) low dropout regulator (LDO) and / or an active current source above the ring oscillator to suppress any noise / ripple reaching the ring oscillator supply voltage. This additional circuitry increases the minimum supply voltage requirement to accommodate the high PSRR circuitry, thus limiting the minimum achievable supply voltage for the ring oscillator. In systems that include ring oscillators (e.g., radio transceivers), this additional high PSRR circuitry can limit the minimum achievable supply voltage for the entire system, thereby increasing overall system power consumption.
[0003] Another problem associated with ring oscillators is their high temperature sensitivity. When used in a phase-locked loop (PLL), this means that once the PLL loop is locked, a large temperature drift can cause the PLL to unlock and require relocking. If the PLL is used for timing in the system, relocking results in increased system complexity or loss of timing information. Summary of the Invention
[0004] The appended claims set forth various aspects of this disclosure. Combinations of features from dependent claims may be combined with features of the independent claim as needed, and not merely as expressly stated in the claims.
[0005] According to a first aspect of this disclosure, an inverter is provided, comprising: a first NMOS transistor including a first gate terminal, a first drain terminal, and a first source terminal; an inverter input coupled to the first gate terminal; an inverter output coupled to the first drain terminal; and a second NMOS transistor including a second gate terminal, a second drain terminal, and a second source terminal, wherein the second source terminal is coupled to the first drain terminal.
[0006] By providing an inverter based on a first NMOS transistor (effectively an NMOS driver) and a second NMOS transistor (effectively an NMOS load), the delay between the inverter input and output signals is less sensitive to the inverter's supply voltage. This lower supply sensitivity allows for a reduction in supply voltage and lower power consumption. Similarly, multiple such inverters can form the basis of a ring oscillator with an oscillation frequency less sensitive to supply voltage fluctuations, resulting in a reduction in the ring oscillator's supply voltage. This reduction in supply voltage to the inverter or ring oscillator ultimately leads to lower overall power consumption in devices or systems that include inverters or ring oscillators.
[0007] According to a second aspect of this disclosure, a ring oscillator is provided, comprising: a plurality of inverters arranged in a ring, wherein each inverter includes an inverter input and an inverter output, and wherein the inverter output of each inverter in the ring is coupled to the inverter input of a corresponding next inverter in the ring; and wherein at least one of the plurality of inverters further comprises: a first NMOS transistor including a first gate coupled to the corresponding inverter input, a first drain coupled to the corresponding inverter output, and a first source; and a second NMOS transistor including a second gate, a second drain, and a second source, wherein the second source is coupled to the first drain.
[0008] Because the ring oscillator is less sensitive to power supply voltage, it can provide higher output quality and / or lower power consumption than conventional ring oscillators.
[0009] In some embodiments, the inverter may further include a bias voltage input coupled to the second gate terminal.
[0010] Controlling the bias voltage at the bias voltage input can help control the delay of an inverter or the oscillation frequency of a ring oscillator.
[0011] In some embodiments, the inverter may further include a resistor coupled between the bias voltage input and the second gate terminal.
[0012] By coupling a resistor to the gate of the second NMOS transistor, the inverter gain is increased at the oscillation frequency, which helps to ensure oscillation.
[0013] In some embodiments, the resistor is a variable resistor.
[0014] By changing the resistance, the resistor can be used, for example, to calibrate the delay of an inverter or the oscillation frequency of a ring oscillator during a single-process calibration, because the value of the resistor controls the charging current at the inverter output at the oscillation frequency.
[0015] In some embodiments, the inverter or ring oscillator further includes: a circuit system configured to generate a bias voltage at the bias voltage input, the bias voltage varying with temperature.
[0016] By controlling the bias voltage to vary with temperature, the temperature-dependent variation of the inverter delay can be offset, and thus the temperature-dependent variation of the oscillation frequency of the inverter-based ring oscillator can be offset.
[0017] In some embodiments, the inverter may further include at least one capacitor coupled between the inverter output and a reference voltage.
[0018] The at least one capacitor can be used to set or calibrate the delay of the inverter, or the oscillation frequency or phase of the ring oscillator.
[0019] The at least one capacitor can be coupled to one of the inverter output and the reference voltage via a switch (e.g., a transistor).
[0020] The at least one capacitor may include multiple switched capacitors coupled in parallel. This allows the overall value of the at least one capacitor, in the form of multiple switched capacitors coupled in parallel, to be programmed or controlled via a digital signal through a switch. The at least one capacitor may include a switched capacitor DAC.
[0021] In some embodiments, the inverter may further include at least one variable capacitor coupled between the inverter output and the control voltage.
[0022] In some embodiments, the at least one variable capacitor includes a MOS varactor diode. A control voltage can be coupled to the gate of the MOS varactor diode to control the capacitance of the variable capacitor.
[0023] The at least one variable capacitor can be used to tune the delay of the inverter, or the oscillation frequency or phase of the ring oscillator. For example, when used as a voltage-controlled oscillator in a phase-locked loop or frequency-locked loop, the control voltage can provide phase and / or frequency control of the ring oscillator.
[0024] In some embodiments, the second drain terminal is coupled to the power supply voltage.
[0025] In some embodiments, the first source terminal is coupled to a reference voltage.
[0026] In some embodiments, the ring oscillator further includes: a circuit system including an output coupled to the bias voltage input of the at least one inverter; the circuit system is configured to generate a bias voltage at its output.
[0027] This can provide an additional path for controlling the delay of the inverter and thus the frequency or phase of the ring oscillator.
[0028] In some embodiments, the bias voltage depends on temperature.
[0029] By controlling the bias voltage to vary with temperature, the temperature-dependent variation in inverter delay can be offset, and consequently, the temperature-dependent variation in the oscillation frequency of the inverter-based ring oscillator. There are at least two opposing mechanisms controlling inverter delay: as temperature increases, the threshold voltage decreases, but the mobility also decreases. Whether the bias voltage needs to increase or decrease with temperature depends on the semiconductor process.
[0030] In some embodiments, the bias voltage has a first temperature dependence on temperatures above a predetermined temperature offset and a second different temperature dependence on temperatures below a predetermined temperature offset.
[0031] By independently controlling the temperature dependence of the bias voltage above a predetermined temperature offset (e.g., the operating temperature, such as room temperature) and the temperature dependence of the bias voltage below the predetermined temperature offset, the stability of inverters and ring oscillators relative to temperature variations can be improved. This allows the bias voltage to better accommodate the nonlinear dependence of the inverter drive current with temperature.
[0032] In some embodiments, the circuit system is configured to receive the control voltage and further control the bias voltage based on the control voltage.
[0033] In some embodiments, the circuit system is configured to generate the bias voltage based on a temperature-dependent current.
[0034] The temperature-dependent current can be a current that is proportional to the absolute temperature.
[0035] In some embodiments, the circuit system includes: a first portion configured to generate a bias current based on the temperature-dependent current, wherein the bias current varies linearly with temperature at a first slope at temperatures below the predetermined temperature offset, and wherein the bias current varies linearly with temperature at a second slope at temperatures above the predetermined temperature offset; and a second portion configured to generate the bias voltage based on the bias current.
[0036] In some embodiments, the first portion of the circuit system includes a current subtraction circuit configured to subtract the current, which is proportional to the absolute temperature, from a constant current.
[0037] In some embodiments, the circuit system is configured to receive a control voltage and, depending on the control voltage, control the gain of the bias current.
[0038] This provides an additional path for controlling the inverter's delay and thus the frequency or phase of the ring oscillator. Specifically, by controlling the gain of the temperature-dependent bias current using a control voltage, any frequency or phase drift caused by temperature effects not compensated for solely by the temperature-dependent bias can be corrected. When used in a phase-locked loop (PLL), this additional tuning path can help maintain PLL lock-in over a wider temperature range without requiring recalibration.
[0039] When used as a voltage-controlled oscillator in a phase-locked loop, the control voltage can provide frequency control for the ring oscillator.
[0040] In some embodiments, the circuit system includes at least one RC filter for filtering the bias current.
[0041] This filter slows down the feedback loop of the additional tuning path, ensuring that only slow changes in the control voltage are used to control the inverter's delay via the bias voltage input. Therefore, when a ring oscillator is used in a PLL, the additional tuning path does not affect the PLL's noise performance or loop dynamics. The filter also helps remove any noise generated in the circuit system.
[0042] In some embodiments, the second part includes a replication delay unit, which includes the replication of a first NMOS transistor and a second NMOS transistor.
[0043] Using a replication delay unit helps the bias voltage track the process changes caused by temperature effects in the inverter.
[0044] In some embodiments, the gate and drain terminals of the replicated first NMOS transistor are coupled to the source terminal of the replicated second NMOS transistor; the gate terminal of the replicated second NMOS transistor is coupled to the drain terminal of the second NMOS transistor; and the output of the second portion of the circuit system is coupled to the drain terminal of the second NMOS transistor.
[0045] In some embodiments, the ring oscillator output may be coupled to the inverter output of one of the plurality of inverters of the ring oscillator.
[0046] In some embodiments, the at least one inverter further includes: at least one variable capacitor coupled between the inverter output and a control voltage; and the ring oscillator further includes: a circuit system including an output coupled to a bias voltage input of the at least one inverter; the circuit system being configured to generate a temperature-varying bias voltage at its output; wherein the circuit system is configured to receive the control voltage and control the gain of the bias voltage based on the control voltage.
[0047] Therefore, two paths are provided for controlling the frequency or phase of the ring oscillator via a control voltage. The circuit system may include a low-pass filter so that high-frequency variations in the control voltage are not fed back to the bias voltage input of the inverter.
[0048] According to another aspect of this disclosure, a phase-locked loop is provided, which includes the ring oscillator according to the second aspect of this disclosure.
[0049] The phase-locked loop may further include a phase comparator for outputting a control signal based on the difference between the phase of the signal at the output of the ring oscillator and the phase of a reference signal.
[0050] The phase comparator may include a loop filter for filtering high-frequency components from the control signal.
[0051] In some embodiments, the ring oscillator is coupled to the output of the phase comparator via a first path and a second path.
[0052] In some embodiments, the at least one inverter of the ring oscillator includes a bias voltage input coupled to the second gate terminal; the ring oscillator includes a circuit system including an output coupled to the bias voltage input of the at least one inverter, wherein the circuit system is configured to generate a bias voltage at its output, and wherein the circuit system is configured to receive the control voltage and control the bias voltage based on the control voltage; wherein the circuit system is configured to receive the control voltage via the second path.
[0053] It will be understood that any feature described herein that is suitable for inclusion in one or more aspects or embodiments of this disclosure is intended to be generalizable across any and all aspects and embodiments of this disclosure. Other aspects of this disclosure will be understood by those skilled in the art based on the specification, claims, and drawings of this disclosure. The foregoing general description and the following detailed description are exemplary and explanatory only and do not limit the scope of the claims. Attached Figure Description
[0054] Exemplary embodiments of this disclosure will be described by way of example only with reference to the accompanying drawings, in which similar reference numerals denote similar elements, and in the drawings:
[0055] Figure 1 A ring oscillator according to an exemplary embodiment of the present disclosure is schematically shown;
[0056] Figure 2 A delay unit including an inverter is schematically shown according to an exemplary embodiment of the present disclosure;
[0057] Figure 3A current subtraction circuit (top) is schematically shown, the current subtraction circuit including components for generating a current subtraction function for... Figure 2 The circuit system in which the inverter in the delay unit is biased by the bias voltage, and a schematic diagram of the (bottom) input current and the temperature-varying differential current output by the current subtraction circuit is shown.
[0058] Figure 4 The diagram schematically shows a bias current generating circuit (top), which includes components for generating bias current for... Figure 2 In the circuit system of the inverter in the delay unit, the bias voltage is biased by the circuit system. The diagram shows (middle) the input current and the differential current generated in the bias current generation circuit as varying with temperature, and (bottom) the bias current generated by the bias current generation circuit as varying with temperature.
[0059] Figure 5 This illustration schematically shows an example embodiment of a device according to the present disclosure. Figure 1 The bias voltage generation circuit of the ring oscillator; and
[0060] Figure 6 This illustration schematically shows an example embodiment of the present disclosure including... Figure 1 The phase-locked loop of the ring oscillator. Detailed Implementation
[0061] Ring oscillators are known for their small size and are often used as an alternative to LC voltage-controlled oscillators (VCOs) to save space when phase noise requirements are not stringent. A simple ring oscillator consists of an odd number of cascaded inverter units, with the output of the last inverter connected to the input of the first inverter. As a signal propagates through each inverter, it experiences a delay, and therefore the oscillation frequency of the ring oscillator depends on the delay of each inverter and the total number of inverters in the ring. Since the delay of each inverter depends on the time taken to charge / discharge its output capacitor, the oscillation frequency of the ring oscillator can be controlled by controlling the capacitance of the output capacitor and / or by controlling the current available for charging and / or discharging the output capacitor.
[0062] Ring oscillators are typically based on CMOS inverters, which are known for their simplicity and rail-to-tail swing. Because the swing of a CMOS inverter is equal to its supply voltage, the supply voltage directly controls the current drive strength of the inverter device and thus affects the oscillation frequency of the ring oscillator. In practice, in many designs, the supply voltage of a CMOS ring oscillator is used to control its frequency. However, this can also be a drawback of such ring oscillators. Any ripple on the supply voltage of a CMOS ring oscillator will modulate the oscillation frequency and generate noise at the output of the ring oscillator. For example, if a CMOS ring oscillator is used as a clock source for an analog-to-digital converter (ADC), this noise can degrade clock quality and the quality of the ADC output.
[0063] In a System-on-a-Chip (SoC), there is typically a switching regulator (e.g., a DC-DC converter) to efficiently set the power supply voltage for a radio. Due to the switching nature of these converters, there is always a ripple of tens of millivolts (mV) on the converter's generated output voltage. If this voltage is used directly as the power supply for a CMOS ring oscillator, it can generate strong noise due to the ring oscillator's power supply sensitivity. To reduce the impact of this ripple, low-dropout (LDO) voltage regulators and / or current sources with high power supply rejection ratios (PSRR) are typically used to suppress the ripple before it reaches the ring oscillator. The power supply rejection of an LDO or current source depends on the voltage drop across it. The higher the voltage drop, the better the achievable PSRR. Therefore, to achieve adequate suppression of power supply noise, the switching converter output voltage must be set high enough that there is a sufficient voltage drop across the LDO or current source to provide adequate suppression. This can increase the overall power consumption of the system, including the ring oscillator.
[0064] Figure 1 A ring oscillator according to an exemplary embodiment of the present disclosure is schematically shown, the ring oscillator being in the form of a five-stage ring oscillator 100 having an oscillation frequency of, for example, 2 GHz. However, the ring oscillator according to the present disclosure can be designed with any odd number of delay units (stages) 200 based on frequency requirements.
[0065] The ring oscillator 100 includes an odd number (five in this example) of delay units 200 coupled in a ring arrangement. That is, the output 220 of each inverter unit 200 is coupled to the input 210 of the corresponding next inverter unit in the ring. The ring oscillator 100 is coupled to a supply voltage Vdd 110 and a reference voltage or ground. The output Vbuf 120 of the ring oscillator 110 is coupled via a buffer to the output 220 of one of the inverter units 200. The ring oscillator 100 includes various control inputs, including a bias voltage input Vbias 130, a capacitor control 140, and another control input Rgate 150 (see [link to relevant documentation]). Figure 2 , Figure 1 (Not shown in the image). These control inputs can be used to control or calibrate the delay between the inverter input 210 and the inverter output 220 for all delay units 200, and thus control or calibrate the oscillation frequency of the ring oscillator 100.
[0066] Each delay unit 200 includes an inverter 230 according to this disclosure and a corresponding capacitor 240 for tuning the inverter 230. For simplicity, the corresponding tuning capacitor 240 is... Figure 1 The capacitor is represented as a single variable capacitor with a single control input 140. However, each tuning capacitor 240 may include multiple capacitors, each of which can optionally be controlled individually, as referenced. Figure 2 describe.
[0067] Figure 2 A delay unit 200 according to an exemplary embodiment of the present disclosure is schematically shown. The delay unit 200 includes an inverter 230 and a corresponding capacitor 240 for tuning the inverter 230.
[0068] Inverter 230 includes a first NMOS transistor 250 (actually a common-source NMOS 'driver') and a second NMOS transistor 260 (actually a common-drain NMOS 'load'). The first NMOS transistor 250 includes a first gate terminal 252, a first drain terminal 254, and a first source terminal 256. The second NMOS transistor 260 includes a second gate terminal 262, a second drain terminal 264, and a second source terminal 266. The second source terminal 266 is coupled to the first drain terminal 254. The inverter input Vin 210 is coupled to the first gate terminal 252. The inverter output Vout 220 is coupled to the first drain terminal 254.
[0069] The second drain terminal 264 is coupled to the supply voltage Vdd 110, and the first source terminal 256 is coupled to ground or a reference voltage. The bias voltage input Vbias 130 is coupled to the second gate terminal 262 via a variable resistor 270. Another control voltage input Rgate 150 is provided to control the value of the variable resistor 270.
[0070] Capacitors 240 for tuning inverter 230 are coupled in parallel to inverter output Vout 220. These capacitors include a first capacitor Cbin 242, a second capacitor Ctherm 244, and a variable capacitor Cvar 246. Capacitor control 140 includes a first control input cap_bini 142 for controlling the value of the first capacitor Cbin 242, a second control input cap_therm 144 for controlling the effective value of the second capacitor Ctherm 244, and a third control input Vtune 146 for controlling the effective value of the variable capacitor Cvar 246.
[0071] Each of the first capacitor Cbin 242 and the second capacitor Ctherm 244 is provided in the form of a programmable switched capacitor DAC, comprising a plurality of switched capacitors coupled in parallel. Each switched capacitor included in the first capacitor 242 and the second capacitor 244 includes a fixed capacitor having a first terminal coupled to the inverter output Vout 220 and a second terminal coupled to ground or a reference voltage via corresponding transistors 243, 245. A first control input 144 and a second control input 142 are coupled to the respective gates of the transistors for switching the corresponding first capacitor Cbin 242 or second capacitor Ctherm 244. The overall value of the first capacitor 242 and the second capacitor 244 can thus be programmed or controlled by digital control signals cap_bini and cap_therm received at the first control input 142 and the second control input 144.
[0072] The variable capacitor Cvar 246 includes a fixed capacitor 247 and a varactor 248, both series-coupled between the inverter output Vout 220 and the third control input 146, configured to receive a tuning voltage Vtune 146. The varactor 248 is provided by a MOSFET transistor 248. The fixed capacitor 247 is coupled between the inverter output Vout 220 and a node coupled to both the source and drain of the MOSFET transistor 248. The tuning voltage Vtune 146 is coupled to the gate of the MOSFET transistor to control the capacitance of the varactor 248. The capacitance of the MOS varactor diode depends on the DC voltage across it, but is linear only over a narrow voltage range. Therefore, a bias voltage varbias_hi / mid / lo 148 is applied to the source and drain of the MOSFET transistor 248. To increase the linear range of the variable capacitor 246, several different varactor diodes 248, each series-coupled with a corresponding fixed capacitor 247, can be coupled in parallel and biased with different voltages. When the ring oscillator 100 is used as a voltage-controlled oscillator (VCO) in a phase-locked loop (PLL), and Vtune is the tuning voltage for the VCO, this feature can improve the linearity of the VCO gain Kvco through the tuning voltage Vtune 146. Figure 2 In the embodiment shown, three varactor diodes 248 are coupled in parallel and biased using different corresponding bias voltages 148 (varbias_hi, varbias_mid, and varbias_lo).
[0073] Those skilled in the art will understand that Figure 2 The arrangement of capacitors Cbin 242, Ctherm 244 and Cvar 246 shown is only one example, and other combinations or arrangements of capacitors may alternatively or additionally couple to the inverter output to control the delay of inverter 230 and thus the oscillation frequency of ring oscillator 100.
[0074] Since the power supply voltage Vdd 110 is connected to the drain of the second NMOS transistor 260 (i.e., the second drain terminal 264), the drive current of the delay cell 200 is not affected by the power supply voltage when the first NMOS transistor 250 and the second NMOS transistor 260 are operating in the saturation region.
[0075] The second (common-drain) NMOS transistor 260 has low output resistance, and therefore the inverter 230 has low gain. To ensure oscillation of the ring oscillator 100, a gate resistor (Rgate) 270 is added at the gate of the second NMOS transistor (i.e., the second gate terminal 262). At the oscillation frequency, the gate-source capacitance (Cgs) of the second (common-drain) NMOS transistor 260 is shorted, and the actual load seen by the first NMOS transistor 250 (the common-source NMOS 'driver') is the resistor Rgate 270. This increases the gain of the inverter 230 at the oscillation frequency and ensures oscillation.
[0076] Unlike CMOS inverters, inverter 230 requires biasing. Biasing is performed by a replica bias circuit that generates a bias voltage Vbias at bias voltage input 130, which is coupled to the gate 262 of a second (common-drain) NMOS transistor 260 via resistor Rgate 270. Since this bias voltage Vbias 130 controls the drive strength of inverter 230, the oscillation frequency of the ring oscillator 100 is sensitive to variations in the bias voltage Vbias at node 130. However, bias voltage input 130 does not carry any DC current and can be largely filtered by a large RC filter to suppress any ripple coupled through the power supply. Furthermore, the value of the variable resistor Rgate 270 controls the charging current at inverter output Vout 220 and can also be used for coarse tuning of the oscillation frequency.
[0077] Calibration of the ring oscillator 100 (e.g., a voltage-controlled oscillator (VCO) for use in a phase-locked loop (PLL)) can be achieved as follows. A programmable variable resistor Rgate 270 can be used for single-process calibration by appropriately setting the control voltage input Rgate 150. Programmable capacitors DAC 242, 244 can be used to adjust the oscillator frequency to near the target frequency before closing the PLL loop. A variable capacitor Cvar 246 (including a MOS varactor diode 248) is used for continuous tracking and is controlled by a control voltage Vtune 146, which can correspond to the tuning voltage of the PLL loop. There is also the possibility of controlling the oscillation frequency via Vbias 130, which can be used as described below. Figures 3 to 5 The temperature tracking loop is described.
[0078] Another significant issue with ring oscillators is their temperature sensitivity. Because the threshold voltage, mobility, and other parameters of a MOS transistor are temperature-dependent, the drive current of the inverter can change with temperature. In a ring oscillator, this can cause frequency drift. When used in a phase-locked loop (PLL), this means that once the PLL is locked, a large temperature drift can cause the PLL to disengage and require relocking.
[0079] To improve the temperature stability of the inverter unit 200 and the ring oscillator 100 disclosed above, the bias voltage Vbias 130 is varied with temperature to counteract the effects of temperature on the inverter 230. For example, the bias voltage Vbias 130 may increase substantially with temperature. To better approximate the desired temperature correction and thus achieve more stable operation over a wider temperature range, a bias voltage Vbias 130 is generated that has a first temperature dependence on temperatures above a predetermined temperature offset and a second, different temperature dependence on temperatures below a predetermined temperature offset.
[0080] Figures 3 to 5 A bias voltage generation circuit 500 is shown for generating a bias voltage Vbias 130 for biasing the inverter unit 200 of the ring oscillator 100. As will be described in more detail below, the bias voltage generation circuit 500 includes first portions 400, 510, 520 for generating a bias current Ibias, which is temperature-dependent and has a gain controlled by a control voltage Vtune 146 for tuning the ring oscillator 100. The bias voltage generation circuit 500 also includes a second portion 530 for generating a bias voltage from the bias current, the second portion comprising a copy of the inverter 230.
[0081] Figure 3 A current subtraction circuit 300 is schematically shown for generating a current i_m1 that is proportional to temperature (T) in a first temperature range and constant with temperature in a second temperature range. The first temperature range corresponds to temperatures below a predetermined temperature offset, and the second temperature range corresponds to temperatures including and above the predetermined temperature offset. The current subtraction circuit 300 subtracts the absorber PTAT (proportional to absolute temperature) current (represented by ic_10u) from the constant source current (represented by ic_10u), and feeds the difference i_m1 between the two currents into an NMOS current mirror 350. The output i_m1 of the current mirror 350 is the difference between the two currents (ic_10u - ipc_10u) at a temperature where the source current is higher than the absorber current and is otherwise zero. Figure 3 The plot shows the temperature dependence of currents ic_10u, ipc_10u, and i_m1. The predetermined temperature offset can correspond to, for example, room temperature. Figure 3 The temperature is 27°C as indicated in the diagram shown, and can be adjusted by changing the value of the source constant current ic_10u.
[0082] Figure 4 A bias current generating circuit 400 for outputting a bias current Ibias is schematically shown, the bias current generating circuit including... Figure 3 The current subtraction circuit 300. In this circuit 400, the current subtraction circuit 300 is... Figure 3 The piecewise double-slope current i_m1 generated by the current subtraction circuit 300 is weighted and combined with the weighted versions of currents ipc and ic to generate a piecewise linear double-slope bias current Ibias at the output 410 of the bias current generation circuit 400. Figure 4 The upper part of the drawing indicates the temperature dependence of currents ic_10u, ipc_10u, i_m1, and i_m2. Figure 4 The lower plot shows the temperature dependence of the bias current Ibias, where a predetermined temperature offset is indicated by 27°C. Below the predetermined temperature offset, the bias current Ibias varies linearly with temperature according to a first slope 450. Above the predetermined temperature offset, the bias current Ibias varies linearly with temperature according to a second slope 452. Figure 4 In the circuit, three different current mirror ratios are adjustable, allowing the current to be independently controlled using control inputs iptat_hot, iptat_cold, and ioffset at a predetermined temperature offset (e.g., room temperature) and at current slopes 450 below and above the predetermined temperature offset. The value of the bias current Ibias at the predetermined temperature offset can be controlled using the ioffset input. The current-temperature slope 450 at temperatures below the predetermined temperature offset can be controlled using the iptat_cold input, independent of the current-temperature slope 452 at temperatures above the predetermined temperature offset, which can be controlled using the iptat_hot input. This idea can be extended to more segments to synthesize more nonlinear current distribution curves if desired. In this way, the temperature-dependent frequency drift of the ring oscillator 100 can be reduced.
[0083] When the ring oscillator 100 is used as the VCO in the PLL, the temperature stability of the PLL can be further improved by adding a second tuning path that corrects for any drift not compensated for by the PTAT bias described above. References will follow below. Figure 5 In this mechanism described, the control voltage Vtune 146 from the loop filter of the PLL is fed not only to the varactor diode 246 included in the tuning capacitor 240 of the ring oscillator 100, but also to control the bias current Ibias 410 (by... Figure 4The circuit 400 shown generates and then controls the bias voltage Vbias 130 for each inverter 230. This second tuning path controls the bias voltage Vbias 130 through a slow mechanism, thereby increasing the effective VCO tuning gain at low frequencies. Due to the slow nature of this second tuning path, it does not affect the noise performance or loop dynamics of the PLL.
[0084] Figure 5 A bias voltage generation circuit 500 for generating a bias voltage Vbias 130 is schematically shown. The output 502 of the bias voltage generation circuit 500 is coupled to the bias voltage input 130 of the inverter 230 of the inverter unit 200. The bias voltage generation circuit 500 includes a circuit 400 for generating a bias current Ibias 410 as described above. The bias current Ibias 410 and a control voltage Vtune 146 are input to a temperature compensation section 510 of the circuit 500, which provides a mechanism for the second tuning path discussed above. In the temperature compensation section 510, the control voltage Vtune 146 is buffered to avoid loading a loop filter and is subsequently used to selectively control all or part of the gain of the bias current Ibias 410. The effective gain of the temperature compensation section 510 is adjusted by Vtune, which controls how much of the bias current Ibias 410 is controlled by this loop. The bias current Ibias 410 is used to control a first current mirror 512 with a first gain (2Kb_gain) that increases with the control parameter Kb_gain, and a second current mirror 514 with a second gain (1-Kb_gain) that decreases with the control parameter Kb_gain. Therefore, when Kb_gain increases, the current carried by the first current mirror 512 increases, while the current carried by the second current mirror 514 decreases. The current at the output 518 of the temperature compensation section 510 includes the entire current in the second current mirror 514 ((1-Kb_gain.Ibias) but only a portion of the current in the first current mirror 512 (2Kb_gain.Ibias). The portion of the current in the first current mirror 512 that goes to the output 518 is controlled by Vtune and is proportional to Vtune-vdd / 2 (determined by the differential pair 516). Therefore, by changing kb_gain, we change the portion of the current controlled by Vtune, and thus change the effective gain of the temperature compensation portion 510.
[0085] The output current iout 512 from the temperature compensation section 510 is then largely filtered by the RC filter 520 and subsequently fed to the delay unit replication bias circuit section 530 to generate the bias voltage Vbias 130 for the ring oscillator 100. The RC filter has the dual function of slowing down this loop and filtering noise generated in the bias voltage generation circuit 500. This second tuning path effectively increases the VCO gain Kvco and thus the loop gain for slow changes (below the corner frequency of the RC filter 520), but has no effect on faster changes. The temperature compensation section 510 can be bypassed, for example, during startup, to charge the capacitor.
[0086] Finally, the filtered bias current iout is input to the second part 530 of the bias voltage generation circuit 500 to generate the bias voltage Vbias 130. The second part 530 includes a replication delay unit 532, which includes replicas 534 and 536 of the first NMOS transistor 250 and the second NMOS transistor 260 of the inverter 230. In the replication delay unit 532, the gate and drain terminals of the replicated first NMOS transistor 534 are coupled to the source terminal of the replicated second NMOS transistor 536. The gate terminal of the replicated second NMOS transistor 536 is coupled to the drain terminal of the second NMOS transistor 534. The output 502 of the bias voltage generation circuit 500 is coupled to the drain terminal of the second NMOS transistor. An additional RC filter 538 helps suppress any ripple from the power supply before it reaches the bias voltage Vbias 130.
[0087] Figure 5 A plot of the bias voltage Vbias against temperature T is also shown. The thick trace indicates that when... Figure 4 The bottom plot shows the bias voltage Vbias 130 obtained using a piecewise linear bias current Ibias 410 with a double slope. For comparison, Figure 5 The fine traces shown in the plot illustrate the bias voltage Vbias130 obtained by alternatively using a single-slope linear bias current. The dual-slope version can produce an inverter and therefore better elimination of temperature effects in the ring oscillator. This is because the drive current of inverter 230 does not change linearly with temperature. Various parameters of circuit 500 can be adjusted based on simulation results to optimize the temperature dependence of Vbias. If further improvement in temperature stability is required, a bias current Ibias with temperature dependence including more than two linear slopes can be used. Although... Figure 5The diagram shows the bias voltage Vbias as increasing with temperature, but in other embodiments, the bias voltage Vbias may need to decrease with temperature. Whether Vbias increases or decreases with temperature will depend on the semiconductor process. This is because there are at least two opposing mechanisms controlling inverter delay: as temperature increases, the threshold voltage decreases, but the mobility also decreases.
[0088] Figure 6 A phase-locked loop 700 incorporating a ring oscillator 100 according to an embodiment of the present disclosure is schematically shown. A reference signal fref is received at input 710 of the phase-locked loop 700. The ring oscillator 100 outputs a signal fout to output 760 of the phase-locked loop 700. A phase comparator 720 (optionally via a frequency divider 780) is coupled to both input 710 and output 760 and is configured to output an error signal depending on the difference between the phase of the ring oscillator output signal fout and the phase of the reference signal fref. Optionally, a low-pass filter 730 is arranged to receive the error signal from the phase comparator 720 and is configured to output a control voltage Vtune for controlling the frequency and / or phase of the ring oscillator 100. The control voltage Vtune controls the frequency / phase of the ring oscillator 100 via two paths 740, 750. In the first path 740, a control voltage Vtune is connected to a third control input 146 of each inverter 200 to control the effective value of a variable capacitor Cvar 246 coupled in parallel to the corresponding inverter output 220. In the second path 750, the control voltage Vtune is input to the circuit system 500 to generate a bias voltage Vbias applied to the bias voltage input 130 of each inverter 100.
[0089] While specific exemplary embodiments of this disclosure have been described above, it should be understood that many modifications, including additions and / or substitutions, may be made within the scope of the appended claims.
Claims
1. A ring oscillator, characterized in that, The ring oscillator includes: Multiple inverters, the multiple inverters being arranged in a ring, Each inverter includes an inverter input and an inverter output, wherein the inverter output of each inverter in the loop is coupled to the inverter input of the corresponding next inverter in the loop; and At least one of the plurality of inverters further comprises: A first NMOS transistor includes a first gate coupled to the input of the corresponding inverter, a first drain coupled to the output of the corresponding inverter, and a first source coupled to the output of the corresponding inverter; and The second NMOS transistor includes a second gate terminal, a second drain terminal, and a second source terminal, wherein the second source terminal is coupled to the first drain terminal.
2. The ring oscillator according to claim 1, characterized in that, The at least one inverter further includes: A bias voltage input, coupled to the second gate terminal; and A resistor coupled between the bias voltage input and the second gate terminal.
3. The ring oscillator according to claim 2, characterized in that, The resistor is a variable resistor.
4. The ring oscillator according to any one of the preceding claims, characterized in that, The at least one inverter further includes: At least one capacitor is coupled between the inverter output and the reference voltage.
5. The ring oscillator according to any one of the preceding claims, characterized in that, The at least one inverter further includes: At least one variable capacitor is coupled between the inverter output and the control voltage.
6. The ring oscillator according to any one of the preceding claims, characterized in that: The second drain terminal is coupled to the power supply voltage; and / or The first source terminal is coupled to the reference voltage.
7. The ring oscillator according to any one of the preceding claims, characterized in that, The ring oscillator further includes: A circuit system comprising an output coupled to the bias voltage input of the at least one inverter; The circuit system is configured to generate a bias voltage at its output that varies with temperature.
8. The ring oscillator according to claim 7, characterized in that, The bias voltage has a first temperature dependence on temperatures above a predetermined temperature offset and a second different temperature dependence on temperatures below the predetermined temperature offset.
9. The ring oscillator according to claim 7 or claim 8, characterized in that, The circuit system is configured to generate the bias voltage based on temperature-dependent current.
10. A phase-locked loop, characterized in that, The phase-locked loop includes: The ring oscillator according to any of the preceding claims; and A phase comparator is used to output a control signal based on the difference between the phase of the signal at the output of the ring oscillator and the phase of a reference signal, for controlling the frequency and / or phase of the ring oscillator.