Burr optimization digital-to-analog converter and slope compensation circuit

Abstract

The invention relates to a glitch optimization digital-to-analog converter and a slope compensation circuit. The glitch optimization digital-to-analog converter comprises a thermometer decoder, a synchronous circuit module, a bit control signal generation module, a pull-up or pull-down pulse generation module, a pull-up or pull-down circuit and an R2R circuit. A bit control signal generation module, a pull-up or pull-down pulse generation module and a pull-up circuit or a pull-down circuit are arranged in the digital-to-analog converter, so that the output burr directions of the digital-to-analog converter are uniformly upward or downward, and normal overturning of a first edge of a voltage comparator is ensured; the stable operation of the slope compensation system of the power supply can be ensured under the condition that burrs do not need to be eliminated.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a glitch-optimized digital-to-analog converter and a slope compensation circuit. Background Technology

[0002] Slope compensation circuits are commonly used in traditional peak current control systems to ensure stable system operation. However, in traditional slope compensation circuits, when the number of digital slope steps within a switching cycle is too small, glitches on the output slope of the digital-to-analog converter (DAC) can easily cause the comparator (CMP) to overshoot, resulting in instability in the control system.

[0003] R2R DACs are often used to generate programmable ramp compensation circuits. However, abrupt changes in the binary digital encoding of the DAC can easily introduce large glitches, which is an inherent characteristic of the R-2R structure.

[0004] Each digital bit inside a DAC corresponds to an analog switch, and the switching on and off actions of these switches require a certain amount of time. These switches cannot be perfectly synchronized, and there will inevitably be slight time differences. DAC glitches are caused by the difference in the on and off times of the analog switches inside the DAC when the input data changes. Although the input data is input in parallel, due to factors such as different resistance and capacitance distributions in the transmission path, the waveform transition edges are not synchronized, resulting in a time difference. This further leads to time deviations in switch switching, causing analog outputs unrelated to the input data to appear at the output, until the state switching stabilizes.

[0005] There are several ways to address DAC glitches, including using Gray coding, reconstruction filters (RCF), and track-and-hold amplifiers (THA). However, Gray coding is not suitable for segmented R2R structures, RCF is not only bulky but also reduces the DAC's conversion speed, THA introduces additional power consumption or hysteresis, and high-speed clocks can cause clock feedthrough in the analog circuitry. Summary of the Invention

[0006] The objective of this invention is to provide a glitch-optimized digital-to-analog converter and a slope compensation circuit. By incorporating a bit control signal generation module, a pull-up or pull-down pulse generation module, and a pull-up or pull-down circuit into the digital-to-analog converter, the output glitch direction of the digital-to-analog converter is uniformly upward or downward, ensuring the normal flipping of the first edge of the voltage comparator. This allows for the stable operation of the power supply slope compensation system without the need to eliminate glitch.

[0007] This invention provides a glitch-optimized digital-to-analog converter, characterized in that it comprises: A thermometer decoder, configured to receive a first-class digital signal of a digital ramp signal and decode it to generate a thermometer code; The synchronization circuit module is configured to synchronize the thermometer code with the second type of digital signal of the digital ramp signal. A bit control signal generation module is arranged after the synchronization module circuit and is configured to delay the thermometer code and the second type of digital signal, and generate a first bit control signal and a second bit control signal accordingly. The flipping of the first bit control signal and the second bit control signal lags behind the generation of the pull-up pulse, and the first bit control signal lags behind the second bit control signal. A pull-up pulse generation module is connected to the synchronization module circuit and the bit control signal generation module, and is configured to receive a second bit control signal and a second type of digital signal to generate a pull-up pulse; A pull-up circuit is arranged after the pull-up pulse generation module and is configured to receive pull-up pulses to generate pull-up current. The R2R circuit is connected to the pull-up circuit.

[0008] This invention provides a glitch-optimized digital-to-analog converter, comprising: A thermometer decoder, configured to receive a first-class digital signal of a digital ramp signal and decode it to generate a thermometer code; The synchronization circuit module is configured to synchronize the thermometer code with the second type of digital signal of the digital ramp signal. A bit control signal generation module is arranged after the synchronization module circuit and is configured to delay the thermometer code and the second type of digital signal to generate a first bit control signal and a second bit control signal, wherein the flipping of the first bit control signal and the second bit control signal lags behind the generation of the pull-down pulse, and the first bit control signal lags behind the second bit control signal. A pull-down pulse generation module is connected to the synchronization module circuit and the bit control signal generation module, and is configured to receive a second bit control signal and a second type of digital signal to generate a pull-down pulse; A pull-down circuit is arranged after the pull-down pulse generation module and is configured to receive pull-down pulses to generate pull-down current; The R2R circuit is connected to the pull-down circuit.

[0009] Furthermore, the synchronization circuit module includes multiple D flip-flops.

[0010] Furthermore, the bit control signal generation module includes: The first signal generation circuit is configured to receive synchronized thermometer codes, perform delay processing, and generate a first bit control signal; the first signal generation circuit includes a first delay unit and two first inverting amplifiers connected in series. The second signal generation circuit is configured to receive the synchronized second type of digital signal, perform delay processing, and generate a second bit control signal, wherein the first bit control signal lags behind the second bit control signal; the second signal generation circuit is a second delay unit.

[0011] Furthermore, the pull-up pulse generation module includes an XOR gate, a NOR gate, and a second inverting amplifier arranged sequentially, wherein: The first input of the XOR gate is connected to the input of the second delay unit and the second input of the NOR gate; the second input of the XOR gate is connected to the output of the second delay unit; the output of the XOR gate is connected to the first input of the NOR gate. The output of the NOR gate is connected to the input of the second inverting amplifier, and the output of the second inverting amplifier is used to output the pull-up pulse.

[0012] Furthermore, the pull-down pulse or the pulse width of the pull-down pulse is 1 ns.

[0013] This invention provides a slope compensation circuit, comprising: A ramp generation module, configured to generate digital ramp signals; A glitch-optimized digital-to-analog converter is arranged after the ramp generation module and configured to generate a ramp voltage signal based on a digital ramp signal. A voltage comparator is placed after the glitch-optimized digital-to-analog converter and is configured to output a comparison result based on the input sampled signal and the ramp voltage signal.

[0014] The present invention also provides a method for optimizing the output glitches of a digital-to-analog converter, comprising: A digital ramp signal is generated by a ramp generation module, the digital ramp signal comprising a first type of digital signal and a second type of digital signal; The thermometer decoder receives the first type of digital signal and decodes it to generate thermometer code; The synchronization circuit module synchronizes the thermometer code with the second type of digital signal. The bit control signal generation module delays the thermometer code and the second type of digital signal to generate a first bit control signal and a second bit control signal, respectively. The flipping of the first bit control signal and the second bit control signal lags behind the generation of the pull-up pulse or pull-down pulse, and the first bit control signal lags behind the second bit control signal. The pull-up pulse generation module receives the second bit control signal and the second type of digital signal to generate a pull-up pulse, or the pull-down pulse generation module receives the second bit control signal and the second type of digital signal to generate a pull-down pulse; Pull-up current is generated by receiving pull-up pulses from the pull-up circuit, or pull-down current is generated by receiving pull-down pulses from the pull-down circuit; The R2R circuit receives the pull-up or pull-down current, the first bit control signal, and the second bit control signal, and outputs the ramp voltage signal.

[0015] Furthermore, the voltage comparator outputs the comparison result based on the input sampling signal and the ramp voltage signal.

[0016] The present invention also provides a microcontroller having the above-described slope compensation circuit.

[0017] The present invention has at least the following beneficial effects: This invention, by setting a bit control signal generation module, a pull-up or pull-down pulse generation module, and a pull-up or pull-down circuit in the digital-to-analog converter, ensures that the output glitches of the digital-to-analog converter are uniformly downward for upward slopes and uniformly upward for downward slopes. This guarantees the normal flipping of the first edge of the voltage comparator and ensures the stable operation of the power supply slope compensation system without the need to eliminate glitches. Attached Figure Description

[0018] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the embodiments of the invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by identical or similar reference numerals for clarity.

[0019] Figure 1 The waveforms of the digital-to-analog converter output and voltage comparator output in the existing downslope are shown.

[0020] Figure 2 The waveforms of the digital-to-analog converter output and voltage comparator output in the existing upslope are shown.

[0021] Figure 3 A schematic diagram of a slope compensation circuit according to an embodiment of the present invention is shown.

[0022] Figure 4 A schematic diagram of a synchronization circuit module according to an embodiment of the present invention is shown.

[0023] Figure 5 A schematic diagram of the digital signal flipping before and after synchronization of a synchronization circuit module according to an embodiment of the present invention is shown.

[0024] Figure 6 A schematic diagram of a bit control signal generation module and a pull-up pulse generation module according to an embodiment of the present invention is shown.

[0025] Figure 7 The output waveform of a glitch-optimized digital-to-analog converter according to an embodiment of the present invention is shown. Detailed Implementation

[0026] It should be noted that the components in the accompanying drawings may be shown exaggerated for illustrative purposes and may not be to scale.

[0027] In this invention, the various embodiments are merely intended to illustrate the solutions of the invention and should not be construed as limiting.

[0028] In this invention, unless otherwise specified, the quantifiers “a” and “one” do not exclude scenarios involving multiple elements.

[0029] It should also be noted that, in the embodiments of the present invention, only a portion of the parts or components may be shown for clarity and simplicity. However, those skilled in the art will understand that, under the teachings of the present invention, the required parts or components can be added as needed for specific scenarios.

[0030] It should also be noted that within the scope of this invention, the terms "same", "equal", and "equal to" do not mean that the two values ​​are absolutely equal, but allow for a certain reasonable error. In other words, the terms also cover "substantially the same", "substantially equal", and "substantially equal to".

[0031] It should also be noted that in the description of this invention, the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not explicitly or implicitly suggest that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0032] Furthermore, the embodiments of the present invention describe the process steps in a specific order. However, this is only for the convenience of distinguishing each step, and is not a limitation on the order of each step. In different embodiments of the present invention, the order of each step can be adjusted according to the process.

[0033] Each digital bit inside a DAC corresponds to an analog switch, and the switching on and off actions of these switches require a certain amount of time. These switches cannot be perfectly synchronized, inevitably resulting in slight time differences. Even if the input data is transmitted in parallel (theoretically arriving simultaneously), in actual circuits, the transmission path lengths and parasitic parameters (such as resistance R and capacitance C) of each data point differ. This difference causes the waveform switching edges of the switches to be asynchronous, further amplifying the switching time deviation and disrupting the ideal state of parallel synchronization. Before the switches are fully stable, some switches have already switched, while others remain in a transition state, causing a temporary imbalance in the current distribution of the R2R resistor network. This imbalance results in a brief voltage / current signal at the DAC output that is unrelated to the final target analog quantity—a glitch. Only when all switches stabilize at the target state and the resistor network returns to balance will the output return to the normal analog quantity corresponding to the input data.

[0034] This invention proposes a glitch-optimized digital-to-analog converter and a ramp compensation circuit to ensure stable system operation without completely eliminating glitches at the DAC output.

[0035] Figure 1 The waveforms of the digital-to-analog converter output and voltage comparator output in the existing downslope are shown. Figure 2 The waveforms of the digital-to-analog converter output and voltage comparator output in the existing upslope are shown.

[0036] This invention is based on the inventor's following insights: In edge-triggered upslope compensation or downslope compensation applications, it is not necessary to completely eliminate glitches at the DAC output to ensure stable system operation. For downslopes, it is only necessary to standardize the glitches, ensuring that all glitches at the DAC output are upward. Similarly, for upslopes, the goal is to ensure that all glitches at the DAC output are downward, thereby guaranteeing that the first toggling edge of the voltage comparator VCMP can toggle correctly. The principle is as follows: exist Figure 1 In the downward ramp shown, edge A represents the edge where the voltage comparator flips correctly, and edge B represents the edge where the voltage comparator flips prematurely. In the downward ramp of the digital-to-analog converter, downward spikes will cause the voltage comparator to flip prematurely.

[0037] Figure 1 The first line is the ramp voltage signal output by the digital-to-analog converter, the second line is the sampling signal IN_P of the input voltage comparator, and the third line is the comparison result output by the voltage comparator based on the sampling signal and the ramp voltage signal.

[0038] exist Figure 2In the downslope shown, edge C represents the edge where the voltage comparator VCMP flips correctly, and edge D represents the edge where the voltage comparator VCMP flips prematurely. In the upslope of the DAC, upward spikes will cause the voltage comparator VCMP to flip prematurely.

[0039] Figure 2 The first line is the sampling signal IN_P of the input voltage comparator, the second line is the ramp voltage signal output by the digital-to-analog converter, and the third line is the comparison result output by the voltage comparator based on the sampling signal and the ramp voltage signal.

[0040] In power supply slope compensation applications, the next stage is triggered by the edge of a voltage comparator during each slope cycle. Therefore, ensuring the correct first edge of the voltage comparator's flip is sufficient to guarantee stable operation of the slope compensation system. In other words, downward glitches must be avoided in downslope applications, and upward glitches must be avoided in upslope applications.

[0041] To solve the problem of voltage comparators failing to flip correctly due to glitches at the output of digital-to-analog converters (DACs), this invention unifies the glitches at the DAC output, ensuring that all glitches are either upward or downward, thus guaranteeing that the first flip edge of the voltage comparator can flip correctly.

[0042] Figure 3 A schematic diagram of a slope compensation circuit according to an embodiment of the present invention is shown.

[0043] like Figure 3 As shown, a slope compensation circuit includes a slope generation module 100, a glitch-optimized digital-to-analog converter 200, and a voltage comparator 300 connected in sequence. The slope generation module 100 is configured to generate a digital slope signal. The digital-to-analog converter 200 is arranged after the slope generation module 100, and is configured to generate a slope voltage signal based on the digital slope signal. The voltage comparator 300 is arranged after the glitch-optimized digital-to-analog converter 200, and is configured to output a comparison result based on the input sampled signal and the slope voltage signal.

[0044] The glitch-optimized digital-to-analog converter 200 includes: a thermometer decoder 201, a synchronization circuit module 202, a bit control signal generation module 203, a pull-up or pull-down pulse generation module 204, a pull-up or pull-down circuit 205, and an R2R circuit 206.

[0045] The thermometer decoder 201 is connected to the ramp generation module 100 and is configured to receive the first type of digital signal of the digital ramp signal and decode it to generate thermometer code. The digital ramp signal is a binary digital code. The high-order binary digital code of the digital ramp signal, that is, the first type of digital signal, is decoded by the thermometer decoder 201 to generate thermometer code. The low-order binary digital code of the digital ramp signal, that is, the second type of digital signal, is directly transmitted to the synchronization circuit module 202.

[0046] The synchronization circuit module 202 is connected to the ramp generation module 100 and the thermometer decoder 201. The synchronization circuit module 202 is configured to synchronize the thermometer code with the second type of digital signal of the digital ramp signal.

[0047] The bit control signal generation module 203 is arranged after the synchronization module circuit 202 and is configured to delay the thermometer code and the second type of digital signal, and generate a first bit control signal and a second bit control signal accordingly. The flipping of the first bit control signal and the second bit control signal lags behind the generation of the pull-up pulse or pull-down pulse. The first bit control signal lags behind the second bit control signal and is used to control the switching of the R2R circuit.

[0048] The first bit of the control signal corresponds to the thermometer code, and the second bit of the control signal corresponds to the second type of digital signal.

[0049] The pull-up or pull-down pulse generation module 204 is connected to the synchronization module circuit 202 and the bit control signal generation module 203, and is configured to receive the second bit control signal and the second type of digital signal to generate pull-up or pull-down pulses.

[0050] Pull-up or pull-down circuit 205 is arranged after pull-up or pull-down pulse generation module 204 and is configured to receive pull-up pulse or pull-down pulse to generate pull-up current or pull-down current, so that the output glitch direction of R2R circuit 206 is fixed to upward or downward, that is, the glitch output of glitch optimization digital-to-analog converter 200 is fixed to upward or downward.

[0051] The R2R circuit outputs a ramp voltage signal, and the direction of the spike is fixed to either upward or downward.

[0052] In digital-to-analog converters, the R2R circuit (R-2R resistor network) is the core functional unit for converting digital signals to analog signals. Its core function is to convert the input binary digital code into a continuous analog signal proportional to the digital quantity through the current / voltage distribution of the resistor network.

[0053] During the normal transition of the digital ramp signal in a digital-to-analog converter (DAC), sudden changes can cause significant glitches in the DAC output with unpredictable direction. This invention addresses this by standardizing the output glitches of the DAC, ensuring that the glitches have a fixed direction.

[0054] The following section uses a downhill ramp application as an example to introduce the workflow of a glitch-optimized digital-to-analog converter.

[0055] The thermometer decoder 201 receives the first type of digital signal of the digital ramp signal generated by the ramp generation module 100 and decodes it to generate thermometer code.

[0056] The synchronization circuit module 202 synchronizes the thermometer code and the second type of digital signal of the digital ramp signal. This ensures that the frequencies of the thermometer code and the second type of digital signal are the same as the sampling rate of the glitch-optimized digital-to-analog converter.

[0057] The bit control signal generation module 203 delays the thermometer code and the second type of digital signal, causing the thermometer code to lag behind the second type of digital signal, and generates a first bit control signal and a second bit control signal accordingly, which are used to control the switching of the R2R circuit. The toggling of the first bit control signal and the second bit control signal lags behind the generation of the pull-up pulse.

[0058] The first bit of the control signal corresponds to the thermometer code, and the second bit of the control signal corresponds to the second type of digital signal.

[0059] The pull-up pulse generation module receives the second bit control signal and the second type of digital signal to generate a pull-up pulse.

[0060] The pull-up circuit receives the pull-up pulse and generates a pull-up current, which fixes the output glitch direction of the R2R circuit 206 to be upward, that is, fixes the glitch output of the glitch optimization digital-to-analog converter 200 to be upward.

[0061] Figure 4 A schematic diagram of a synchronization circuit module according to an embodiment of the present invention is shown. Figure 5 A schematic diagram of the digital signal flipping before and after synchronization of a synchronization circuit module according to an embodiment of the present invention is shown. Figure 6 A schematic diagram of a bit control signal generation module and a pull-up pulse generation module according to an embodiment of the present invention is shown. Figure 7 The output waveform of a glitch-optimized digital-to-analog converter according to an embodiment of the present invention is shown.

[0062] like Figure 4As shown, the first type of digital signal of the digital ramp signal is decoded to obtain thermometer codes T1-Tn, and B1-Bn is the second type of digital signal that has not been decoded. The thermometer codes T1-Tn and the second type of digital signal B1-Bn are synchronized by a synchronization circuit module composed of D flip-flops to obtain the digital signals Bn_syn and Tn_syn. One D flip-flop corresponds to one bit.

[0063] like Figure 5 As shown, before synchronization, the thermometer codes T1-Tn and the second type of digital signals B1-Bn do not flip simultaneously. After being synchronized by the synchronization circuit module composed of D flip-flops (DFF), Bn_syn and Tn_syn will flip simultaneously.

[0064] like Figure 6 As shown, the bit control signal generation module 203 includes a first signal generation circuit and a second signal generation circuit. The first signal generation circuit includes a first delay unit 3011 and two first inverting amplifiers 3012 connected in series. The second signal generation circuit is a second delay unit 3021.

[0065] Because the first signal generation circuit has two more first inverting amplifiers 3012 than the second signal generation circuit, the signal travels a longer "distance", causing the first bit control signal Tn_en to lag behind the second bit control signal Bn_en.

[0066] The pull-up pulse generation module includes an XOR gate 401, a NOR gate 402, and a second inverting amplifier 403.

[0067] The first input terminal of the XOR gate 401 is connected to the input terminal of the second delay unit 3021 and the second input terminal of the NOR gate 402; the second input terminal of the XOR gate 401 is connected to the output terminal of the second delay unit 3021; ​​and the output terminal of the XOR gate 401 is connected to the first input terminal of the NOR gate 402.

[0068] The output of the NOR gate 402 is connected to the input of the second inverting amplifier 403, and the output of the second inverting amplifier 403 is used to output a pull-up pulse.

[0069] The bit control signal generation module 203 is equipped with a first delay unit 3011 and a second delay unit 3021. The purpose of this is to ensure that the output of the pull-up pulse Pulse_en is before the flip of the first bit control signal Tn_en and the second bit control signal Bn_en.

[0070] The synchronized thermometer code Tn_syn is used by the first signal generation circuit to generate the first bit control signal Tn_en.

[0071] The synchronized second type of digital signal Bn_syn is transmitted to the bit control signal generation module and enters the second signal generation circuit to generate the second bit control signal. At the same time, the synchronized second type of digital signal Bn_syn enters the pull-up pulse generation module.

[0072] After synchronization, the second type of digital signal Bn_syn is input to the bit control signal generation module and then transmitted to the pull-up pulse generation module. Simultaneously, it passes through the second signal generation circuit to generate the second bit control signal Bn_en, which is then transmitted to both the R2R circuit and the pull-up pulse generation module. The pull-up pulse generation module outputs the pull-up pulse Pulse_en. The pulse width of the pull-up pulse Pulse_en is only about 1ns. This is to charge the binary node of the R2R circuit at the moment of switching, ensuring that the output DAC_out of the glitch-optimized digital-to-analog converter does not produce downward glitches, but rather that all glitches are upward. The output waveform of the glitch-optimized digital-to-analog converter is shown below. Figure 7 As shown.

[0073] The first bit control signal Tn_en and the second bit control signal Bn_en are the enable signals for the R2R circuit switch. The first bit control signal Tn_en lags behind the second bit control signal Bn_en, which helps to reduce the generation of glitches.

[0074] The up-slope application of the glitch-optimized digital-to-analog converter is similar to the down-slope application described above, except that the pull-up pulse generation module is replaced with a pull-down pulse generation module, and the pull-up circuit is replaced with a pull-down circuit. The pull-down pulse width is only about 1 ns.

[0075] The aforementioned slope compensation circuit can be applied to microcontrollers or digital signal processors.

[0076] The present invention also provides a method for optimizing the output glitches of a digital-to-analog converter, comprising: Step 1: A digital ramp signal is generated by the ramp generation module. The digital ramp signal includes a first type of digital signal and a second type of digital signal. The digital ramp signal is a binary digital code, and the first type of digital signal is the high-order binary digital code relative to the second type of digital signal.

[0077] Step 2: The thermometer decoder receives the first type of digital signal and decodes it to generate thermometer code.

[0078] Step 3: The synchronization circuit module synchronizes the thermometer code with the second type of digital signal.

[0079] Step 4: The bit control signal generation module performs delay processing on the thermometer code and the second type of digital signal to generate the first bit control signal and the second bit control signal respectively. The flipping of the first bit control signal and the second bit control signal lags behind the generation of the pull-up pulse or pull-down pulse, and the first bit control signal lags behind the second bit control signal.

[0080] Step 5: The pull-up pulse generation module receives the second bit control signal and the second type of digital signal to generate a pull-up pulse, or the pull-down pulse generation module receives the second bit control signal and the second type of digital signal to generate a pull-down pulse.

[0081] Step 6: The pull-up circuit receives the pull-up pulse to generate the pull-up current, or the pull-down circuit receives the pull-down pulse to generate the pull-up current.

[0082] Step 7: The R2R circuit receives the pull-up or pull-down current, the first bit control signal, and the second bit control signal, and outputs a ramp voltage signal. The glitches in the ramp voltage signal are uniformly upward or downward.

[0083] Step 8: The voltage comparator outputs the comparison result based on the input sampling signal and the ramp voltage signal.

[0084] While some embodiments of the present invention have been described in this application, those skilled in the art will understand that these embodiments are merely illustrative. Numerous variations, alternatives, and improvements will arise in those skilled in the art under the teachings of this invention without departing from its scope. The appended claims are intended to define the scope of the invention and thereby cover methods and structures within the scope of the claims themselves and their equivalents.

Claims

1. A glitch-optimized digital-to-analog converter, characterized in that, include: A thermometer decoder, configured to receive a first-class digital signal of a digital ramp signal and decode it to generate a thermometer code; The synchronization circuit module is configured to synchronize the thermometer code with the second type of digital signal of the digital ramp signal. A bit control signal generation module is arranged after the synchronization module circuit and is configured to delay the thermometer code and the second type of digital signal, and generate a first bit control signal and a second bit control signal accordingly. The flipping of the first bit control signal and the second bit control signal lags behind the generation of the pull-up pulse, and the first bit control signal lags behind the second bit control signal. A pull-up pulse generation module is connected to the synchronization module circuit and the bit control signal generation module, and is configured to receive a second bit control signal and a second type of digital signal to generate a pull-up pulse; A pull-up circuit is arranged after the pull-up pulse generation module and is configured to receive pull-up pulses to generate pull-up current. The R2R circuit is connected to the pull-up circuit.

2. A glitch-optimized digital-to-analog converter, characterized in that, include: A thermometer decoder, configured to receive a first-class digital signal of a digital ramp signal and decode it to generate a thermometer code; The synchronization circuit module is configured to synchronize the thermometer code with the second type of digital signal of the digital ramp signal. A bit control signal generation module is arranged after the synchronization module circuit and is configured to delay the thermometer code and the second type of digital signal, and generate a first bit control signal and a second bit control signal accordingly. The flipping of the first bit control signal and the second bit control signal lags behind the generation of the pull-down pulse, and the first bit control signal lags behind the second bit control signal. A pull-down pulse generation module is connected to the synchronization module circuit and the bit control signal generation module, and is configured to receive a second bit control signal and a second type of digital signal to generate a pull-down pulse; A pull-down circuit is arranged after the pull-down pulse generation module and is configured to receive pull-down pulses to generate pull-down current; The R2R circuit is connected to the pull-down circuit.

3. The glitch-optimized digital-to-analog converter according to claim 1 or 2, characterized in that, The synchronization circuit module includes multiple D flip-flops.

4. The glitch-optimized digital-to-analog converter according to claim 1 or 2, characterized in that, The bit control signal generation module includes: The first signal generation circuit is configured to receive synchronized thermometer codes, perform delay processing, and generate a first bit control signal; the first signal generation circuit includes a first delay unit and two first inverting amplifiers connected in series. The second signal generation circuit is configured to receive the synchronized second type of digital signal, perform delay processing, and generate a second bit control signal, wherein the first bit control signal lags behind the second bit control signal; the second signal generation circuit is a second delay unit.

5. The glitch-optimized digital-to-analog converter according to claim 3, characterized in that, The pull-up pulse generation module includes an XOR gate, a NOR gate, and a second inverting amplifier arranged sequentially, wherein: The first input of the XOR gate is connected to the input of the second delay unit and the second input of the NOR gate; the second input of the XOR gate is connected to the output of the second delay unit; the output of the XOR gate is connected to the first input of the NOR gate. The output of the NOR gate is connected to the input of the second inverting amplifier, and the output of the second inverting amplifier is used to output the pull-up pulse.

6. The glitch-optimized digital-to-analog converter according to claim 1 or 2, characterized in that, The pull-down pulse or the pulse width of the pull-down pulse is 1 ns.

7. A slope compensation circuit, characterized in that, include: A ramp generation module, configured to generate digital ramp signals; The glitch-optimized digital-to-analog converter as described in any one of claims 1 to 6 is arranged after the ramp generation module and configured to generate a ramp voltage signal based on the digital ramp signal. A voltage comparator is placed after the glitch-optimized digital-to-analog converter and is configured to output a comparison result based on the input sampled signal and the ramp voltage signal.

8. A method for optimizing the output glitches of a digital-to-analog converter, characterized in that, include: A digital ramp signal is generated by a ramp generation module, the digital ramp signal comprising a first type of digital signal and a second type of digital signal; The thermometer decoder receives the first type of digital signal and decodes it to generate thermometer code; The synchronization circuit module synchronizes the thermometer code with the second type of digital signal. The bit control signal generation module delays the thermometer code and the second type of digital signal to generate a first bit control signal and a second bit control signal, respectively. The flipping of the first bit control signal and the second bit control signal lags behind the generation of the pull-up pulse or pull-down pulse, and the first bit control signal lags behind the second bit control signal. The pull-up pulse generation module receives the second bit control signal and the second type of digital signal to generate a pull-up pulse, or the pull-down pulse generation module receives the second bit control signal and the second type of digital signal to generate a pull-down pulse; Pull-up current is generated by receiving pull-up pulses from the pull-up circuit, or pull-down current is generated by receiving pull-down pulses from the pull-down circuit; The R2R circuit receives the pull-up or pull-down current, the first bit control signal, and the second bit control signal, and outputs the ramp voltage signal.

9. The method according to claim 7, characterized in that, The voltage comparator outputs the comparison result based on the input sampled signal and the ramp voltage signal.

10. A microcontroller unit, characterized in that, It has the slope compensation circuit as described in claim 7.

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