Dynamic precision-adjustable multipath parallel analog-to-digital converter

Abstract

The invention discloses a multi-channel parallel analog-to-digital converter with dynamically adjustable precision, which is characterized in that the existing digital interface resource (especially an LVDS receiver) in a chip is used as an analog voltage comparator to construct a multi-channel parallel sigma-delta modulator. Each path of conversion unit sets a counting target value through a programmable counter, so that the conversion precision and the sampling time of the path are independently and dynamically adjusted. And each path is started under a unified synchronous signal to realize synchronous sampling. A set of calibration system is further integrated, a high-precision external reference source is sampled through a specially-arranged reference conversion unit, and digital results of the high-precision external reference source are provided for all common channels, so that automatic calibration and temperature compensation of the system are achieved. According to the scheme, the design of the multi-path high-precision ADC is greatly simplified, and the ADC has the advantages of high integration level, low cost and easiness in implementation.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits and mixed signal processing technology, and particularly to a circuit structure for an analog-to-digital converter (ADC). Specifically, this invention provides an ADC architecture and its operation method that features dynamically adjustable conversion accuracy, multi-channel parallel synchronous sampling capability, and easy integration. It can be easily constructed using ASIC chips, FPGA soft cores, or discrete components, and offers advantages such as adjustable accuracy, controllable timing, easy scalability, and low cost. Background Technology

[0002] Analog-to-digital converters (ADCs) are key components in modern electronic systems that connect the physical analog world with digital information processing systems; their performance directly determines the data acquisition quality of the entire system. In many applications, such as industrial control, medical monitoring, battery management systems, and multi-sensor fusion systems, it is often necessary to simultaneously acquire multiple analog signals.

[0003] Currently, mainstream technologies for achieving multi-channel sampling have significant limitations. The first is the use of multiple independent ADC chips. While this approach guarantees performance, system cost, power consumption, and board area increase linearly with the number of channels, making integration difficult. The second is a time-division multiplexing scheme using analog multiplexers with a single ADC. Although this reduces hardware costs, the sequential sampling of each channel's signal makes strict time synchronization impossible, leading to phase differences between channels and making it unsuitable for applications requiring precise analysis of the timing relationships of multi-channel signals. The third is integrating multiple fixed-precision ADC cores on a single chip. While this solves the synchronization and integration problems, the resolution and sampling rate of each ADC core are fixed.

[0004] However, in practical applications, the characteristics of signals and the system's signal requirements are often dynamic. For example, in vibration monitoring, most of the time the signal is a stable low-amplitude signal, requiring only low-precision monitoring, while occasional impact signals require high-precision capture. In battery management systems, the system is mostly in a low-precision monitoring state, requiring high-precision measurement only under specific operating conditions. Using a fixed-precision ADC cannot adapt to these dynamic needs, resulting in wasted power consumption and data processing resources in low-demand scenarios, while failing to provide sufficient performance when high-demand scenarios arise.

[0005] Furthermore, the limitations of the above solutions become even more pronounced in high-end applications requiring simultaneous sampling of high channel counts (e.g., tens or even hundreds). Whether using multiple independent ADC chips or a dedicated analog chip integrating multiple fixed ADCs, both approaches suffer from high system complexity, large size, and high cost. More importantly, mainstream digital processing devices (such as the digital logic sections of FPGAs and ASICs) typically do not integrate such a large number of high-precision analog ADC units. Therefore, engineers are forced to adopt a hybrid architecture of "digital main chip + multiple external ADC chips." This architecture not only increases the number of components, board area, and wiring complexity, but also introduces more signal integrity issues, power consumption, and overall cost, becoming a core bottleneck in realizing high-density data acquisition systems.

[0006] Therefore, there is an urgent need in this field for an analog-to-digital conversion solution that can simultaneously achieve high integration, truly synchronous sampling, flexible dynamic precision adjustment, and low implementation cost. An ideal solution should be able to directly utilize the abundant existing resources on digital chip platforms to construct an analog-to-digital conversion array with extremely high channel counts in the simplest way, thereby fundamentally reducing system complexity, size, and cost. Summary of the Invention

[0007] I. Purpose of the Invention

[0008] The present invention aims to provide a dynamically adjustable precision multi-channel parallel analog-to-digital converter to solve the following problems existing in the prior art:

[0009] The sampling accuracy and sampling time of existing analog-to-digital converters are usually fixed and cannot be dynamically and flexibly adjusted according to actual application requirements. As a result, they cannot keep up with changes in sampling requirements and can only be selected according to the highest requirements, which is costly and inefficient.

[0010] Existing multi-channel synchronous sampling solutions either result in system complexity, high cost, and large size due to the use of independent chips, or fail to achieve true synchronous sampling due to the use of analog switches for time-division multiplexing, making it difficult to balance performance, cost, and integration in high-channel-count applications.

[0011] Traditional analog circuit design, especially schemes that integrate a large number of high-precision voltage comparators, faces challenges such as design complexity, large chip area, high power consumption, and difficulty in offset voltage calibration.

[0012] II. Technical Solution

[0013] To achieve the above objectives, the present invention adopts the following technical solution:

[0014] A dynamically adjustable precision multi-channel parallel analog-to-digital converter (ADC) includes a control module, a reference ADC unit, and N ordinary ADC units, where N is a positive integer greater than or equal to 1. The control module is connected to all ADC units via a configuration bus and provides a unified synchronization start signal to all units.

[0015] 1. Core Structure of the Analog-to-Digital Converter

[0016] Reference Figure 1 Each of the analog-to-digital conversion units includes:

[0017] 1-bit Σ-Δ modulator: used for oversampling and noise shaping of analog input signals, outputting a 1-bit bit stream;

[0018] Sampling counter: Its enable input is connected to the output of the 1-bit Σ-Δ modulator to count the high or low levels in the 1-bit bit stream; the sampling counter also has a clear input, which is cleared in the next clock cycle when a clear signal is received.

[0019] Programmable Counter: A programmable counter connected to the control module, used to store predefined counting target values ​​and perform counting. Its output is connected to the reset input of the sampling counter. The programmable counter is configured to output a flag signal indicating that the conversion is complete when its count value reaches the counting target value, which also serves as the reset signal for the sampling counter. At the same time, the current count value of the sampling counter is output as the digital result of this analog-to-digital conversion. By configuring different counting target values ​​for the setting register, the conversion accuracy and conversion time of each analog-to-digital conversion unit can be dynamically adjusted.

[0020] 2. Dynamic adjustment and synchronous sampling principle

[0021] Reference Figure 2 Its working principle is as follows: Upon receiving a unified synchronization start signal, all sampling counters and programmable counters on all paths begin counting simultaneously. When the count value reaches its preset target value, the programmable counter outputs a flag signal indicating that the conversion is complete, which also serves as a reset signal for the sampling counter. Simultaneously, the current count value of the sampling counter is output as the digital result of this analog-to-digital conversion. By configuring different target count values ​​for the programmable counters of different paths, each path can independently end the conversion at different times, thereby achieving the purpose of dynamically adjusting the conversion accuracy (the larger the target count value, the higher the accuracy) and conversion time (the larger the target count value, the longer the time).

[0022] 3. Automatic calibration mechanism

[0023] Reference Figure 3Each analog-to-digital converter (ADC) unit also includes a calibration circuit. The calibration circuit has three input terminals: a data input terminal connected to the output of the sampling counter for this channel, a reference input terminal connected to the output of the reference ADC unit, and a configuration input terminal connected to a configuration constant in the control module. The calibration circuit performs the following calculation: Final Output = (Data Input - Reference Input) + Configuration Constant.

[0024] The structure of the reference analog-to-digital converter unit is the same as that of a regular unit, but its analog input is connected to a high-precision, stable external reference voltage source, the reference input is connected to a value of all zeros, and the configuration input is connected to a factory-set constant, so that its output is directly equal to the sum of the sampled value of the reference voltage and the factory constant. This value serves as a "scale" connected to the reference input of all regular channels. Through the above subtraction operation, the effects of common-mode interference, power supply voltage fluctuations, temperature changes, and other factors coupled in the signal path can be effectively offset, thereby realizing the automatic sampling calibration function and significantly improving the overall accuracy and long-term stability of the system.

[0025] 4. Preferred Implementation Scheme with High Integration and Low Cost

[0026] Reference Figure 4 To achieve high integration and low cost, in a preferred embodiment of the present invention, the 1-bit Σ-Δ modulator is composed of very few external components and internal digital chip resources. Specifically, the modulator includes:

[0027] External passive network: The sample-and-hold and feedback filtering network consists of two resistors (R1, R2) and two capacitors (C1, C2). The low-pass filter formed by R1 and C1 acts as a digital-to-analog converter, and the low-pass filter formed by R2 and C2 acts as a sample-and-hold circuit. The resistance values ​​of R1 and R2 are equal, and the capacitance values ​​of C1 and C2 are equal to avoid introducing additional static errors.

[0028] Internal Digital Resources: The voltage comparator in the modulator is implemented using a large number of low-voltage differential signal receivers integrated within the digital chip. The LVDS receiver itself is a high-performance differential comparator; by connecting its positive and negative inputs to the sampling signal and feedback signal respectively, it perfectly performs the function of 1-bit analog-to-digital conversion. This design greatly reduces the dependence on external dedicated analog chips, making it possible to integrate dozens or even hundreds of analog-to-digital converters within a single digital chip (such as an FPGA or ASIC), fundamentally reducing system complexity, size, and cost.

[0029] III. Beneficial Effects

[0030] Compared with the prior art, the present invention has the following significant advantages:

[0031] Dynamic and flexible, allocated on demand: By simply configuring the counting target value through software, the accuracy and speed of each channel can be adjusted in real time and independently, realizing intelligent sampling resource management. While ensuring the sampling quality of key signals, the overall energy efficiency of the system is optimized.

[0032] True synchronization and data consistency: All channels start working under a unified synchronization start signal, ensuring strict consistency of multi-channel sampled data on the time axis, making it very suitable for applications with stringent timing requirements such as multi-sensor fusion, coulomb counting, and phase measurement.

[0033] High precision and high stability: Built-in reference channel and unique calibration algorithm (such as...) Figure 3 As shown, it can automatically cancel common-mode error and has a strong suppression effect on power supply noise, temperature drift and process deviation, ensuring the long-term accuracy and reliability of measurement results.

[0034] High integration and low cost: The core analog comparison function is implemented by utilizing the readily available and abundant LVDS interface resources in the digital chip (such as...). Figure 4 As shown in the figure, with minimal external resistors and capacitors, it breaks through the design barriers of traditional analog ADCs. This makes building ultra-high channel number analog-to-digital converter arrays simple and economical, greatly reducing the hardware complexity and total cost of the system. Attached Figure Description

[0035] Figure 1 Overall structure diagram of a multi-channel parallel analog-to-digital converter

[0036] Figure 2 Schematic diagram of multi-channel adjustable precision sampling

[0037] Figure 3 Schematic diagram of automatic calibration

[0038] Figure 4 Example diagram of the solution Specific implementation methods

[0039] The preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings. This embodiment demonstrates how to construct a multi-channel parallel analog-to-digital converter with dynamic precision adjustment and automatic calibration functions using FPGA internal resources and a small number of external components.

[0040] Example: A multi-channel dynamically adjustable ADC system based on FPGA and LVDS interface

[0041] Reference Figures 1 to 4 The core architecture of this system integrates most of the circuitry inside the FPGA, placing only a simple analog front-end outside the chip, thereby achieving high integration and low cost.

[0042] 1. System Overall Structure: Division of Labor Between Off-Chip and On-Chip

[0043] The core of the system is an FPGA digital device, which internally implements the control module (101) and all digital logic functions.

[0044] Outside the FPGA chip, each analog-to-digital conversion unit (including general-purpose and reference units) contains only two passive networks:

[0045] Sample and hold circuit (201): It consists of resistors and capacitors.

[0046] Digital-to-analog converter (202): It consists of a 1-bit switch (usually a transistor or analog switch driven by an FPGA pin) and a network of resistors and capacitors, or it can be directly composed of the FPGA's general-purpose I / O and resistors and capacitors.

[0047] Inside the FPGA chip, complete digital and interface logic is implemented for each conversion unit (102, 103):

[0048] General purpose voltage comparator (203): Innovatively implemented by a large number of LVDS receivers integrated on an FPGA chip;

[0049] Sampling counter (204): Used to count the output level of a general-purpose voltage comparator;

[0050] Programmable counter (205): Used to count the total sampling time;

[0051] Calibration circuit (206): used to calibrate the output of the sampling counter to form accurate sampling results.

[0052] The control module (101) stores configuration constants (207) and can distribute them to each channel, while also controlling the counting target value of each programmable counter.

[0053] 2. Distinguishing between reference channel and ordinary channel

[0054] This system comprises two functional units:

[0055] Ordinary conversion unit (102): Its external sample-and-hold circuit (201) is connected to the analog signal to be measured.

[0056] Reference conversion unit (103): Its external sample-and-hold circuit (201) is connected to an externally provided high-precision, stable reference voltage source Vref. Note that the reference conversion unit (103) itself is a special general conversion unit (102), not a reference voltage source.

[0057] Apart from the difference in analog input signal, the reference input of the calibration circuit (206) of the reference conversion unit (103) is directly grounded, which is equivalent to all zero input. The rest of the circuit structure (203, 204, 205) inside the FPGA is exactly the same as that of the ordinary conversion unit (102).

[0058] 3. Core Transformation and Dynamic Adjustment Process

[0059] The analog signal (or reference voltage) is fed into the FPGA pin via an external sample-and-hold circuit (201) and connected to the positive input of the LVDS receiver (203). The general-purpose voltage comparator (203), which is composed of the LVDS receiver, compares it with the feedback voltage from the external digital-to-analog converter (202) connected to the negative input, and outputs a 1-bit bit stream. This bit stream controls the switching state of the external digital-to-analog converter (202) to form a closed-loop feedback; on the other hand, it is sent to the sampling counter (204) for counting.

[0060] The control module (101) independently sets the target count value for each programmable counter (205). Under a unified synchronous start signal, all counters start working. When a programmable counter (205) of a certain channel reaches the target value, it generates a conversion completion signal and latches the value of the sampling counter (204) at that moment as the original conversion result. By configuring different target values, independent and dynamic adjustment of the accuracy and conversion time of each path is achieved. Through the internal logic of the FPGA, single conversion and cyclic conversion modes can be switched, and the target count value of each channel does not have to be an integer multiple, which has extremely high flexibility.

[0061] 4. Detailed Explanation of Automatic Calibration Mechanism

[0062] The calibration of this invention is performed in the digital domain. The raw conversion result of each path is processed in the calibration circuit (206), which performs the following operations:

[0063] Final output = (raw data input - baseline input) + configuration constant (207)

[0064] in:

[0065] Raw data input: Output value from the local sampling counter (204).

[0066] Reference input: The output value from the reference conversion unit (103). This value is the digital result obtained by the reference conversion unit (103) after sampling and converting the external reference voltage Vref, and it serves as the "ruler" of the system.

[0067] Configuration constant (207): Provided by the control module (101) for fine-tuning the channel offset.

[0068] The essence of this calibration mechanism lies in the fact that any common-mode error affecting the entire system (such as power supply fluctuations, temperature drift, etc.) will simultaneously and proportionally affect the original outputs of the ordinary unit (102) and the reference unit (103). By performing a subtraction operation (original data - reference data) in the calibration circuit (206) of the ordinary unit, these common-mode errors are effectively canceled out, thereby significantly improving the overall accuracy and long-term stability of the system.

[0069] When the target count value of the reference conversion unit (103) is different from that of the ordinary conversion unit (102), the reference input data for calibration needs to be scaled proportionally before entering the calibration circuit (206) to match the numerical differences of different target count values.

[0070] In summary, this invention innovatively uses the LVDS receiver inside the FPGA as a voltage comparator, working in conjunction with a minimalist external RC network, to construct a highly integrated multi-channel ADC system capable of easily achieving parallel sampling of hundreds of analog signals. The system achieves a flexible accuracy-speed tradeoff through the target value of a programmable counter, and utilizes a single, structurally identical reference sampling channel to achieve efficient global digital calibration.

[0071] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A dynamically adjustable precision multi-channel parallel analog-to-digital converter, comprising multiple parallel analog-to-digital conversion units, characterized in that, Each of the aforementioned analog-to-digital conversion units includes: (1) A 1-bit Σ-Δ modulator is used to oversample and noise-shape the analog input signal and output a 1-bit bit stream; (2) A sampling counter, whose enable input is connected to the output of the 1-bit Σ-Δ modulator, counts the high or low levels in the 1-bit bit stream; the sampling counter also has a clear input, which is cleared in the next clock cycle when a clear signal is received. (3) A programmable counter connected to the control module is used to store a predefined counting target value and count, and its output is connected to the clear input terminal of the sampling counter; wherein, the programmable counter is configured to: when its count value reaches the counting target value, output a flag signal indicating that the conversion is completed and simultaneously serve as the clear signal of the sampling counter, and output the current count value of the sampling counter as the digital result of the analog-to-digital conversion; by configuring different counting target values ​​for the setting register, the conversion accuracy and conversion time of each analog-to-digital conversion unit can be dynamically adjusted.

2. The dynamically adjustable precision multi-channel parallel analog-to-digital converter according to claim 1, characterized in that: The 1-bit Σ-Δ modulator includes a general-purpose voltage comparator, a 1-bit digital-to-analog converter (DAC), and a sample-and-hold circuit. The general-purpose voltage comparator performs a 1-bit DAC function, and its output is the 1-bit bitstream output of the 1-bit Σ-Δ modulator, connected to the input of the 1-bit DAC. The output of the 1-bit DAC is connected back to the negative input of the general-purpose voltage comparator, forming a feedback loop. The analog input signal is connected to the positive input of the general-purpose voltage comparator through the sample-and-hold circuit.

3. A dynamically adjustable precision multi-channel parallel analog-to-digital converter according to claim 2, characterized in that, The general-purpose voltage comparator is implemented by a low-voltage differential signal receiver or a voltage comparator.

4. A dynamically adjustable precision multi-channel parallel analog-to-digital converter according to claim 1, characterized in that: The programmable counters in each analog-to-digital conversion unit can be independently configured to different target counting values; each sampling counter and programmable counter starts counting after receiving a unified synchronization start signal and runs independently until the conversion is complete.

5. A dynamically adjustable precision multi-channel parallel analog-to-digital converter according to claim 1, characterized in that: Each analog-to-digital conversion unit also includes a calibration circuit; the calibration circuit has a data input terminal, a reference input terminal and a configuration input terminal, the data input terminal is connected to the output of the sampling counter of this channel, and the configuration input terminal is connected to the control module or set to a constant; The calibration circuit is used to perform calibration calculations on the digital values ​​of the data input terminal based on the digital values ​​of the reference input terminal and the configuration input terminal, and output the calibrated digital result as the final sampling result of this channel.

6. A dynamically adjustable precision multi-channel parallel analog-to-digital converter according to claim 5, characterized in that: A reference analog-to-digital converter (ADC) is provided; the reference ADC has the same structure as a regular ADC, but its calibration circuit's reference input is connected to all zeros, and its configuration input is connected to a factory-set configuration constant. The analog input terminal of the reference analog-to-digital converter is connected to a high-precision and stable reference voltage source; The final sampling result output of the reference analog-to-digital converter unit is used as the digital value of the reference voltage and connected to the reference input terminal of all ordinary analog-to-digital converter units.

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