Radio frequency power detector with offset and temperature compensation

Abstract

The invention relates to a radio frequency power detector with offset and temperature compensation. Wireless circuitry may include a transmit line carrying a signal and a power detector measuring the signal. The detector may include a rectifier coupled to the comparator through a differential path. An offset calibration digital-to-analog converter (OSDAC), a reference generator, and a multiplexer may be disposed on a negative line of the differential path. The OSDAC may generate an offset compensation voltage by superimposing different offset voltages over time to a voltage on the second line. The reference generator may generate a set of threshold voltages by superimposing different reference voltages to the offset compensation voltage. A temperature sensor may adjust the reference voltages used to generate the threshold voltages based on a temperature of the power detector. The multiplexer may route different threshold voltages to the negative input of the comparator.

Description

Technical Field

[0001] This disclosure relates in its entirety to electronic devices, including electronic devices having wireless communication circuitry. Background Technology

[0002] Electronic devices can possess wireless communication capabilities. Electronic devices with wireless communication capabilities have wireless communication circuits, which have one or more antennas. The wireless transceiver circuit within the wireless communication circuit uses the antennas to transmit and receive radio frequency signals.

[0003] The radio frequency (RF) signal transmitted by the antenna can be fed through a power amplifier configured to amplify the low-power analog signal into a high-power signal more suitable for long-distance transmission over the air. The RF signal received at the antenna can be fed through a low-noise amplifier configured to amplify the low-power analog signal into a high-power signal for processing at the receiver. A power detector can be used to measure the power level of either the power amplifier or the low-noise amplifier. Designing a satisfactory power detector can be challenging. Summary of the Invention

[0004] Electronic devices may include wireless circuitry. Wireless circuitry may include radio frequency (RF) transmission lines carrying RF signals. Wireless circuitry may include power detectors that measure the power level of RF signals.

[0005] The power detector may include a rectifier coupled to the comparator via a differential signal path. The differential signal path may include a first line coupled to the positive input of the comparator and a second line coupled to the negative input of the comparator. An offset-calibrated digital-to-analog converter (OSDAC), a reference generator, and a multiplexer may be disposed on the second line. Digital logic may be operatively coupled to the outputs of the comparator and the multiplexer.

[0006] The OSDAC can be calibrated and controlled to generate offset-compensated voltages by superimposing different offset voltages onto the voltage on the second line over time. The offset voltages cancel out the offset imposed by the rectifier given its current operating conditions. A reference generator can be calibrated and controlled to generate a set of threshold voltages by superimposing different reference voltages onto the offset-compensated voltages. A temperature sensor can adjust the reference voltages used to generate the threshold voltages based on the temperature of the power detector. The temperature sensor can, for example, adjust an adjustable current source in the reference generator based on temperature. A multiplexer routes different threshold voltages to the negative input of a comparator. A low-pass filter filters common-mode noise from the voltage supplied to the positive input of the comparator. The comparator can provide an output signal to digital logic. The digital logic can control the multiplexer based on the output signal. The digital logic can output a digital code based on the output signal and indicating the power level of the RF signal. Attached Figure Description

[0007] Figure 1 These are illustrations of exemplary electronic devices with wireless circuitry according to some implementation schemes.

[0008] Figure 2 This is a diagram of an exemplary wireless circuit with a radio frequency amplifier according to some implementation schemes.

[0009] Figure 3 This is a diagram illustrating an exemplary power detector coupled to the output of an RF amplifier according to some embodiments.

[0010] Figure 4 This is a diagram illustrating an exemplary power detector with offset capability and temperature compensation capability according to some implementation schemes.

[0011] Figure 5 This is a circuit diagram of an exemplary circuit in a power detector with offset capability and temperature compensation capability according to some implementation schemes.

[0012] Figure 6 This is a flowchart illustrating exemplary operations involved in operating a power detector according to some implementation schemes.

[0013] Figure 7 This is a timing diagram illustrating an example of how an exemplary power detector can perform offset calibration operations according to some implementation schemes.

[0014] Figure 8 This is a timing diagram illustrating an example of how an exemplary power detector can perform a threshold calibration operation according to some implementation schemes.

[0015] Figure 9 This is a timing diagram illustrating an example of how an exemplary power detector can measure radio frequency signals according to some implementation schemes. Detailed Implementation

[0016] Electronic devices, such as Figure 1 The device 10 may include wireless circuitry. This wireless circuitry may include radio frequency (RF) amplifiers, such as power amplifiers and low-noise amplifiers. The power amplifiers may amplify the RF signal in the transmit path, while the low-noise amplifiers may amplify the RF signal in the receive path. Power detection circuitry (sometimes referred to as a power detector) may be coupled to the outputs of these RF amplifiers. The power detector coupled to the output of the RF power amplifier may be configured to run an adaptive power control algorithm for adjusting the power level of the power amplifier, while the power detector coupled to the output of the RF low-noise amplifier may be used to run an automatic gain control algorithm for adjusting the power level of the low-noise amplifier.

[0017] Figure 1The electronic device 10 may be: a computing device, such as a laptop computer, desktop computer, computer monitor containing an embedded computer, tablet computer, cellular phone, media player, or other handheld or portable electronic device; a smaller device, such as a wristwatch, a hanging device, a headset or handset, a device embedded in glasses, goggles, or a helmet; or other equipment worn on the user's head (e.g., an augmented reality, virtual reality, or mixed reality head-mounted display); or another wearable or micro device, a television, a computer monitor without an embedded computer, a gaming device, a navigation device, an embedded system (such as a system in which electronic equipment with a display is installed in a kiosk or a car), a voice-controlled speaker connected to the wireless Internet, a home entertainment device, a remote control device, a game controller, a peripheral user input device, a wireless base station or access point, equipment that enables the functionality of two or more of these devices; or other electronic equipment.

[0018] like Figure 1 As shown in the functional block diagram, device 10 may include components located on or within an electronic device housing, such as housing 12. Housing 12 (sometimes referred to as a shell) may be formed of plastic, glass, ceramic, fiber composite material, metal (e.g., stainless steel, aluminum, metal alloys, etc.), other suitable materials, or combinations of these materials. In some embodiments, part or all of housing 12 may be formed of a dielectric or other low-conductivity material (e.g., glass, ceramic, plastic, sapphire, etc.). In other embodiments, housing 12 or at least some of the structures constituting housing 12 may be formed of metallic elements.

[0019] Device 10 may include control circuitry 14. Control circuitry 14 may include storage devices, such as storage circuitry 16. Storage circuitry 16 may include hard disk drive storage devices, non-volatile memory (e.g., flash memory configured to form a solid-state drive or other electrically programmable read-only memory), volatile memory (e.g., static random access memory or dynamic random access memory), etc. Storage circuitry 16 may include storage devices integrated within device 10, and / or removable storage media.

[0020] Control circuitry 14 may include processing circuitry, such as processing circuitry 18. Processing circuitry 18 may be used to control the operation of device 10. Processing circuitry 18 may include one or more processors, such as a microprocessor, microcontroller, digital signal processor, host processor, baseband processor integrated circuit, application-specific integrated circuit, central processing unit (CPU), graphics processing unit (GPU), etc. Control circuitry 14 may be configured to perform operations in device 10 using hardware (e.g., dedicated hardware or circuitry), firmware, and / or software. Software code for performing operations in device 10 may be stored on storage circuitry 16 (e.g., storage circuitry 16 may include a non-transitory (tangible) computer-readable storage medium storing software code). This software code may sometimes be referred to as program instructions, software, data, instructions, or code. The software code stored on storage circuitry 16 may be executed by processing circuitry 18.

[0021] Control circuitry 14 can be used to run software on device 10, such as satellite navigation applications, internet browsing applications, Voice over Internet Protocol (VoIP) telephone calling applications, email applications, media playback applications, operating system functions, etc. To support interaction with external equipment, control circuitry 14 can be used to implement communication protocols. Communication protocols that can be implemented using control circuitry 14 include Internet Protocol, Wireless Local Area Network (WLAN) protocols (e.g., IEEE 802.11 protocol—sometimes referred to as...). ), such as Protocols used for other short-range wireless communication links, such as protocols or other Wireless Personal Area Network (WPAN) protocols, IEEE 802.11ad protocols (e.g., Ultra Wideband protocols), cellular phone protocols (e.g., 3G protocols, 4G (LTE) protocols, 3GPP 5th Generation (5G) New Radio (NR) protocols, 6th Generation (6G) protocols, THz protocols, sub-THz protocols, etc.), antenna diversity protocols, satellite navigation system protocols (e.g., Global Positioning System (GPS) protocols, Global Navigation Satellite System (GLONASS) protocols, etc.), antenna-based spatial ranging protocols, optical communication protocols, or any other desired communication protocol. Each communication protocol may be associated with a corresponding Radio Access Technology (RAT), which specifies the physical connection method used to implement the protocol.

[0022] Device 10 may include input-output circuitry 20. Input-output circuitry 20 may include input-output device 22. Input-output device 22 may be used to allow data to be supplied to device 10 and to allow data to be provided from device 10 to external devices. Input-output device 22 may include user interface devices, data port devices, and other input-output components. For example, input-output device 22 may include touch sensors, displays (e.g., touch-sensitive displays and / or force-sensitive displays), light-emitting components such as displays without touch sensor capability, buttons (mechanical, capacitive, optical, etc.), scroll wheels, touchpads, keypads, keyboards, microphones, cameras, buttons, speakers, status indicators, audio jacks and other audio port components, digital data port devices, motion sensors (accelerometers, gyroscopes, and / or compasses for detecting motion), capacitive sensors, proximity sensors, magnetic sensors, force sensors (e.g., force sensors coupled to a display to detect pressure applied to the display), etc. In some configurations, keyboards, headphones, displays, pointing devices such as touchpads, mice and joysticks, and other input-output devices can be coupled to device 10 using wired or wireless connections (e.g., some input-output devices in input-output devices 22 can be peripherals coupled to the main processing unit or other parts of device 10 via wired or wireless links).

[0023] Input-output circuitry 20 may include wireless circuitry 24 to support wireless communication. Wireless circuitry 24 (sometimes referred to herein as wireless communication circuitry 24) may include one or more antennas. Wireless circuitry 24 may also include baseband processor circuitry, transceiver circuitry, amplifier circuitry, filter circuitry, switching circuitry, RF transmission lines, and / or any other circuitry for transmitting and / or receiving RF signals using antennas.

[0024] Wireless circuit 24 can transmit and / or receive radio frequency signals within a corresponding frequency band of a radio frequency (sometimes referred to herein as the communication band or simply the "band"). The frequency band processed by wireless circuit 24 may include the wireless local area network (WLAN) band (e.g., (IEEE 802.11) or other WLAN communication bands, such as the 2.4 GHz WLAN band (e.g., 2400 MHz to 2480 MHz), the 5 GHz WLAN band (e.g., 5180 MHz to 5825 MHz), 6E band (e.g., 5925MHz to 7125MHz), 7-band and / or other Frequency bands (e.g., 1875MHz to 5160MHz); Wireless Personal Area Network (WPAN) frequency bands such as 2.4GHz Frequency bands or other WPAN communication bands; cellular phone bands (e.g., bands from approximately 600 MHz to approximately 5 GHz, 3G bands, 4G LTE bands, 5G New Radio Frequency Range 1 (FR1) band below 10 GHz, 5G New Radio Frequency Range 2 (FR2) band between 20 GHz and 60 GHz, etc.); other centimeter or millimeter wave bands between 10 GHz and 100 GHz; sub-THz bands between approximately 100 GHz and 10 THz (e.g., 6G bands); near field communication (NFC) bands (e.g., 13.56 MHz); satellite navigation bands (e.g., GPS bands from 1565 MHz to 1610 MHz, GLONASS bands, BDS bands, etc.); ultra-wideband (UWB) bands operating under the IEEE 802.15.4 protocol and / or other ultra-wideband communication protocols; communication bands under the 3GPP wireless communication standards family; in IEEE Communication bands under the 802.XX standard family; and / or any other desired bands of interest.

[0025] Figure 2 This is a diagram showing exemplary components within wireless circuit 24. For example... Figure 2 As shown, wireless circuitry 24 may include a processor such as processor 26, radio frequency (RF) transceiver circuitry such as RF transceiver 28, RF front-end circuitry such as RF front-end module (FEM) 40, and antenna 42. Processor 26 may be a baseband processor, application processor, general-purpose processor, microprocessor, microcontroller, digital signal processor, host processor, dedicated signal processing hardware, or other type of processor. Processor 26 may be coupled to transceiver 28 via path 34. Transceiver 28 may be coupled to antenna 42 via RF transmit line path 36. RF front-end module 40 may be disposed on RF transmit line path 36 between transceiver 28 and antenna 42.

[0026] exist Figure 2In the example, for clarity, wireless circuit 24 is illustrated as including only a single processor 26, a single transceiver 28, a single front-end module 40, and a single antenna 42. Generally, wireless circuit 24 may include any desired number of processors 26, any desired number of transceivers 28, any desired number of front-end modules 40, and any desired number of antennas 42. Each processor 26 may be coupled to one or more transceivers 28 via a corresponding path 34. Each transceiver 28 may include transmitter circuitry 30 configured to output uplink signals to antenna 42, may include receiver circuitry 32 configured to receive downlink signals from antenna 42, and may be coupled to one or more antennas 42 via a corresponding RF transmit line path 36. Each RF transmit line path 36 may have a corresponding front-end module 40 disposed thereon. If desired, two or more front-end modules 40 may be disposed on the same RF transmit line path 36. If desired, one or more RF transmit line paths 36 in wireless circuit 24 may be implemented without any front-end modules disposed thereon.

[0027] The RF transmit line path 36 can be coupled to an antenna feed section on the antenna 42. The antenna feed section can, for example, include a positive antenna feed terminal and a ground antenna feed terminal. The RF transmit line path 36 can have a positive transmit line signal path coupled to a positive antenna feed terminal on the antenna 42. The RF transmit line path 36 can also have a ground transmit line signal path coupled to a ground antenna feed terminal on the antenna 42. This example is merely illustrative, and in general, the antenna 42 can be fed using any desired antenna feeding scheme. If desired, the antenna 42 can have multiple antenna feed sections coupled to one or more RF transmit line paths 36.

[0028] RF transmission line path 36 may include a means for connecting device 10 ( Figure 1 The transmitting lines in device 10 are used to route the radio frequency antenna signals. The transmitting lines in device 10 may include coaxial cables, microstrip transmitting lines, stripline transmitting lines, edge-coupled microstrip transmitting lines, edge-coupled stripline transmitting lines, and transmitting lines formed by combinations of these types of transmitting lines. The transmitting lines in device 10 (such as the transmitting lines in radio frequency transmitting line path 36) can be integrated into rigid and / or flexible printed circuit boards.

[0029] During wireless transmission, processor 26 can provide a transmit signal (e.g., a digital or baseband signal) to transceiver 28 via path 34. Transceiver 28 may also include circuitry for converting the transmit (baseband) signal received from processor 26. For example, transceiver circuitry 28 may include mixer circuitry for up-converting (or modulating) the transmit (baseband) signal to radio frequency before transmission via antenna 42. The processor 26 communicates with transceiver 28 in this manner. Figure 2 The examples provided are merely illustrative. Generally, transceiver 28 can communicate with a baseband processor, application processor, general-purpose processor, microcontroller, microprocessor, or one or more processors within circuit 18. Transceiver circuit 28 may also include digital-to-analog converter (DAC) circuitry and / or analog-to-digital converter (ADC) circuitry for converting signals between the digital and analog domains. Transceiver 28 can transmit radio frequency (RF) signals via transmitter (TX) 30 through RF transmission line path 36 and front-end module 40 via antenna 42. Antenna 42 can transmit the RF signal to external wireless equipment by radiating it into free space.

[0030] When performing wireless reception, antenna 42 can receive radio frequency (RF) signals from external wireless equipment. The received RF signals can be transmitted to transceiver 28 via RF transmission line path 36 and front-end module 40. Transceiver 28 may include circuitry, such as receiver (RX) 32, for receiving signals from front-end module 40 and for converting the received RF signals into corresponding baseband signals. For example, transceiver 28 may include mixer circuitry for down-converting (or demodulating) the received RF signals to baseband frequencies before transmitting the received signals via path 34 to processor 26.

[0031] The front-end module (FEM) 40 may include radio frequency front-end circuitry that operates on radio frequency signals transmitted (transmitted and / or received) via radio frequency transmit line path 36. FEM 40 may include, for example, front-end module (FEM) components such as radio frequency filter circuitry 44 (e.g., low-pass filter, high-pass filter, notch filter, band-pass filter, multiplexer circuitry, duplexer circuitry, dual-channel circuitry, triplexer circuitry, etc.), switching circuitry 46 (e.g., one or more radio frequency switches), radio frequency amplifier circuitry 48 (e.g., one or more power amplifier circuitry 50 and / or one or more low-noise amplifier circuitry 52), signal attenuators, impedance matching circuitry (e.g., circuitry that helps match the impedance of antenna 42 to the impedance of radio frequency transmit line 36), antenna tuning circuitry (e.g., a network of capacitors, resistors, inductors, and / or switches that adjust the frequency response of antenna 42), radio frequency coupler circuitry, charge pump circuitry, power management circuitry, digital control and interface circuitry, and / or any other desired circuitry that operates on the radio frequency signals transmitted and / or received by antenna 42. Each of the front-end module components can be mounted on a common (shared) substrate, such as a rigid printed circuit board substrate or a flexible printed circuit board substrate. If desired, the various front-end module components can also be integrated into a single integrated circuit chip. If desired, amplifier circuit 48 and / or other components in front-end 40 (such as filter circuit 44) can also be implemented as part of transceiver circuit 28.

[0032] Filter circuit 44, switching circuit 46, amplifier circuit 48, and other circuits may be arranged along RF transmit line path 36, may be incorporated into FEM 40, and / or may be incorporated into antenna 42 (e.g., to support antenna tuning, to support operation in a desired frequency band, etc.). These components (sometimes referred to herein as antenna tuning components) may be adjusted (e.g., using control circuit 14) to adjust the frequency response and wireless performance of antenna 42 over time.

[0033] Transceiver 28 may be separate from front-end module 40. For example, transceiver 28 may be formed on another substrate such as the main logic board of device 10, a rigid printed circuit board, or a flexible printed circuit that is not part of front-end module 40. Although for clarity, in Figure 1In the example, control circuitry 14 is shown separate from wireless circuitry 24, but wireless circuitry 24 may include processing circuitry and / or storage circuitry, the processing circuitry forming part of processing circuitry 18, and the storage circuitry forming part of storage circuitry 16 of control circuitry 14 (e.g., portions of control circuitry 14 may be implemented on wireless circuitry 24). As an example, portions of processor 26 and / or transceiver 28 (e.g., a host processor on transceiver 28) may form part of control circuitry 14. Control circuitry 14 (e.g., portions of control circuitry 14 formed on processor 26, portions of control circuitry 14 formed on transceiver 28, and / or portions of control circuitry 14 separate from wireless circuitry 24) may provide control signals (e.g., via one or more control paths in device 10) to control the operation of front-end module 40.

[0034] Transceiver 28 may include a frequency band for processing WLAN communications (e.g., (IEEE 802.11) or other WLAN communication bands, such as the 2.4 GHz WLAN band (e.g., 2400 MHz to 2480 MHz), the 5 GHz WLAN band (e.g., 5180 MHz to 5825 MHz), 6E band (e.g., 5925MHz to 7125MHz) and / or others Wireless LAN transceiver circuitry covering a frequency band (e.g., 1875MHz to 5160MHz); handling 2.4GHz. Wireless personal area network transceiver circuits for frequency bands or other WPAN communication bands; cellular phone transceiver circuits that process cellular phone frequency bands (e.g., bands from approximately 600 MHz to approximately 5 GHz, 3G bands, 4G LTE bands, 5G New Radio Frequency Range 1 (FR1) band below 10 GHz, 5G New Radio Frequency Range 2 (FR2) band between 20 GHz and 60 GHz, 6G bands above 100 GHz, etc.); near field communication (NFC) transceiver circuits that process near field communication frequency bands (e.g., 13.56 MHz); satellite navigation receiver circuits that process satellite navigation frequency bands (e.g., GPS band from 1565 MHz to 1610 MHz, GLONASS band, BeiDou Navigation Satellite System (BDS) band, etc.); and circuits that use IEEE... Ultra-wideband (UWB) transceiver circuitry for handling communications using the 802.15.4 protocol and / or other ultra-wideband communication protocols; and / or any other desired radio frequency transceiver circuitry for covering any other desired communication frequency band of interest.

[0035] Wireless circuit 24 may include one or more antennas, such as antenna 42. Antenna 42 can be formed using any desired antenna structure. For example, antenna 42 may be an antenna with a resonant element, formed from a loop antenna structure, patch antenna structure, inverted F-shaped antenna structure, slot antenna structure, planar inverted F-shaped antenna structure, helical antenna structure, monopole antenna, dipole, a combination of these designs, etc. Two or more antennas 42 may be arranged in one or more phased antenna arrays (e.g., for transmitting radio frequency signals at millimeter-wave frequencies). Parasitic elements may be included in antenna 42 to modulate antenna performance. Antenna 42 may be provided with a conductive cavity that supports the antenna resonant element of antenna 42 (e.g., antenna 42 may be a cavity-backed antenna, such as a cavity-backed slot antenna).

[0036] The radio frequency amplifier can be coupled to a power detector for power level monitoring purposes. Figure 3 This is a diagram illustrating an exemplary power detector coupled to the output of an RF amplifier. (Example...) Figure 3 As shown, wireless circuit 24 may have one or more antennas 42 coupled to transmit path 72 and receive path 74 via a radio frequency duplex circuit such as duplexer 60. Duplexer 60 may have a first port coupled to a shared antenna 42, a second port coupled to transmit path 72 (e.g., a second port configured to receive amplified radio frequency signals radiated by antenna 42), and a third port coupled to receive path 74 (e.g., a third port to which radio frequency signals received by antenna 42 are transmitted).

[0037] Receive path 74 (sometimes referred to herein as receive chain 74) may include low-noise amplifier (LNA) circuitry 52, down-conversion mixer circuitry (such as mixer 68), and data converter (such as analog-to-digital converter (ADC) 66). LNA circuitry 52 may include one or more amplifiers coupled in series and / or parallel. Mixer 68 may use a local oscillator signal to down-convert (or demodulate) the radio frequency signal to a baseband frequency (or intermediate frequency). The analog-to-digital converter (ADC) circuitry 66 may then convert the demodulated signal from the analog domain to the digital domain to generate a corresponding digital baseband signal. Mixer 68 and ADC circuitry 66 are sometimes considered part of receiver circuitry 32. The digital baseband signal may then be received by one or more processors 26. Processor 26 may represent one or more processors, such as a baseband processor, application processor, digital signal processor, microcontroller, microprocessor, central processing unit (CPU), programmable device, combination of these circuits, and / or one or more processors within circuitry 18 (see [link to relevant documentation]). Figure 1 ).

[0038] The circuitry described above for processing signals received by antenna 42 is sometimes collectively referred to as a wireless receiving circuit. If necessary, one or more additional front-end module components (such as...) Figure 2 The RF filter circuit 44 (e.g., low-pass filter, high-pass filter, notch filter, band-pass filter, attenuator, multiplexer circuit, duplexer circuit, dual-signal circuit, triplexer circuit, etc.), switching circuit 46 (e.g., one or more RF switches), impedance matching circuit, antenna tuning circuit (e.g., a network of capacitors, resistors, inductors and / or switches to adjust the frequency response of antenna 42), RF coupler circuit, charge pump circuit, power management circuit and / or any other desired front-end module circuit may optionally be coupled along the RF receive line path at the input and / or output of LNA circuit 52.

[0039] On the other hand, the transmission path 74 (sometimes referred to herein as transmission chain 74) may include a power amplifier (PA) circuit 50, an up-conversion mixer circuit (such as mixer 64), and a data converter (such as digital-to-analog converter (DAC) 62). The processor 26 may generate a digital baseband signal, sometimes referred to as the digital signal for transmission. The DAC circuit 62 may convert the digital baseband signal from the digital domain to the analog domain to generate a corresponding analog baseband signal. The mixer 64 may use a local oscillator signal to up-convert (or modulate) the radio frequency signal to radio frequency (or intermediate frequency). The DAC circuit 62 and the mixer 64 are sometimes considered part of the transmitter circuit 30. The up-converted radio frequency signal may then be fed to the amplifier circuit 50. The PA circuit 52 may include one or more amplifiers coupled in series and / or parallel, configured to amplify the signal for transmission by the antenna 42.

[0040] The circuitry described above for preparing the signal to be transmitted by antenna 42 is sometimes collectively referred to as the wireless transmission circuitry. If necessary, one or more additional front-end module components (such as...) Figure 2 The RF filter circuit 44 (e.g., low-pass filter, high-pass filter, notch filter, band-pass filter, attenuator, multiplexer circuit, duplexer circuit, dual-signal circuit, triplexer circuit, etc.), switching circuit 46 (e.g., one or more RF switches), impedance matching circuit, antenna tuning circuit (e.g., a network of capacitors, resistors, inductors and / or switches for adjusting the frequency response of antenna 42), RF coupler circuit, charge pump circuit, power management circuit and / or any other desired front-end module circuit may optionally be coupled along the RF transmit line path to the input and / or output of amplifier circuit 50.

[0041] The power (transmit) amplifier 50 and the low-noise (receive) amplifier 52 can be collectively referred to as the radio frequency amplifier. A power detection circuit can be coupled to the output of the radio frequency amplifier to enable power monitoring operation. (See also...) Figure 3 A first power detection circuit, such as power detector 70-TX, may be coupled to the output of the transmit amplifier circuit 50, while a second power detection circuit, such as power detector 70-RX, may be coupled to the output of the receive amplifier circuit 52. Power detector 70-TX can be used to detect or measure the output power level of the radio frequency signal generated at the output of amplifier circuit 50. An automatic power control (APC) algorithm can then use the detected output power level to dynamically adjust the gain of power amplifier circuit 50 to ensure the transmit path outputs a signal at the desired power level. The APC algorithm, which may run on processor 26 or other control circuitry in device 10, can compare the measured output power level to a reference power level. If the output power level is too high, the APC algorithm can reduce the gain of amplifier 50. If the output power level is too low, the APC algorithm can increase the gain of amplifier 50.

[0042] A power detector 70-RX can be used to detect or measure the output power level of the RF signal generated at the output of the receiver amplifier circuit 52. An automatic gain control (AGC) algorithm can then use the detected output power level to dynamically adjust the gain of the LNA circuit 52 to ensure that the receiver path outputs a signal at the desired power level, regardless of the signal strength reaching the input of the circuit 52. An AGC algorithm that can run on the processor 26 or other control circuitry in device 10 can be used to ensure a constant output power level from the circuit 52. If the input signal is weak, the AGC algorithm can increase the gain of the amplifier 52 to maintain a constant output level. If the input signal is strong, the AGC algorithm can decrease the gain of the amplifier 52 to prevent the output level from becoming too high.

[0043] Figure 3 The example (where power detectors 70-TX and 70-RX are coupled at the output of the RF amplifier) ​​is illustrative. If desired, wireless circuitry 24 may include one or more additional power detectors 70 coupled to one or more points along transmit path 72 and / or receive path 74. For example, one or more power detectors 70 may be coupled to the output of DAC 62, the output of mixer 64 and / or any other point along transmit path 72, the output of mixer 68, the output of ADC 66 and / or any other point along path 74.

[0044] In the specific implementation described herein as an example, wireless circuit 24 may include a power detector 70 comprising a front-end rectifier that converts RF power into a low-frequency differential output voltage, a baseband comparator, and specific absorption rate (SAR) logic for detecting threshold crossovers. These types of comparator-based power detectors compare a differential reference voltage against different static thresholds. In mission mode, the rectifier output varies over a high dynamic range, which can make the comparator difficult to implement and prone to errors if not handled carefully. Furthermore, for RF signals with a constant input power level, the voltage output by the rectifier will also vary with process variations, temperature variations, and process angles. Additionally, the rectifier introduces an offset voltage to its output that drifts with temperature over time and, if not mitigated, can affect the accuracy of the power detector.

[0045] Figure 4 This is a schematic circuit diagram of an exemplary power detector 70 that mitigates these problems. Figure 4 The power detector 70 can form a power detector 70-TX ( Figure 3 ), power detector 70-RX ( Figure 3 ) or coupled to path 36 along the RF transmit line. Figure 2 Another power detector 70 at any desired location.

[0046] like Figure 4 As shown, the power detector 70 may include rectifier circuitry (such as rectifier 76), comparator circuitry (such as comparator 86), baseband circuitry (such as compensation circuitry 92), switching circuitry (such as multiplexer (MUX) 106 (e.g., 3-1 MUX)), and processing circuitry (such as SAR logic 112 (e.g., forming...). Figure 1 (Digital logic of a portion of the control circuit 14). Rectifier 76 may have inputs coupled to RF transmit line path 36. Rectifier 76 may have a first output terminal and a second output terminal, which are communicatively coupled to corresponding first and second input terminals of comparator 86 via differential signal path 78. Differential signal path 78 includes a first (positive) signal line 78P and a second (negative) signal line 78N.

[0047] Signal line 78P couples the first output terminal of rectifier 76 to the first input terminal 88 of comparator 86 (e.g., the positive input terminal of comparator 86). Signal line 78N couples the second output terminal of rectifier 76 to the second input terminal 90 of comparator 86 (e.g., the negative input terminal of comparator 86). Signal lines 78P and 78N form a differential pair of signal lines and transmit a differential signal. The differential signal can be characterized by a positive voltage V0P on signal line 78P and a corresponding negative voltage V0N on signal line 78N.

[0048] Compensation circuitry 92 and multiplexer 106 may be disposed on signal line 78N (e.g., multiplexer 106 may be coupled in series on signal line 78N between compensation circuitry 92 and comparator 86). Compensation circuitry 92 may include an input amplifier (such as amplifier 94), an offset calibration digital-to-analog converter (OSDAC), a reference (threshold) generation circuit (such as reference (threshold) generator (REFGEN) 100), an interstage amplifier (such as amplifier 98), and a set of N output amplifiers (such as amplifier 104). OSDAC 96 may be coupled in series on signal line 78N between amplifier 94 and amplifier 98. Amplifier 98 may be coupled in series on signal line 78N between OSDAC 96 and reference generator 100. Reference generator 100 may have a set of N outputs, each of which is coupled to multiplexer 106 via a corresponding signal line 102. A corresponding amplifier 104 may be provided on each of the signal lines 102 between the reference generator 100 and the multiplexer 106.

[0049] Multiplexer 106 may have N input terminals (ports) 108. Each input terminal 108 is coupled to a corresponding signal line 102. The signal lines 102 may be coupled in parallel between multiplexer 106 and reference generator 100. Multiplexer 106 also has an output terminal (port) 110 coupled to a second input terminal 90 of comparator 86. Multiplexer 106 may have control terminals (ports) coupled to SAR logic 112 via control path 116 (e.g., digital control path). Multiplexer 106 may couple one of the N input terminals 108 of the multiplexer to the output terminal 110 of the multiplexer based on a control signal ctrl1 (e.g., a digital control signal) received from SAR logic 112 via control path 116. The control signal ctrl1 can switch the multiplexer 106 between different switching states over time, thereby controlling which of its N input terminals 108 is coupled to the comparator 86 via the output terminal 110 over time.

[0050] N can be any integer greater than or equal to one. N can correspond to the number of different threshold voltages VTH that can be generated by reference generator 100 and provided to input terminal 90 of comparator 86 via multiplexer 106. Figure 4In the example, there are N=3 outputs of the reference generator 100 coupled to N=3 signal lines 102 (e.g., first signal line 102-1, second signal line 102-2, and third signal line 102-3), N amplifiers 104 disposed on the signal lines 102 (e.g., first amplifier 104-1 disposed on signal line 102-1, second amplifier 104-2 disposed on signal line 102-2, and third amplifier 104-3 disposed on signal line 102-3), and the multiplexer 106 has N=3 input terminals 108 (e.g., first input terminal 108-1 coupled to signal line 102-1, second input terminal 108-2 coupled to signal line 102-2, and third input terminal 108-3 coupled to signal line 102-3).

[0051] Reference generator 100 can generate, output, and / or produce a corresponding threshold voltage VTH on each of the signal lines 102 (e.g., a first threshold voltage VTH1 on signal line 102-1, a second threshold voltage VTH2 on signal line 102-2, and a third signal path VTH3 on signal line 102-3). Multiplexer 106 can (e.g., based on control signal ctrl1, which controls multiplexer 106 to couple a selected one of the multiplexer's input terminals 108 and therefore a selected one of the signal lines 102 to the multiplexer's output terminal 110 and therefore the comparator 86's input terminal 90) provide a selected one of the threshold voltages VTH to the comparator 86's input terminal 90 at a given time. This example is illustrative and not limiting. In general, N can be equal to two, N can be equal to one, N can be equal to four, or N can be equal to more than four (e.g., compensation circuit 92 can provide any desired number N of different threshold voltages VTH to the comparator 86's input terminal 90).

[0052] The power detector 70 may also include a filter, such as a low-pass filter (LPF) 80, disposed on the signal line 78P. As an example, the LPF 80 may include a resistor 82 coupled in series along the signal line 78P and a shunt capacitor 84 coupled between the signal line 78P and ground. The LPF 80 can help reduce high-frequency common-mode (CM) from the signal supplied to the comparator 86.

[0053] As the radio frequency signal rfsig propagates along the radio frequency transmission line path 36, at least some of the radio frequency signal can be (e.g., via a signal splitter, signal coupler, transformer, etc.) tapped from the radio frequency transmission line path 36 and provided to the input of the rectifier 76. The rectifier 76 receives signals at power level P. in The radio frequency signal rfsig is located at [location]. The power detector 70 can measure or estimate the power level P of the radio frequency signal rfsig.in The SAR logic 112 can generate digital outputs, such as characterizing or identifying the measured power level P of the radio frequency signal rfsig. in The power code pcode (e.g., a three-bit power code).

[0054] Rectifier 76 may include square-law devices and / or other rectifier circuitry that rectify the radio frequency signal rfsig received at the input of the rectifier, converting the radio frequency rfsig into a lower-frequency differential output voltage represented by voltage VOP on signal line 78P and voltage VON on signal line 78N. Signal line 78P transmits voltage VOP (e.g., via LPF 80) to input terminal 88 of comparator 86. LPF 80 removes CM noise from voltage VOP to help prevent erroneous detection by comparator 86. Comparator 86 may receive signals at corresponding voltage levels VOP. ip The voltage V0P is located at the point of application. The compensation circuit 92 can receive the voltage V0N. The amplifier 94 can amplify the voltage V0N (e.g., amplify it to a level suitable for subsequent processing by the OSDAC circuit 96).

[0055] In fact, rectifier 76 introduces a non-zero offset voltage into the voltage V0P / V0N. Even when the power level P of the RF signal rfsig... in When equal to zero, the non-zero offset voltage also gives the voltage V0P / V0N a non-zero amplitude. The amplitude of the offset voltage varies with time depending on the temperature of the wireless circuit 24 and between devices 10 due to device-to-device process variations. If the offset voltage is not properly compensated, the power detector 70 will measure the power level P. in It may exhibit insufficient accuracy at times.

[0056] In some implementations, the compensation circuit 92 includes a fixed circuit that always superimposes the same constant (static) DC voltage onto the voltage V0N on the signal line 78N to help mitigate the offset voltage introduced by the rectifier 76. However, this type of circuit will superimpose the same DC voltage onto the voltage V0N even after the actual offset of the rectifier 76 has changed due to temperature variations in the device 10. This may prevent the compensation circuit 92 from fully compensating for the actual offset voltage, thus limiting the accuracy of the power detector 70 in measuring the RF signal rfsig.

[0057] To mitigate these issues, OSDAC 96 can superimpose a dynamic offset voltage VOS onto voltage VON, thereby shifting the amplitude of voltage VON up or down (e.g., shifting the offset voltage VOS) in a manner that fully compensates for the actual offset introduced by rectifier 76. Compensation circuit 92 can receive an offset calibration signal VOSCAL (e.g., a digital offset calibration signal) via control terminal 93 (e.g., the digital control port of compensation circuit 92). The offset calibration signal VOSCAL controls OSDAC 96 to dynamically switch, scan, sweep over, or search for different offset voltages VOS applied to voltage VON until the actual offset introduced by rectifier 76 has been completely canceled out by the offset voltage VOS.

[0058] If needed, the offset calibration signal VOSCAL can also control the compensation circuit 92 to perform an offset (OSDAC) calibration operation, which maps different settings or codes of the OSDAC 96 to different amplitudes of the offset voltage VOS to help ensure that the correct offset voltage VOS is superimposed on the voltage VON when measuring the RF signal rfsig. In this way, the OSDAC 96 can generate an offset compensation voltage (sometimes referred to herein as VON+VOS) and can provide the offset compensation voltage to the reference generator 100. The amplifier 98 can amplify the offset compensation voltage output by the OSDAC circuit 96 (e.g., amplify it to a level suitable for subsequent processing by the reference generator 100). The offset compensation voltage is also sometimes referred to herein as an offset mitigation voltage (e.g., with amplitude VON+VOS).

[0059] Reference generator 100 can use the offset compensation voltage received from OSDAC 96 to generate N threshold voltages VTH output to signal line 102. Each threshold voltage VTH may include a different corresponding threshold voltage VREF superimposed by reference generator 100 to the offset compensation voltage received from OSDAC 96 (e.g., threshold voltage VTH1 may be equal to the offset mitigation voltage plus a first threshold voltage VREF1, threshold voltage VTH2 may be equal to the offset mitigation voltage plus a second threshold voltage VREF2, and threshold voltage VTH3 may be equal to the offset mitigation voltage plus a third threshold voltage VREF3). If desired, reference generator 100 may generate the reference voltage VREF based on the current temperature of wireless circuit 24 in a manner that helps mitigate the effects of temperature variations on the operation of power detector 70 (e.g., for inclusion in the threshold voltage VTH). Compensation circuit 92 can receive a reference (threshold) calibration signal VREFCAL (e.g., a digital reference calibration signal) via control terminal 96 (e.g., the digital control port of compensation circuit 92). The reference calibration signal VREFCAL can control the reference generator 100 to dynamically switch, scan, sweep over, or search for different threshold voltages VREF included in each threshold voltage VTH output by the reference generator 100.

[0060] If needed, the reference calibration signal VREFCAL can also control the compensation circuit 92 to perform a threshold calibration operation, which maps different settings or codes of the reference generator 100 to different amplitudes of the reference voltage VREF included in the threshold voltage VTH. This can, for example, help ensure that the correct reference voltage is superimposed on the offset compensation voltage given the current temperature of the wireless circuit 24. In this way, the reference generator 100 can generate offset and temperature-compensated threshold voltages VTH, and these threshold voltages can be provided to the corresponding inputs 108 of the multiplexer 106 via signal line 102. The amplifier 104 can amplify the threshold voltage VTH output by the reference generator 100 (e.g., amplify it to a level suitable for comparison by the comparator 86 with the voltage VOP to mitigate headroom issues, etc.).

[0061] SAR logic 112 can use the control signal crtrl1 to control multiplexer 106 to rapidly switch (switch back and forth) between providing different threshold voltages VTH from different input terminals 108 to input terminals 110 of the multiplexer and thus input terminals 90 of comparator 86, while comparator 86 concurrently receives voltage VOP at input terminal 88. The amplitude of the threshold voltage VTH received at input terminal 90 is determined by the voltage level V. in Characterization. Comparator 86 can represent the voltage level (V) at input terminal 88. ip ) and the voltage level at input terminal 90 (V inThe comparison is performed to generate a corresponding comparator signal csig on comparator output path 114. Comparator 86 can provide the comparator signal csig to SAR logic 112 through comparator output path 114. When the voltage level V ip The amplitude exceeds the voltage level V in When the amplitude is such that the comparator signal csig can have a first logic value, and when the voltage level V... in The amplitude exceeds the voltage level V ip When the amplitude is such that the comparator signal can have a second logic value.

[0062] If needed, SAR logic 112 can adjust the state of multiplexer 106 based on the comparator signal csig (e.g., providing a specific threshold VTH to input terminal 90 of comparator 86). For example, SAR logic 112 can control multiplexer 106 to provide an appropriate threshold VTH to comparator 86 so that comparator 86 corresponds to the power level P of the RF signal rfsig. in The voltage V0P is compared (e.g., such that when the power level P...). in A higher threshold VTH is used when the power level is relatively high, and when the power level P in (A lower threshold VTH is used when the value is relatively low). SAR logic 112 can also output a power code pcode based on the comparator signal csig and the corresponding threshold VTH used to generate the comparator signal csig. These thresholds are known to SAR logic 112 because SAR logic 112 uses the control signal ctrl1 to control which thresholds VTH are applied to comparator 86 by multiplexer 106 over time.

[0063] Power code (pcode) may include or identify power level (P). in Or includes power level P in The power range. In one example, the power code pcode can be a three-bit power code. In this example, SAR logic 112 can be used when the power level P is measured via comparator 86. in When the power level P is measured via comparator 86 within a first power range (e.g., less than -22 dBm), the output power code pcode is used as a first digital value (such as "000"), and the power level P is measured via comparator 86. in In the second power range (e.g., less than or greater than -22dBm and less than -16dBm), the output power code pcode is used as a second digital value (such as "001") (e.g., where "1" is the least significant bit (LSB) of the power code and the first "0" is the most significant bit (MSB) of the power code), when the power level P is measured via comparator 86. inIn the third power range (e.g., less than or greater than -16 dBm and less than -10 dBm), the power code pcode is output as a third digital value (such as "011"), and when the power level P is measured via comparator 86 in In the fourth power range (e.g., less than or greater than -10 dBm), the output power code pcode is used as a fourth digital value (such as "111"). This example is illustrative and not limiting. SAR logic 112 can output a power level P that is used to identify the power level at any desired level of accuracy. in The power code pcode can be any desired number of bits. SAR logic 112 can output the power code pcode to other processing circuitry in device 10 (e.g., ...). Figure 1 The control circuit 14). The processing circuit can be based on the power code Pcode and the measured power level P of the radio frequency signal RFSIG. in To perform any desired action. Power codes (pcodes) are sometimes referred to as hot codes (pcodes) in this article.

[0064] In this way, the power detector 70 can use the comparator signal csig to perform offset cancellation across temperature and threshold fine-tuning to remove the effect of comparator offset on power detection accuracy. Supplying the offset compensation threshold voltage (such as the threshold voltage VTH) directly to the input terminal 90 of the comparator 86 allows the comparator 86 to be implemented as a dual-input comparator with a limited input range without sacrificing measurement accuracy.

[0065] Figure 5 This is an example circuit diagram illustrating how the OSDAC 96 and reference generator 100 can be implemented in compensation circuit 92. Figure 5 In the example, OSDAC 96 is implemented as a first resistive DAC (RDAC), and reference generator 100 is implemented as a second RDAC. This is exemplary, and other circuit architectures can be used to implement OSDAC 96 and / or reference generator 100 if desired.

[0066] like Figure 5 As shown, the OSDAC 96 may include a resistor line 122 coupled between a supply voltage Vdd and a reference voltage (such as ground 120). The OSDAC 96 may include a set of resistors 124 coupled in series along the resistor line 122. The input of the OSDAC 96 may be formed by a node 131 on the resistor line 122, which receives a voltage V0N on the signal line 78N. The output of the OSDAC 96 may be coupled to the input of the amplifier 98 via the signal line 130.

[0067] The OSDAC 96 may include (e.g., in parallel) a set of switches 126 coupled between different nodes on resistor line 122 and signal line 130. In its simplest form, each switch 126 may be implemented using a corresponding transistor having a first source-drain terminal coupled to resistor line 122, a second source-drain terminal coupled to signal line 130, and a gate terminal coupled to control line 128. The terms "source" and "drain" are sometimes used interchangeably when referring to the current-conducting terminals of a metal-oxide-semiconductor transistor. Therefore, the source and drain terminals are sometimes referred to as "source-drain" terminals (e.g., a transistor having a gate terminal, a first source-drain terminal, and a second source-drain terminal). Each resistor 124 may have a corresponding first and second switch 126 coupled to resistor line 122 on either side of the resistor 124.

[0068] The OSDAC 96 can receive a control signal ctrl2 (e.g., a digital control signal) via control line 128 (e.g., a digital control path). The control signal ctrl2 can turn different groups, sets, or combinations of switches 126 on or off. When a switch is on, active, closed, or enabled, current flows between the source and drain terminals of the switch (e.g., from resistor line 122 to signal line 130). A specific group of switches 126 that is turned on can couple a corresponding number of resistors 124 between the supply voltage Vdd and signal line 130, causing the OSDAC 96 to superimpose a corresponding offset voltage VOS onto the input voltage VON (e.g., different numbers of active switches 126 cause different numbers of resistors 124 to be active in the OSDAC, thereby causing different magnitudes of offset voltage VOS to be superimposed onto the input voltage VON).

[0069] The control signal ctrl2 can set the offset voltage VOS to be equal to (or as close as possible to) the offset actually applied to the voltage VON by the rectifier 76 under the current operating conditions of the given power detector 70, but opposite to that offset (e.g., the offset voltage VOS may have the same magnitude but opposite sign relative to the offset voltage generated by the rectifier 76). The control signal ctrl2 may include an offset calibration signal VOSCAL. Figure 4 The control signal ctrl2 in the control circuit or interface circuit can be generated based on the offset calibration signal VOSCAL, and / or a specific value (digital code) carried by the control signal ctrl2 can be calibrated using the offset calibration signal VOSCAL. The value of the offset voltage VOS is dynamic and can be updated over time as the operating conditions of device 10 change (e.g., using the control signal ctrl2).

[0070] After superimposing the correct offset voltage VOS onto the voltage V0N, the OSDAC 96 outputs the superimposed signal to signal line 130 as an offset compensation voltage with an amplitude equal to V0N + VOS. Amplifier 98 can amplify the offset compensation voltage if needed. Reference generator 100 receives the offset compensation voltage from amplifier 98 via signal line 130.

[0071] Reference generator 100 may include a resistor line 142 coupled between a supply voltage Vdd and a reference voltage (such as ground 120). Reference generator 100 may include a set of resistors 168 coupled in series along resistor line 142. The input to reference generator 100 may be formed by a node 134 on resistor line 142, which is coupled to signal line 130 and receives offset compensation voltage via signal line 130. Reference generator 100 may include a first adjustable current source 138 coupled in series between resistor 168 and supply voltage Vdd on resistor line 142. Reference generator 100 may include a second adjustable current source 140 coupled in series between resistor 168 and ground 120 on resistor line 142.

[0072] Reference generator 100 may include a set of switches 166 coupled between nodes on resistor line 142 and signal line 135 (e.g., switches 166 may be coupled in parallel between signal path 135 and resistor line 142). Each resistor 168 may have a corresponding first switch and second switch 166 coupled to resistor line 142 on either side of the resistor 168. Signal line 102-1 may be coupled to a first node 137 on signal path 135 (e.g., forming a first output of reference generator 100). Signal line 102-2 may be coupled to a second node 148 on signal path 135 (e.g., forming a second output of reference generator 100).

[0073] Reference generator 100 may include an additional set of switches 170 connected in parallel between nodes on resistor line 142 (e.g., fewer nodes than those coupled to switch 166) and signal line 102-3. Switches 170 do not couple resistor line 142 to signal path 135, signal line 102-2, or signal line 102-1. Switches 170 may, for example, be coupled to nodes on resistor line 142 between signal line 102-2 and adjustable current source 138 (e.g., switches 170 may switchably couple a subset of resistors 168 on resistor line 142 (such as half of resistors 168 on resistor line 142) to signal line 102-3).

[0074] Reference generator 100 can receive control signal ctrl4 (e.g., a digital control signal) via control line 156 (e.g., a digital control path). Control signal ctrl4 can turn different groups, sets, or combinations of switches 166 and / or 170 on or off. A specific number of switches 166 turned on between node 148 and adjustable current source 138 controls the number of resistors 168 used or coupled between adjustable current source 138 and signal line 102-2. This causes reference generator 100 to superimpose a corresponding reference voltage VREF2 onto the offset mitigation signal received from OSDAC 96 (e.g., where the amplitude of reference voltage VREF2 can be changed by adjusting the number of switches 166 turned on and thus the number of resistors 168 used and coupled between adjustable current source 138 and signal line 102-2). Amplifier 104-2 can amplify this superimposed signal to generate a threshold voltage VTH2 on signal line 102-2 (e.g., where VTH2 = V0N + VOS + VREF2).

[0075] Simultaneously, a specific number of switches 166 connected between node 137 and the adjustable current source 138 control the number of resistors 168 used or coupled between the adjustable current source 138 and signal line 102-1. This causes the reference generator 100 to superimpose a corresponding reference voltage VREF1 onto the offset mitigation signal received from the OSDAC 96 (e.g., where the amplitude of the reference voltage VREF1 can be changed by adjusting the number of switches 166 connected and thus the number of resistors 168 used and coupled between the adjustable current source 138 and signal line 102-1). Amplifier 104-1 can amplify this superimposed signal to generate a threshold voltage VTH1 on signal line 102-1 (e.g., where VTH1 = V0N + VOS + VREF1).

[0076] Simultaneously, a specific number of switches 170 are turned on to control the number of resistors 168 used or coupled between the adjustable current source 138 and signal line 102-3. This causes the reference generator 100 to superimpose the corresponding reference voltage VREF3 onto the offset mitigation signal received from the OSDAC 96 (e.g., where the amplitude of the reference voltage VREF3 can be changed by adjusting the number of switches 170 turned on and thus the number of resistors 168 used and coupled between the adjustable current source 138 and signal line 102-3). Amplifier 104-4 can amplify this superimposed signal to generate a threshold voltage VTH3 on signal line 102-3 (e.g., where VTH3 = V0N + VOS + VREF3). The reference voltage VREF3 has a larger amplitude than the reference voltage VREF2. The reference voltage VREF2 has a larger amplitude than the reference voltage VREF1. If needed, the reference generator 100 can be generalized to generate N different reference voltages of varying amplitudes for comparator 86 to detect the crossover point of voltage VOP.

[0077] Amplifier 104-4 may include one or more amplifier stages. If desired, amplifier 104-3 may include a first amplifier 154 and a second amplifier 152, the second amplifier having an output coupled to the input of amplifier 154. Amplifier 152 may be, for example, an operational amplifier having a first input coupled to switch 170 and a second input coupled to the output of that amplifier via resistor 158. An additional resistor (such as resistor 160) may couple resistor 158 and the second input of amplifier 152 to signal line 162. Resistor 158 may, for example, have a higher resistance than resistor 160. Signal line 162 may be coupled to signal line 130. Signal line 162 may transmit an offset compensation voltage (V0N+VOS) to amplifier 152 via resistor 160. Amplifier 152, resistor 158, and resistor 160 may collectively form attenuation circuit 164. The attenuation circuit 164 can, for example, attenuate the signal received from the switch 170 to provide additional headroom for the amplifier 154 (e.g., to prevent the signal from saturating the amplifier 154 when the reference voltage VREF3 has the highest amplitude of the reference voltage generated by the reference generator 100, which can help maintain power detection accuracy).

[0078] The compensation circuit 92 may also include a temperature sensor circuit, such as a temperature sensor 136. The temperature sensor 136 can generate an indication of the compensation circuit 92, the power detector 70, and the wireless circuit 24. Figure 1Temperature sensor data of the temperature at one or more locations in device 10. If needed, some or all components of power detector 70 may be integrated into a shared substrate (such as a single integrated circuit chip). Temperature sensor 136 may, for example, measure the temperature at one or more locations on the integrated circuit chip.

[0079] Temperature sensor 136 can be coupled to the control inputs of adjustable current sources 138 and 140 via control path 132. Temperature sensor 136 can provide control signal ctrl3 to adjustable current sources 138 and 140 via control path 132. Control signal ctrl3 can control, set, and / or adjust (e.g., dynamically change) the amount of current generated by adjustable current sources 138 and 140 via resistor line 142 based on temperature sensor data generated by temperature sensor 136 (e.g., based on the temperature of power detector 70). This can help fine-tune or adjust the reference voltages VREF1, VREF2, and VREF3 included in threshold voltages VTH1, VTH2, and VTH3 to compensate for any drift or offset associated with temperature changes in the power detector.

[0080] The control signal ctrl4 may include the reference calibration signal VREFCAL. Figure 4 The control signal ctrl4 in the power detector 70 can be generated by the control circuitry or interface circuitry based on the reference calibration signal VREFCAL, and / or a specific value (digital code) carried by the control signal ctrl4 can be calibrated using the reference calibration signal VREFCAL. The value of each reference voltage VREF and therefore each threshold voltage VTH is dynamic and can be updated over time as the operating conditions of device 10 change (e.g., using the control signal ctrl4). If needed, the reference calibration signal VREFCAL can also be used to calibrate the control signal ctrl3 (e.g., to map a specific digital code in the control signal ctrl3 to a specific current level generated by the adjustable current sources 138 and 140, which will mitigate the effects of temperature variations in the power detector 70).

[0081] Figure 6This is a flowchart illustrating exemplary operations involved when using power detector 70 to measure radio frequency signals. At operation 180, power detector 70 may perform calibration of OSDAC 96 (e.g., mapping control codes and OSDAC settings / switch configurations to a specific offset voltage VOS to mitigate the offset voltage generated by rectifier 76, even as the offset voltage generated by rectifier 76 changes over time). Alternatively or additionally, power detector 70 may perform calibration of reference generator 100 (e.g., mapping control codes, REFGEN settings / switch configurations, and / or current source settings to a specific reference voltage VREF to be included in the threshold voltage VTH, even as the thermal conditions of power detector 70 change over time). Power detector 70 may perform these calibrations at an initial time (e.g., during device assembly, manufacturing, testing, etc.) and / or in the field. If desired, power detector 70 may perform these calibrations periodically over time and / or temperature. If desired, power detector 70 may... Figure 6 These calibrations continue to be performed during or between one or more iterations of the remaining operations.

[0082] The calibration of OSDAC 96 can generate optimal (calibration) settings for OSDAC 96 (e.g., codes for controlling switch 126 as needed to generate a suitable offset voltage VOS to mitigate the offset imposed by rectifier 76 under thermal conditions and / or process variations of a given power detector 70). The calibration of reference generator 100 can generate optimal (calibration) settings for reference generator 100 and adjustable current sources 138 and 140 (e.g., codes for controlling switch 166, switch 170 and / or adjustable current sources 138 and 140 as needed to mitigate thermal effects under thermal conditions and / or process variations of a given power detector 70).

[0083] At operation 182, RF transmission line path 36 can begin transmitting the RF signal rfsig. Power detector 70 can begin measuring the power level P of the RF signal rfsig. in .

[0084] At operation 184, rectifier 76 converts the RF signal rfsig into differential voltages V0P / V0N on signal lines 78P and 78N, respectively. Signal line 78P transmits voltage V0P to input terminal 88 of comparator 86. LPF 80 removes CM noise from voltage V0P. Signal line 78N transmits voltage V0N to compensation circuit 92. Rectifier 76 applies a non-zero offset voltage to the differential voltages. The magnitude of the non-zero offset may vary depending on the temperature and / or process variations of power detector 70.

[0085] At operation 186, the OPSDAC 96 can use its optimal (calibrated) settings to superimpose the corresponding offset voltage VOS onto the voltage V0N, which reverses or cancels the non-zero offset applied by the rectifier 76, thereby producing an offset compensation voltage (V0N+VOS).

[0086] At operation 188, reference generator 100 can use its optimal (calibrated) settings to convert the offset compensation voltage (V0N+VOS) into a suitable threshold voltage VTH, while mitigating thermal / temperature effects (e.g., by superimposing a suitable reference voltage VREF1 onto the offset compensation voltage to generate threshold voltage VTH1, by superimposing a suitable reference voltage VREF2 onto the offset compensation voltage to generate threshold voltage VTH2, and by superimposing a suitable reference voltage VREF3 onto the offset compensation voltage to generate threshold voltage VTH3). Reference generator 100 can provide each generated threshold voltage VTH to multiplexer 106 via corresponding signal lines 102. Figure 4 The different corresponding input terminals 108.

[0087] At operation 190, SAR logic 112 can control multiplexer 106 to pass one or more of the threshold voltages VTH received from reference generator 100 to input 90 of comparator 86 based on the comparator signal csig output by comparator 86. If needed, SAR logic 112 can control multiplexer 106 to rapidly switch or switch back and forth between providing different threshold voltages VTH to comparator 86 over time.

[0088] At operation 192, comparator 86 can compare the voltage VOP received at its input terminal 88 with the threshold voltage VTH received from multiplexer 106 to generate / update the comparator signal csig. For example, this can indicate the power level P when / when the voltage VOP exceeds the threshold VTH3. in Relatively high. For example, when the voltage V0P does not exceed the threshold VTH1, this can indicate the power level P. in Relatively low. Whether the voltage V0P exceeds different thresholds VTH can indicate the true power level P containing the radio frequency signal rfsig. in The power level range.

[0089] At operation 194, SAR logic 112 can generate a power code pcode based on the comparator signal csig and the corresponding threshold VTH used to generate the comparator signal csig. The power code pcode can, for example, identify or estimate (e.g., detected using power detector 70) the power level P of the radio frequency signal rfsig. inSAR logic 112 can pass the power code pcode to other circuits in device 10 for further processing. SAR logic 112 can also adjust or update the switching of multiplexer 106 based on the comparator signal csig. Because CM noise (e.g., via LPF 80) is removed from voltage VOP, the specific offset voltage applied by rectifier 76 (e.g., given the current temperature of power detector 70) is removed by OSDAC 96, and thermal effects are also considered in the generation of reference voltage VREF and therefore threshold voltage VTH, the power code pcode accurately represents the true power level P of the RF signal rfsig. in Regardless of the temperature of the power detector 70 or any process variations.

[0090] At operation 196, device 10 can base its operation on the power code pcode output by SAR logic 112 (e.g., based on the power level P of the radio frequency signal rfsig measured using power detector 70). in To perform one or more actions. For example, device 10 can adjust one or more power amplifiers (e.g., Figure 3 The gain of the power amplifier circuit 50 can be adjusted to adjust one or more low-noise amplifiers (e.g., Figure 3 The gain of the low-noise amplifier circuit 52) ​​can detect and mitigate interference or blocking signals present at one or more frequencies in the received radio frequency signal, adjust the power level of the transmitted signal to meet SAR requirements or specifications imposed on device 10, adjust the amplifier to maximize the linearity and / or efficiency of the amplifier, adjust antenna tuning, adjust antenna beamforming, switch different antennas into or out of use, and / or perform any other desired actions based on the power code pcode. While the power detector 70 continues to measure the radio frequency signal rfsig, the processing can loop back to operation 184 via path 198.

[0091] Figure 7 This is an example (for example, in processing) Figure 6 The timing diagram for an example of the offset calibration of OSDAC 96 (operation 180) is shown. Curve 200 illustrates the comparator signal csig output by comparator 86. Curve 202 illustrates the amplitude of the reference voltage VREF1. Curve 206 plots the voltage V received at input terminal 88 of comparator 86. ip Curve 206 plots the voltage V received at input terminal 90 of comparator 86. in Curve 208 plots the offset calibration signal VOSCAL provided to the compensation circuit 92.

[0092] During offset calibration, compensation circuit 92 and multiplexer 106 can be configured (e.g., using a first digital control code) to generate a single constant reference voltage VREF1, which is provided as part of a threshold voltage VTH1 to input terminal 90 of comparator 86. A binary search process can be used to find a specific code for use by the offset calibration signal VOSCAL based on the output state of comparator 86. For example, the offset calibration signal VOSCAL can switch codes exactly 100ns before the shift, thereby changing the amplitude of the offset voltage VOS superimposed on voltage VON by OSDAC 96. This causes the amplitude of the threshold voltage VTH1 output by reference generator 100 (which is equal to VON + VOS + VREF1) and therefore the voltage V received at input terminal 90 to change. in The change is shown as a drop in curve 204, denoted as 207. The binary search continues to sweep across the code of the offset calibration signal VOSCAL until the voltage V... in And thus the comparator signal csig (curve 200) stabilizes at a specific amplitude. Once this occurs, the code of the offset calibration signal VOSCAL also stabilizes to the calibration code used for the offset calibration signal VOSCAL (e.g., as shown during time period 208), thereby corresponding to the specific offset voltage VOS used by the OSDAC 96 under the current operating conditions of the power detector 70.

[0093] Figure 8 This is an example (for example, in processing) Figure 6 The timing diagram shows an example of the calibration of the reference voltage of the reference generator 100 (operation 180). Curve 218 illustrates the comparator signal csig output by comparator 86. Curve 214 illustrates the amplitude of the reference voltage VREF1. Curve 212 plots the voltage V received at input terminal 88 of comparator 86. ip Curve 210 plots the voltage V received at input terminal 90 of comparator 86. in Curve 220 plots the reference calibration signal VREFCAL provided to the compensation circuit 92.

[0094] During this calibration (sometimes referred to as threshold fine-tuning), the input terminal 90 of comparator 86 rapidly switches between two adjacent references. A binary search process is then performed to identify the code of the reference calibration signal VREFCAL for the current device operating conditions based on the output of SAR logic 112. Approximately three times the clock cycle of the power detector can be used to stabilize the SAR logic. Once this occurs, the code of the reference calibration signal VREFCAL is also stabilized to the calibration code used for the reference calibration signal VREFCAL (e.g., as shown during time period 208), thus corresponding to the specific reference voltage VREF used by the reference generator 100 under the given current operating conditions of the power detector 70.

[0095] Figure 9 This illustrates how a power detector 70 can measure the power P of a radio frequency signal rfsig. in Here is an example timing diagram. Curve 224 plots the amplitude of the RF signal rfsig received by power detector 70 (e.g., when transmitting an OFDM waveform). Curve 226 plots the threshold voltage VTH3. Curve 228 plots the threshold voltage VTH2. Curve 230 plots the threshold voltage VTH1. Curve 234 plots the voltage V received at input terminal 90 of comparator 86. in Curve 236 plots the voltage V received at input terminal 88 of comparator 86. ip Curve 238 plots the comparator signal csig output by comparator 86. Curve 240 plots the specific code of the power code pcode output by SAR logic 112. Curve 242 illustrates the clock signal used for clocking the power detector 70.

[0096] As shown in curve 224, the power P of the radio frequency signal rfsig in This can vary over time. As shown in curve 234, multiplexer 106 can switch or switch back and forth between providing different threshold voltages VTH to input terminal 90 of comparator 96 to match voltage V. ip Comparison. As shown by peak 244 in curve 238, the power level P... in Peak 242 in curve 238 causes comparator 86 to output the corresponding pulse 244 in the comparator signal csig. As shown in curve 240, SAR logic 112 can respond to the appearance of peak 244 in curve 238 by outputting the corresponding power code pcode (e.g., the power level P that includes the power level of peak 242 in curve 224). in (The specific power code corresponding to the range). This example is illustrative and not restrictive.

[0097] The above text combined Figures 1 to 9The described methods and operations can be performed by components of device 10 using software, firmware, and / or hardware (e.g., dedicated circuitry or hardware). Software code for performing these operations can be stored on a non-transitory computer-readable storage medium (e.g., a tangible computer-readable storage medium) stored on one or more components of device 10 (e.g., ...). Figure 1 The storage circuit 16 and / or wireless communication circuit 24). This software code may sometimes be referred to as software, data, instructions, program instructions, or code. Non-transitory computer-readable storage media may include drives, non-volatile memory such as non-volatile random access memory (NVRAM), removable flash drives or other removable media, other types of random access memory, etc. The software stored on the non-transitory computer-readable storage medium may be processed by processing circuitry on one or more components of device 10 (e.g., processing circuitry in wireless communication circuitry 24, ...). Figure 1 The processing circuitry (e.g., 18) executes the operation. This processing circuitry may include a microprocessor, application processor, digital signal processor, central processing unit (CPU), application-specific integrated circuit (ASIC) with processing circuitry, or other processing circuitry.

[0098] For one or more aspects, at least one of the components shown in one or more of the foregoing figures may be configured to perform one or more operations, techniques, processes or methods set forth in the following embodiments section.

[0099] Example

[0100] Further exemplary aspects are provided in the following sections.

[0101] Example 1 includes a wireless circuit comprising: a radio frequency (RF) transmission line configured to transmit an RF signal; a power detector operatively coupled to the RF transmission line and configured to measure the power of the RF signal, the power detector including a rectifier configured to convert the RF signal into a differential voltage, the differential voltage including a first voltage on a first signal line and a second voltage on a second signal line; a comparator having a first input coupled to the rectifier via the first signal line and a second input coupled to the rectifier via the second signal line; and a digital-to-analog converter (DAC) disposed on the second signal line, the DAC being configured to superimpose a dynamic offset voltage onto the second voltage, which changes over time.

[0102] Example 2 includes the wireless circuitry according to Example 1, wherein the DAC may optionally include a resistive DAC (RDAC).

[0103] Example 3 includes the wireless circuit according to Example 2, wherein the RDAC optionally includes: a resistor line coupled between a power supply voltage and a ground voltage; and a set of switches coupled in parallel between a node on the resistor line and a third signal line.

[0104] Example 4 includes the wireless circuit according to Example 3, the wireless circuit optionally including one or more processors, the one or more processors being configured to: provide the dynamic offset voltage having a first amplitude at a first time by turning on the first set of switches; and provide the dynamic offset voltage having a second amplitude at a second time by turning on the second set of switches, the second amplitude being different from the first amplitude.

[0105] Example 5 includes the wireless circuit according to Example 3, the wireless circuit optionally further including: an additional RDAC, the additional RDAC being operatively coupled between the third signal line and the second input of the comparator.

[0106] Example 6 includes the wireless circuitry according to Example 5, the wireless circuitry optionally further including a multiplexer operatively coupled between the additional RDAC and the second input of the comparator.

[0107] Example 7 includes the wireless circuit according to Example 9, wherein the multiplexer optionally has a first input terminal coupled to the additional RDAC via a fourth signal line, a second input terminal coupled to the additional RDAC via a fifth signal line, and a third input terminal coupled to the additional RDAC via a sixth signal line.

[0108] Example 8 includes the wireless circuit according to Example 7, wherein the additional RDAC is optionally configured to: generate a first threshold voltage on the fourth signal line by superimposing a first reference voltage onto the second voltage and the dynamic offset voltage; generate a second threshold voltage on the fifth signal line by superimposing a second reference voltage onto the second voltage and the dynamic offset voltage; and generate a third threshold voltage on the sixth signal line by superimposing a third reference voltage onto the second voltage and the dynamic offset voltage.

[0109] Example 9 includes the wireless circuit according to Example 8, the wireless circuit optionally further including digital logic operatively coupled to the comparator and the multiplexer, wherein the comparator is optionally configured to generate a comparator signal based on the first voltage and a first threshold voltage, a second threshold voltage and a third threshold voltage, and the digital logic is configured to adjust the multiplexer based on the comparator signal.

[0110] Example 10 includes the wireless circuit according to Example 9, the wireless circuit optionally further including: an amplifier located on a radio frequency transmit line path; and one or more processors, wherein the digital logic is optionally configured to output a digital code based on the comparator signal, the digital code representing the power of the radio frequency signal, and the one or more processors are configured to adjust the gain of the amplifier based on the digital code.

[0111] Example 11 includes the wireless circuit according to Example 8, the wireless circuit optionally further including: a temperature sensor configured to measure the temperature of the rectifier, and the additional RDAC configured to adjust the first reference voltage, the second reference voltage and the third reference voltage based on the temperature of the rectifier.

[0112] Example 12 includes the wireless circuit according to Example 1, the wireless circuit optionally further including: a low-pass filter disposed on the first signal line and configured to reduce common-mode noise of the first voltage.

[0113] Example 13 includes a power detector configured to measure the power of an radio frequency (RF) signal and comprising: a rectifier configured to receive the RF signal; a comparator having a first input coupled to the rectifier via a first signal line and a second output coupled to the rectifier via a second signal line, the rectifier being configured to output a first voltage on the first signal line and a second voltage on the second signal line; and a digital-to-analog converter (DAC) located on the second signal line, the DAC being configured to superimpose a first offset voltage onto the second voltage at a first time and to superimpose a second offset voltage onto the second voltage at a second time, the second offset voltage being different from the first offset voltage.

[0114] Example 14 includes a power detector according to Example 13, the power detector optionally further including a reference generator disposed on the second signal line between the DAC and the second input of the comparator.

[0115] Example 15 includes a power detector according to Example 14, the power detector optionally further including a multiplexer disposed on the second signal line between the reference generator and the second input of the comparator.

[0116] Example 16 includes a power detector according to Example 15, the power detector optionally further including: digital logic coupled to the output of the comparator and configured to control the multiplexer to route different threshold voltages generated by the reference generator to the second input of the comparator.

[0117] Example 17 includes a power detector according to Example 16, wherein the digital logic is optionally configured to output a digital code identifying the measured power of the radio frequency signal.

[0118] Example 18 includes a power detector according to Example 14, wherein the output of the DAC is optionally communicatively coupled to the input of the reference generator via a third signal line, the DAC optionally including: a set of resistors coupled in series between a power supply voltage and a ground voltage; and a set of switches that couple the nodes between the resistors in the set of resistors in parallel to the third signal line.

[0119] Example 19 includes a power detector according to Example 13, the power detector optionally further including: a temperature sensor configured to measure the temperature of the power detector, the DAC configured to superimpose a first offset voltage onto a second voltage when the temperature has a first value, and the DAC configured to superimpose a second offset voltage onto the second voltage when the temperature has a second value different from the first value.

[0120] Example 20 includes a power detector configured to measure the power of a signal and comprising: a rectifier configured to receive the signal; a first signal line coupled to a first output of the rectifier; a second signal line coupled to a second output of the rectifier; a comparator having a first input coupled to the first signal line and a second input coupled to the second signal line; a digital-to-analog converter (DAC) located on the second signal line; a reference generator located on the second signal line between the DAC and a second input of the comparator; a multiplexer located on the second signal line between the reference generator and a second input of the comparator; digital logic operatively coupled to the comparator and the multiplexer and configured to output a digital code indicating the measured power; and a low-pass filter located on the first signal line.

[0121] Example 21 includes a wireless circuit comprising: a transmit line configured to transmit a radio frequency (RF) signal; a power detector operatively coupled to the transmit line and configured to measure the power of the RF signal, the power detector including a rectifier configured to convert the RF signal into a differential voltage, the differential voltage including a first voltage on a first signal line and a second voltage on a second signal line; a comparator having a first input coupled to the rectifier via the first signal line and a second input coupled to the rectifier via the second signal line; a reference generator disposed on the second signal line, wherein the reference generator is configured to generate a threshold voltage based on the second voltage, and the comparator is configured to compare the first voltage with the threshold voltage; and a temperature sensor configured to measure the temperature of the power detector, the reference generator being configured to adjust the threshold voltage based on the measured temperature.

[0122] Example 22 includes the wireless circuit according to Example 21, the wireless circuit optionally further including: a multiplexer having a first input and a second input coupled to the reference generator, and having an output coupled to the second input of the comparator.

[0123] Example 23 includes the wireless circuitry described in Example 22, wherein the reference generator optionally includes a resistive digital-to-analog converter (RDAC).

[0124] Example 24 includes the wireless circuit according to Example 23, wherein the RDAC optionally includes: a set of resistors coupled between a power supply voltage and a ground voltage; and a set of switches that couple the set of resistors to a third signal line coupled to the first input of the multiplexer.

[0125] Example 25 includes the wireless circuit according to Example 24, the wireless circuit optionally further including: an additional set of switches that couples a subset of the set of resistors to a fourth signal line that couples to the second input of the multiplexer.

[0126] Example 26 includes the wireless circuit according to Example 25, wherein the reference generator is optionally configured to output the threshold voltage to the third signal line and is configured to output an additional threshold voltage to the fourth signal line, the additional threshold voltage being optionally greater than the threshold voltage, and the comparator is optionally configured to compare the first voltage with the additional threshold voltage.

[0127] Example 27 includes the wireless circuit according to Example 26, the wireless circuit optionally further including: an offset-compensated digital-to-analog converter (OSDAC) located on the second signal line between the reference generator and the rectifier, the OSDAC being configured to superimpose an offset voltage onto the second voltage to generate an offset-compensated voltage, wherein the reference generator is optionally configured to generate the threshold voltage and the additional threshold voltage based on the offset-compensated voltage.

[0128] Example 28 includes the wireless circuit according to Example 27, the wireless circuit optionally further including: a first amplifier disposed on the third signal line; and a second amplifier disposed on the fourth signal line.

[0129] Example 29 includes the wireless circuit according to Example 28, the wireless circuit optionally further including: a third amplifier disposed on the fourth signal line between the second amplifier and the second input of the multiplexer.

[0130] Example 30 includes the wireless circuit according to Example 29, wherein the second amplifier optionally has a first input coupled to the additional set of switches, the second amplifier has an output coupled to the third amplifier and a second input of the second amplifier, and the wireless circuit optionally includes: a first resistor coupled between the output of the second amplifier and the second input of the second amplifier; and a second resistor coupling the second input of the second amplifier to the output of the OSDAC.

[0131] Example 31 includes the wireless circuit according to Example 24, the wireless circuit optionally further including: a first adjustable current source, the first adjustable current source being coupled in series between the set of resistors and the power supply voltage; and a second adjustable current source, the second adjustable current source being coupled in series between the set of resistors and the ground voltage.

[0132] Example 32 includes the wireless circuitry according to Example 24, wherein the temperature sensor is optionally configured to adjust the first adjustable current source and the second adjustable current source based on the measured temperature.

[0133] Example 33 includes the wireless circuit according to Example 32, the wireless circuit optionally further including: digital logic operatively coupled to the comparator and the multiplexer, wherein the comparator is optionally configured to generate a comparator signal based on the first voltage and the threshold voltage, and the digital logic is configured to adjust the multiplexer based on the comparator signal.

[0134] Example 34 includes the wireless circuit according to Example 33, the wireless circuit optionally further including: an amplifier located on a radio frequency transmit line path; and one or more processors, wherein the digital logic is optionally configured to output a digital code based on the comparator signal, the digital code representing the power of the radio frequency signal, and the one or more processors are configured to adjust the gain of the amplifier based on the digital code.

[0135] Example 35 includes the wireless circuit according to Example 21, the wireless circuit optionally further including: a low-pass filter disposed on the first signal line and configured to reduce common-mode noise of the first voltage.

[0136] Example 36 includes a power detector configured to measure the power of a signal and comprising: a rectifier configured to receive the signal; a comparator having a first input coupled to the rectifier via a first signal line and a second output coupled to the rectifier via a second signal line, the rectifier being configured to output a first voltage on the first signal line and a second voltage on the second signal line; a digital-to-analog converter (DAC) located on the second signal line and configured to generate an offset compensation voltage by superimposing an offset voltage onto the second voltage; and a reference generator located on the second signal line between the DAC and the second input of the comparator, wherein the reference generator is configured to generate a first threshold voltage by superimposing a first reference voltage onto the offset compensation voltage and a second threshold voltage by superimposing a second reference voltage onto the offset compensation voltage, the comparator being configured to compare the first voltage with the first threshold voltage and the second threshold voltage, and to adjust the second reference voltage over time.

[0137] Example 37 includes a power detector according to Example 16, wherein the reference generator optionally includes: a first adjustable current source; a second adjustable current source; a set of resistors coupled in series between the first and second adjustable current sources; a first set of switches coupling the set of resistors to a third signal path, wherein the reference generator is optionally configured to output a first threshold voltage to the third signal path; and a second set of switches coupling a subset of the set of resistors to a fourth signal path, wherein the reference generator is configured to output a second threshold voltage to the fourth signal path, and the reference generator is configured to adjust the second reference voltage over time by adjusting the first and second adjustable current sources.

[0138] Example 38 includes a power detector according to Example 37, the power detector optionally further including: a temperature sensor configured to measure the temperature of the power detector, the reference generator optionally being configured to adjust the first adjustable current source and the second adjustable current source based on the measured temperature.

[0139] Example 39 includes a power detector according to Example 38, the power detector optionally further including: a multiplexer located on the second signal path between the reference generator and the second input of the comparator, wherein the multiplexer optionally has a first input coupled to the third signal path, a second input coupled to the fourth signal path, and an output coupled to the second input of the comparator; and digital logic configured to regulate the multiplexer based on the output of the comparator.

[0140] Example 30 includes a power detector configured to measure the power of a signal and comprising: a rectifier configured to receive the signal; a first signal line coupled to a first output of the rectifier; a second signal line coupled to a second output of the rectifier; a comparator having a first input coupled to the first signal line and a second input coupled to the second signal line; a reference generator located on the second signal line; and a multiplexer that multiplexes the reference generator and the comparator at the first output of the second signal line. The two inputs are located on the second signal line, wherein the reference generator includes a first adjustable current source and a second adjustable current source, a set of resistors series coupled between the first adjustable current source and the second adjustable current source, a set of switches communicatively coupled to the set of resistors to the multiplexer, an amplifier having a first input coupled to the set of switches and having an output communicatively coupled to the multiplexer, a first resistor coupling the output of the amplifier to a second input of the amplifier, and a second resistor configured to pass an offset-compensated version of the second voltage to the second input of the amplifier.

[0141] As is widely recognized, the use of personally identifiable information should comply with privacy policies and practices that are generally accepted to meet or exceed industry or governmental requirements for protecting user privacy. Specifically, personally identifiable information data should be managed and processed to minimize the risk of unintentional or unauthorized access or use, and the nature of authorized use should be clearly explained to users.

[0142] The foregoing is merely illustrative and various modifications can be made to the described implementation scheme. The foregoing implementation scheme can be implemented individually or in any combination.

[0143] This application claims priority to U.S. Patent Application No. 18 / 830,865, filed September 11, 2024, and U.S. Provisional Patent Application No. 18 / 830,891, filed September 11, 2024, the entire contents of which are incorporated herein by reference.

Claims

1. A wireless circuit, the wireless circuit comprising: A radio frequency (RF) transmission line configured to transmit radio frequency (RF) signals; as well as A power detector, operatively coupled to the radio frequency transmit line and configured to measure the power of the radio frequency signal, the power detector comprising... A rectifier configured to convert the radio frequency signal into a differential voltage, the differential voltage including a first voltage on a first signal line and a second voltage on a second signal line; A comparator having a first input coupled to the rectifier via a first signal line and a second input coupled to the rectifier via a second signal line, and A digital-to-analog converter (DAC) is disposed on the second signal line and is configured to superimpose a dynamic offset voltage onto the second voltage, which changes over time.

2. The wireless circuit of claim 1, wherein the DAC comprises a resistive DAC (RDAC).

3. The wireless circuit according to claim 2, wherein the RDAC comprises: A resistor line, the resistor line being coupled between the power supply voltage and the ground voltage; as well as A set of switches, which are coupled in parallel between a node on the resistor line and a third signal line.

4. The wireless circuit of claim 3, further comprising one or more processors, the one or more processors being configured to: By turning on the first set of switches, a dynamic offset voltage with a first amplitude is provided at the first moment; and By turning on the second set of switches, a dynamic offset voltage with a second amplitude is provided at a second time, the second amplitude being different from the first amplitude.

5. The wireless circuit according to claim 3, further comprising: An additional RDAC is provided, which is operatively coupled between the third signal line and the second input of the comparator.

6. The wireless circuit according to claim 5, further comprising: A multiplexer capable of being operatively coupled between the additional RDAC and the second input of the comparator.

7. The wireless circuit of claim 6, wherein the multiplexer has a first input terminal coupled to the additional RDAC via a fourth signal line, a second input terminal coupled to the additional RDAC via a fifth signal line, and a third input terminal coupled to the additional RDAC via a sixth signal line.

8. The wireless circuit of claim 7, wherein the additional RDAC is configured as follows: A first threshold voltage on the fourth signal line is generated by superimposing a first reference voltage onto the second voltage and the dynamic offset voltage. A second threshold voltage on the fifth signal line is generated by superimposing a second reference voltage onto the second voltage and the dynamic offset voltage, and A third threshold voltage is generated on the sixth signal line by superimposing a third reference voltage onto the second voltage and the dynamic offset voltage.

9. The wireless circuit according to claim 8, further comprising: Digital logic operatively coupled to the comparator and the multiplexer, wherein the comparator is configured to generate a comparator signal based on a first voltage and a first threshold voltage, a second threshold voltage, and a third threshold voltage, and the digital logic is configured to adjust the multiplexer based on the comparator signal.

10. The wireless circuit according to claim 9, further comprising: An amplifier located on the radio frequency transmit line path; as well as One or more processors, wherein the digital logic is configured to output a digital code based on the comparator signal, the digital code representing the power of the radio frequency signal, and the one or more processors are configured to adjust the gain of the amplifier based on the digital code.

11. The wireless circuit according to claim 8, further comprising: A temperature sensor is configured to measure the temperature of the rectifier, and the additional RDAC is configured to adjust the first reference voltage, the second reference voltage, and the third reference voltage based on the temperature of the rectifier.

12. The wireless circuit according to claim 1, further comprising: A low-pass filter is disposed on the first signal line and configured to reduce the common-mode noise of the first voltage.

13. A power detector configured to measure the power of a radio frequency signal and comprising: A rectifier configured to receive the radio frequency signal; A comparator having a first input coupled to the rectifier via a first signal line and a second output coupled to the rectifier via a second signal line, the rectifier being configured to output a first voltage on the first signal line and a second voltage on the second signal line; as well as A digital-to-analog converter (DAC) is located on the second signal line, and the DAC is configured to superimpose a first offset voltage onto the second voltage at a first time. At a second time, a second offset voltage is superimposed on the second voltage, and the second offset voltage is different from the first offset voltage.

14. The power detector according to claim 13, further comprising: A reference generator is provided on the second signal line between the DAC and the second input of the comparator.

15. The power detector according to claim 14, further comprising: A multiplexer is provided on the second signal line between the reference generator and the second input of the comparator.

16. The power detector according to claim 15, further comprising: Digital logic coupled to the output of the comparator and configured to control the multiplexer to route different threshold voltages generated by the reference generator to the second input of the comparator.

17. The power detector of claim 16, wherein the digital logic is configured to output a digital code identifying the measured power of the radio frequency signal.

18. The power detector of claim 14, wherein the output of the DAC is communicatively coupled to the input of the reference generator via a third signal line, the DAC comprising: A set of resistors, the set of resistors being coupled in series between the power supply voltage and the ground voltage; as well as A set of switches that couples the nodes between the resistors in the set of resistors in parallel to the third signal line.

19. The power detector according to claim 13, further comprising: A temperature sensor is configured to measure the temperature of the power detector, the DAC is configured to superimpose a first offset voltage onto a second voltage when the temperature has a first value, and the DAC is configured to superimpose a second offset voltage onto the second voltage when the temperature has a second value different from the first value.

20. A power detector configured to measure the power of a signal and comprising: A rectifier configured to receive the signal; A first signal line, the first signal line being coupled to a first output of the rectifier; A second signal line is coupled to the second output of the rectifier; A comparator having a first input coupled to the first signal line and a second input coupled to the second signal line; A digital-to-analog converter (DAC) located on the second signal line; A reference generator is located on the second signal line between the DAC and the second input of the comparator; A multiplexer located on the second signal line between the reference generator and the second input of the comparator; Digital logic, which is operatively coupled to the comparator and the multiplexer and configured to output a digital code indicating the measured power; as well as A low-pass filter, wherein the low-pass filter is located on the first signal line.

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