A single photon analog domain front-end circuit for event-driven vision sensors

Abstract

The application provides a single-photon analog domain front-end circuit for an event-driven vision sensor, and relates to the technical field of digital-analog hybrid integrated circuits. The single-photon analog domain front-end circuit comprises: an analog counting sub-circuit, which is used for generating a digital pulse in response to reflected photons of a target scene within a preset time window, and converting the digital pulse into first and second voltage signals; an event-driven vision sensor unit, which is used for storing a first intensity value, subtracting the first intensity value from a second intensity value, and outputting an intensity difference of adjacent frames; a high-low threshold comparator, which is used for comparing the intensity difference with a high threshold voltage and a low threshold voltage respectively, and generating an event decision signal; an output buffer, which is used for performing level shift processing on the event decision signal, and outputting an image; and an ADC unit, which is used for quantizing the second voltage signal into a digital signal. In this way, on-chip resource consumption is small, readout rate is high, and the defect of imaging blur when recording high-speed moving objects in traditional passive imaging is overcome.

Description

A single-photon analog domain front-end circuit for event-driven vision sensors Technical Field

[0001] This invention relates to the field of mixed-signal integrated circuit technology, and more particularly to a single-photon analog domain front-end circuit for event-driven vision sensors. Background Technology

[0002] Silicon-based single-photon image sensors, with their single-photon-level sensitivity, precise ranging, and extremely high imaging accuracy, hold significant value in aerospace, border defense, coastal defense, and autonomous driving. These silicon-based single-photon image sensors can be categorized into active and passive imaging systems based on the presence or absence of a light source. The core detection performance of both active and passive imaging systems is limited by the performance of the receiver chip, specifically in terms of photoelectric conversion efficiency, ranging accuracy, spatial resolution, power consumption, image refresh rate, and robustness. With the rapid development of advanced complementary metal-oxide-semiconductor (CMOS) technology and artificial intelligence, silicon-based single-photon avalanche photodiode (SPAD) image sensors, combining high performance, low power consumption, intelligence, and integration, have become a key direction for the development of next-generation optoelectronic imaging technology.

[0003] To achieve event-driven visual perception, existing technologies typically employ digital-domain single-photon event vision sensor (EVS) solutions. However, digital-domain single-photon EVS solutions require the integration of multiple-bit counters, memory, and digital logic units within each pixel. These complex digital circuits themselves occupy a large transistor area, and the N-well isolation region required for PMOS transistors further increases the pixel size, resulting in a low fill factor and high on-chip resource consumption. The serial digital processing link in digital-domain single-photon EVS solutions introduces clock cycle or logic gate delays, and the cumulative delay of the entire processing link becomes a speed bottleneck, limiting the system's readout rate. Furthermore, the event flow in digital-domain single-photon EVS solutions is difficult to coordinate with the quantization process of analog-to-digital conversion used for intensity imaging, causing the intensity image output by the ADC to still contain motion information from the entire exposure time, making it difficult to overcome the blurring defects of traditional passive imaging when recording high-speed moving objects. Summary of the Invention

[0004] The purpose of this invention is to provide a single-photon analog domain front-end circuit for event-driven vision sensors, which solves the problems of high on-chip resource consumption, low system readout rate, and difficulty in overcoming the imaging blur of traditional passive imaging when recording high-speed moving objects.

[0005] To address the aforementioned technical problems, the embodiments of the present invention provide the following technical solutions:

[0006] The present invention provides a single-photon analog domain front-end circuit for an event-driven vision sensor, comprising: an analog counter sub-circuit, an event-driven vision sensor unit, a high-low threshold comparator, an output buffer, and an ADC unit;

[0007] The analog counter circuit is used to receive reflected photons from the target scene within a preset time window, and generate digital pulses in response to the reflected photons, converting the digital pulses into corresponding first voltage signals and second voltage signals.

[0008] An event-driven vision sensor unit is connected to an analog counter circuit to store a first intensity value and calculate the difference between the first intensity value and a second intensity value to output the intensity difference between adjacent frames. The first intensity value is the intensity value corresponding to the first voltage signal in the current time window, and the second intensity value is the intensity value corresponding to the first voltage signal in the previous time window.

[0009] A high-low threshold comparator, connected to an event-driven vision sensor unit, is used to compare the intensity difference with the high threshold voltage and the low threshold voltage respectively to generate an event decision signal;

[0010] The output buffer, connected to the high and low threshold comparators, is used to perform level shifting on the event decision signal and output the image.

[0011] The ADC unit, connected to the analog counter circuit, is used to quantize the second voltage signal into a digital signal.

[0012] Compared to existing technologies, this invention provides a single-photon analog domain front-end circuit for an event-driven visual sensor, comprising an analog counter circuit, an event-driven visual sensor unit, a high-low threshold comparator, an output buffer, and an ADC unit. The analog counter circuit receives reflected photons from a target scene within a preset time window and generates digital pulses in response to the reflected photons, converting the digital pulses into corresponding first and second voltage signals. The event-driven visual sensor unit, connected to the analog counter circuit, stores a first intensity value and calculates the difference between the first and second intensity values ​​to output the intensity difference between adjacent frames. The first intensity value is the intensity value corresponding to the first voltage signal within the current time window, and the second intensity value is the intensity value corresponding to the first voltage signal within the previous time window. The high-low threshold comparator, connected to the event-driven visual sensor unit, compares the intensity difference with a high threshold voltage and a low threshold voltage, respectively, to generate an event decision signal. The output buffer, connected to the high-low threshold comparator, performs level shifting processing on the event decision signal and outputs an image. The ADC unit, connected to the analog counter circuit, quantizes the second voltage signal into a digital signal. In this way, by using the analog counting sub-circuit and the event-driven vision sensor unit, the intensity difference between adjacent frames can be calculated by combining analog counting and capacitor time-division multiplexing. The analog domain approach makes the analog counting sub-circuit and the event-driven vision sensor unit very compact and miniaturized, resulting in low on-chip resource consumption. The event-driven vision sensor unit outputs the intensity difference. When the high and low threshold comparators compare the intensity difference and generate an event decision signal, the corresponding output buffer outputs the image. The output image is greatly simplified in response to the event decision signal, resulting in a high readout rate. The event decision signal can guide or correct the digital signal output by the ADC unit, which can overcome the imaging blurring defect of traditional passive imaging when recording high-speed moving objects. Attached Figure Description

[0013] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of the invention are illustrated by way of example and not limitation, with the same or corresponding reference numerals denoteing the same or corresponding parts, wherein:

[0014] Figure 1 schematically shows a framework diagram of a single-photon analog domain front-end circuit for an event-driven vision sensor;

[0015] Figure 2 schematically shows the circuit diagram of the analog counter circuit and the event-driven vision sensor unit;

[0016] Figure 3 schematically illustrates the principle of capacitor time-division multiplexing in an event-driven vision sensor unit;

[0017] Figure 4 schematically illustrates the operation timing diagram of the event-driven vision sensor unit;

[0018] Figure 5 schematically shows the circuit diagram of the high and low threshold comparator and the output buffer;

[0019] Figure 6 schematically illustrates the low threshold comparator C. PL Circuit diagram of 1;

[0020] Figure 7 schematically illustrates the high threshold comparator C. PH Circuit diagram of 1;

[0021] Figure 8 schematically shows the circuit diagram of the first three-state gate;

[0022] Figure 9 schematically shows the circuit diagram of the second tri-state gate. Detailed Implementation

[0023] The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings and examples. The detailed description of the following embodiments and the accompanying drawings are used to illustrate the principles of the present invention by way of example, but should not be used to limit the scope of the present invention. The present invention can be implemented in many different forms and is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

[0024] The following is a detailed description of a single-photon analog domain front-end circuit for an event-driven vision sensor according to an embodiment of the present invention.

[0025] Referring to Figure 1, which schematically illustrates a framework diagram of a single-photon analog domain front-end circuit for an event-driven vision sensor, this embodiment of the invention proposes a single-photon analog domain front-end circuit for an event-driven vision sensor, including: an analog counter sub-circuit, an event-driven vision sensor unit, a high and low threshold comparator, an output buffer, and an ADC unit.

[0026] The analog counter circuit is used to receive reflected photons from the target scene within a preset time window, and generate digital pulses in response to the reflected photons, converting the digital pulses into corresponding first voltage signals and second voltage signals.

[0027] The event-driven vision sensor (EVS) unit is connected to the analog counter circuit to store the first intensity value and calculate the difference between the first intensity value and the second intensity value to output the intensity difference between adjacent frames. The first intensity value is the intensity value corresponding to the first voltage signal in the current time window, and the second intensity value is the intensity value corresponding to the first voltage signal in the previous time window.

[0028] A high-low threshold comparator, connected to an event-driven vision sensor unit, is used to compare the intensity difference with the high threshold voltage and the low threshold voltage respectively to generate an event decision signal;

[0029] The output buffer, connected to the high and low threshold comparators, is used to perform level shifting on the event decision signal and output the image.

[0030] The ADC unit, connected to the analog counter circuit, is used to quantize the second voltage signal into a digital signal.

[0031] Specifically, the digital pulse is generated by the quenching transistor MQ in the analog counter circuit. The current time window and the previous time window are two adjacent time windows, and the intensity difference between adjacent frames is output at the end of the two adjacent time windows. The high threshold voltage and the low threshold voltage are predefined threshold voltages, and the high threshold voltage can be expressed as V. TH The low threshold voltage can be expressed as V TL The event decision signal is used to guide and correct the digital signal to achieve high-definition dynamic visual imaging. The high and low threshold comparator generates the event decision signal, and the corresponding output buffer outputs the image. If the high and low threshold comparator does not generate an event decision signal, the corresponding output buffer will not output an image.

[0032] In this embodiment, Figure 2 schematically shows the circuit diagram of the analog counting sub-circuit and the event-driven vision sensor unit. Referring to Figure 2, the analog counting sub-circuit includes: a SPAD device, a quenching transistor MQ, a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a capacitor C0, and a switch S1.

[0033] The cathode of the SPAD device is connected to voltage VHV; the anode of the SPAD device is connected to the drain of both quench transistor MQ and transistor M1; the gate of quench transistor MQ is connected to voltage VQ, and the source of quench transistor MQ is grounded; the gate of transistor M1 is connected to the time window signal Gate; the source of transistor M1 is connected to the drain of transistor M2 and the gate of transistor M4; the gate of transistor M2 is connected to the inverted signal of the time window signal Gate. The transistor M2 source is grounded; the transistor M3 gate is connected to the reset signal RST, the transistor M3 drain is connected to the bias voltage VRT, the transistor M3 source is connected to the transistor M4 drain, one end of capacitor C0, the input of the ADC unit, and the event-driven vision sensor unit, and the other end of capacitor C0 is connected to the event-driven vision sensor unit; the transistor M4 source is connected to the transistor M5 drain and the transistor M6 gate; the transistor M5 gate is connected to the bias voltage VG, and the transistor M5 source is connected to the voltage source VS; the transistor M6 source is connected to the transistor M6 drain, the substrate, and one end of switch S1, and the other end of switch S1 is connected to the event-driven vision sensor unit.

[0034] Specifically, the source of transistor M1, the drain of transistor M2, and the gate of transistor M4 are all connected to node N1. The source of transistor M3, the drain of transistor M4, and one end of capacitor C0 are all connected to node N2. The source of transistor M4, the drain of transistor M5, and the gate of transistor M6 are all connected to node N3.

[0035] Referring to Figure 2, the gate of transistor M1 is connected to the time window signal Gate, which is provided by an external digital circuit. The control signal of transistor M2 is inversely related to the time window signal Gate. When the analog counter sub-circuit is disabled, transistor M2 continuously pulls the input of the analog counter down to ground potential to prevent noise from affecting node N1. The analog counter mainly consists of transistors M3, M4, M5, and M6, and capacitor C0, which is a metal-insulator-metal (MIM) capacitor. Before the analog counter starts counting, node N2 is reset to the bias voltage VRT via the reset signal RST. It should be noted that node N2 is reset to the potential of the reset signal RST minus the threshold voltage of transistor M3. Then, the SPAD event signal of node N1 and transistor M6 at node N3 form a charge transfer amplifier (CTA) to achieve charge transfer and thus analog counting; transistor M6 can be regarded as a MOS capacitor Cp. The voltage source VS can be biased above GND, and the bias voltage VG is lower than the threshold voltage of transistor M5, causing transistor M5 to operate in the weak inversion region. The overbias voltage of the SPAD device and the potential of the time window signal Gate need to be set appropriately to ensure that the potential of node N1 is higher than the threshold voltage of transistor M4, thereby ensuring the normal operation of CTA.

[0036] In this embodiment, referring to Figure 2, the event-driven vision sensor unit includes: transistor M7, transistor M8, and a switch. Switch S11, switch S12, capacitor C1 and capacitor C2;

[0037] The gate of transistor M7 is connected to the switch control signal S2. The drain of transistor M7 is connected to one end of capacitor C0 and the drain of transistor M8. The source of transistor M7 is connected to one end of capacitor C1. The other end of capacitor C1 is connected to output OUT1 and one end of switch S11. The gate of transistor M8 is connected to the switch control signal S3. The source of transistor M8 is connected to one end of capacitor C2. The other end of capacitor C2 is connected to output OUT2 and one end of switch S12. The other end of switch S12 is connected to the other end of switch S11. Outputs OUT1 and OUT2 are both connected to the high and low threshold comparators. One end of the switch is connected to the other end of the switch S1. The other end is connected to the bias voltage VM.

[0038] Specifically, Figure 3 schematically shows the principle of capacitor time-division multiplexing of the event-driven vision sensor unit. As shown in Figure 3, the EVS unit can time-division multiplex the intensity value corresponding to the first voltage signal output by the analog counter circuit, and can realize the difference between adjacent frames. Initially, no intensity accumulates on capacitors C0, C1, and C2. Then, the switch control signal S2 is turned on and off, and the second intensity value I1 of the first frame is stored in capacitors C0 and C1, while no intensity value accumulates on capacitor C2. The switch control signal S3 is then turned on and off, and the first intensity value I2 of the second frame accumulates. At this point, capacitor C1 still contains the second intensity value I1 of the first frame, while the first intensity value I2 of the second frame is stored in capacitors C0 and C2. Next, the magnitudes of the second intensity value I1 and the first intensity value I2 of the second frame need to be compared. The switch control signal S2 is turned on upward to calculate the difference between the first intensity value I2 of the second frame and the second intensity value I1 of the first frame. At this point, the first intensity value I2 of the second frame is still stored in capacitor C2. After the difference is calculated, the switch control signal S2 is turned on and off again in the same manner as the first frame, and the intensity value I3 of the third frame accumulates in capacitors C0 and C1. Then, the switch control signal S3 is turned on downward again to calculate the difference between the intensity value I3 of the third frame and the first intensity value I2 of the second frame. By analogy, the comparison of intensity values ​​between adjacent frames is achieved through the above time-division operation. Specifically, the second intensity value I1 of the first frame is the intensity value corresponding to the first voltage signal in the previous time window, the first intensity value I2 of the second frame is the intensity value corresponding to the first voltage signal in the current time window, and the intensity value I3 of the third frame is the intensity value corresponding to the first voltage signal in the next time window.

[0039] Figure 4 schematically illustrates the operation timing diagram of the event-driven vision sensor unit. Referring to Figure 4, before the analog counter subcircuit and EVS unit are enabled, the time window signal Gate, the reset signal RST, and the switch control signal S2 are simultaneously enabled. However, the reset signal RST ends after a brief reset, and the total capacitance of the analog counter becomes the parallel capacitance of capacitors C0 and C1. The pulse width of the switch control signal S2 is approximately 2μs to 10μs. When the switch control signal S2 and the time window signal Gate are no longer enabled, capacitors C0 and C1 are disconnected, and the voltage result corresponding to the second intensity value I1 of the first frame is equally stored in capacitors C0 and C1. In the second frame, the reset signal RST resets the second intensity value I1 of the first frame stored in capacitor C0. Then, with the enable of the switch control signal S3 and the time window signal Gate, the total capacitance becomes a parallel connection of capacitors C0 and C2. When the intensity value counting ends and capacitors C0 and C2 are disconnected, the first intensity value I2 of the second frame is again equally stored in capacitors C0 and C2. At this time, the difference is calculated through the capacitors (i.e., capacitors C0 and C1). First, switch S11 disconnects from GND, making output OUT1 floating. At the same time, switch control signal S2 disconnects from GND, and the lower stage board of capacitor C0 is connected to a bias voltage VM. Then, switch control signal S2 is enabled again, turning on capacitors C0 and C1, and the voltage difference between the two adjacent frames is calculated (i.e., the voltage value of capacitor C0 minus the voltage value of capacitor C1). The difference between the two intensity values ​​is completed the instant switch control signal S2 is turned on. The time period t3 is the time left for the high and low threshold comparator to make subsequent decisions. After the difference between the second intensity value I1 of the first frame and the first intensity value I2 of the second frame is calculated, the voltage data on capacitor C0 is used. The first intensity value I2 of the second frame is still backed up in capacitor C2. At this time, the switch control signal S2 is turned on again simultaneously with the reset signal RST and the time window signal Gate, so that the intensity value I3 of the third frame is stored on capacitors C0 and C1. Similarly, the switch control signal S3 is turned on again to calculate the difference between the first intensity value I2 of the second frame and the intensity value I3 of the third frame. Subsequent operations are carried out in the same manner.

[0040] In this embodiment, quenching transistors MQ, M1, M2, M3, M4, M5, M6, M7, and M8 are all NMOS transistors.

[0041] In this embodiment, FIG5 schematically shows the circuit diagram of the high and low threshold comparator and the output buffer. Referring to FIG5, the high and low threshold comparator includes a first high and low threshold comparator and a second high and low threshold comparator.

[0042] The first high and low threshold comparator includes a high threshold comparator C.PH 1. Low threshold comparator C PL 1. Buffer B1 and buffer B2;

[0043] High threshold comparator C PH The inverting input of 1 and the low threshold comparator C PL The inverting input of 1 is connected to the output OUT1, and the low threshold comparator C PL The non-inverting input of 1 is connected to the low threshold voltage V. TL Connection, low threshold comparator C PL The output of 1 is connected to one end of buffer B1, and the high threshold comparator C PH The non-inverting input of 1 is connected to the high threshold voltage V. TH Connection, high threshold comparator C PH The output terminal of buffer B1 is connected to one end of buffer B2, and the other ends of buffer B1 and buffer B2 are both connected to the output buffer.

[0044] In this embodiment, referring to Figure 5, the second high-low threshold comparator includes a high threshold comparator C. PH 2. Low threshold comparator C PL 2. Buffer B3 and Buffer B4;

[0045] High threshold comparator C PH The inverting input of 2 and the low threshold comparator C PL The inverting inputs of 2 are all connected to the output OUT2, and the low threshold comparator C PL The non-inverting input of 2 is connected to the low threshold voltage V. TL Connection, low threshold comparator C PL The output of 2 is connected to one end of buffer B3, and the high threshold comparator C PH The non-inverting input of 2 is connected to the high threshold voltage V. TH Connection, high threshold comparator C PH The output of buffer B2 is connected to one end of buffer B4, and the other ends of buffers B3 and B4 are both connected to the output buffer.

[0046] In this embodiment, Figure 6 schematically illustrates the low threshold comparator C. PL The circuit diagram for 1 is shown in Figure 6, with the low threshold comparator C. PL 1 includes transmission gate T1, transmission gate T2, transmission gate T3, capacitor Cc, and inverter INV_L;

[0047] The input of transmission gate T1 is connected to the output OUT1. The output of transmission gate T1 is connected to one end of capacitor Cc and the output of transmission gate T2. The input of transmission gate T2 is connected to the low threshold voltage V. TL connect;

[0048] The other end of capacitor Cc is connected to both the input of transmission gate T3 and the input of inverter INV_L. The output of inverter INV_L is connected to the output of transmission gate T3 and the low threshold comparator C. PL The output COM_L of 1 is connected to one end of buffer B1.

[0049] In this embodiment, Figure 7 schematically illustrates the high threshold comparator C. PH The circuit diagram for 1 is shown in Figure 7, with the high threshold comparator C. PH 1 includes transmission gate T4, transmission gate T5, transmission gate T6, transmission gate T7, capacitor Cc1, capacitor Cc2, inverter INV_H1, and inverter INV_H2;

[0050] The input of transmission gate T4 is connected to output OUT1. The output of transmission gate T4 is connected to one end of capacitor Cc1 and the output of transmission gate T5. The input of transmission gate T5 is connected to the high threshold voltage V. TH connect;

[0051] The other end of capacitor Cc1 is connected to both the input of transmission gate T6 and the input of inverter INV_H1. The output of inverter INV_H1 is connected to both the output of transmission gate T6 and one end of capacitor Cc2.

[0052] The other end of capacitor Cc2 is connected to both the input of transmission gate T7 and the input of inverter INV_H2. The output of inverter INV_H2 is connected to the output of transmission gate T7 and the high threshold comparator Cc2. PH The output COM_H of 1 is connected, and the output COM_H is connected to one end of buffer B2.

[0053] Specifically, the low threshold comparator C PL The circuit structure of 2 and the low threshold comparator C PL The structure is the same as 1. Low threshold comparator C PL 2 includes transmission gates T12, T13, and T14, capacitor Cc3, and inverter INV_L1;

[0054] The input of transmission gate T12 is connected to output OUT2. The output of transmission gate T12 is connected to one end of capacitor Cc3 and the output of transmission gate T13. The input of transmission gate T13 is connected to the low threshold voltage V. TL Connections: The other end of capacitor Cc3 is connected to both the input of transmission gate T14 and the input of inverter INV_L1. The output of inverter INV_L1 is connected to the output of transmission gate T14 and the low threshold comparator C. PL The output COM_L of 2 is connected to all terminals, and the output COM_L is connected to one end of buffer B3.

[0055] Specifically, the high threshold comparator C PH The circuit structure of 2 and the high threshold comparator C PH The structure is the same as 1. High threshold comparator C PH 2 includes transmission gates T15, T16, T17, and T18, capacitors Cc4 and Cc5, inverters INV_H3 and INV_H4;

[0056] The input terminal of transmission gate T15 is connected to output OUT2. The output terminal of transmission gate T15 is connected to one end of capacitor Cc4 and the output terminal of transmission gate T16. The input terminal of transmission gate T16 is connected to the high threshold voltage V. TH Connections: The other end of capacitor Cc4 is connected to the input of transmission gate T17 and the input of inverter INV_H3. The output of inverter INV_H3 is connected to the output of transmission gate T17 and one end of capacitor Cc5. The other end of capacitor Cc5 is connected to the input of transmission gate T18 and the input of inverter INV_H4. The output of inverter INV_H4 is connected to the output of transmission gate T18 and the high threshold comparator C. PH The output COM_H of 2 is connected, and the output COM_H is connected to one end of buffer B4.

[0057] Specifically, as shown in Figures 6 and 7, the other end of capacitor Cc1, the input of transmission gate T6, and the input of inverter INV_H1 are all connected to node Vx. Using a low-threshold comparator C... PL Taking 1 as an example, let's explain the working principle of the circuit. When the input signal value OUT1 reaches the set low threshold voltage V... TL When node Vx reaches the threshold VT1 corresponding to INV_L, the low threshold comparator C will... PL The output of 1 is flipped. It should be noted that enable signals P1 and P2 are enabled on the rising edge of time interval t3 in Figure 4. Time interval t3 is the time allotted for the high and low threshold comparators to make subsequent decisions. After the intensity values ​​of two adjacent frames are subtracted, the output OUT1 corresponding to the intensity difference is sent to the low threshold comparator C. PL 1 and high threshold comparator C PH During the comparison period, enable signals P1 and P2 are activated, thereby turning on the low threshold comparator C. PL 1 and high threshold comparator C PH The internal transmission gate allows for dynamic comparison of the intensity difference with both the high and low threshold voltages. After comparison, a corresponding event decision signal is output. As shown in Figures 6 and 7, the high threshold comparator C... PH 1 to low threshold comparator C PLThe reason for having an additional stage is as follows: When the input signal is below the low threshold voltage, the low threshold comparator C... PL 1. The output is high. When the input signal is higher than the low threshold voltage, the low threshold comparator C... PL The output of 1 is low. This is to ensure that the low-threshold comparator C is triggered. PL 1. Output consistency, low threshold comparator C above the low threshold voltage PL The output of 1 must also be high, so the low threshold comparator C... PL 1. Add one stage to make it a high-threshold comparator C PH 1. In addition, the low threshold comparator C PL The output range is between the threshold voltage VT1 and the bias voltage VDD15, so a level shift must be performed before outputting, i.e., VT1 is processed to 0V.

[0058] In this embodiment, FIG8 schematically shows the circuit diagram of the first tri-state gate. Referring to FIG5 and FIG8, the output buffer includes a first output buffer and a second output buffer.

[0059] The first output buffer includes a first tri-state gate, a transmission gate T8, and a transmission gate T9; the first tri-state gate includes transistors M9, M10, M11, M12, M13, and M14; transistors M9, M10, and M11 are all NMOS transistors, and transistors M12, M13, and M14 are all PMOS transistors.

[0060] The input terminal of transmission gate T8 is connected to the other end of buffer B1, and the input terminal of transmission gate T9 is connected to the other end of buffer B3. The output terminals of transmission gates T8 and T9 are both connected to the gate terminals of transistors M9 and M12. The source terminal of transistor M12 is connected to the bias voltage VDD15. The drain terminal of transistor M12 is connected to the drain terminal of transistor M9, the gate terminal of transistor M11, and the gate terminal of transistor M13. The source terminal of transistor M9 is grounded. The source terminal of transistor M13 is connected to the bias voltage VDD15. The drain terminal of transistor M13 is connected to the source terminal of transistor M14. The gate terminal of transistor M14 is connected to the inverted bias voltage SEL. The drain terminal of transistor M14 is connected to the output OUTL and the drain terminal of transistor M10. The gate terminal of transistor M10 is connected to the bias voltage SEL. The source terminal of transistor M10 is connected to the drain terminal of transistor M11. The source terminal of transistor M11 is grounded.

[0061] In this embodiment, Figure 9 schematically shows the circuit diagram of the second tri-state gate. Referring to Figures 5 and 9, the second output buffer includes a second tri-state gate, a transmission gate T10, and a transmission gate T11; the second tri-state gate includes transistors M15, M16, M17, M18, M19, and M20; transistors M15, M16, and M17 are all NMOS transistors, and transistors M18, M19, and M20 are all PMOS transistors;

[0062] The input terminal of transmission gate T10 is connected to the other end of buffer B2, and the input terminal of transmission gate T11 is connected to the other end of buffer B4. The output terminals of transmission gates T10 and T11 are both connected to the gate terminals of transistors M15 and M18. The source terminal of transistor M18 is connected to the bias voltage VDD15. The drain terminal of transistor M18 is connected to the drain terminal of transistor M15, the gate terminal of transistor M17, and the gate terminal of transistor M19. The source terminal of transistor M15 is grounded. The source terminal of transistor M19 is connected to the bias voltage VDD15. The drain terminal of transistor M19 is connected to the source terminal of transistor M20. The gate terminal of transistor M20 is connected to the inverted bias voltage SEL. The drain terminal of transistor M20 is connected to the output OTH and the drain terminal of transistor M16. The gate terminal of transistor M16 is connected to the bias voltage SEL. The source terminal of transistor M16 is connected to the drain terminal of transistor M17. The source terminal of transistor M17 is grounded.

[0063] Specifically, as shown in Figure 5, the image output from the output buffer is transmitted to the horizontal bus through the first and second tri-state gates. Because the output of the corresponding pixel of the image is a digital pulse from 0 to the bias voltage VDD15, a high-impedance node needs to be implemented through the first and second tri-state gates to ensure the correctness of the data during bus switching.

[0064] In Figure 8, transistor M9 has a width of 0.4 μm and a length of 0.13 μm; transistor M12 has a width of 0.8 μm and a length of 0.13 μm; transistors M13 and M14 both have a width of 2 μm and a length of 0.13 μm; transistors M10 and M11 both have a width of 1.2 μm and a length of 0.13 μm. In Figure 9, transistor M15 has a width of 0.4 μm and a length of 0.13 μm; transistor M18 has a width of 0.8 μm and a length of 0.13 μm; transistors M19 and M20 both have a width of 2 μm and a length of 0.13 μm; transistors M16 and M17 both have a width of 1.2 μm and a length of 0.13 μm.

[0065] Specifically, by using the ADC unit to quantize the output voltage of the analog counter, the event decision signal can guide and correct the quantization data of the ADC unit, breaking through the limitation of traditional passive imaging in recording high-speed moving objects with blurred images.

[0066] This invention supports moving target detection by employing a difference calculation method combining analog counting in the analog counting sub-circuit and capacitor time-division multiplexing in the EVS unit to achieve difference calculation of intensity values ​​between adjacent frames. Precise intra-pixel threshold voltage comparison enables accurate division of intensity changes and event discrimination, while high-speed output of single-bit data is achieved through level shifting processing. This analog domain EVS unit features low on-chip resource consumption and dynamic power consumption, meeting the requirements for real-time detection, capture of fast targets, and low-power two-dimensional passive imaging. This invention utilizes passive imaging, meaning the EVS unit has no active light source, thus significantly improving its stability. The transistors used in the analog counting sub-circuit and EVS unit of this invention are all NMOS transistors, maximizing the fill factor. Since PMOS transistors require an N-well implementation environment, this introduces necessary process rule distances in most P-type substrate-based processes, increasing pixel size. The analog domain circuit architecture of this invention makes the single-photon analog domain front-end circuit very compact and miniaturized, meaning lower on-chip resource overhead and suitability for large-scale array integration. This invention is applicable to indoor or outdoor security monitoring and other applications requiring low power consumption and high frame rate.

[0067] The single-photon analog domain front-end circuit of this invention includes: an analog counter sub-circuit, an event-driven visual sensor unit, a high-low threshold comparator, an output buffer, and an ADC unit. The analog counter sub-circuit receives reflected photons from a target scene within a preset time window and generates digital pulses in response to the reflected photons, converting the digital pulses into corresponding first and second voltage signals. The event-driven visual sensor unit, connected to the analog counter sub-circuit, stores a first intensity value and calculates the difference between the first and second intensity values ​​to output the intensity difference between adjacent frames. The first intensity value is the intensity value corresponding to the first voltage signal within the current time window, and the second intensity value is the intensity value corresponding to the first voltage signal within the previous time window. The high-low threshold comparator, connected to the event-driven visual sensor unit, compares the intensity difference with a high threshold voltage and a low threshold voltage respectively to generate an event decision signal. The output buffer, connected to the high-low threshold comparator, performs level shifting processing on the event decision signal and outputs an image. The ADC unit, connected to the analog counter sub-circuit, quantizes the second voltage signal into a digital signal. In this way, by using the analog counting sub-circuit and the event-driven vision sensor unit, the intensity difference between adjacent frames can be calculated by combining analog counting and capacitor time-division multiplexing. The analog domain approach makes the analog counting sub-circuit and the event-driven vision sensor unit very compact and miniaturized, resulting in low on-chip resource consumption. The event-driven vision sensor unit outputs the intensity difference. When the high and low threshold comparators compare the intensity difference and generate an event decision signal, the corresponding output buffer outputs the image. The output image is greatly simplified in response to the event decision signal, resulting in a high readout rate. The event decision signal can guide or correct the digital signal output by the ADC unit, which can overcome the imaging blurring defect of traditional passive imaging when recording high-speed moving objects.

[0068] While specific embodiments of the present invention have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and are not intended to limit the scope of the invention. Those skilled in the art should understand that modifications can be made to the above embodiments or equivalent substitutions can be made to some technical features without departing from the scope and spirit of the invention. In particular, as long as there is no structural conflict, the various technical features mentioned in the embodiments can be combined in any manner.

[0069] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A single-photon analog domain front-end circuit for an event-driven vision sensor, characterized in that, The single-photon analog domain front-end circuit includes: an analog counter sub-circuit, an event-driven visual sensor unit, a high-low threshold comparator, an output buffer, and an ADC unit. The analog counter sub-circuit receives reflected photons from the target scene within a preset time window and generates digital pulses in response to the reflected photons, converting the digital pulses into corresponding first and second voltage signals. The event-driven visual sensor unit, connected to the analog counter sub-circuit, stores a first intensity value and calculates the difference between the first and second intensity values, outputting the intensity difference between adjacent frames. The first intensity value is the intensity value corresponding to the first voltage signal within the current time window, and the second intensity value is the intensity difference between adjacent frames. The intensity value is the intensity value corresponding to the first voltage signal within the previous time window; the high and low threshold comparator, connected to the event-driven vision sensor unit, is used to compare the intensity difference with the high threshold voltage and the low threshold voltage respectively to generate an event decision signal; the output buffer, connected to the high and low threshold comparator, is used to perform level shifting processing on the event decision signal and output an image; the ADC unit, connected to the analog counting sub-circuit, is used to quantize the second voltage signal into a digital signal, wherein the image output by the output buffer is used to guide and correct the digital signal output by the ADC unit to obtain the final output image that overcomes imaging blur.

2. The single-photon analog domain front-end circuit for an event-driven vision sensor according to claim 1, characterized in that, The analog counting sub-circuit includes: a SPAD device, a quenching transistor MQ, transistor M1, transistor M2, transistor M3, transistor M4, transistor M5, transistor M6, capacitor C0, and switch S1; the cathode of the SPAD device is connected to voltage VHV, and the anode of the SPAD device is connected to the drain of both the quenching transistor MQ and the drain of transistor M1; the gate of the quenching transistor MQ is connected to voltage VQ, and the source of the quenching transistor MQ is grounded; the gate of transistor M1 is connected to the time window signal Gate, and the source of transistor M1 is connected to the drain of both transistor M2 and the gate of transistor M4; the gate of transistor M2 is connected to the inverted signal of the time window signal Gate, and the source of transistor M2 is grounded; The gate of transistor M3 is connected to the reset signal RST, the drain of transistor M3 is connected to the bias voltage VRT, the source of transistor M3 is connected to the drain of transistor M4, one end of capacitor C0, the input of the ADC unit, and the event-driven vision sensor unit, and the other end of capacitor C0 is connected to the event-driven vision sensor unit; the source of transistor M4 is connected to the drain of transistor M5 and the gate of transistor M6; the gate of transistor M5 is connected to the bias voltage VG, and the source of transistor M5 is connected to the voltage source VS; the source of transistor M6 is connected to the drain of transistor M6, the substrate, and one end of switch S1, and the other end of switch S1 is connected to the event-driven vision sensor unit.

3. The single-photon analog domain front-end circuit for an event-driven vision sensor according to claim 2, characterized in that, The event-driven vision sensor unit includes: transistor M7, transistor M8, and a switch. The circuit consists of switches S11 and S12, capacitors C1 and C2; the gate of transistor M7 is connected to the switch control signal S2, the drain of transistor M7 is connected to one end of capacitor C0 and the drain of transistor M8, the source of transistor M7 is connected to one end of capacitor C1, and the other end of capacitor C1 is connected to output OUT1 and one end of switch S11; the gate of transistor M8 is connected to the switch control signal S3, the source of transistor M8 is connected to one end of capacitor C2, the other end of capacitor C2 is connected to output OUT2 and one end of switch S12, the other end of switch S12 is connected to the other end of switch S11, and outputs OUT1 and OUT2 are both connected to the high and low threshold comparator; the switches... One end of the switch is connected to the other end of the switch S1. The other end is connected to the bias voltage VM.

4. The single-photon analog domain front-end circuit for an event-driven vision sensor according to claim 3, characterized in that, The quenching transistor MQ, transistor M1, transistor M2, transistor M3, transistor M4, transistor M5, transistor M6, transistor M7 and transistor M8 are all NMOS transistors.

5. The single-photon analog domain front-end circuit for an event-driven vision sensor according to claim 3, characterized in that, The high-low threshold comparator includes a first high-low threshold comparator and a second high-low threshold comparator; the first high-low threshold comparator includes a high threshold comparator C. PH 1. Low threshold comparator C PL 1. Buffers B1 and B2; the high threshold comparator C PH The inverting input of 1 and the low threshold comparator C PL The inverting input terminals of 1 are all connected to the output OUT1, and the low threshold comparator C PL The non-inverting input of 1 is connected to the low threshold voltage V. TL Connection, the low threshold comparator C PL The output of 1 is connected to one end of the buffer B1, and the high threshold comparator C PH The non-inverting input of 1 is connected to the high threshold voltage V. TH Connection, the high threshold comparator C PH The output terminal of 1 is connected to one end of the buffer B2, and the other ends of the buffer B1 and the other ends of the buffer B2 are both connected to the output buffer.

6. The single-photon analog domain front-end circuit for an event-driven vision sensor according to claim 5, characterized in that, The second high-low threshold comparator includes a high threshold comparator C. PH 2. Low threshold comparator C PL 2. Buffers B3 and B4; the high threshold comparator C PH The inverting input of 2 and the low threshold comparator C PL The inverting input terminals of 2 are all connected to the output OUT2, and the low threshold comparator C PL The non-inverting input of 2 is connected to the low threshold voltage V. TL Connection, the low threshold comparator C PL The output of 2 is connected to one end of the buffer B3, and the high threshold comparator C PH The non-inverting input of 2 is connected to the high threshold voltage V. TH Connection, the high threshold comparator C PH The output terminal of 2 is connected to one end of the buffer B4, and the other ends of the buffer B3 and the other ends of the buffer B4 are both connected to the output buffer.

7. The single-photon analog domain front-end circuit for an event-driven vision sensor according to claim 5, characterized in that, The low threshold comparator C PL The system includes transmission gates T1, T2, and T3, a capacitor Cc, and an inverter INV_L. The input of transmission gate T1 is connected to the output OUT1. The output of transmission gate T1 is connected to one end of the capacitor Cc and the output of transmission gate T2. The input of transmission gate T2 is connected to the low threshold voltage V. TL Connections: The other end of capacitor Cc is connected to both the input of transmission gate T3 and the input of inverter INV_L. The output of inverter INV_L is connected to the output of transmission gate T3 and the low threshold comparator C. PL The output COM_L of buffer B1 is connected to one end of buffer B1.

8. The single-photon analog domain front-end circuit for an event-driven vision sensor according to claim 5, characterized in that, The high threshold comparator C PH The system includes transmission gates T4, T5, T6, and T7, capacitors Cc1 and Cc2, inverters INV_H1 and INV_H2; the input terminal of transmission gate T4 is connected to the output OUT1, the output terminal of transmission gate T4 is connected to one end of capacitor Cc1 and the output terminal of transmission gate T5, and the input terminal of transmission gate T5 is connected to the high threshold voltage V. TH Connections: The other end of capacitor Cc1 is connected to the input of transmission gate T6 and the input of inverter INV_H1. The output of inverter INV_H1 is connected to the output of transmission gate T6 and one end of capacitor Cc2. The other end of capacitor Cc2 is connected to the input of transmission gate T7 and the input of inverter INV_H2. The output of inverter INV_H2 is connected to the output of transmission gate T7 and the high threshold comparator C. PH The output COM_H of 1 is connected, and the output COM_H is connected to one end of the buffer B2.

9. The single-photon analog domain front-end circuit for an event-driven vision sensor according to claim 6, characterized in that, The output buffer includes a first output buffer and a second output buffer; the first output buffer includes a first tri-state gate, a transmission gate T8, and a transmission gate T9; the first tri-state gate includes transistors M9, M10, M11, M12, M13, and M14; transistors M9, M10, and M11 are all NMOS transistors, and transistors M12, M13, and M14 are all PMOS transistors; the input terminal of transmission gate T8 is connected to the other end of buffer B1, the input terminal of transmission gate T9 is connected to the other end of buffer B3, and the output terminals of transmission gate T8 and transmission gate T9 are both connected to the gate terminal of transistor M9 and the gate terminal of transistor M14. The gate of transistor M12 is connected to the bias voltage VDD15. The drain of transistor M12 is connected to the drain of transistor M9, the gate of transistor M11, and the gate of transistor M13. The source of transistor M9 is grounded. The source of transistor M13 is connected to the bias voltage VDD15. The drain of transistor M13 is connected to the source of transistor M14. The gate of transistor M14 is connected to the inverted bias voltage SEL. The drain of transistor M14 is connected to the output OUTL and the drain of transistor M10. The gate of transistor M10 is connected to the bias voltage SEL. The source of transistor M10 is connected to the drain of transistor M11. The source of transistor M11 is grounded.

10. The single-photon analog domain front-end circuit for an event-driven vision sensor according to claim 9, characterized in that, The second output buffer includes a second tri-state gate, a transmission gate T10, and a transmission gate T11; the second tri-state gate includes transistors M15, M16, M17, M18, M19, and M20; transistors M15, M16, and M17 are all NMOS transistors, and transistors M18, M19, and M20 are all PMOS transistors; the input terminal of transmission gate T10 is connected to the other end of buffer B2, the input terminal of transmission gate T11 is connected to the other end of buffer B4, and the output terminals of transmission gates T10 and T11 are both connected to the gate terminals of transistors M15 and M18, respectively. The source terminal of transistor M18 is connected to the bias voltage VDD15. The drain terminal of transistor M18 is connected to the drain terminal of transistor M15, the gate terminal of transistor M17, and the gate terminal of transistor M19. The source terminal of transistor M15 is grounded. The source terminal of transistor M19 is connected to the bias voltage VDD15. The drain terminal of transistor M19 is connected to the source terminal of transistor M20. The gate terminal of transistor M20 is connected to the inverted bias voltage SEL. The drain terminal of transistor M20 is connected to the output OTH and the drain terminal of transistor M16. The gate terminal of transistor M16 is connected to the bias voltage SEL. The source terminal of transistor M16 is connected to the drain terminal of transistor M17. The source terminal of transistor M17 is grounded.

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