Memory cell, memory array and control method thereof, memory device and manufacturing method thereof

Abstract

A memory cell, a memory array and a control method thereof, a memory device and a manufacturing method thereof, the memory cell comprising: a device pillar having a first end and a second end opposite to each other in an axial direction of the device pillar; the gate structure surrounds the device column in the circumferential direction, and the gate structure is separated from the first end and the second end in the axial direction of the device column; the storage capacitor is located on the side, close to the first end, of the device column in the axial direction of the device column, and the storage capacitor is electrically connected with the first end. According to the technical scheme of the invention, the control capability of the gate structure on the channel is stronger, and the area of the storage unit is smaller, so that the storage density of the storage array comprising the storage unit can be effectively improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a memory cell, a memory array and its control method, a memory device and its manufacturing method. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration. For storage devices, the requirements for storage density and read / write speed are becoming increasingly stringent.

[0003] To improve integration and reduce costs, the size of storage cells is constantly shrinking, while the circuit density inside storage devices is increasing. This shrinking of storage cell size and increasing of internal circuit density make it increasingly difficult to further increase storage density and read / write speeds. Summary of the Invention

[0004] The problem solved by this invention is how to further increase storage density and improve read / write speed in storage devices.

[0005] To address the above problems, the present invention provides a storage unit, comprising:

[0006] The device post has a first end and a second end that are opposite to each other along the axial direction of the device post; a gate structure that surrounds the device post circumferentially; and a storage capacitor that is located on the side of the device post closer to the first end along the axial direction of the device post and is electrically connected to the first end.

[0007] Optionally, the device pillar is cylindrical; the storage capacitor is cylindrical.

[0008] Optionally, the gate structure includes a gate electrode and a gate dielectric layer, wherein the gate dielectric layer is located between the gate electrode and the device pillar.

[0009] Optionally, the gate electrode extends from at least one side of the gate dielectric layer along the axial direction of the device pillar.

[0010] Optionally, the gate electrode is made of polycrystalline silicon or a metal; the gate dielectric layer is made of an oxide.

[0011] Optionally, the gate structure extends along a predetermined direction in a plane perpendicular to the axial direction of the device pillar.

[0012] Optionally, the second end is electrically connected to the bit line through a via structure; or, the second end is in direct contact with the bit line.

[0013] Optionally, the storage capacitor is located on the end face of the first end.

[0014] Furthermore, the present invention also provides a storage array, comprising:

[0015] The storage unit, which is the storage unit of the present invention, is arranged in an array in a plane perpendicular to the axial direction of the device column.

[0016] Optionally, the gate electrodes of the gate structures in adjacent memory cells along the row direction are integrally connected.

[0017] Optionally, the gate electrodes of the gate structures in adjacent memory cells along the column direction are separated.

[0018] Optionally, the storage cells of adjacent rows are staggered along the row direction; the storage cells of adjacent columns are staggered along the column direction.

[0019] Optionally, it also includes: a bit line along the axial direction of the device post, the bit line being located on the side of the device post near the second end, the bit line extending along the column direction in a plane perpendicular to the axial direction of the device post; memory cells in the same column are connected to the same bit line.

[0020] Optionally, the storage cells of adjacent columns are interleaved with the two adjacent bit lines.

[0021] Optionally, it also includes: word lines, which extend in a row direction in a plane perpendicular to the axial direction of the device pillars; memory cells in the same row are connected to the same word line;

[0022] Optionally, adjacent rows of storage cells are interleaved with the two adjacent word lines.

[0023] Accordingly, the present invention also provides a control method for a memory array, wherein the memory array is the memory array of the present invention; the control method includes: applying a first voltage to a bit line while applying a second voltage to an adjacent bit line, wherein the second voltage is not equal to the first voltage.

[0024] Optionally, the memory array includes a first bit line, a second bit line, ..., an nth bit line arranged sequentially, where n is the number of bit lines; the step of applying a first voltage to a bit line while applying a second voltage to an adjacent bit line includes: applying a first voltage to the (2p-1)th bit line while applying a second voltage to the 2pth bit line, where p is an integer greater than 0.

[0025] Optionally, in the step of applying a first voltage to the 2p-1 bit line and applying a second voltage to the 2p bit line, the first voltage is applied to all 2p-1 bit lines while the second voltage is applied to all 2p bit lines.

[0026] Optionally, the step of applying a first voltage to a bit line and applying a second voltage to an adjacent bit line further includes: applying a first voltage to the 2qth bit line and applying a second voltage to the 2q-1th bit line, where q is an integer greater than 0.

[0027] Optionally, in the step of applying a first voltage to the 2q-1 bit line while simultaneously applying a second voltage to the 2q-1 bit line, the first voltage is applied to all 2q bit lines while the second voltage is applied to all 2q-1 bit lines.

[0028] Optionally, during a read operation, the first voltage is the read voltage; during a write operation, the first voltage is the write voltage; and during an erase operation, the first voltage is the erase voltage.

[0029] Optionally, the second voltage is the default voltage.

[0030] Accordingly, the present invention also provides a storage device, comprising:

[0031] The storage array is the storage array of the present invention; the controller is adapted to apply a first voltage to a bit line while simultaneously applying a second voltage to an adjacent bit line, the second voltage being unequal to the first voltage.

[0032] Optionally, the storage array includes a first bit line, a second bit line, ..., an nth bit line arranged sequentially, where n is the number of bit lines; the controller is adapted to apply a first voltage to the (2p-1)th bit line while simultaneously applying a second voltage to the 2pth bit line, where p is an integer greater than 0.

[0033] Optionally, the controller applies a first voltage to all 2p-1 bit lines while simultaneously applying a second voltage to all 2p bit lines.

[0034] Optionally, the controller is also adapted to apply a first voltage to the 2q-1 bit line while simultaneously applying a second voltage to the 2q-1 bit line, where q is an integer greater than 0.

[0035] Optionally, the controller applies a first voltage to all 2q-th bit lines while simultaneously applying a second voltage to all 2q-1-th bit lines.

[0036] Optionally, during a read operation, the first voltage is the read voltage; during a write operation, the first voltage is the write voltage; and during an erase operation, the first voltage is the erase voltage.

[0037] Optionally, the second voltage is the default voltage.

[0038] Furthermore, the present invention also provides a method for manufacturing a storage device, comprising:

[0039] A device post is formed having a second end and a first end opposite to each other along the axial direction of the device post; a gate structure is formed circumferentially around the device post; a storage capacitor is formed on the side of the device post near the first end along the axial direction of the device post, the storage capacitor being electrically connected to the first end.

[0040] Optionally, the step of forming the device pillar includes: providing a substrate; etching the substrate to form a substrate and a device pillar protruding from the front side of the substrate.

[0041] Optionally, the step of forming a gate structure circumferentially surrounding the device pillar includes: forming a gate dielectric layer circumferentially surrounding the device pillar; and forming a gate electrode on the gate dielectric layer.

[0042] Optionally, it further includes: forming a bit line on the side of the device post near the second end, the bit line being electrically connected to the second end of the device post.

[0043] Optionally, in the step of forming a bit line on the side of the device post near the second end, a bit line in contact with the second end of the device post is formed; or, the manufacturing method further includes forming a via structure electrically connected to the second end before forming the bit line on the side of the device post near the second end.

[0044] Optionally, in the step of forming the device pillar, the device pillar protrudes from the front side of the substrate; the manufacturing method further includes: before the step of forming a bit line on the side of the device pillar near the second end, removing the substrate to expose the second end.

[0045] Optionally, the step of removing the substrate to expose the second end includes: removing the substrate along the back side of the substrate, the back side being disposed opposite to the front side.

[0046] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0047] In the technical solution of this invention, in the memory cell, the gate structure surrounds the device pillar along the axial direction, and the storage capacitor is located on one side of the first end of the device pillar along the axial direction and connected to the first segment. The gate structure completely surrounds the device pillar, effectively ensuring the gate structure's control over the channel; moreover, in the memory cell, the channel in the device pillar extends axially; in the plane perpendicular to the axial direction of the device pillar, the area of ​​the memory cell is small, effectively improving the storage density of the memory array including the memory cell.

[0048] In an optional embodiment of the present invention, the storage cells in adjacent rows of the storage array are staggered along the column direction. This staggered arrangement of storage cells in adjacent rows, with the cells densely packed in a plane perpendicular to the axis of the device pillars, effectively increases the distribution density of the storage cells. This increased storage density also provides the hardware basis for an odd-even interval operating mode, maximizing storage density, minimizing wasted area, and achieving a balance between read / write speed and storage density.

[0049] In an optional embodiment of the present invention, adjacent column storage cells are connected to adjacent bit lines along the row direction; while applying a first voltage to a bit line, a second voltage is applied to adjacent bit lines, the second voltage being unequal to the first voltage. When the storage device is operating, unequal voltages are applied to adjacent bit lines; a first voltage is applied to a bit line for reading and writing data, and a second voltage is applied to adjacent bit lines to shield coupling capacitors; this odd-even interval operating mode effectively shields the coupling between bit lines, effectively ensuring the speed of read and write operations.

[0050] In the optional embodiment of the present invention, the second voltage is the default voltage, which is Vcc / 2. This solution can be implemented without making major modifications to the internal circuitry of the storage device, thus effectively reducing the difficulty of implementation. Attached Figure Description

[0051] Figure 1 This is a schematic diagram of the circuit structure of a storage array;

[0052] Figure 2 These are three-dimensional structural schematic diagrams of some embodiments of the storage array of the present invention;

[0053] Figure 3 This is along some embodiments of the storage array of the present invention. Figure 2 A top view of the structure in the direction of A;

[0054] Figure 4 This is along some embodiments of the storage array of the present invention. Figure 3 A schematic diagram of the cross-sectional structure at the location of line B1B2 in the middle;

[0055] Figure 5 This is along some embodiments of the storage array of the present invention. Figure 3 A schematic diagram of the cross-sectional structure at the location of line C1C2 in the middle;

[0056] Figure 6 These are schematic diagrams of the circuit structure of some embodiments of the storage array of the present invention;

[0057] Figures 7 to 22 This is a schematic diagram of the intermediate structures of each step in some embodiments of the storage device manufacturing method of the present invention. Detailed Implementation

[0058] As the background technology shows, with the continuous iteration of storage device technology, the storage density requirements of storage devices are getting higher and higher, and it is becoming increasingly difficult to further increase the storage density of storage devices.

[0059] Furthermore, as storage density increases, the size requirements of components within the storage device also increase, with component sizes shrinking and the distances between components decreasing. This leads to increasingly stronger coupling between storage cells, and the coupling capacitance between adjacent bit lines in the storage device becomes larger and larger.

[0060] Specifically, such as Figure 1 As shown, in the storage array of the storage device, the storage cells 11 are arranged in a rectangular array, and the row and column directions of the storage array are perpendicular to each other. In the storage array, bit lines BL extend along the column direction and are arranged parallel to each other along the row direction; word lines WL extend along the row direction and are arranged parallel to each other along the column direction. Storage cells 11 located in the same row are connected to the same word line WL; storage cells 11 located in the same column are connected to the same bit line BL.

[0061] When the storage array is working, when the word line WL is applied with working voltage, all storage cells 11 in the same row are turned on and can work. That is, all bit lines BL can be applied with working voltage so that the storage cells 11 in the entire row start working at the same time. Since the distance between adjacent bit lines BL is small, the coupling effect between adjacent bit lines BL is strong, which affects the sense margin of the storage device and affects the further improvement of read and write speed.

[0062] To solve the aforementioned technical problem, the present invention provides a storage unit, comprising:

[0063] The device post has a first end and a second end that are opposite to each other along the axial direction of the device post; a gate structure that surrounds the device post circumferentially and is separated from both the first end and the second end along the axial direction of the device post; and a storage capacitor that is located on the side of the device post closer to the first end along the axial direction of the device post and is electrically connected to the first end.

[0064] In this invention, the gate structure of the memory cell surrounds the device pillar along the axial direction, and the storage capacitor is located on one side of the first end of the device pillar along the axial direction and connected to the first segment. The gate structure completely surrounds the device pillar, effectively ensuring the gate structure's control over the channel; furthermore, the channel in the device pillar extends axially within the memory cell; and the area of ​​the memory cell is small in a plane perpendicular to the axial direction of the device pillar, effectively increasing the storage density of the memory array including the memory cell.

[0065] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0066] refer to Figures 2 to 5 The diagram shows a structural schematic of an embodiment of the storage array of the present invention.

[0067] in, Figure 2 This is a three-dimensional structural diagram of an embodiment of the storage array of the present invention; Figure 3 yes Figure 2 A top view of the structure along direction A; Figure 4 yes Figure 3 A schematic diagram of the cross-sectional structure along line B1B2 in the middle; Figure 5 yes Figure 3 A schematic diagram of the cross-sectional structure along line C1C2.

[0068] The storage array includes storage cells 101 arranged in a regular array.

[0069] The storage cell 101 includes: a device post 110 having a first end and a second end opposite to each other along the axial direction of the device post 110; a gate structure 120 surrounding the device post 110 circumferentially, and separated from both the first end (not shown) and the second end (not shown) along the axial direction z of the device post 110; and a storage capacitor 130 located on the side of the device post 110 closer to the first end along the axial direction of the device post 110, and electrically connected to the first end.

[0070] Within the array plane parallel to the memory array, the memory cell has a smaller area, resulting in a higher memory density. Furthermore, the memory cell is a gate all around (GAA) structure, and the gate structure 120 has strong control over the channel, effectively ensuring the performance of the memory array.

[0071] The specific technical solutions of embodiments of the storage array and storage unit of the present invention will be described in detail below with reference to the accompanying drawings.

[0072] The memory array includes memory cells 101 arranged in a regular array. Each memory cell 101 includes a device pillar 110, a gate structure 120, and a storage capacitor 130.

[0073] The device post 110 is used to form a switching device to control the opening and closing of the storage unit 101.

[0074] Specifically, the device pillar 110 is made of silicon. For example, the material of the device pillar 110 can be selected from monocrystalline silicon, polycrystalline silicon, or amorphous silicon. In other embodiments of the present invention, the material of the device pillar can also be other semiconductor materials. For example, the material of the device pillar can also be a group IV semiconductor material such as germanium or silicon-germanium; the material of the device pillar can also be a group III-V semiconductor material such as gallium arsenide; and even, the material of the device pillar can be a group II-VI semiconductor material. The material of the device pillar can be selected from any material suitable for forming a switching device.

[0075] The device post 110 has an axial direction and extends along the axial direction; along the axial direction of the device post 110, the device post 110 has a first end and a second end, wherein the first end is adapted to be connected to the storage capacitor 130; and the second end is adapted to be connected to the bit line BL.

[0076] like Figures 2 to 5 As shown, in some embodiments of the present invention, the device post 110 is cylindrical. Setting the device post 110 to a cylindrical shape minimizes sharp corner structures and avoids excessive concentration of electric field that could affect the performance of the memory cell. In a plane perpendicular to the axial direction of the device post 110, the end faces of both the first and second ends of the device post 110 are circular.

[0077] The gate structure 120 is suitable for controlling the channel conduction and cutoff of the switching device formed by the device pillars 110.

[0078] The device pillar 110 also has a circumferential direction around which its axial direction is the axis of rotation; the gate structure 120 surrounds the device pillar 110 circumferentially; in the memory cell, the channel in the device pillar 110 extends along an axial direction perpendicular to the device pillar 110; and the memory cell 101 is a gate all around (GAA) memory cell, and the gate structure 120 has strong control over the channel, which can effectively ensure the performance of the memory array.

[0079] In some embodiments of the present invention, the gate structure 120 includes a gate electrode 122 and a gate dielectric layer 121, the gate dielectric layer 121 being located between the gate electrode 122 and the device pillar 110. The gate electrode 122 is adapted to be electrically connected to an external circuit, and the gate dielectric layer 121 is adapted to provide electrical insulation between the gate electrode 122 and the device pillar 110.

[0080] In some embodiments, the gate structure 120 is one of a polysilicon gate structure and a metal gate structure. In some exemplary embodiments, the gate electrode 122 is made of polysilicon or a metal; the gate dielectric layer 121 is made of an oxide, for example, the oxide may be silicon oxide or a high-k gate dielectric layer.

[0081] In some embodiments of the present invention, the gate structure 120 extends along a predetermined direction in a plane perpendicular to the axial direction of the device pillar 110. The extending direction of the gate structure 120 is perpendicular to the axial direction of the device pillar 110. For example, ... Figures 2 to 5 As shown, the gate structure 120 extends along the first direction x.

[0082] In some embodiments, the gate electrode 122 extends from at least one side of the gate dielectric layer 121 along the axial direction of the device pillar 110. For example... Figures 2 to 5 As shown, along the axial direction of the device post 110, the gate electrode 122 extends from both sides of the gate dielectric layer 121; the dimension of the gate dielectric layer 121 along the axial direction of the device post 110 is larger than the dimension of the gate electrode 122 along the axial direction of the device post 110, and the gate electrode 122 is located only on the surface of the gate dielectric layer 121.

[0083] The storage capacitor 130 is suitable for storing data.

[0084] Along the axial direction of the device post 110, the storage capacitor 130 is located on one side of the first end of the device post 110. The device post 110 and the storage capacitor 130 are stacked along the axial direction of the device post 110; in a plane perpendicular to the axial direction of the device post 110, the projected area of ​​the storage cell is small.

[0085] In some embodiments of the present invention, the storage capacitor 130 is located on the end face of the first end of the device post 110; the surface of the storage capacitor 130 facing the device post 110 is in direct contact with the end face of the first end of the device post 110, so as to realize the electrical connection between the storage capacitor 130 and the device post 110.

[0086] like Figures 2 to 5 As shown, in some embodiments of the present invention, the storage capacitor 130 is cylindrical. Setting the storage capacitor 130 to a cylindrical shape minimizes sharp corner structures, preventing excessive electric field concentration that could cause tip discharge and affect the performance of the storage cell.

[0087] Continue to refer to Figure 2 Combined with reference Figures 3 to 5 The storage array has an array plane, and a plurality of storage cells 110 in the storage array are arranged in a regular array along the row and column directions in the array plane.

[0088] It should be noted that, Figures 2 to 5 In the array, the first direction x and the second direction y are both parallel to the array plane, and the first direction x and the second direction y are perpendicular to each other; the third direction z is perpendicular to the array plane. Here, the first direction x is the row direction, and the second direction z is the column direction.

[0089] It should also be noted that, such as Figures 2 to 5 In some embodiments shown, the row direction and the column direction are perpendicular to each other; in other embodiments of the present invention, the row direction and the column direction may intersect but not be perpendicular.

[0090] like Figures 2 to 5 As shown, in some embodiments of the example, the device pillar 110 is perpendicular to the array plane of the memory array; the axial direction of the device pillar 110 is perpendicular to the array plane; the array plane is a plane perpendicular to the axial direction of the device pillar 110; within the array plane of the memory array, the projected area of ​​the memory cell is small; and the memory density of the memory array is large.

[0091] It should be noted that the axial direction of the device pillar 110 is perpendicular to the array plane; the array plane is a plane perpendicular to the axial direction of the device pillar 110; and the circumferential direction of the device pillar 110 is parallel to the array plane. The gate structure 120 extends in a plane perpendicular to the axial direction of the device pillar 110, and the gate structure 120 extends in a plane parallel to the array plane.

[0092] In some embodiments, the gate electrodes 122 of the gate structures 120 in adjacent memory cells 101 along the extension direction are integrally connected; the gate electrodes 120 of the gate structures 120 in adjacent memory cells 101 along the perpendicular extension direction are separated.

[0093] In some exemplary embodiments, in the memory array, the gate structure 120 extends along the row direction, and the gate electrodes 122 of the gate structures 120 in adjacent memory cells 101 along the row direction are integrally connected, thereby enabling the simultaneous activation of the switching devices of multiple memory cells 101 in the same row under row selection; the gate electrodes 122 of the gate structures 120 in adjacent memory cells 101 along the column direction are separated, thereby enabling independent operation of the switching devices in a single memory cell 101 under row and column selection.

[0094] like Figures 2 to 5 As shown, in some embodiments, the gate structure 120 extends along a first direction x; the gate electrodes 122 of the gate structures 120 in adjacent memory cells 101 along the first direction x are integrally connected; and the gate electrodes 122 of the gate structures 120 in adjacent memory cells 101 along the second direction y are separated.

[0095] Specifically, the gate electrode 122 is elongated; within the array plane, the gate electrode 122 extends along the row direction (i.e., the first direction x) and spans the range of multiple device pillars 110; each device pillar 110 and the gate electrode 122 have a gate dielectric layer 121 between them.

[0096] Reference Figure 6 In some embodiments of the present invention, storage units 101 in adjacent rows are staggered along the row direction; storage units 101 in adjacent columns are staggered along the column direction. In the column direction, a storage unit 101 is located between two adjacent storage units 101 in an adjacent row; in the row direction, a storage unit 101 is located between two adjacent storage units 101 in an adjacent column. In the storage array, the storage units 101 are arranged in a hexagonal close-packed configuration; the higher the arrangement density of the storage units 101, the higher the storage density of the storage array.

[0097] like Figure 3 As shown, in the second direction y, a storage cell 101 is located between two adjacent storage cells 101 in an adjacent row; in the first direction x, a storage cell 101 is located between two adjacent storage cells 101 in an adjacent column.

[0098] Specifically, the storage unit has rows 1, 2, ..., m arranged sequentially along the column direction, where m is the number of rows of storage units in the storage array; the storage unit has columns 1, 2, ..., n arranged sequentially along the row direction, where n is the number of columns of storage units in the storage array; the storage units in the i-th row are staggered with the storage units in the (i+1)-th row along the row direction; the storage units in the j-th column are staggered with the storage units in the (j+1)-th column along the column direction, where i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to 1 and less than or equal to n.

[0099] like Figure 3 and Figure 6 As shown, storage cells 101b and 101d are located in the same row, and storage cells 101a and 101c are located in the adjacent rows of the rows where storage cells 101b and 101d are located; along the row direction, storage cells 101a and 101c are located between storage cells 101b and 101d. Storage cells 101a and 101c are located in the same column, and storage cells 101b and 101d are located in the column of the column where storage cells 101a and 101c are located; along the column direction, storage cells 101b and 101d are located between storage cells 101a and 101c.

[0100] Continue to refer to Figures 2 to 6In some embodiments of the present invention, the storage array further includes: a bit line BL (e.g., ... Figure 6 (As shown by the blue dashed line and the blue solid line), along the axial direction of the device post 110, the bit line is located on the side of the device post 110 near the second end, and in a plane perpendicular to the axial direction of the device post 110, the bit line extends along the column direction.

[0101] The bit line BL is electrically connected to the second end of the device post 110 to enable data operation within the storage cell. Along the axial direction of the device post 110, the bit line BL, the device post 110, and the storage capacitor 130 are stacked sequentially. The device post 110 is located between the bit line BL and the storage capacitor 130.

[0102] In some embodiments of the present invention, the bit line BL is electrically connected to the device post 110 through a via structure; a via structure is provided between the bit line BL and the second end of the device post 110, and the via structure is in contact with the end faces of both the bit line BL and the second end of the device post 110.

[0103] In other embodiments of the present invention, the bit line BL may also be in direct contact with the bit line; the bit line BL is located on the end face of the second end of the device post 110; the surface of the bit line BL is in direct contact with the surface of the device post 110.

[0104] Storage cells in the same column are connected to the same bit line BL. Within the array plane, the bit line BL runs along the column direction (i.e.,...). Figure 3 Extending in the second direction (y), along the row direction (i.e. Figure 3 The first direction (x) is arranged sequentially; along the column direction, the bit lines BL span multiple rows of the storage cells and are connected to multiple rows of the storage cells. Specifically, each storage cell has n bit lines BL, namely the 1st bit line, the 2nd bit line, ..., the nth bit line, and the n bit lines correspond one-to-one with the n columns of storage cells 101.

[0105] In some embodiments, the memory cells of adjacent columns are staggered along the column direction; in the array plane, the bit lines BL extend along the column direction; the memory cells of adjacent columns are staggered with two adjacent bit lines BL.

[0106] Specifically, a storage cell 101 in a column is connected to a bit line BL; storage cells 101 in adjacent columns and rows are connected to adjacent bit lines BL. Storage cells in odd-numbered rows (or even-numbered rows) of column a are connected to the a-th bit line (e.g., ...). Figure 6 (As shown by the solid blue line in the middle) are connected, and the storage cells of the even-numbered rows (or odd-numbered rows) in the (a+1)th column are connected to the (a+1)th bit line (as shown by the solid blue line in the middle). Figure 6 (as shown by the blue dashed line in the middle) are connected, where a is an integer greater than or equal to 1 and less than or equal to n-1.

[0107] like Figure 6 As shown, in some embodiments of the present invention, the storage array further includes: word lines WL (e.g. Figure 6 (As shown by the red dashed and red solid lines), in a plane perpendicular to the axis of the device column 110, the word line WL extends along the row direction; the memory cells 101 in the same row are connected to the same word line WL.

[0108] Within the array plane, the word line WL is along the row direction (i.e. Figure 3 Extending in the first direction x), along the column direction (i.e. Figure 3 The word lines (WL) are arranged sequentially in the second direction (y). Along the row direction, the word lines (WL) span multiple columns of the storage cells and are connected to all of the multiple columns of the storage cells. Specifically, each storage cell has m word lines (WL), namely the 1st word line, the 2nd word line, ..., the mth word line, and the m word lines correspond one-to-one with the m rows of storage cells.

[0109] like Figures 2 to 5 As shown, a word line WL is connected to the gate structure 122 of the memory cell 101 in the same row. Specifically, in the gate structure 120 of the memory cell in the same row, the gate electrode 122 extends along the row direction and is integrally connected; the word line WL is connected to the memory cell 101 in the same row through the integrally connected gate electrode 122.

[0110] In some embodiments, the storage cells 101 in adjacent rows are staggered along the row direction; in the array plane, the word lines WL extend along the row direction; the storage cells in adjacent rows are staggered with two adjacent word lines WL.

[0111] Specifically, the storage units of odd-numbered columns (or even-numbered columns) in row b are related to the root word line (e.g., ...). Figure 6 (As shown by the solid red line in the middle) are connected, and the storage units of the even-numbered columns (or odd-numbered columns) in the (b+1)th row are connected to the (b+1)th word line (as shown by the solid red line in the middle). Figure 6 (as shown by the red dashed line in the middle) are connected, where b is an integer greater than or equal to 1 and less than or equal to m-1.

[0112] Accordingly, the present invention also provides a method for controlling a storage array.

[0113] Reference Figure 6 The storage device includes: a storage array, wherein the storage array is the storage array of the present invention; the control method includes: applying a first voltage to a bit line while applying a second voltage to an adjacent bit line, wherein the second voltage is not equal to the first voltage.

[0114] like Figures 2 to 5As shown, the storage array is the storage array of the present invention. It is reasonable to refer to the aforementioned storage array for the specific technical solution of the storage array; therefore, the present invention will not repeat it here.

[0115] In the control method, different voltages are applied to adjacent bit lines BL at the same time so that the two adjacent bit lines BL play different roles: one bit line BL is used to operate on the connected memory cell 101 (e.g., one of read operation, write operation and erase operation), and the other bit line BL is used to shield the coupling effect of other bit lines BL.

[0116] The first voltage is suitable for operating the loaded storage cell 101. The first voltage is the operating voltage for operating the connected storage cell 101. The first voltage is determined based on the operation performed on the storage cell 101.

[0117] In some examples, during a read operation, the first voltage is a read voltage; in some examples, during a write operation, the first voltage is a write voltage; in some examples, during an erase operation, the first voltage is an erase voltage.

[0118] Specifically, the read voltage is suitable for reading data stored in the connected storage unit; the write voltage is suitable for writing data to the connected storage unit; and the erase voltage is suitable for erasing data stored in the connected storage unit.

[0119] The second voltage is suitable for preventing adjacent bit lines BL from being in a floating state so that the applied bit lines BL can serve as shielding coupling.

[0120] In some embodiments, the second voltage is a default voltage. Setting the second voltage as the default voltage avoids the adjacent bit line BL from being in a floating state, while eliminating the need to introduce a new voltage and make significant changes to the circuit to generate and apply the second voltage, effectively reducing the complexity of the implementation process.

[0121] For example, the second voltage is determined based on the voltage (Vcc) of the access circuit. For instance, the second voltage is half the voltage of the access circuit, Vcc / 2. In other embodiments of the invention, the second voltage may also be other fixed voltage values ​​to avoid the loaded bit line being in a floating state.

[0122] In some embodiments, the memory array includes a first bit line, a second bit line, ..., an nth bit line arranged sequentially, where n is the number of bit lines; the step of applying a first voltage to a bit line while applying a second voltage to an adjacent bit line includes: applying a first voltage to the (2p-1)th bit line while applying a second voltage to the 2pth bit line, where p is an integer greater than 0.

[0123] Specifically, to the 2p-1th bit line (e.g. Figure 6 A first voltage is applied (as shown by the solid blue line in the middle) to operate the connected memory cell 101; simultaneously, a voltage is applied to the 2p root bit line (as shown by the solid blue line in the middle). Figure 6 (As shown by the blue dashed line in the middle) A second voltage is applied to shield the coupling effect of other surrounding bit lines BL.

[0124] Continue to refer to Figure 6 In some specific embodiments, in the step of applying a first voltage to the 2p-1 bit line and applying a second voltage to the 2p bit line, the first voltage is applied to all 2p-1 bit lines while the second voltage is applied to all 2p bit lines.

[0125] Simultaneously applying a first voltage to all 2p-1 bit lines to operate on the corresponding connected memory cell 101, a second voltage is simultaneously applied to all 2p bit lines to ensure that the bit lines with the first voltage applied (such as...) Figure 6 The bit line shown by the solid blue line in the middle) and the bit line with the applied second voltage (such as...) Figure 6 The bit lines (shown by the blue dashed lines) are spaced apart, and there are bit lines with a second voltage applied between adjacent bit lines with the first voltage applied. The bit lines with the second voltage applied act as metal shields between adjacent bit lines with the first voltage applied, which can effectively reduce or even eliminate the coupling between adjacent bit lines with the first voltage applied.

[0126] In addition, in some embodiments, the step of applying a first voltage to a bit line and applying a second voltage to an adjacent bit line simultaneously includes: applying a first voltage to the 2qth bit line and applying a second voltage to the 2q-1th bit line simultaneously, where q is an integer greater than 0.

[0127] Specifically, to the 2q-1th bit line (e.g. Figure 6 A first voltage is applied (as shown by the blue dashed line in the middle) to operate the connected memory cell 101; simultaneously, a voltage is applied to the 2qth bit line (as shown by the dashed blue line in the middle). Figure 6 (As shown by the solid blue line) A second voltage is applied to shield the coupling effect of other surrounding bit lines BL.

[0128] In some specific embodiments, in the step of applying a first voltage to the 2q-1 bit line while simultaneously applying a second voltage to the 2q-1 bit line, the first voltage is applied to all 2q-1 bit lines while the second voltage is applied to all 2q-1 bit lines, similarly ensuring that the bit lines with the first voltage applied (such as...) Figure 6 The bit line shown by the blue dashed line) and the bit line with the applied second voltage (such as...) Figure 6 The bit lines (shown by the solid blue lines) are spaced apart, and the bit line with the second voltage acts as a metal shield between adjacent bit lines with the first voltage.

[0129] While applying a first voltage to all odd-numbered bit lines, a second voltage is applied to the even-numbered bit lines; while applying a second voltage to all even-numbered bit lines, a first voltage is applied to the odd-numbered bit lines. When the storage device is working, the bit lines operate in an odd-even interval mode, which can effectively shield the coupling effect between bit lines and effectively ensure the speed of read and write operations.

[0130] In some embodiments of the present invention, the storage array further includes multiple word lines WL (e.g., Figure 6 (As shown by the solid or dashed red line in the middle), specifically, the storage array also includes the first word line, the second word line, ..., the mth word line arranged in sequence, where m is the number of word lines; the control method also includes: applying a working voltage to a word line WL.

[0131] Apply operating voltage to the word line to enable row selection of memory cell 101.

[0132] Specifically, the time when the working voltage is applied to the word line WL is no later than the time when the first voltage is applied to the bit line and the second voltage is applied to the adjacent bit line: in some embodiments, the working voltage is applied to the word line WL while the first voltage is applied to the bit line and the second voltage is applied to the adjacent bit line; in other embodiments, the working voltage is applied to the word line WL, and then the first voltage is applied to the bit line and the second voltage is applied to the adjacent bit line.

[0133] In some embodiments, in the memory array, memory cells in adjacent rows are alternately connected to two adjacent word lines WL; and memory cells in adjacent columns are alternately connected to two adjacent bit lines BL.

[0134] When the storage array is working, it sends data to the 2c-1th word line (e.g., ...). Figure 6 When applying the operating voltage to activate the connected memory cell (as shown by the solid line in the middle), a first voltage is applied to all 2p-1 bit lines to activate them. A second voltage is applied to the 2p bit lines between the activated 2p-1 bit lines to provide metal shielding. A second voltage is applied to the 2c word line (as shown by the solid line in the middle). Figure 6(As shown by the dashed line in the middle) When the working voltage is applied to turn on the connected memory cell, a first voltage is applied to all the 2q bit lines to make all the 2q bit lines work. A second voltage is applied to the 2q-1 bit lines between the working 2q bit lines to provide a metal shielding effect.

[0135] Accordingly, the present invention also provides a storage device.

[0136] refer to Figure 6 The diagram shows a circuit structure schematic of an embodiment of the storage device of the present invention.

[0137] The storage device includes: a storage array, wherein the storage array is the storage array of the present invention; and a controller, which is adapted to apply a first voltage to a bit line while simultaneously applying a second voltage to an adjacent bit line, wherein the second voltage is not equal to the first voltage.

[0138] like Figures 2 to 5 As shown, the storage array is the storage array of the present invention. It is reasonable to refer to the aforementioned storage array for the specific technical solution of the storage array; therefore, the present invention will not repeat it here.

[0139] It should be noted that, in some embodiments, the controller is suitable for executing the various steps of the control method of the present invention. The specific technical solution of the controller can be found in the embodiments of the aforementioned control method.

[0140] The controller is connected to the bit line BL and applies voltage to the bit line BL to make the bit line BL work.

[0141] Specifically, the controller applies different voltages to adjacent bit lines BL at the same time, so that the two adjacent bit lines BL play different roles: one bit line BL is used to operate the connected memory cell 101 (e.g., one of read operation, write operation and erase operation), and the other bit line BL is used to shield the coupling effect of the other bit lines BL.

[0142] The first voltage is suitable for operating the loaded storage cell 101. The first voltage is the operating voltage for operating the connected storage cell 101. The first voltage is determined based on the operation performed on the storage cell 101.

[0143] In some examples, during a read operation, the first voltage is a read voltage; in some examples, during a write operation, the first voltage is a write voltage; in some examples, during an erase operation, the first voltage is an erase voltage.

[0144] Specifically, the read voltage is suitable for reading data stored in the connected storage unit; the write voltage is suitable for writing data to the connected storage unit; and the erase voltage is suitable for erasing data stored in the connected storage unit.

[0145] The second voltage is suitable for preventing adjacent bit lines BL from being in a floating state so that the applied bit lines BL can serve as shielding coupling.

[0146] In some embodiments, the second voltage is a default voltage. Setting the second voltage as the default voltage avoids the adjacent bit line BL from being in a floating state, while eliminating the need to introduce a new voltage and make significant changes to the circuit to generate and apply the second voltage, effectively reducing the complexity of the implementation process.

[0147] For example, the second voltage is determined based on the voltage (Vcc) of the access circuit. For instance, the second voltage is half the voltage of the access circuit, Vcc / 2. In other embodiments of the invention, the second voltage may also be other fixed voltage values ​​to avoid the loaded bit line being in a floating state.

[0148] Continue to refer to Figure 6 The controller uses a bit-line BL parity interval operation for control.

[0149] In some embodiments of the present invention, the memory array includes a first bit line, a second bit line, ..., an nth bit line arranged in sequence, where n is the number of bit lines; the controller applies a first voltage to the (2p-1)th bit line and applies a second voltage to the 2pth bit line, where p is an integer greater than 0.

[0150] like Figure 6 As shown, specifically, the controller includes: a first control element 141, which is connected to the bit line BL; the first control element 141 applies a first voltage to the 2p-1 bit line to operate the connected memory cell 101, and applies a second voltage to the 2p bit line to shield the coupling effect of other surrounding bit lines BL.

[0151] In some embodiments, the controller applies a first voltage to all 2p-1 bit lines while simultaneously applying a second voltage to all 2p bit lines. When simultaneously applying the first voltage to all 2p-1 bit lines to operate on the corresponding connected memory cell 101, the second voltage is simultaneously applied to all 2p bit lines so that the bit lines with the first voltage applied (e.g., ...) Figure 6 The bit line shown by the solid blue line in the middle) and the bit line with the applied second voltage (such as...) Figure 6The bit lines (shown by the blue dashed lines) are spaced apart, and there are bit lines with a second voltage applied between adjacent bit lines with the first voltage applied. The bit lines with the second voltage applied act as metal shields between adjacent bit lines with the first voltage applied, which can effectively reduce or even eliminate the coupling between adjacent bit lines with the first voltage applied.

[0152] For example, such as Figure 6 As shown, the controller has a first control element 141, which is connected to a plurality of bit lines BL; the first control element 141 simultaneously applies a first voltage to all bit lines 2p-1 and simultaneously applies a second voltage to all bit lines 2p.

[0153] Furthermore, in some embodiments, the controller applies a first voltage to the 2q-th bit line while simultaneously applying a second voltage to the 2q-1-th bit line, where q is an integer greater than 0. Specifically, as shown below... Figure 6 In some embodiments shown, the first control element 141 applies a first voltage to the 2q-1th bit line to operate the connected memory cell 101, while simultaneously applying a second voltage to the 2qth bit line to shield the coupling effect of other surrounding bit lines BL.

[0154] In some corresponding embodiments, the controller applies a first voltage to all 2q-th bit lines while simultaneously applying a second voltage to all 2q-1-th bit lines, similarly causing the bit lines applying the first voltage (such as...) to... Figure 6 The bit line shown by the blue dashed line) and the bit line with the applied second voltage (such as...) Figure 6 The bit lines (shown by the solid blue lines) are spaced apart, and the bit line with the second voltage acts as a metal shield between adjacent bit lines with the first voltage.

[0155] The controller applies a first voltage to all odd-numbered bit lines while applying a second voltage to even-numbered bit lines; the controller applies a second voltage to all even-numbered bit lines while applying a first voltage to odd-numbered bit lines; when the storage device is working, the bit lines operate in an odd-even interval mode, which can effectively shield the coupling effect between bit lines and effectively ensure the speed of read and write operations.

[0156] Continue to refer to Figure 6 In some embodiments of the present invention, the storage array further includes multiple word lines WL (e.g., Figure 6 (As shown by the solid or dashed red line in the middle), specifically, the storage array also includes the first word line, the second word line, ..., the mth word line arranged in sequence, where m is the number of word lines; the controller applies a working voltage to the word line WL to perform row selection on the storage cell 101.

[0157] like Figure 6As shown, specifically, the controller further includes: a second control element 142, which is connected to the word line WL; the second control element 142 applies a working voltage to the word line to enable the connected memory cell, so as to perform row selection on the memory cell 101.

[0158] Specifically, the second control element 142 applies a working voltage to the word line WL at a time no later than the time the first control element 141 applies a first voltage to the bit line BL and applies a second voltage to the adjacent bit line BL. In some embodiments, the second control element 142 applies a working voltage to the word line WL while the first control element 141 applies a first voltage to the bit line and applies a second voltage to the adjacent bit line. In other embodiments, the second control element 142 applies a working voltage to the word line WL, and then the first control element 141 applies a first voltage to the bit line and applies a second voltage to the adjacent bit line.

[0159] In some embodiments, in the memory array, memory cells in adjacent rows are alternately connected to two adjacent word lines WL; and memory cells in adjacent columns are alternately connected to two adjacent bit lines BL.

[0160] When the storage array is working, it sends data to the 2c-1th word line (e.g., ...). Figure 6 When applying the operating voltage to activate the connected memory cell (as shown by the solid line in the middle), a first voltage is applied to all 2p-1 bit lines to activate them. A second voltage is applied to the 2p bit lines between the activated 2p-1 bit lines to provide metal shielding. A second voltage is applied to the 2c word line (as shown by the solid line in the middle). Figure 6 (As shown by the dashed line in the middle) When the working voltage is applied to turn on the connected memory cell, a first voltage is applied to all the 2q bit lines to make all the 2q bit lines work. A second voltage is applied to the 2q-1 bit lines between the working 2q bit lines to provide a metal shielding effect.

[0161] In addition, the present invention also provides a method for manufacturing a storage device.

[0162] It should be noted that the manufacturing method described herein is suitable for manufacturing the storage device of the present invention. Specific embodiments of the manufacturing method can be found in the aforementioned embodiments of the storage device.

[0163] refer to Figures 7 to 22 The diagram shows a structural schematic of the intermediate structures of each step in some embodiments of the manufacturing method of the storage device of the present invention.

[0164] refer to Figure 7 Combined with reference Figures 8 to 11 ,in Figure 9 yes Figure 8A top view of the structure along direction D in an embodiment of the manufacturing method of the storage device shown; Figure 10 yes Figure 9 A schematic cross-sectional view of the structure at positions E1 and E2 in an embodiment of the manufacturing method of the storage device shown; Figure 11 yes Figure 9 A schematic cross-sectional view of the structure at positions F1 and F2 in an embodiment of the manufacturing method of the storage device shown.

[0165] First, a device post 110 is formed, the device post 110 having a second end and a first end that are opposite to each other along the axial direction of the device post 110.

[0166] The device post 110 is used to form a switching device to control the opening and closing of the memory cell.

[0167] In some embodiments of the present invention, the step of forming the device pillar 110 includes: as follows Figure 7 As shown, a substrate 101 is provided; as Figures 8 to 10 As shown, the substrate 101 is etched (e.g. Figure 7 As shown), a substrate 102 is formed and a device pillar 110 protruding from the front side of the substrate 102.

[0168] The substrate 101 is used to provide a process foundation and mechanical support.

[0169] Specifically, the material of the substrate 101 is silicon. For example, the material of the substrate 101 can be selected from monocrystalline silicon, polycrystalline silicon, or amorphous silicon. In other embodiments of the present invention, the material of the substrate can also be other semiconductor materials. For example, the material of the substrate can also be a group IV semiconductor material such as germanium or silicon-germanium; the material of the substrate can also be a group III-V semiconductor material such as gallium arsenide; and even, the material of the substrate can be a group II-VI semiconductor material. The material of the substrate can be selected from any material suitable for forming a switching device.

[0170] The step of etching the substrate 101 includes: forming a patterned layer (not shown in the figure) on one surface of the substrate 101; using the patterned layer as a mask, etching the substrate 101 to form the substrate 102 and the device pillar 110.

[0171] The graphical layer is suitable for defining the size and position of the device pillar 110.

[0172] The patterned layer can be a patterned photoresist layer, which can be formed by exposing and developing spin-coated photoresist; the patterned layer can also be a hard mask layer, which can be formed by etching a deposited mask material layer.

[0173] In the step of etching the substrate 101, a portion of the substrate 101 is etched, and the remaining thickness of the substrate 101 that is not etched is suitable for forming the substrate 102. The remaining substrate 101 after etching is suitable for forming the device pillar 110.

[0174] The substrate 102 is adapted to provide mechanical support during the process; the device pillar 110 is adapted to form a switching device to control the opening and closing of the memory cell.

[0175] Both the substrate 102 and the device pillar 110 are etched from the substrate 101, and the materials of the substrate 102 and the device pillar 110 correspond to the material of the substrate 101. In some exemplary embodiments, the material of the substrate 101 is silicon; the material of the substrate 102 and the device pillar 110 is also silicon.

[0176] like Figure 8 As shown, the first direction x and the second direction y are both parallel to the front surface of the substrate 102; the third direction z is perpendicular to the front surface of the substrate 102. The device post 110 protrudes from the front surface of the substrate 102, and the axial direction of the device post 110 is the third direction z. For example, the axial direction of the cylindrical device post 110 is parallel to the generatrix direction of the cylinder, and the generatrix direction of the device post 110 is perpendicular to the front surface of the substrate 102.

[0177] The device post 110 protrudes from the front side of the substrate 102. The first end and the second end of the device post 110 are opposite ends along the axial direction. The second end is connected to the front side of the substrate 102, and the first end is away from the substrate 102.

[0178] like Figures 9 to 11 As shown, in some embodiments, in the step of forming device pillars 110, a plurality of device pillars 110 are formed on the front side of the substrate 102, and the plurality of device pillars 110 are arranged in a regular array on the front side of the substrate 102; the front side of the substrate 102 is parallel to the array plane of the memory array; the first direction x and the second direction y are both parallel to the array plane; the third direction z is perpendicular to the array plane; the axial direction of the device pillars 110 is perpendicular to the array plane.

[0179] For example, the first direction x is the row direction of a plurality of device pillars 110 arranged in a regular array, and the second direction y is the column direction of a plurality of device pillars 110 arranged in a regular array.

[0180] It should be noted that, Figures 9 to 11In some embodiments shown, the first direction x and the second direction y are perpendicular to each other; that is, in the multiple device pillars 110 arranged in a regular array, the row direction and the column direction are perpendicular to each other. In other embodiments of the present invention, the row direction and the column direction may only intersect and are not perpendicular.

[0181] like Figures 9 to 11 As shown, in some embodiments of the present invention, the device posts 110 in adjacent rows are staggered along the row direction; the device posts 110 in adjacent columns are staggered along the column direction, so that the plurality of device posts 110 are arranged in a hexagonal close-packed arrangement.

[0182] Specifically, the multiple device columns 110 arranged in a regular array have rows 1, 2, ..., m arranged sequentially along the column direction, where m is the number of rows of the device columns 110; the multiple device columns 110 arranged in a regular array have columns 1, 2, ..., n arranged sequentially along the row direction, where n is the number of columns of the device columns 110; the device columns 110 in the i-th row are alternately arranged with the device columns 110 in the (i+1)-th row along the row direction; the device columns 110 in the j-th column are alternately arranged with the device columns 110 in the (j+1)-th column along the column direction, where i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to 1 and less than or equal to n.

[0183] like Figure 9 As shown, device pillars 110b and 110d are located in the same row, and device pillars 110a and 110c are located in the adjacent rows of the rows containing device pillars 110b and 110d; along the row direction, device pillars 110a and 110c are located between device pillars 110b and 110d. Device pillars 110a and 110c are located in the same column, and device pillars 110b and 110d are located in the column containing device pillars 110a and 110c; along the column direction, device pillars 110b and 110d are located between device pillars 110a and 110c.

[0184] It should be noted that, Figure 10 and Figure 11 The adjacent row of device columns 110 is shown in dashed lines.

[0185] It should also be noted that the arrangement of the device pillars 110 is consistent with the arrangement of the storage cells 101, and the arrangement of the device pillars 110 can be referred to the aforementioned embodiment of the storage array.

[0186] refer to Figure 12 Combined with reference Figure 13 ,in Figure 13 yes Figure 12 A top view of the structure along the D2 direction; Figure 13 and Figure 9 The directions shown are consistent.

[0187] After the device pillar 110 is formed, a gate structure 120 is formed around the device pillar 110 in the circumferential direction. Along the axial direction of the device pillar 110, the gate structure 120 is separated from both the second end and the first end.

[0188] The circumferential direction of the device pillar 110 lies in a plane perpendicular to its axial direction. The axial direction of the device pillar 110 is perpendicular to the front surface of the substrate 102. The circumferential direction of the device pillar 110 is parallel to the front surface of the substrate 102. The circumferential direction of the device pillar 110 is parallel to the array plane of a plurality of device pillars 110 arranged in a regular array.

[0189] The gate structure 120 surrounds the device pillar 110 in a plane parallel to the array plane. The memory cell is a gate all around (GAA) memory cell. The gate structure 120 has strong control over the channel, which can effectively ensure the performance of the memory array. The channel in the device pillar 110 extends along the third direction z of the array plane of multiple device pillars 110 arranged in a regular array. Within the array plane, the area of ​​the formed memory cell is small, which can effectively improve the storage density.

[0190] In some embodiments of the present invention, the step of forming a gate structure 120 surrounding the device pillar 110 in the circumferential direction includes: forming a gate dielectric layer 121 surrounding the device pillar 110 in the circumferential direction; and forming a gate electrode 122 on the gate dielectric layer 121.

[0191] In some embodiments, the gate structure 120 is one of a polysilicon gate structure and a metal gate structure. In some exemplary embodiments, the gate electrode 122 is made of polysilicon or a metal; the gate dielectric layer 121 is made of an oxide, for example, the oxide may be silicon oxide or a high-k gate dielectric layer.

[0192] It should be noted that in the step of forming the gate structure 120, the corresponding material is patterned based on the shape and distribution of the gate structure 120; the shape and distribution of the formed gate structure 120 can be referred to the foregoing embodiments.

[0193] In some embodiments of the present invention, the gate structure 120 extends along a predetermined direction in a plane parallel to the substrate 102. The axial direction of the device pillars 110 is perpendicular to the array plane of the plurality of device pillars 110 arranged in a regular array, and the gate structure 120 extends along a predetermined direction in the array plane of the plurality of device pillars 110 arranged in a regular array.

[0194] Specifically, such as Figure 12 and Figure 13As shown, the gate electrode 122 is elongated; in the array plane of multiple device pillars 110 arranged in a regular array, the gate electrode 122 extends along the row direction (i.e., the first direction x) and spans the range of the distribution of multiple device pillars 110; each device pillar 110 and the gate electrode 122 have a gate dielectric layer 121 between them.

[0195] In some embodiments, the gate electrode 122 extends from at least one side of the gate dielectric layer 121 along the axial direction of the device pillar 110. For example... Figures 2 to 5 As shown, along the axial direction of the device pillar 110, the gate electrode 122 extends from both sides of the gate dielectric layer 121; along the third direction z, the size of the gate dielectric layer 121 is larger than the size of the gate electrode 122, and the gate electrode 122 is located only on the surface of the gate dielectric layer 121.

[0196] like Figure 12 As shown, along the axial direction (i.e., the third direction z) of the device pillar 110, the gate structure 120 is separated from both the first and second ends of the device pillar 110.

[0197] In some embodiments of the example, the manufacturing method further includes: after forming the device pillar 110 and before forming the gate structure 120, forming a first dielectric layer 103 on the substrate 102, the first dielectric layer 103 covering a portion of the sidewall of the device pillar 110 near the substrate 102; in the step of forming the gate structure 120, the gate structure 120 is formed on the first dielectric layer 103.

[0198] The first dielectric layer 103 is used to achieve electrical insulation between adjacent device pillars 110.

[0199] Specifically, the material of the first dielectric layer 103 is a dielectric material; for example, the material of the first dielectric layer 103 can be a dielectric material such as silicon oxide, and the first dielectric layer 103 can also be a low-k dielectric material, or even an ultra-low-k dielectric material.

[0200] For example, the step of forming the first dielectric layer 103 includes: forming a dielectric material on the substrate 102, the dielectric material filling between adjacent device pillars 110; removing a portion of the dielectric material to expose a portion of the surface of the device pillars 110, thereby forming the first dielectric layer 103.

[0201] It should be noted that, Figure 13 The first dielectric layer 103 is omitted; only a portion of the structure is shown for clarity.

[0202] refer to Figure 14 Combined with reference Figure 15 ,in Figure 13 yes Figure 12 A top view of the structure along the D3 direction; Figure 15 and Figure 13 The directions shown are consistent.

[0203] After the gate structure 120 is formed, a storage capacitor 130 is formed on the side of the device post 110 close to the first end along the axial direction of the device post 110, and the storage capacitor 130 is electrically connected to the first end.

[0204] The device pillar 110 and the storage capacitor 130 are stacked along a third direction z perpendicular to the front side of the substrate 102; the device pillar 110 is located between the storage capacitor 130 and the substrate 102.

[0205] In some specific embodiments, in the step of forming the storage capacitor 130, the storage capacitor 130 is formed on the end face of the first end of the device post 110. The surface of the storage capacitor 130 facing the device post 110 is in direct contact with the end face of the first end of the device post 110 to achieve an electrical connection between the storage capacitor 130 and the device post 110.

[0206] Continue to refer to Figure 14 and Figure 15 In some embodiments of the present invention, the manufacturing method further includes: after forming the storage capacitor 130, forming a second dielectric layer (not shown in the figure).

[0207] The second dielectric layer is suitable for achieving electrical insulation between adjacent memory cells.

[0208] The second dielectric layer fills the space between adjacent device pillars 110 and adjacent storage capacitors 130, and exposes the storage capacitors 130. The top surface of the second dielectric layer is flush with the end face of the storage capacitor 103 facing away from the substrate 102.

[0209] Specifically, the material of the second dielectric layer is a dielectric material; for example, the material of the second dielectric layer can be a dielectric material such as silicon oxide, and the first dielectric layer 103 can also be a low-k dielectric material, or even an ultra-low-k dielectric material.

[0210] In some embodiments, a first dielectric layer 103 (e.g., ...) is also formed on the substrate 102. Figure 12 (As shown); in the step of forming the second dielectric layer, the second dielectric layer is formed on the first dielectric layer 103. For example, the material of the second dielectric layer may be the same as the material of the first dielectric layer 103.

[0211] For example, the step of forming the second dielectric layer includes: forming a dielectric material on the substrate 102, the dielectric material filling between adjacent storage capacitors 130, the dielectric material also covering the end face of the storage capacitor 130 away from the substrate 102; removing a portion of the thickness of the dielectric material to form the second dielectric layer such that the top surface of the second dielectric layer is flush with the end face of the storage capacitor 103 facing away from the substrate 102.

[0212] It should be noted that, Figure 14 and Figure 15 The first dielectric layer 103 and the second dielectric layer are omitted; only a portion of the structure is shown for clarity.

[0213] refer to Figures 16 to 22 ,in Figure 17 yes Figure 16 A top view of the structure along the D4 direction; Figure 18 yes Figure 17 A schematic diagram of the cross-sectional structure along line E3E4 in the middle; Figure 19 yes Figure 17 Schematic diagram of the cross-sectional structure at positions F3 and F4 along the middle; Figure 21 yes Figure 18 Cross-sectional structural diagrams at the same location; Figure 22 yes Figure 19 A schematic diagram of the cross-sectional structure at the same location.

[0214] In some embodiments of the present invention, the manufacturing method further includes: forming a bit line BL (e.g., on the side of the device post 110 near the second end) on the side of the post 110. Figures 3 to 5 As shown in the figure, the bit line BL is electrically connected to the second end of the device post 110.

[0215] In some embodiments, in the step of forming a bit line BL on the side of the device post 110 near the second end, a bit line BL is formed that directly contacts the second end of the device post 110; the bit line BL directly contacts the end face of the second end of the device post 110.

[0216] like Figures 16 to 22 In some embodiments shown, the manufacturing method further includes removing the substrate 102 to expose the second end of the device post 110 before forming a bit line BL on the side of the device post 110 near the second end.

[0217] Specifically, before forming the bit line BL on the side of the device post 110 near the second end, the substrate 102 is removed to expose the end face of the second end of the device post 110; the bit line BL is formed directly on the end face of the second end of the device post 110.

[0218] like Figures 16 to 19 As shown, in some embodiments of the present invention, the step of removing the substrate 102 to expose the second end of the device pillar 110 includes: after forming the storage capacitor 130, inverting the structure to expose the back side of the substrate 102, wherein the back side of the substrate 102 is disposed opposite to the front side of the substrate 102.

[0219] It should be noted that in some embodiments, the manufacturing method further includes: after forming the storage capacitor 130, forming a second dielectric layer; in the step of inverting the structure to expose the back side of the substrate 102, after forming the second dielectric layer, inverting the structure to expose the back side of the substrate 102.

[0220] It should also be noted that, Figure 16 and Figure 17 The first dielectric layer 103 and the second dielectric layer are omitted; only a portion of the structure is shown for clarity.

[0221] like Figures 20 to 22 In some embodiments shown, the substrate 102 is removed (e.g., Figures 16 to 19 As shown, the step of exposing the second end of the device post 110 further includes: after inverting the structure to expose the back side of the substrate 102, removing the substrate 102 along the back side of the substrate 102.

[0222] Specifically, the step of removing the substrate 102 along the back side of the substrate 102 includes: thinning the substrate 102 by grinding; etching the thinned substrate 102 until the end face of the second end of the device pillar 110 is exposed.

[0223] In some embodiments, a first dielectric layer 103 is also formed on the substrate 102 between adjacent device pillars 110; in the step of removing the substrate 102 along the back side of the substrate 102, the substrate 102 is removed to expose the first dielectric layer 103, and the surface of the exposed first dielectric layer 103 is flush with the end face of the second end of the device pillar 110.

[0224] Reference Figures 3 to 5 After exposing the end face of the second end of the device post 110, the bit line BL is formed. Specifically, in the step of forming the bit line BL, the bit line BL is formed on the end face of the exposed second end.

[0225] In some of the example embodiments, such as Figure 3 As shown, the device pillars in adjacent columns are staggered along the column direction; comparison Figure 4 and Figure 5 It can be seen that the second end of the device post 110 in the adjacent column is in contact with the adjacent bit line BL, and the device post 110 in the adjacent column is in contact with the bit line BL adjacent along the row direction.

[0226] It should be noted that in other embodiments of the present invention, the bit line is electrically connected to the second end of the device post 110 through a via structure; the manufacturing method includes: forming a via structure electrically connected to the second end before forming the bit line on the side of the device post near the second end; in the step of forming the bit line, a bit line electrically connected to the via structure is formed.

[0227] In summary, in the aforementioned memory cell, the gate structure surrounds the device pillar along the axial direction, and the storage capacitor is located on one side of the first end of the device pillar along the axial direction and connected to the first segment. The gate structure completely surrounds the device pillar, effectively ensuring the gate structure's control over the channel; furthermore, in the memory cell, the channel in the device pillar extends axially; and in the plane perpendicular to the axial direction of the device pillar, the area of ​​the memory cell is small, effectively increasing the storage density of the memory array including the memory cell.

[0228] Furthermore, in the storage array, the storage cells in adjacent rows are staggered along the column direction. This staggered arrangement of adjacent rows of storage cells, with the cells densely packed in a plane perpendicular to the axis of the device pillars, effectively increases the distribution density of the storage cells. This increased storage density also provides the hardware basis for an odd-even interval operating mode, maximizing storage density, minimizing wasted area, and achieving a balance between read / write speed and storage density.

[0229] Furthermore, adjacent column storage cells are connected to adjacent bit lines along the row direction; while applying a first voltage to a bit line, a second voltage is applied to adjacent bit lines, the second voltage being unequal to the first voltage. During operation, the storage device applies unequal voltages to adjacent bit lines; a bit line is applied with the first voltage for reading and writing data, while adjacent bit lines are applied with the second voltage to shield coupling capacitors. This odd-even bit line interval operating mode effectively shields the coupling between bit lines, ensuring efficient read and write operations.

[0230] In addition, the second voltage is the default voltage, which is Vcc / 2. This solution can be implemented without making major modifications to the internal circuitry of the storage device, effectively reducing the difficulty of implementation.

[0231] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A storage unit, characterized in that, include: A device post having a first end and a second end opposite to each other along the axial direction of the device post; A gate structure that surrounds the device pillars circumferentially; A storage capacitor is located along the axial direction of the device post, on the side of the device post closer to the first end, and is electrically connected to the first end.

2. The storage unit as claimed in claim 1, characterized in that, The device pillars are cylindrical; the storage capacitor is cylindrical.

3. The storage unit as described in claim 1, characterized in that, The gate structure includes a gate electrode and a gate dielectric layer, wherein the gate dielectric layer is located between the gate electrode and the device pillar.

4. The storage unit as described in claim 3, characterized in that, Along the axial direction of the device pillar, at least one side of the gate dielectric layer extends out of the gate electrode.

5. The storage unit as described in claim 3, characterized in that, The gate electrode is made of either polycrystalline silicon or a metal; the gate dielectric layer is made of an oxide.

6. The storage unit as claimed in claim 1, characterized in that, The gate structure extends along a predetermined direction in a plane perpendicular to the axial direction of the device pillar.

7. The storage unit as claimed in claim 1, characterized in that, The second end is electrically connected to the bit line through a via structure; Alternatively, the second end may be in direct contact with the bit line.

8. The storage unit as claimed in claim 1, characterized in that, The storage capacitor is located on the end face of the first end.

9. A storage array, characterized in that, include: The storage cell, as described in any one of claims 1 to 8, comprises a plurality of storage cells arranged in an array in a plane perpendicular to the axial direction of the device column.

10. The storage array as claimed in claim 9, characterized in that, The gate electrodes of the gate structure in adjacent memory cells along the row direction are connected as a single unit.

11. The storage array as claimed in claim 9, characterized in that, In adjacent memory cells along the column direction, the gate electrode phases of the gate structure are separated.

12. The storage array as claimed in claim 9, characterized in that, The storage cells of adjacent rows are staggered along the row direction; The storage cells of adjacent columns are staggered along the column direction.

13. The storage array as described in claim 9 or 12, characterized in that, It also includes: a bit line along the axial direction of the device post, the bit line being located on the side of the device post near the second end, and extending along the column direction in a plane perpendicular to the axial direction of the device post; Storage cells in the same column are connected to the same bit line.

14. The storage array as claimed in claim 13, characterized in that, The storage cells of adjacent columns are interleaved with the two adjacent bit lines.

15. The storage array as described in claim 9 or 12, characterized in that, Also includes: The word line extends along the row direction in a plane perpendicular to the axial direction of the device column; Storage cells in the same row are connected to the same word line.

16. The storage array as claimed in claim 15, characterized in that, The storage cells in adjacent rows are interleaved with the two adjacent word lines.

17. A method for controlling a storage array, characterized in that, The storage array is as described in any one of claims 9 to 16; The control method includes: applying a first voltage to a bit line while simultaneously applying a second voltage to an adjacent bit line, wherein the second voltage is not equal to the first voltage.

18. The control method as described in claim 17, characterized in that, The storage array includes a first bit line, a second bit line, ..., an nth bit line arranged sequentially, where n is the number of bit lines; The step of applying a first voltage to a bit line and simultaneously applying a second voltage to an adjacent bit line includes: applying a first voltage to the (2p-1)th bit line and simultaneously applying a second voltage to the 2pth bit line, where p is an integer greater than 0.

19. The control method as described in claim 18, characterized in that, In the step of applying a first voltage to the 2p-1 bit line and applying a second voltage to the 2p bit line, the first voltage is applied to all 2p-1 bit lines while the second voltage is applied to all 2p bit lines.

20. The control method as described in claim 18, characterized in that, The step of applying a first voltage to a bit line and applying a second voltage to an adjacent bit line further includes: applying a first voltage to the 2qth bit line and applying a second voltage to the 2q-1th bit line, where q is an integer greater than 0.

21. The control method as described in claim 20, characterized in that, In the step of applying a first voltage to the 2q-1 bit line while simultaneously applying a second voltage to the 2q-1 bit line, the first voltage is applied to all 2q-1 bit lines at the same time as the second voltage is applied to all 2q-1 bit lines.

22. The control method as described in claim 17, characterized in that, During a read operation, the first voltage is the read voltage; during a write operation, the first voltage is the write voltage; during an erase operation, the first voltage is the erase voltage.

23. The control method as described in claim 17, characterized in that, The second voltage is the default voltage.

24. A storage device, characterized in that, include: A storage array, as described in any one of claims 9 to 16; A controller, which is adapted to apply a first voltage to a bit line while simultaneously applying a second voltage to an adjacent bit line, the second voltage being unequal to the first voltage.

25. The storage device as claimed in claim 24, characterized in that, The storage array includes a first bit line, a second bit line, ..., an nth bit line arranged sequentially, where n is the number of bit lines; The controller is adapted to apply a first voltage to the 2p-1 bit line while simultaneously applying a second voltage to the 2p bit line, where p is an integer greater than 0.

26. The storage device as claimed in claim 25, characterized in that, The controller applies a first voltage to all bit lines 2p-1 and a second voltage to all bit lines 2p.

27. The storage device as claimed in claim 24, characterized in that, The controller is also adapted to apply a first voltage to the 2q-1 bit line while simultaneously applying a second voltage to the 2q-1 bit line, where q is an integer greater than 0.

28. The storage device as claimed in claim 27, characterized in that, The controller applies a first voltage to all 2q-th bit lines while simultaneously applying a second voltage to all 2q-1-th bit lines.

29. The storage device as claimed in claim 24, characterized in that, During a read operation, the first voltage is the read voltage; during a write operation, the first voltage is the write voltage; during an erase operation, the first voltage is the erase voltage.

30. The storage device as claimed in claim 24, characterized in that, The second voltage is the default voltage.

31. A method for manufacturing a storage device, characterized in that, include: A device post is formed, the device post having a second end and a first end that are opposite to each other along the axial direction of the device post; A gate structure is formed that surrounds the device pillars in the circumferential direction; A storage capacitor is formed on the side of the device post near the first end along the axial direction of the device post, and the storage capacitor is electrically connected to the first end.

32. The manufacturing method as described in claim 31, characterized in that, The steps for forming device pillars include: Provide a base; The substrate is etched to form a substrate and device pillars protruding from the front side of the substrate.

33. The manufacturing method as described in claim 31, characterized in that, The steps of forming a gate structure that surrounds the device pillars circumferentially include: A gate dielectric layer is formed around the device pillars in the circumferential direction; A gate electrode is formed on the gate dielectric layer.

34. The manufacturing method as described in claim 31, characterized in that, Also includes: A bit line is formed on the side of the device post near the second end, and the bit line is electrically connected to the second end of the device post.

35. The manufacturing method as described in claim 34, characterized in that, In the step of forming a bit line on the side of the device post near the second end, a bit line is formed that contacts the second end of the device post; Alternatively, the manufacturing method may further include forming a via structure electrically connected to the second end before forming a bit line on the side of the device post near the second end.

36. The manufacturing method as described in claim 34, characterized in that, In the step of forming the device pillar, the device pillar protrudes from the front side of the substrate; The manufacturing method further includes removing the substrate to expose the second end before forming a bit line on the side of the device post near the second end.

37. The manufacturing method as described in claim 36, characterized in that, The step of removing the substrate to expose the second end includes: removing the substrate along the back side of the substrate, the back side being disposed opposite to the front side.

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