Semiconductor memory device with inductor

Abstract

The invention discloses a semiconductor memory device having an inductor. The semiconductor memory device includes: a substrate; a peripheral structure including a plurality of lower wiring layers vertically stacked on the substrate; a memory structure disposed on the peripheral structure and including a memory cell array in the first region; an input / output pad disposed over the memory structure in the second region; and an inductor disposed in at least one of the plurality of lower wiring layers and vertically overlapping the input / output pad.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0116014, filed with the Korean Intellectual Property Office on August 28, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to a semiconductor technology, and more specifically, to a semiconductor memory device having an inductor. Background Technology

[0004] As the operating speed of semiconductor memory devices increases, so does the data rate. Increasing the data rate while maintaining channel characteristics degrades signal integrity (SI) characteristics; therefore, measures to improve SI characteristics are being investigated. Summary of the Invention

[0005] Various embodiments of this disclosure relate to a semiconductor memory device having an inductor.

[0006] In an embodiment, the semiconductor memory device may include: a substrate; a peripheral structure including a plurality of lower wiring layers vertically stacked on the substrate; a memory structure disposed on the peripheral structure and including a memory cell array in a first region; input / output pads disposed above the memory structure in a second region; and an inductor disposed in at least one of the plurality of lower wiring layers and vertically overlapping the input / output pads.

[0007] In an embodiment, the semiconductor memory device may include: a substrate; a peripheral structure including a first lower wiring layer located above the substrate and a second lower wiring layer located above the first lower wiring layer; a memory structure disposed on the peripheral structure and including a three-dimensional memory cell array in a first region; input / output pads disposed in a second region above the memory structure; a first inductor disposed in the first lower wiring layer to vertically overlap with the input / output pads; and a second inductor disposed in the second lower wiring layer to vertically overlap with the input / output pads.

[0008] According to embodiments of this disclosure, by arranging the inductor to overlap with the input / output pads, the increase in layout area due to the presence of the inductor can be suppressed.

[0009] According to embodiments of this disclosure, signal integrity (SI) characteristics can be improved without increasing the layout area by arranging inductors to overlap with input / output pads and utilizing inductors to increase high-frequency gain and improve cutoff frequency. Attached Figure Description

[0010] Figure 1 This is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure.

[0011] Figure 2 It is shown Figure 1 Plan view of input / output pads and inductors.

[0012] Figure 3 This is a block diagram illustrating a system including a semiconductor memory device according to an embodiment of the present disclosure.

[0013] Figure 4 and Figure 5 This is a circuit diagram illustrating an input buffer of a semiconductor memory device according to an embodiment of the present disclosure.

[0014] Figure 6 and Figure 7 This is a circuit diagram illustrating the terminal circuitry of a semiconductor memory device according to an embodiment of the present disclosure.

[0015] Figure 8 This is a circuit diagram illustrating an amplifier circuit of a semiconductor memory device according to an embodiment of the present disclosure.

[0016] Figure 9 This is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure.

[0017] Figure 10 and Figure 11 This is a circuit diagram illustrating an input buffer of a semiconductor memory device according to an embodiment of the present disclosure.

[0018] Figure 12 and Figure 13 This is a circuit diagram illustrating the terminal circuitry of a semiconductor memory device according to an embodiment of the present disclosure.

[0019] Figure 14 This is a circuit diagram illustrating an amplifier circuit of a semiconductor memory device according to an embodiment of the present disclosure. Detailed Implementation

[0020] Embodiments of this disclosure are described in detail with reference to the accompanying drawings. Specific structural or functional descriptions of the embodiments are provided as examples to illustrate the concepts disclosed in this application. Examples or embodiments based on the concepts may be implemented in various forms, and the scope of this disclosure is not limited to the examples or embodiments described in this specification.

[0021] The shaded lines throughout the accompanying figures indicate corresponding or similar areas between figures, rather than indicating material related to those areas.

[0022] When one element is identified as “connected” or “coupled” to another element, these elements can be directly connected or coupled, or connected or coupled through one or more intermediate elements. When two elements are identified as “directly connected” or “directly coupled”, one element is directly connected or coupled to the other element without any intermediate elements.

[0023] When one element is identified as being "above", "over", "below", or "under" another element, these elements can be in direct contact with each other, or an intermediate element can be placed between these elements.

[0024] Terms such as “vertical,” “parallel,” “top,” “bottom,” “above,” “below,” “lower,” “lower part,” “above,” “upper,” “side,” “upper part,” “topmost,” “lowest,” “front,” “back,” “left,” “right,” “column,” “row,” and “layer,” as well as other terms that suggest relative spatial relationships or directions, are used only for ease of description or reference to the accompanying drawings and are not intended to limit the scope. Within the scope of this disclosure, other spatial relationships or directions may exist that are not shown in the drawings or described in the specification.

[0025] Terms such as “first” and “second” are used to distinguish various elements and do not imply the size, order, priority, number, or importance of the elements. For example, in one example, the first element may be referred to as the second element, while in another example, the second element may be referred to as the first element.

[0026] In the specification, when an element included in an embodiment is described in the singular, the element may be interpreted as including multiple elements that perform the same or similar functions.

[0027] Figure 1 This is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure.

[0028] Reference Figure 1 The semiconductor memory device 100 includes a substrate 10, a peripheral structure 20, a memory structure 30, input / output pads 40, and an inductor 50.

[0029] The inductor 50 is disposed in the fifth lower wiring layer UM5 of the peripheral structure 20 and vertically overlaps with the input / output pads 40.

[0030] The semiconductor memory device 100 includes a first region R1 and a second region R2. In one embodiment, the second region R2 may be an edge region of the semiconductor memory device 100. In another embodiment, the second region R2 may be a central region of the semiconductor memory device 100.

[0031] The peripheral structure 20 is disposed on the substrate 10. The peripheral structure 20 includes circuit elements 21, lower wiring layers UM1, UM2, UM3, UM4 and UM5, and lower dielectric layers 22a, 22b, 22c, 22d, 22e and 22f.

[0032] Circuit element 21 is disposed in a first region R1 of substrate 10. Circuit element 21 includes a transistor. The transistor includes a first gate electrode 21a disposed on substrate 10, a first gate insulating layer 21b between substrate 10 and the first gate electrode 21a, and a source region 21c and a drain region 21d defined on both sides of the first gate electrode 21a in substrate 10. Circuit element 21 may be a component of peripheral circuitry for controlling the operation of a memory cell array. Peripheral circuitry may include, for example, a row decoder, page buffer circuitry, control logic, voltage generator, and receive interface circuitry, but embodiments are not limited thereto.

[0033] The lower wiring layers UM1, UM2, UM3, UM4, and UM5 include a first lower wiring layer UM1 on substrate 10, a second lower wiring layer UM2 on the first lower wiring layer UM1, a third lower wiring layer UM3 on the second lower wiring layer UM2, a fourth lower wiring layer UM4 on the third lower wiring layer UM3, and a fifth lower wiring layer UM5 on the fourth lower wiring layer UM4. Although Figure 1 Five lower wiring layers are shown, but embodiments of this disclosure are not limited thereto. In other embodiments, the semiconductor memory device 100 includes at least two lower wiring layers. In the first region R1, wirings 23a, 23b, 23c, 23d, and 23e are respectively disposed in the first lower wiring layer UM1, the second lower wiring layer UM2, the third lower wiring layer UM3, the fourth lower wiring layer UM4, and the fifth lower wiring layer UM1.

[0034] The lower dielectric layers 22a, 22b, 22c, 22d, 22e, and 22f include a first lower dielectric layer 22a, a second lower dielectric layer 22b, a third lower dielectric layer 22c, a fourth lower dielectric layer 22d, a fifth lower dielectric layer 22e, and a sixth lower dielectric layer 22f. The first lower dielectric layer 22a, the second lower dielectric layer 22b, the third lower dielectric layer 22c, the fourth lower dielectric layer 22d, the fifth lower dielectric layer 22e, and the sixth lower dielectric layer 22f may include silicon oxide, silicon nitride, or silicon oxynitride.

[0035] A first lower dielectric layer 22a is disposed on the substrate 10 and covers the circuit element 21. A first lower wiring layer UM1 is disposed on the first lower dielectric layer 22a. A second lower dielectric layer 22b is disposed on the first lower dielectric layer 22a and covers the first lower wiring layer UM1.

[0036] The second lower wiring layer UM2 is disposed on the second lower dielectric layer 22b. The third lower dielectric layer 22c is disposed on the second lower dielectric layer 22b and covers the second lower wiring layer UM2.

[0037] The third lower wiring layer UM3 is disposed on the third lower dielectric layer 22c. The fourth lower dielectric layer 22d is disposed on the third lower dielectric layer 22c and covers the third lower wiring layer UM3.

[0038] The fourth lower wiring layer UM4 is disposed on the fourth lower dielectric layer 22d. The fifth lower dielectric layer 22e is disposed on the fourth lower dielectric layer 22d and covers the fourth lower wiring layer UM4.

[0039] The fifth lower wiring layer UM5 is disposed on the fifth lower dielectric layer 22e. The sixth lower dielectric layer 22f is disposed on the fifth lower dielectric layer 22e and covers the fifth lower wiring layer UM5.

[0040] The fifth lower routing layer UM5 can be the layer closest to the memory structure 30 among the lower routing layers UM1, UM2, UM3, UM4, and UM5 of the peripheral structure 20, that is, the uppermost lower routing layer.

[0041] The memory structure 30 is disposed on the peripheral structure 20. The memory structure 30 includes a memory cell array (MCA) and an upper dielectric layer 34. The memory cell array (MCA) is disposed in the first region R1.

[0042] The memory cell array (MCA) includes a source plate 31, a gate stack structure 32, and multiple cell connectors 33.

[0043] The source plate 31 is disposed on the peripheral structure 20. The source plate 31 includes a doped semiconductor.

[0044] The gate stack structure 32 includes multiple interlayer insulating layers 32a and multiple gate electrode layers 32b, which are alternately stacked on the source plate 31. The interlayer insulating layers 32a include silicon oxide. The gate electrode layers 32b include a conductive material, such as tungsten (W). The gate electrode layers 32b can form word lines.

[0045] The cell connector 33 can extend vertically through the gate stack structure 32 to the source plate 31. The cell connector 33 includes a channel layer 33a and a cell gate insulating layer 33b. The cell gate insulating layer 33b may have a straw or cylindrical shell shape surrounding the outer wall of the channel layer 33a. The cell gate insulating layer 33b may include a tunnel insulating layer, a charge storage layer, and a barrier layer, which are stacked sequentially starting from the outer wall of the channel layer 33a. In some embodiments, the cell gate insulating layer 33b may have an ONO (oxide-nitride-oxide) stack structure, in which oxide layers, nitride layers, and oxide layers are stacked sequentially.

[0046] Memory cells can be configured such that word lines surround cell connectors 33. Memory cells arranged vertically along a cell connector 33 are included in a cell string. Multiple cell strings can be configured corresponding to multiple cell connectors 33, and the memory cells can be arranged in a three-dimensional manner. Memory structure 30 can include a three-dimensional array of memory cells.

[0047] Bit line BL is disposed on gate stack structure 32 and cell connector 33. Bit line contact BLC is disposed below bit line BL to connect bit line BL and channel layer 33a.

[0048] The upper dielectric layer 34 is disposed in the first region R1 and the second region R2 of the peripheral structure 20. The upper dielectric layer 34 covers the peripheral structure 20, the source plate 31, the gate stack structure 32, the cell connector 33 and the bit line BL.

[0049] Input / output pads 40 are disposed in the second region R2 of memory structure 30. Inductor 50 is disposed in the fifth lower wiring layer UM5 of peripheral structure 20 and vertically overlaps with input / output pads 40.

[0050] To achieve integration, the size of components included in semiconductor memory devices is decreasing. If the size of inductors decreases, the quality factor (Q factor) deteriorates and parasitic capacitance components increase. Therefore, reducing the size of inductors is more complex than reducing the size of other components. According to embodiments of this disclosure, because inductor 50 is configured to vertically overlap with input / output pads 40, an increase in the size of the semiconductor memory device 100 due to the presence of inductor 50 can be avoided.

[0051] The inductor 50 is disposed in the fifth lower wiring layer UM5, which is the uppermost of the lower wiring layers UM1, UM2, UM3, UM4, and UM5 included in the peripheral structure 20. No conductive pattern is provided between the inductor 50 and the substrate 10. The first lower dielectric layer 22a to the fifth lower dielectric layer 22e are disposed between the substrate 10 and the inductor 50.

[0052] The parasitic capacitance between the substrate 10 and the inductor 50 is inversely proportional to the thickness of the dielectric between the substrate 10 and the inductor 50. Because the inductor 50 is located in the uppermost fifth lower wiring layer UM5 among the lower wiring layers UM1, UM2, UM3, UM4 and UM5 included in the peripheral structure 20, the parasitic capacitance between the inductor 50 and the substrate 10 has a smaller value compared to the case where the inductor 50 is located in a lower wiring layer other than the fifth lower wiring layer UM5.

[0053] Although Figure 1 The inductor 50 is disposed on the uppermost fifth lower wiring layer UM5 among the lower wiring layers UM1, UM2, UM3, UM4 and UM5, but this disclosure is not limited thereto. For example, if the parasitic capacitance between the inductor 50 and the substrate 10 is less than a preset threshold, the inductor 50 can be disposed in a lower wiring layer other than the fifth lower wiring layer UM5. In addition, the inductor can be disposed in at least two lower wiring layers.

[0054] The sixth lower dielectric layer 22f and the upper dielectric layer 34 are located between the inductor 50 and the input / output pads 40. The thickness of the upper dielectric layer 34 between the inductor 50 and the input / output pads 40 is greater than the thickness of the gate stack structure 32. The parasitic capacitance between the inductor 50 and the input / output pads 40 is inversely proportional to the thickness of the dielectric between the inductor 50 and the input / output pads 40. No conductive pattern is provided between the inductor 50 and the input / output pads 40.

[0055] Because no conductive pattern is provided between inductor 50 and input / output pads 40, and an upper dielectric layer 34 with a thickness greater than that of the gate stack structure 32 is provided between inductor 50 and input / output pads 40, the parasitic capacitance between inductor 50 and input / output pads 40 is relatively small. When the number of stacked gate electrode layers 32b is increased to achieve high-capacitance applications, the height of the gate stack structure 32 increases, and the thickness of the upper dielectric layer 34 also increases. Therefore, the more layers in the gate stack structure 32, the smaller the parasitic capacitance between the input / output pads 40 and inductor 50.

[0056] As described later, inductor 50 may be included in the receiver interface circuitry. When an inductor is used to configure the receiver interface circuitry, high-frequency gain and cutoff frequency can be increased.

[0057] As is well known, the performance of a receiver interface circuit is affected not only by the inductance of the inductor but also by its Q factor. The Q factor of an inductor is related to the capacitive coupling between the inductor and the parasitic capacitance between the inductor and adjacent conductive patterns. As the parasitic capacitance increases, the Q factor of the inductor decreases.

[0058] According to embodiments of this disclosure, by placing the inductor 50 in the uppermost fifth lower wiring layer UM5 among the lower wiring layers UM1, UM2, UM3, UM4, and UM5 of the peripheral structure 20, the parasitic capacitance between the inductor 50 and the substrate 10, and the parasitic capacitance between the inductor 50 and the input / output pads 40, can be relatively small. Therefore, the Q factor of the inductor 50 can be increased, and the SI characteristics of the receiver interface circuit configured using the inductor 50 can be improved.

[0059] Figure 2 It is shown Figure 1 Plan view of input / output pads and inductors.

[0060] Reference Figure 2 The inductor 50 is vertically overlapped with the input / output pads 40. In the plan view, the inductor 50 is positioned within the area of ​​the input / output pads 40.

[0061] Inductor 50 can have a spiral shape. Figure 2 In this embodiment, inductor 50 has a quadrilateral spiral shape, but other embodiments are not limited to this. For example, inductor 50 may have a circular or hexagonal spiral shape.

[0062] Figure 3 This is a block diagram illustrating a system including a semiconductor memory device according to an embodiment of the present disclosure.

[0063] Reference Figure 3 The system 200 includes a first device 210, a second device 220, and a transmission line TL connecting the first device 210 and the second device 220.

[0064] For example, the first device 210 may be a memory controller, while the second device 220 may be a semiconductor memory device according to this disclosure. Although for ease of explanation, Figure 3 The diagram illustrates a configuration for explaining one-way communication, wherein the first device 210 operates as a transmitting device and the second device 220 operates as a receiving device, but each of the first device 210 and the second device 220 can perform both transmitting and receiving operations, enabling the system 200 to perform bidirectional communication.

[0065] In addition, although for ease of explanation, Figure 3 Only a pair of input / output pads PADC and PADM and a transmission line TL connected to the pair of input / output pads PADC and PADM are shown, but each of the first device 210 and the second device 220 may include multiple input / output pads connected by multiple transmission lines.

[0066] The transmission driver DR of the first device 210 can output the output signal SO to the input / output pad PADC based on the transmit signal ST from the internal circuit INTC. The receive interface circuit 221 of the second device 220 can receive the input signal SIG through the input / output pad PADM and provide the buffered signal SB to the internal circuit INTM.

[0067] The receiving interface circuit 221 includes a terminal circuit ODT, a buffer block BF, an amplifier circuit (not shown), etc.

[0068] Figure 4 This is a circuit diagram illustrating an input buffer of a semiconductor memory device according to an embodiment of the present disclosure.

[0069] Reference Figure 4 , Figure 3 The buffer block BF is shown as input buffer 400, which includes a pair of differential input transistors TN1 and TN2, a first resistor R1 and a second resistor R2, and a first inductor L1 and a second inductor L2. Additionally, input buffer 400 further includes an enable transistor TN3, a first capacitor C1, and a second capacitor C2.

[0070] The pair of differential input transistors TN1 and TN2 includes a first input transistor TN1 and a second input transistor TN2. The first input transistor TN1 is connected between the first node N1 and the third node N3, and the second input transistor TN2 is connected between the second node N2 and the third node N3.

[0071] The first input signal INN is applied to the gate of the first input transistor TN1. The second input signal INP is applied to the gate of the second input transistor TN2. The first input signal INN and the second input signal INP can be signals received from an external device through input / output pads.

[0072] The first input transistor TN1 changes the voltage level of the first node N1 based on the first input signal INN. The first input transistor TN1 can be an N-channel MOS transistor. The drain of the first input transistor TN1 can be connected to the first node N1, the source of the first input transistor TN1 can be connected to the third node N3, and the gate of the first input transistor TN1 can receive the first input signal INN.

[0073] The second input transistor TN2 changes the voltage level of the second node N2 based on the second input signal INP. The second input transistor TN2 can be an N-channel MOS transistor. The drain of the second input transistor TN2 can be connected to the second node N2, the source of the second input transistor TN2 can be connected to the third node N3, and the gate of the second input transistor TN2 can receive the second input signal INP.

[0074] A first resistor R1 and a first inductor L1 are connected in series between the power supply voltage terminal VDD and the first node N1. The first resistor R1 is connected between the power supply voltage terminal VDD and the fourth node N4, and the first inductor L1 is connected between the fourth node N4 and the first node N1.

[0075] The second resistor R2 and the second inductor L2 are connected in series between the power supply voltage terminal VDD and the second node N2. The second resistor R2 is connected between the power supply voltage terminal VDD and the fifth node N5, and the second inductor L2 is connected between the fifth node N5 and the second node N2.

[0076] Each of the first inductor L1 and the second inductor L2 is Figure 1 The inductor 50 in the middle.

[0077] The first capacitor C1 is connected between the first node N1 and the ground voltage terminal GND, and the second capacitor C2 is connected between the second node N2 and the ground voltage terminal GND.

[0078] The first input transistor TN1, the first inductor L1, and the first capacitor C1 are connected to the first node N1. The second input transistor TN2, the second inductor L2, and the second capacitor C2 are connected to the second node N2. The output signal Vout is output through the first node N1 and the second node N2.

[0079] Enable transistor TN3 can connect the ground voltage terminal GND to the third node N3 based on the bias voltage BIAS. When enable transistor TN3 is turned on by the bias voltage BIAS, a current path is formed between the first input transistor TN1 and the second input transistor TN2 and the ground voltage terminal GND. Enable transistor TN3 can be an N-channel MOS transistor. The drain of enable transistor TN3 can be connected to the source of the first input transistor TN1 and the source of the second input transistor TN2, the source of enable transistor TN3 can be connected to the ground voltage terminal GND, and the gate of enable transistor TN3 can receive the bias voltage BIAS.

[0080] exist Figure 4 In this configuration, the first resistor R1 and the second resistor R2 are both connected to the power supply voltage terminal VDD. The first inductor L1 is connected between the first resistor R1 and the first node N1, and the second inductor L2 is connected between the second resistor R2 and the second node N2. However, as will be noted below... Figure 5 The positions of the first resistor R1 and the first inductor L1 can be interchanged, and the positions of the second resistor R2 and the second inductor L2 can also be interchanged.

[0081] Figure 5 This is a circuit diagram illustrating an input buffer of a semiconductor memory device according to an embodiment of the present disclosure. For ease of explanation, descriptions or omissions will be briefly described or omitted from the above references. Figure 4 The elements or configurations described are the same as or overlap with those described.

[0082] Reference Figure 5 The first inductor L1 and the first resistor R1 are connected in series between the power supply voltage terminal VDD and the first node N1. The first inductor L1 is connected between the power supply voltage terminal VDD and the fourth node N4, and the first resistor R1 is connected between the fourth node N4 and the first node N1.

[0083] The second inductor L2 and the second resistor R2 are connected in series between the power supply voltage terminal VDD and the second node N2. The second inductor L2 is connected between the power supply voltage terminal VDD and the fifth node N5, and the second resistor R2 is connected between the fifth node N5 and the second node N2.

[0084] Each of the first inductor L1 and the second inductor L2 can be Figure 1 The inductor 50 in the middle.

[0085] The first input transistor TN1, the first resistor R1, and the first capacitor C1 are connected to the first node N1. The second input transistor TN2, the second resistor R2, and the second capacitor C2 are connected to the second node N2. The output signal Vout of the input buffer 410 is output through the first node N1 and the second node N2.

[0086] exist Figure 4 and Figure 5 In this configuration, the first resistor R1 and the second resistor R2 are configured as load resistors. However, the first resistor R1 can also be replaced by a parasitic resistance assembly of the wiring connecting the first node N1 and the power supply voltage terminal VDD, and the second resistor R2 can also be replaced by a parasitic resistance assembly of the wiring connecting the second node N2 and the power supply voltage terminal VDD. Therefore, the first resistor R1 and the second resistor R2 are omitted, and the two ends of the first inductor L1 are connected to the power supply voltage terminal VDD and the first node N1, respectively, and the two ends of the second inductor L2 are connected to the power supply voltage terminal VDD and the second node N2, respectively.

[0087] Figure 6 This is a circuit diagram illustrating the terminal circuitry of a semiconductor memory device according to an embodiment of the present disclosure.

[0088] Reference Figure 6 The terminal circuit 600 includes a terminal resistor R and an inductor L, which are connected between the power supply voltage terminal VDD and the input / output pad PADM.

[0089] Terminal resistor R is connected between the power supply voltage terminal VDD and inductor L. Inductor L is connected between terminal resistor R and input / output pad PADM. Inductor L can be... Figure 1 50 inductors.

[0090] exist Figure 6 In the diagram, terminal resistor R is connected to the power supply voltage terminal VDD, and inductor L is connected between terminal resistor R and input / output pad PADM, but as will be referred to below. Figure 7 The positions of the terminal resistor R and the inductor L can be interchanged.

[0091] Figure 7 This is a circuit diagram illustrating the terminal circuitry of a semiconductor memory device according to an embodiment of the present disclosure.

[0092] Reference Figure 7 The terminal circuit 610 includes an inductor L and a terminal resistor R, which are connected between the power supply voltage terminal VDD and the input / output pad PADM.

[0093] Inductor L is connected between the power supply voltage terminal VDD and the terminal resistor R. Inductor L can be... Figure 1 The inductor 50. Terminal resistor R is connected between inductor L and input / output pad PADM.

[0094] exist Figure 6 and Figure 7 In this configuration, the terminal resistor R is set as the load resistor; however, the terminal resistor R can be replaced by a parasitic resistance assembly of the wiring connecting the power supply voltage terminal VDD and the input / output pad PADM. In this case, the terminal resistor R is omitted, and the two ends of the inductor L are connected to the power supply voltage terminal VDD and the input / output pad PADM, respectively.

[0095] Figure 8 This is a diagram illustrating an amplifier circuit of a semiconductor memory device according to an embodiment of the present disclosure.

[0096] Reference Figure 8 The amplifier circuit 800 includes a first transistor TNa, a second transistor TNb, an inductor La, a first resistor Ra, and a second resistor Rb.

[0097] The first transistor TNa is connected between the ground voltage terminal GND and the first node N11. The first transistor TNa can receive the input signal Vin, amplify the received input signal Vin, and provide the amplified signal to the first node N11.

[0098] The first transistor TNa can be an N-channel MOS transistor. The drain of the first transistor TNa can be connected to the source of the second transistor TNb, the source of the first transistor TNa can be connected to the ground voltage terminal GND, and the gate of the first transistor TNa can receive the input signal Vin. The input signal Vin can be a signal provided from a semiconductor memory device including amplifier circuit 800.

[0099] The second transistor TNb is connected between the first node N11 and the second node N12. The second transistor TNb can receive amplified signals from the first transistor TNa through the first node N11, and can provide an output signal Vout through the second node N12.

[0100] The second transistor TNb can be an N-channel MOS transistor. The source of the second transistor TNb is connected to the drain of the first transistor TNa, the drain of the second transistor TNb is connected to the second node N12, and the gate of the second transistor TNb is connected to the third node N13.

[0101] Inductor La is connected between the third node N13 and the input / output pad PADM. Inductor La can be... Figure 1 The inductor 50. The first resistor Ra is connected between the power supply voltage terminal VDD and the second node N12. The second resistor Rb is connected between the second node N12 and the ground voltage terminal GND.

[0102] The second transistor TNb, the first resistor Ra, and the second resistor Rb are all connected to the second node N12, and the output signal Vout of the amplifier circuit 800 is output through the second node N12.

[0103] Figure 9 This is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure. For ease of explanation, descriptions or omissions related to the above references will be simplified or omitted. Figure 1 The described elements or configurations overlap.

[0104] Reference Figure 9 The semiconductor memory device 100' includes a substrate 10, a peripheral structure 20', a memory structure 30, an input / output pad 40, a first inductor 51, and a second inductor 52.

[0105] The first inductor 51 and the second inductor 52 are vertically overlapped on the input / output pads 40.

[0106] The second inductor 52 is disposed in the fifth lower wiring layer UM5, which is the uppermost layer among the lower wiring layers UM1, UM2, UM3, UM4 and UM5 included in the peripheral structure 20'. The first inductor 51 is disposed in the fourth lower wiring layer UM4, which is the second uppermost layer among the lower wiring layers UM1, UM2, UM3, UM4 and UM5 included in the peripheral structure 20'.

[0107] The fifth lower routing layer UM5 among the lower routing layers UM1, UM2, UM3, UM4 and UM5 included in the peripheral structure 20' is set to be closest to the memory structure 30, and the fourth lower routing layer UM4 among the lower routing layers UM1, UM2, UM3 and UM4 included in the peripheral structure 20' is set to be closest to the fifth lower routing layer UM5.

[0108] The second inductor 52 is positioned further away from the substrate 10 than the first inductor 51. The parasitic capacitance between the second inductor 52 and the substrate 10 has a smaller value than the parasitic capacitance between the first inductor 51 and the substrate 10.

[0109] Although not shown, each of the first inductor 51 and the second inductor 52 may have a helical shape in the plan view. The helical rotation direction of the first inductor 51 and the helical rotation direction of the second inductor 52 may be opposite to each other. For example, the rotation direction of the first inductor 51 may be counterclockwise, and the rotation direction of the second inductor 52 may be clockwise.

[0110] Figure 10 This is a circuit diagram illustrating an input buffer of a semiconductor memory device according to an embodiment of the present disclosure. For ease of explanation, descriptions or omissions will be briefly described or omitted from the above references. Figure 4 The described elements or configurations overlap.

[0111] Reference Figure 10 The input buffer 420 includes a pair of differential input transistors TN1 and TN2, a first resistor R1 and a second resistor R2, and a first inductor L11, a second inductor L12, a third inductor L21, and a fourth inductor L22. Additionally, the input buffer 420 further includes an enable transistor TN3, a first capacitor C1, and a second capacitor C2.

[0112] The first inductor L11, the second inductor L12, and the first resistor R1 are connected in series between the first node N1 and the power supply voltage terminal VDD. The first inductor L11 is connected between the first node N1 and the sixth node N6, the second inductor L12 is connected between the sixth node N6 and the fourth node N4, and the first resistor R1 is connected between the fourth node N4 and the power supply voltage terminal VDD.

[0113] The third inductor L21, the fourth inductor L22, and the second resistor R2 are connected in series between the second node N2 and the power supply voltage terminal VDD. The third inductor L21 is connected between the second node N2 and the seventh node N7, the fourth inductor L22 is connected between the seventh node N7 and the fifth node N5, and the second resistor R2 is connected between the fifth node N5 and the power supply voltage terminal VDD.

[0114] The first input transistor TN1, the first inductor L11, and the first capacitor C1 are connected together to the first node N1. The second input transistor TN2, the third inductor L21, and the second capacitor C2 are connected together to the second node N2. The output signal Vout is output through the first node N1 and the second node N2.

[0115] Each of the first inductor L11 and the third inductor L21 can be Figure 9 The first inductor 51. Each of the second inductor L12 and the fourth inductor L22 can be Figure 9 The second inductor 52. The parasitic capacitance between the first inductor L11 and the third inductor L21 and the substrate 10 can have a larger value than the parasitic capacitance between the second inductor L12 and the fourth inductor L22 and the substrate 10.

[0116] When the first inductor L11 and the third inductor L21 connected to output nodes N1 and N2 utilize Figure 9 The first inductor 51, which has a relatively large parasitic capacitance, is configured, while the second inductor L12 and the fourth inductor L22 utilize... Figure 9 When configured with a second inductor 52 having a relatively small parasitic capacitance, it is used in conjunction with the first inductor L11 and the third inductor L21. Figure 9 The second inductor 52 is used for configuration, while the second inductor L12 and the fourth inductor L22 utilize Figure 9 Compared to the opposite case where the first inductor 51 is configured, the magnitude of the reduction in cutoff frequency due to parasitic capacitance can be reduced.

[0117] Figure 11 This is a circuit diagram illustrating an input buffer of a semiconductor memory device according to an embodiment of the present disclosure. For ease of explanation, descriptions or omissions will be briefly described or omitted from the above references. Figure 10 The described elements or configurations overlap.

[0118] Reference Figure 11The input buffer 430 has a first resistor R1, a second inductor L12, and a third inductor L11 connected in series between the first node N1 and the power supply voltage terminal VDD. The first resistor R1 is connected between the first node N1 and the fourth node N4, the second inductor L12 is connected between the fourth node N4 and the sixth node N6, and the first inductor L11 is connected between the sixth node N6 and the power supply voltage terminal VDD.

[0119] The second resistor R2, the fourth inductor L22, and the third inductor L21 are connected in series between the second node N2 and the power supply voltage terminal VDD. The second resistor R2 is connected between the second node N2 and the fifth node N5, the fourth inductor L22 is connected between the fifth node N5 and the seventh node N7, and the third inductor L21 is connected between the seventh node N7 and the power supply voltage terminal VDD.

[0120] The first input transistor TN1, the first resistor R1, and the first capacitor C1 are connected together to the first node N1. The second input transistor TN2, the second resistor R2, and the second capacitor C2 are connected together to the second node N2. The output signal Vout is output through the first node N1 and the second node N2.

[0121] Each of the first inductor L11 and the third inductor L21 can be Figure 9 The first inductor 51. Each of the second inductor L12 and the fourth inductor L22 can be Figure 9 The second inductor 52. The parasitic capacitance between the first inductor L11 and the third inductor L21 and the substrate 10 can have a larger value than the parasitic capacitance between the second inductor L12 and the fourth inductor L22 and the substrate 10.

[0122] When the first inductor L11 and the third inductor L21 are connected to the power supply voltage terminal VDD, they utilize... Figure 9 The first inductor 51, which has a relatively large parasitic capacitance, is configured, while the second inductor L12 and the fourth inductor L22 utilize... Figure 9 When configured with a second inductor 52 having a relatively small parasitic capacitance, it is used in conjunction with the first inductor L11 and the third inductor L21. Figure 9 The second inductor 52 is used for configuration, while the second inductor L12 and the fourth inductor L22 utilize Figure 9 Compared to the opposite case where the first inductor 51 is configured, the magnitude of the reduction in cutoff frequency due to parasitic capacitance can be reduced.

[0123] Figure 12 This is a circuit diagram illustrating the terminal circuitry of a semiconductor memory device according to an embodiment of the present disclosure.

[0124] Reference Figure 12The terminal circuit 620 includes a first inductor L31, a second inductor L32, and a terminal resistor R, which are connected in series between the input / output pad PADM and the power supply voltage terminal VDD.

[0125] The first inductor L31 is connected between the input / output pad PADM and the first node N1. The second inductor L32 is connected between the first node N1 and the second node N2. The terminal resistor R is connected between the second node N2 and the power supply voltage terminal VDD.

[0126] The first inductor L31 can be Figure 9 The first inductor 51, and the second inductor L32 can be Figure 9 The second inductor 52. The value of the parasitic capacitance between the first inductor L31 and the substrate 10 can be greater than the value of the parasitic capacitance between the second inductor L32 and the substrate 10.

[0127] When the first inductor L31 connected to the input / output pad PADM utilizes Figure 9 The first inductor 51, which has a relatively large parasitic capacitance, is configured, while the second inductor L32 utilizes... Figure 9 When configured with a second inductor 52 having a relatively small parasitic capacitance, it is used in conjunction with the first inductor L31. Figure 9 The second inductor 52 is configured, and the second inductor L32 utilizes Figure 9 Compared to the opposite case where the first inductor 51 is configured, the magnitude of the cutoff frequency reduction due to parasitic capacitance can be reduced.

[0128] Reference Figure 13 The terminal circuit 630 includes a terminal resistor R, a second inductor L32 and a first inductor L31, which are connected in series between the input / output pad PADM and the power supply voltage terminal VDD.

[0129] Terminal resistor R is connected between input / output pad PADM and first node N1. Second inductor L32 is connected between first node N1 and second node N2. First inductor L31 is connected between second node N2 and power supply voltage terminal VDD.

[0130] The first inductor L31 can be Figure 9 The first inductor 51, and the second inductor L32 can be Figure 9 The second inductor 52. The value of the parasitic capacitance between the first inductor L31 and the substrate 10 can be greater than the value of the parasitic capacitance between the second inductor L32 and the substrate 10.

[0131] When the first inductor L31 connected to the power supply voltage terminal VDD utilizes Figure 9 The first inductor 51, which has a relatively large parasitic capacitance, is configured, while the second inductor L32 utilizes... Figure 9 When configured with a second inductor 52 having a relatively small parasitic capacitance, it is used in conjunction with the first inductor L31. Figure 9 The second inductor 52 is configured, and the second inductor L32 utilizes Figure 9 Compared to the opposite case where the first inductor 51 is configured, the magnitude of the cutoff frequency reduction due to parasitic capacitance can be reduced.

[0132] Figure 14 This is a circuit diagram illustrating an amplifier circuit of a semiconductor memory device according to an embodiment of the present disclosure. For ease of explanation, descriptions or omissions will be briefly presented or omitted from the above references. Figure 8 The elements or configurations described are the same as or overlap with those described.

[0133] Reference Figure 14 The amplifier circuit 810 includes a first transistor TNa, a second transistor TNb, a first inductor La1 and a second inductor La2, as well as a first resistor Ra and a second resistor Rb.

[0134] The first inductor La1 and the second inductor La2 are connected in series between the input / output pad PADM and the third node N13. The first inductor La1 is connected between the input / output pad PADM and the fourth node N14, and the second inductor La2 is connected between the fourth node N14 and the third node N13.

[0135] The first inductor La1 can be Figure 9 The first inductor 51, and the second inductor La2 can be Figure 9 The second inductor 52. The value of the parasitic capacitance between the first inductor La1 and the substrate 10 can be greater than the value of the parasitic capacitance between the second inductor La2 and the substrate 10.

[0136] When the first inductor La1 connected to the power supply voltage terminal PADM utilizes Figure 9 The first inductor 51, which has a relatively large parasitic capacitance, is configured, while the second inductor La2 utilizes... Figure 9 When configured with a second inductor 52 having a relatively small parasitic capacitance, it is used in conjunction with the first inductor La1. Figure 9 The second inductor 52 is configured, and the second inductor La2 utilizes Figure 9 Compared to the opposite case where the first inductor 51 is configured, the magnitude of the cutoff frequency reduction due to parasitic capacitance can be reduced.

[0137] While this disclosure provides for detailed embodiments, those skilled in the art will understand that various modifications, additions, and substitutions can be made to these embodiments without departing from the scope and technical concept of this disclosure. Therefore, the scope of this disclosure should not be limited to the foregoing embodiments. All variations within the equivalent meaning and scope of the claims are included within its scope.

Claims

1. A semiconductor memory device, comprising: Substrate; The peripheral structure includes multiple lower wiring layers stacked vertically on the substrate; A memory structure is disposed on the peripheral structure and includes a memory cell array in the first region; Input / output pads are disposed in the second region above the memory structure; as well as An inductor is disposed in at least one of the plurality of lower wiring layers and vertically overlaps with the input / output pads.

2. The semiconductor memory device according to claim 1, wherein, The plurality of lower wiring layers include: A first lower wiring layer is disposed on the substrate; and The second lower wiring layer is disposed above the first lower wiring layer, and The inductor is disposed in the second lower wiring layer.

3. The semiconductor memory device according to claim 2, wherein, The second lower wiring layer among the plurality of lower wiring layers is positioned closest to the memory structure.

4. The semiconductor memory device according to claim 1, wherein, No conductive pattern is provided between the inductor and the substrate.

5. The semiconductor memory device according to claim 1, wherein, No conductive pattern is provided between the inductor and the input / output pads.

6. The semiconductor memory device according to claim 1, wherein, The memory cell array includes: Multiple electrode layers and multiple interlayer insulating layers, wherein the multiple electrode layers and the multiple interlayer insulating layers are stacked alternately; and The unit plug penetrates the plurality of electrode layers and the plurality of interlayer insulation layers.

7. The semiconductor memory device according to claim 1, wherein, The peripheral structure further includes a receiving interface circuit, which includes the inductor and is connected to the input / output pads.

8. The semiconductor memory device according to claim 1, wherein, The peripheral structure further includes a receiving interface circuit, which includes an input buffer. The input buffer includes: The first input transistor changes the voltage level of the first output node in response to the first input signal; The second input transistor changes the voltage level of the second output node in response to the second input signal; Resistor, connected to the power supply voltage terminal; and The inductor, and The inductor is connected between the resistor and either the first output node or the second output node.

9. The semiconductor memory device according to claim 1, wherein, The peripheral structure further includes a receiving interface circuit, which includes an input buffer. The input buffer includes: The first input transistor changes the voltage level of the first output node in response to the first input signal; The second input transistor changes the voltage level of the second output node in response to the second input signal; A resistor is connected to either the first output node or the second output node; and The inductor, and The inductor is connected between the power supply voltage terminal and the resistor.

10. The semiconductor memory device according to claim 1, wherein, The peripheral structure further includes a receiving interface circuit, which includes an input buffer. The input buffer includes: The first input transistor changes the voltage level of the first output node in response to the first input signal; The second input transistor changes the voltage level of the second output node in response to the second input signal; and The inductor, and One end of the inductor is connected to the power supply voltage terminal, and the other end of the inductor is connected to either the first output node or the second output node.

11. The semiconductor memory device according to claim 1, wherein, The peripheral structure further includes a receiving interface circuit, which includes terminal circuitry. The terminal circuit includes: Resistor, connected to the power supply voltage terminal; and The inductor, and The inductor is connected between the input / output pads and the resistor.

12. The semiconductor memory device according to claim 1, wherein, The peripheral structure further includes a receiving interface circuit, which includes terminal circuitry. The terminal circuit includes: Resistors are connected to the input / output pads; and The inductor, and The inductor is connected between the power supply voltage terminal and the resistor.

13. The semiconductor memory device according to claim 1, wherein, The peripheral structure further includes a receiving interface circuit, which includes terminal circuitry. The terminal circuit includes: The inductor, and One end of the inductor is connected to the power supply voltage terminal, and the other end of the inductor is connected to the input / output pad.

14. The semiconductor memory device according to claim 1, wherein, The peripheral structure further includes a receiving interface circuit, which includes an amplifier circuit. The amplifier circuit includes: A first transistor is connected between a ground voltage terminal and a first node, and changes the voltage level of the first node based on an input signal; A second transistor is connected between the first node and the output node, and provides an output signal to the output node; and The inductor, and The inductor is connected between the input / output pad and the gate of the second transistor.

15. A semiconductor memory device, comprising: Substrate; The peripheral structure includes a first lower wiring layer located above the substrate and a second lower wiring layer located above the first lower wiring layer; A memory structure is disposed on the peripheral structure and includes a three-dimensional memory cell array in the first region; Input / output pads are disposed in the second region above the memory structure; A first inductor is disposed in the first lower wiring layer to vertically overlap with the input / output pads; as well as A second inductor is disposed in the second lower wiring layer to vertically overlap with the input / output pads.

16. The semiconductor memory device according to claim 15, wherein, No conductive pattern is provided between the first inductor and the substrate.

17. The semiconductor memory device according to claim 15, wherein, No conductive pattern is provided between the second inductor and the input / output pads.

18. The semiconductor memory device of claim 15, wherein, The peripheral structure further includes a receiving interface circuit, which is connected to the input / output pads, and The receiving interface circuit includes the first inductor and the second inductor.

19. The semiconductor memory device according to claim 15, wherein, The peripheral structure further includes a receiving interface circuit connected to the input / output pads, and the receiving interface circuit includes an input buffer. The input buffer includes: The first input transistor changes the voltage level of the first output node based on the first input signal; The second input transistor changes the voltage level of the second output node based on the second input signal; Resistor, connected to the power supply voltage terminal; and The first inductor and the second inductor, The first inductor is connected to either the first output node or the second output node, and The second inductor is connected between the first inductor and the resistor.

20. The semiconductor memory device according to claim 15, wherein, The peripheral structure further includes a receiving interface circuit connected to the input / output pads, and the receiving interface circuit includes an input buffer. The input buffer includes: The first input transistor changes the voltage level of the first output node based on the first input signal; The second input transistor changes the voltage level of the second output node based on the second input signal; A resistor is connected to either the first output node or the second output node; and The first inductor and the second inductor, The first inductor is connected to the power supply voltage terminal, and The second inductor is connected between the resistor and the first inductor.

21. The semiconductor memory device according to claim 15, wherein, The peripheral structure further includes a receiving interface circuit, which is connected to the input / output pads, and the receiving interface circuit includes terminal circuitry. The terminal circuit includes: Resistor, connected to the power supply voltage terminal; and The first inductor and the second inductor, The first inductor is connected to the input / output pads, and The second inductor is connected between the resistor and the first inductor.

22. The semiconductor memory device according to claim 15, wherein, The peripheral structure further includes a receiving interface circuit, which is connected to the input / output pads, and the receiving interface circuit includes terminal circuitry. The terminal circuit includes: Resistors are connected to the input / output pads; and The first inductor and the second inductor, The first inductor is connected to the power supply voltage terminal, and The second inductor is connected between the resistor and the first inductor.

23. The semiconductor memory device according to claim 15, wherein, The peripheral structure further includes a receiving interface circuit connected to the input / output pads, and the receiving interface circuit includes an amplifier circuit. The amplifier circuit includes: A first transistor is connected between a ground voltage terminal and a first node, and changes the voltage level of the first node based on an input signal; A second transistor is connected between the first node and the output node, and provides an output signal to the output node; and The first inductor and the second inductor, The first inductor is connected to the input / output pads, and The second inductor is connected between the first inductor and the gate of the second transistor.

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