Semiconductor package and method of forming same

Abstract

The semiconductor package includes a substrate, a first semiconductor die disposed on the substrate, a second semiconductor die stacked on the first semiconductor die and offset from the first semiconductor die in a first direction and a second direction perpendicular to each other, and a third semiconductor die stacked on the first semiconductor die and the second semiconductor die and offset from the first semiconductor die and the second semiconductor die in the first direction. The first semiconductor die includes a first pad and a second pad continuously arranged in a second direction. The second semiconductor die includes a third pad and a fourth pad, and the third semiconductor die includes a fifth pad and a sixth pad, each pad being continuously arranged in the second direction. The first conductive pattern connects the first pad and the fifth pad, and the second conductive pattern connects the second pad, the fourth pad, and the sixth pad. The first and second conductive patterns are spaced apart from the third pad.

Description

Technical Field

[0001] Embodiments of this disclosure relate to semiconductor packaging. Background Technology

[0002] Semiconductor packages can be configured to facilitate the use of integrated circuit chips as components in electronic products. Typically, a semiconductor package includes a printed circuit board (PCB) and a semiconductor chip, which is mounted on the PCB and electrically connected to it using bonding wires or bumps. With advancements in the semiconductor industry, research is underway to improve the reliability of semiconductor packages. Summary of the Invention

[0003] Embodiments of this disclosure provide semiconductor packages with high signal transmission efficiency and high reliability.

[0004] According to embodiments of this disclosure, a semiconductor package includes a substrate, a first semiconductor die disposed on the substrate, a second semiconductor die disposed on the first semiconductor die, a third semiconductor die disposed on the second semiconductor die, a first conductive pattern, and a second conductive pattern. The second semiconductor die is stacked on the first semiconductor die and offset from the first semiconductor die in a first direction and a second direction perpendicular to each other. The third semiconductor die is stacked on the first and second semiconductor dies and offset from the first and second semiconductor dies in a first direction. The first semiconductor die includes a first pad and a second pad, which are continuously arranged in a second direction. The second semiconductor die includes a third pad and a fourth pad, which are continuously arranged in a second direction. The third semiconductor die includes a fifth pad and a sixth pad, which are continuously arranged in a second direction. The first conductive pattern connects the first pad and the fifth pad, and the second conductive pattern connects the second pad, the fourth pad, and the sixth pad. The first and second conductive patterns are spaced apart from the third pad.

[0005] According to embodiments of this disclosure, a semiconductor package includes a substrate, a first semiconductor die disposed on the substrate, a second semiconductor die disposed on the first semiconductor die, a first conductive pattern, and a second conductive pattern. The second semiconductor die is stacked on the first semiconductor die and offset from the first semiconductor die in a first direction and a second direction perpendicular to each other. The substrate includes a first substrate pad and a second substrate pad, which are spaced apart from each other in the second direction. The first semiconductor die includes a first insulating layer and a first pad exposed from the first insulating layer, and the second semiconductor die includes a second pad. The first conductive pattern is disposed between the first substrate pad and the first pad, and the second conductive pattern is disposed between the second substrate pad and the second pad. The second conductive pattern is spaced apart from the first conductive pattern and contacts the top surface of the first insulating layer.

[0006] According to embodiments of this disclosure, a semiconductor package includes a substrate, a semiconductor die stack disposed on the substrate, a molding layer covering the top and side surfaces of the semiconductor die stack, a first conductive pattern, a second conductive pattern, and a third conductive pattern. The semiconductor die stack includes a first semiconductor die disposed on the substrate, a second semiconductor die disposed on the first semiconductor die, a third semiconductor die disposed on the second semiconductor die, and a fourth semiconductor die disposed on the third semiconductor die. The second and fourth semiconductor dies are offset from the first semiconductor die in a first direction and in a second direction, respectively. The third semiconductor die is offset from the first semiconductor die in the first direction and is disposed at the same position as the first semiconductor die in the second direction. The fourth semiconductor die is offset from the second semiconductor die in the first direction and is disposed at the same position as the second semiconductor die in the second direction. The first semiconductor die includes a first signal pad and a first voltage pad spaced apart from each other in the second direction, and the second semiconductor die includes a second signal pad and a second voltage pad spaced apart from each other in the second direction. The third semiconductor die includes a third signal pad and a third voltage pad spaced apart from each other in a second direction, and the fourth semiconductor die includes a fourth signal pad and a fourth voltage pad spaced apart from each other in a second direction. A first conductive pattern connects the first signal pad and the third signal pad, a second conductive pattern connects the second signal pad and the fourth signal pad, and a third conductive pattern connects the first voltage pad, the second voltage pad, the third voltage pad, and the fourth voltage pad.

[0007] According to embodiments of this disclosure, a method for forming a semiconductor package includes forming a semiconductor die stack by stacking a plurality of semiconductor dies on a substrate. The semiconductor dies are stacked sequentially and offset from each other. The method further includes forming an insulating pattern by coating the side surfaces of the semiconductor dies with a polymer insulating material, and forming a conductive pattern by spraying a conductive material onto the top and side surfaces of the semiconductor dies using a nozzle and sintering the conductive material. Attached Figure Description

[0008] The above and other features of this disclosure will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings.

[0009] Figure 1 This is a plan view illustrating a semiconductor package according to an embodiment of the present disclosure.

[0010] Figure 2 yes Figure 1 Perspective view.

[0011] Figure 3 It is along Figure 1 A sectional view taken from line I-I'.

[0012] Figure 4 It is shown Figure 1 An enlarged view of the "EV1" section.

[0013] Figure 5 It is shown Figure 3 An enlarged view of the "EV2" section.

[0014] Figure 6 This is a cross-sectional view showing a semiconductor package according to an embodiment of the present disclosure.

[0015] Figure 7 This is a plan view illustrating a semiconductor package according to an embodiment of the present disclosure.

[0016] Figure 8 yes Figure 7 Perspective view.

[0017] Figure 9 It is along Figure 7 A sectional view taken from line I-I'.

[0018] Figure 10 It is shown Figure 9 An enlarged view of the "EV3" section.

[0019] Figure 11 This is a plan view illustrating a semiconductor package according to an embodiment of the present disclosure.

[0020] Figure 12 yes Figure 11 Perspective view.

[0021] Figure 13 It is shown Figure 11 An enlarged view of the "EV4" section.

[0022] Figure 14 This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the present disclosure. Detailed Implementation

[0023] Embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings. Throughout the drawings, the same reference numerals may refer to the same elements.

[0024] It should be understood that the terms “first,” “second,” “third,” etc., are used herein to distinguish one element from another, and the elements are not limited by these terms. Thus, an “first” element in one embodiment can be described as a “second” element in another embodiment.

[0025] It should be understood that, unless the context clearly indicates otherwise, the description of features or aspects within each implementation should generally be considered applicable to other similar features or aspects in other implementations.

[0026] As used herein, the singular forms “a,” “one,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0027] For ease of description, this document uses spatial relative terms such as “below,” “under,” “down,” “below,” “above,” “up,” etc., to describe the relationship between one element or feature and another element or feature as shown in the figure. It should be understood that, in addition to the orientation shown in the figure, spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figure is flipped, an element described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the example terms “below” and “below” can cover both above and below orientations.

[0028] It should be understood that when a component is referred to as being "on," "connected to," "linked to," or "adjacent to" another component, it may be directly on, directly connected to, linked to, or adjacent to the other component, or there may be intermediate components. It should also be understood that when a component is referred to as being "between" two components, it may be the only component between the two components, or there may be one or more intermediate components. Furthermore, it should be understood that when a component is referred to as "covering" another component, it may be the only component covering the other component, or one or more intermediate components may also cover the other component. Other terms used to describe relationships between components should be interpreted in a similar manner.

[0029] In this document, when two or more elements or values ​​are described as substantially the same or approximately equal to each other, it should be understood that the elements or values ​​are the same, the elements or values ​​are equal to each other within measurement error, or, if measurably unequal, the elements or values ​​are close enough to be functionally equal to each other, as will be understood by one of ordinary skill in the art. For example, the term “about” as used herein includes the value and means within an acceptable deviation of a particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the error (e.g., limitations of the measurement system) associated with the measurement of the particular quantity. For example, “about” may mean within one or more standard deviations as understood by one of ordinary skill in the art, such as within ±30%, 20%, 10%, or 5% of the value. Furthermore, it should be understood that while a parameter may be described herein as having “about” a certain value, depending on the implementation, as understood by one of ordinary skill in the art, the parameter may be exactly a certain value or approximately a certain value within measurement error. Other uses of these terms and similar terms used to describe relationships between components should be interpreted in a similar manner.

[0030] Embodiments of this disclosure provide a semiconductor package designed to improve signal transmission efficiency, reliability, and manufacturability. The package may include a stack of semiconductor dies arranged in an interleaved configuration, which reduces space requirements and overall package height. Instead of conventional bonding wires, conductive patterns can be used to establish connections between the dies. These conductive patterns can directly contact the top and side surfaces of each die and have a shorter length compared to bonding wires, thereby reducing the overall electrical path. Eliminating the wire bonding process can further reduce the required package height and simplify manufacturing.

[0031] Advanced inkjet printing technology can be used to fabricate conductive patterns, which improves accuracy and scalability. Common conductive patterns can be incorporated to effectively manage voltage on the die, improving stability and reliability. Furthermore, semiconductor dies with different signal paths can be efficiently stacked in a single configuration, improving space utilization and reducing package area. Insulating patterns can be included to protect and stabilize the conductive patterns and maintain electrical integrity. Therefore, embodiments of this disclosure can improve the performance, reliability, and efficiency of semiconductor packaging.

[0032] Figure 1 This is a plan view illustrating a semiconductor package according to an embodiment of the present disclosure. Figure 2 yes Figure 1 Perspective view. Figure 3 It is along Figure 1 A sectional view taken from line I-I'. Figure 4 It is shown Figure 1 An enlarged view of the "EV1" section. Figure 5 It is shown Figure 3 An enlarged view of the "EV2" section. For a better understanding of this disclosure, see [the image / view]. Figure 1 and Figure 2 Some components of the semiconductor package are omitted.

[0033] Reference Figure 1 , Figure 2 and Figure 3 The semiconductor package 1000 may include a substrate 1, a semiconductor die stack ST, a mold layer 500, and external connection terminals 18.

[0034] Substrate 1 can be, for example, a printed circuit board (PCB). In embodiments, substrate 1 can be a redistributed substrate. When viewed in a plan view, substrate 1 can have, for example, a rectangular shape. In this specification, the first direction D1 and the second direction D2 can be directions parallel to the side edges of substrate 1. The first direction D1 and the second direction D2 can be orthogonal to each other. The third direction D3 can be a direction perpendicular to the top surface of substrate 1. In this specification, the first direction D1, the second direction D2, and the third direction D3 can be directions of the X-axis, Y-axis, and Z-axis, respectively.

[0035] Substrate 1 may include a plurality of substrate pads 10. The substrate pads 10 may be arranged in a second direction D2. The substrate pads 10 may include a first substrate pad 11, a second substrate pad 12, and a third substrate pad 13, which are arranged in the second direction D2. Although the first substrate pad 11, the second substrate pad 12, and the third substrate pad 13 are shown as arranged sequentially in the second direction D2, the arrangement may be varied depending on the implementation. The first substrate pad 11 and the second substrate pad 12 may each be a signal pad. The third substrate pad 13 may be a ground pad 13G or a power pad 13P. For example, the first substrate pad 11, the second substrate pad 12, the ground pad 13G, the first substrate pad 11, the second substrate pad 12, and the power pad 13P may be arranged sequentially in the second direction D2. In an embodiment, the ground pad 13G and the power pad 13P may be arranged alternately. In this specification, the signal pad may be used to transmit data or control signals. The ground pad can be maintained at 0V and can be used to provide a common reference potential to the circuit. The power pad can be used to apply a power supply voltage to the circuitry of the semiconductor die. The size of the third substrate pad 13 can be larger than the size of the first substrate pad 11 and the second substrate pad 12. For example, the width of the third substrate pad 13 in the second direction D2 can be greater than the width of the first substrate pad 11 in the second direction D2 and the width of the second substrate pad 12 in the second direction D2.

[0036] The semiconductor die stack ST may include a first semiconductor die 100, a second semiconductor die 200, a third semiconductor die 300, a fourth semiconductor die 400, a first conductive pattern 21, a second conductive pattern 22, and a third conductive pattern 30. In this specification, the third conductive pattern 30 may be referred to as the common conductive pattern 30.

[0037] The first semiconductor die 100 to the fourth semiconductor die 400 may include integrated memory circuitry. For example, the first semiconductor die 100 to the fourth semiconductor die 400 may be NAND flash memory chips. The first semiconductor die 100 and the third semiconductor die 300 may be configured to have the same signal path. The second semiconductor die 200 and the fourth semiconductor die 400 may be configured to have the same signal path. The signal paths in the first semiconductor die 100 and the third semiconductor die 300 may be different from the signal paths in the second semiconductor die 200 and the fourth semiconductor die 400. For example, the first semiconductor die 100 and the third semiconductor die 300 may have signal path 0, and the second semiconductor die 200 and the fourth semiconductor die 400 may have signal path 1. Signal path 0 and signal path 1 may refer to signal paths used for data transfer operations and data management operations in the NAND flash memory chip. Signal path 0 and signal path 1 may be used as logical signal paths and physical signal paths. A logical signal path may be a logical path used to manage data in the NAND memory chip. A physical signal channel can be a physical communication path, which is actually used to transmit data. Signal channel 0 and signal channel 1 can operate independently, and in this case, the performance of the semiconductor die stack (ST) can be improved through parallel processing techniques.

[0038] For example, according to an embodiment, the first semiconductor die 100, the second semiconductor die 200, the third semiconductor die 300, and the fourth semiconductor die 400 may each be integrated into an integrated memory circuit. For example, these semiconductor dies may be configured as NAND flash memory chips. The first semiconductor die 100 and the third semiconductor die 300 may share the same signal channel, while the second semiconductor die 200 and the fourth semiconductor die 400 may share different signal channels. The signal channels assigned to the first semiconductor die 100 and the third semiconductor die 300 may be different from those assigned to the second semiconductor die 200 and the fourth semiconductor die 400. For example, the first semiconductor die 100 and the third semiconductor die 300 may utilize signal channel 0, while the second semiconductor die 200 and the fourth semiconductor die 400 may utilize signal channel 1. Signal channels 0 and 1 represent paths for specific operations within the NAND flash memory chip. These paths can support data transfer and data management functions. Signal channels 0 and 1 can each be used as both logical signal channels and physical signal channels. A logic signal path refers to the logical representation used to manage data within a memory chip, while a physical signal path corresponds to the physical communication path that facilitates actual data transmission. Signal path 0 and signal path 1 can operate independently of each other. This independence allows semiconductor die stacks (ST) to utilize parallel processing techniques, which improves their overall performance.

[0039] The first semiconductor die 100, the second semiconductor die 200, the third semiconductor die 300, and the fourth semiconductor die 400 may be stacked in an alternating manner to form a stepped shape. The second semiconductor die 200 may be disposed on the first semiconductor die 100, offset from the first semiconductor die 100 in a first direction D1 and a second direction D2. As will be described below, the first semiconductor dies 100, 200, 300, and 400 may include pads, and the pads may be arranged with a first pitch in the second direction D2. For example, the pads may be arranged continuously and repeatedly in the second direction D2 at a first pitch. The length by which the second semiconductor die 200 is offset from the first semiconductor die 100 in the second direction D2 may be less than or approximately equal to half the first pitch. The third semiconductor die 300 may be disposed on the second semiconductor die 200, offset from the second semiconductor die 200 in the first direction D1 and the second direction D2. The third semiconductor die 300 may be offset from the second semiconductor die 200 by a length less than or approximately equal to half the first pitch in the second direction D2. The third semiconductor die 300 may be offset from the first semiconductor die 100 in the first direction D1 and may be positioned in substantially the same location as the first semiconductor die 100 in the second direction D2. That is, the third semiconductor die 300 may be stacked on top of the first semiconductor die 100 such that it is offset from the first semiconductor die 100 in the first direction D1 but has no displacement in the second direction D2. A fourth semiconductor die 400 may be disposed on top of the third semiconductor die 300 to be offset from both the first semiconductor die 100 and the third semiconductor die 300 in the first direction D1 and the second direction D2. The length of the fourth semiconductor die 400 offset from both the first semiconductor die 100 and the third semiconductor die 300 in the second direction D2 may be less than or approximately equal to half the first pitch. The fourth semiconductor die 400 may be offset from the second semiconductor die 200 in the first direction D1, and may be positioned in the second direction D2 at substantially the same location as the second semiconductor die 200. That is, the fourth semiconductor die 400 may be stacked on the second semiconductor die 200 such that it is offset from the second semiconductor die 200 in the first direction D1, but has no displacement in the second direction D2.

[0040] For example, according to an embodiment, the first semiconductor die 100, the second semiconductor die 200, the third semiconductor die 300, and the fourth semiconductor die 400 can be stacked in an interleaved arrangement to create a stepped configuration. The second semiconductor die 200 can be positioned on the first semiconductor die 100 and can be offset relative to the first semiconductor die 100 along both the first direction D1 and the second direction D2. As further described below, each of the first to fourth semiconductor dies 100, 200, 300, and 400 may include pads arranged along the second direction D2 and having a spacing defined by a first pitch. The degree of offset between the second semiconductor die 200 and the first semiconductor die 100 in the second direction D2 may be less than or approximately equal to half of the first pitch.

[0041] A third semiconductor die 300 may be stacked on top of a second semiconductor die 200 and may be offset from the second semiconductor die 200 in both the first direction D1 and the second direction D2. Similarly, the offset between the third semiconductor die 300 and the second semiconductor die 200 in the second direction D2 may be less than or approximately equal to half the first pitch. In the first direction D1, the third semiconductor die 300 may be offset from the first semiconductor die 100, while in the second direction D2, the third semiconductor die 300 may be positioned with substantially the same alignment as the first semiconductor die 100. For example, the third semiconductor die 300 may be stacked on top of the first semiconductor die 100 such that the third semiconductor die 300 is shifted in the first direction D1 but not in the second direction D2.

[0042] A fourth semiconductor die 400 may be positioned on top of a third semiconductor die 300 and may be offset from both the first semiconductor die 100 and the third semiconductor die 300 along both the first direction D1 and the second direction D2. The offset of the fourth semiconductor die 400 relative to the first semiconductor die 100 and the third semiconductor die 300 in the second direction D2 may also be less than or approximately equal to half the first pitch. In the first direction D1, the fourth semiconductor die 400 may be displaced from the second semiconductor die 200, but in the second direction D2, the fourth semiconductor die 400 may be substantially aligned with the second semiconductor die 200. Therefore, the fourth semiconductor die 400 may be stacked on the second semiconductor die 200, such that the fourth semiconductor die 400 may be offset in the first direction D1 but remain aligned in the second direction D2.

[0043] like Figure 2 and Figure 3As shown, the adhesive layer 40 can be inserted between the first semiconductor die 100 and the second semiconductor die 200, between the second semiconductor die 200 and the third semiconductor die 300, and between the third semiconductor die 300 and the fourth semiconductor die 400. The adhesive layer 40 can be, for example, a die-attach film (DAF). The adhesive layer 40 can include an adhesive polymer material. The adhesive layer 40 can have an area approximately equal to or greater than the area of ​​the bottom surface of each of the semiconductor dies 100, 200, 300, and 400.

[0044] The first semiconductor die 100 may include a first row of pads 110 arranged in a second direction D2. The first row of pads 110 may include a first signal pad 111 and a first voltage pad 112. The first voltage pad 112 may be a first ground pad 112G or a first power pad 112P. For example, the first ground pad 112G and the first power pad 112P may be alternately arranged in the second direction D2. The first signal pad 111 and the first voltage pad 112 may be spaced apart from each other by a first pitch in the second direction D2. The second semiconductor die 200 may include a second row of pads 210 arranged in the second direction D2. The second row of pads 210 may include a second signal pad 211 and a second voltage pad 212. The second voltage pad 212 may be a second ground pad 212G or a second power pad 212P. For example, the second ground pad 212G and the second power pad 212P may be alternately arranged in the second direction D2. The second signal pad 211 and the second voltage pad 212 may be spaced apart from each other by a first pitch in the second direction D2. The third semiconductor die 300 may include a third row of pads 310 arranged in the second direction D2. The third row of pads 310 may include a third signal pad 311 and a third voltage pad 312. The third voltage pad 312 may be a third ground pad 312G or a third power pad 312P. For example, the third ground pad 312G and the third power pad 312P may be alternately arranged in the second direction D2. The third signal pad 311 and the third voltage pad 312 may be spaced apart from each other by a first pitch in the second direction D2. The fourth semiconductor die 400 may include a fourth row of pads 410 arranged in the second direction D2. The fourth row of pads 410 may include a fourth signal pad 411 and a fourth voltage pad 412. The fourth voltage pad 412 can be a fourth ground pad 412G or a fourth power pad 412P. For example, the fourth ground pad 412G and the fourth power pad 412P can be alternately arranged on the second direction D2. The fourth signal pad 411 and the fourth voltage pad 412 can be spaced apart from each other by a first pitch on the second direction D2.

[0045] When in Figure 1When viewed in a plan view, the first substrate pad 11, the first signal pad 111, and the third signal pad 311 can be aligned with each other in the first direction D1. The second substrate pad 12, the second signal pad 211, and the fourth signal pad 411 can be aligned with each other in the first direction D1. The third substrate pad 13, together with the first voltage pad 112, the second voltage pad 212, the third voltage pad 312, and the fourth voltage pad 412, can be aligned with each other in the first direction D1. The first signal pad 111, the second signal pad 211, the third signal pad 311, and the fourth signal pad 411 can be arranged to form a serrated shape extending along the first direction D1. The first voltage pad 112, the second voltage pad 212, the third voltage pad 312, and the fourth voltage pad 412 can be arranged to form a serrated shape extending along the first direction D1. For example, the arrangement of the first signal pad 111, the second signal pad 211, the third signal pad 311 and the fourth signal pad 411 can form a zigzag pattern extending along the first direction D1, and similarly, the first voltage pad 112, the second voltage pad 212, the third voltage pad 312 and the fourth voltage pad 412 can also be configured as a zigzag pattern extending along the first direction D1.

[0046] Each of the first to third substrate pads 11, 12 and 13, the first to fourth signal pads 111, 211, 311 and 411, and the first to fourth voltage pads 112, 212, 312 and 412 may be formed of or include at least one of the following metallic materials: gold, copper, silver, aluminum, nickel and palladium.

[0047] Reference Figure 1 and Figure 2A first conductive pattern 21 can be disposed on a first substrate pad 11, a first signal pad 111, and a third signal pad 311 to connect the first substrate pad 11, the first signal pad 111, and the third signal pad 311 to each other. A second conductive pattern 22 can be disposed on a second substrate pad 12, a second signal pad 211, and a fourth signal pad 411 to connect the second substrate pad 12, the second signal pad 211, and the fourth signal pad 411 to each other. A third conductive pattern 30 can be disposed on a third substrate pad 13, a first voltage pad 112, a second voltage pad 212, a third voltage pad 312, and a fourth voltage pad 412 to connect the third substrate pad 13, the first voltage pad 112, the second voltage pad 212, the third voltage pad 312, and the fourth voltage pad 412 to each other. In other words, the third conductive pattern 30 can be connected together to the substrate 1 and the first semiconductor die 100, the second semiconductor die 200, the third semiconductor die 300, and the fourth semiconductor die 400. When viewed in a plan view, each of the first conductive pattern 21, the second conductive pattern 22, and the third conductive pattern 30 can be a straight line extending in the first direction D1. For example, when viewed in a plan view, the first conductive pattern 21, the second conductive pattern 22, and the third conductive pattern 30 can each extend as a straight line along the first direction D1, while being spaced apart from each other along the second direction D2. The first conductive pattern 21, the second conductive pattern 22, and the third conductive pattern 30 can be spaced apart from each other in the second direction D2. For example, the second conductive pattern 22 and the third conductive pattern 30 can be interposed between two first conductive patterns 21, which are adjacent to each other in the second direction D2.

[0048] Reference Figure 1 and Figure 4The first conductive pattern 21 may have a first width 21W in the second direction D2, the second conductive pattern 22 may have a second width 22W in the second direction D2, and the third conductive pattern 30 may have a third width 30W in the second direction D2. The third width 30W may be greater than the first width 21W and the second width 22W. Voltage pads (e.g., 312) may be spaced apart by a first pitch P1 from other pads (e.g., 311) adjacent to them in the second direction D2. The third width 30W may be less than the first pitch P1. The third width 30W may be greater than approximately half of the first pitch P1 minus the width of the voltage pad (e.g., 312) in the second direction D2 (e.g., 312W). Under given conditions, the third conductive pattern 30 having a third width 30W may contact all of the first voltage pad 112, the second voltage pad 212, the third voltage pad 312, and the fourth voltage pad 412, but may not contact other signal pads 111, 211, 311, and 411. Because the third conductive pattern 30 to which voltage is applied has a third width 30W greater than a certain width, the third conductive pattern 30 can have reduced resistance and can be used to deliver voltage more stably. For example, the third width 30W can be in the range of about 50 μm to about 100 μm.

[0049] For example, according to the implementation method, refer to Figure 1 and Figure 4 The first conductive pattern 21 may have a width specified as 21W in the second direction D2, the second conductive pattern 22 may have a width specified as 22W in the second direction D2, and the third conductive pattern 30 may have a width specified as 30W in the second direction (D2). Of these widths, the third width 30W may be greater than both the first width 21W and the second width 22W. Voltage pads (e.g., 312) may be spaced apart from adjacent pads (e.g., 311) in the second direction D2 by a first pitch P1. The third width 30W may be less than the first pitch P1, but greater than approximately half the first pitch P1 minus the width of the voltage pad (e.g., 312W). Under these conditions, a third conductive pattern 30 with a width of 30W can contact all voltage pads, including the first voltage pad 112, the second voltage pad 212, the third voltage pad 312, and the fourth voltage pad 412, while remaining non-contacting with signal pads 111, 211, 311, and 411. When its width exceeds a certain threshold, the third conductive pattern 30 can exhibit reduced resistance, thereby enabling more stable voltage delivery. For example, the third width 30W can be in the range of approximately 50μm to 100μm.

[0050] Signals included in signal channel 0 can be transmitted via a first conductive pattern 20 connecting the first substrate pad 11, the first signal pad 111, and the third signal pad 31. Signals included in signal channel 1 can be transmitted via a first conductive pattern 20 connecting the second substrate pad 12, the second signal pad 211, and the fourth signal pad 411. For example, signals associated with signal channel 0 can be transmitted via the first conductive pattern 20 connecting the first substrate pad 11, the first signal pad 111, and the third signal pad 311, and similarly, signals associated with signal channel 1 can be transmitted via the first conductive pattern 20 connecting the second substrate pad 12, the second signal pad 211, and the fourth signal pad 411. Ground voltage can be transmitted via a third conductive pattern 30 connecting the ground pad 13G, the first ground pad 112G, the second ground pad 212G, the third ground pad 312G, and the fourth ground pad 412G of substrate 1. The power supply voltage can be transmitted through the third conductive pattern 30 of the power pad 13P, the first power pad 112P, the second power pad 212P, the third power pad 312P, and the fourth power pad 412P connected to the substrate.

[0051] The first conductive pattern 21, the second conductive pattern 22, and the third conductive pattern 33 may be formed of or include at least one of a metallic material (e.g., silver, copper, gold, nickel, and palladium). The first conductive pattern 21, the second conductive pattern 22, and the third conductive pattern 33 may be, for example, a silver-containing metallic pattern.

[0052] Reference Figure 2 , Figure 3 and Figure 5The first conductive pattern 21 may also contact the top and side surfaces of the third semiconductor die 300, the second semiconductor die 200, the first semiconductor die 100, and the top surface of the substrate 1. The second conductive pattern 22 and the third conductive pattern 30 may also contact the top and side surfaces of the fourth semiconductor die 400, the third semiconductor die 300, the second semiconductor die 200, and the first semiconductor die 100. For example, the first semiconductor die 100 may further include a first semiconductor substrate 120 on which an integrated circuit is disposed, a first insulating layer 130, and interconnects. The first signal pad 111 and the first voltage pad 112 may be exposed from the first insulating layer 130. According to an embodiment, the interconnects can electrically connect the integrated circuit to the first signal pad 111 and the first voltage pad 112. The first insulating layer 130 may be formed of or comprise at least one of inorganic insulating materials (e.g., silicon oxide, silicon nitride, and silicon nitride). The interconnect may be formed of or comprise at least one of metallic materials (e.g., copper, aluminum, gold, and silver).

[0053] The second semiconductor die 200 may include a second semiconductor substrate 220, a second insulating layer 230, and interconnects.

[0054] The third semiconductor wafer 300 may include a third semiconductor substrate 320, a third insulating layer 330, and interconnects.

[0055] The fourth semiconductor die 400 may include a fourth semiconductor substrate 420, a fourth insulating layer 430, and interconnects. The semiconductor substrates 220, 320, and 420, insulating layers 230, 330, and 430, and interconnects of the second semiconductor die 200, the third semiconductor die 300, and the fourth semiconductor die 400 may have substantially the same function as the first semiconductor substrate 120, the first insulating layer 130, and interconnects of the first semiconductor die 100 described above, and may be formed of or include the same or similar materials.

[0056] Reference Figure 5 The first conductive pattern 21 can contact the top and side surfaces of the second insulating layer 230, the side surface 220S of the second semiconductor substrate 220, the side surface of the adhesive layer 40, and the top surface of the first insulating layer 130. The sum of the height of the second semiconductor die 200 and the thickness of the adhesive layer 40 can be less than the distance from the side surface of the second semiconductor die 200 to the first row of pads 110.

[0057] Return to reference Figure 3The molding layer 500 may cover the top surface of the substrate 1, the semiconductor die stack ST, and the conductive patterns 21, 22, 30. The molding layer 500 may include, for example, an epoxy molding compound (EMC).

[0058] The substrate 1 may include a lower pad 19 disposed on its bottom surface. The lower pad 19 may be electrically connected to a first substrate pad 11, a second substrate pad 12, and a third substrate pad 13 via interconnects in the substrate 1. External connection terminals 18 may be disposed on the lower pad 19. The external connection terminals 18 may be at least one of, for example, solder balls, solder bumps, and pillars. The external connection terminals 18 may be formed of or include at least one of metallic materials (e.g., silver and tin). This specification illustrates an example in which four semiconductor dies are stacked. However, the implementation is not limited thereto. For example, according to an embodiment, two, eight, or twelve semiconductor dies may be stacked in the manner described above.

[0059] In a semiconductor package according to embodiments of the present disclosure, conductive patterns, instead of bonding wires, can be used to connect a first semiconductor die to a fourth semiconductor die. The conductive patterns can directly contact the top and side surfaces of the semiconductor dies and can have a shorter length than bonding wires, thus reducing the overall length of the electrical path. Furthermore, since no space is required for the wire bonding process, the overall height of the semiconductor package can also be reduced.

[0060] For example, in a semiconductor package according to an embodiment of the present disclosure, conductive patterns are used instead of conventional bonding wires to establish connections between the first and fourth semiconductor dies. The conductive patterns can be designed to directly contact the top and side surfaces of each semiconductor die. Since the length of the conductive patterns is shorter than that of bonding wires, the overall length of the electrical path can be reduced. Furthermore, since the wire bonding process is eliminated, the space typically required by that process is no longer needed, thereby allowing for a reduction in the overall height of the semiconductor package.

[0061] In a semiconductor package according to embodiments of the present disclosure, semiconductor dies with different signal channels can be provided. The semiconductor dies can be stacked to form a serrated shape extending along a first direction, and a linear conductive pattern can be used to connect semiconductor dies having the same signal channel in the first direction. By stacking semiconductor dies with different signal channels in a single semiconductor die stack, the area of ​​the semiconductor package can be reduced. If semiconductor dies with different signal channels are stacked side-by-side and offset in the first direction, it is not desirable to connect the semiconductor dies to the linear conductive pattern because different signal channels are connected to the same conductive pattern. To utilize the conductive pattern, semiconductor dies can be provided to form two different die stacks, each of which contains a die with only signal channels 0 or 1, and in this case, the required area of ​​the semiconductor package can be increased.

[0062] In a semiconductor package according to embodiments of the present disclosure, a common conductive pattern (e.g., a third conductive pattern) can be provided to apply the same voltage to semiconductor dies with different signal channels. Since multiple semiconductor dies are connected to the common conductive pattern, voltage management can be effectively performed. Furthermore, the common conductive pattern can be configured to have a thickness greater than a certain thickness, and in this case, efficient voltage transfer can be achieved.

[0063] For example, in a semiconductor package according to an embodiment of the present disclosure, semiconductor dies with different signal channels may be included. These semiconductor dies may be arranged in a zigzag pattern extending along a first direction, enabling the use of a linear conductive pattern to connect dies sharing the same signal channel in that direction. By integrating semiconductor dies with different signal channels into a single stack configuration, the overall area of ​​the semiconductor package can be reduced. Conversely, if semiconductor dies with different signal channels are arranged side-by-side in an offset manner in the first direction, the use of a linear conductive pattern may become impractical, as it may unintentionally connect dies with different signal channels to the same conductive pattern. To address this issue, separate die stacks may be formed, where each stack contains a die dedicated to only one signal channel (e.g., channel 0 or channel 1). However, this approach may increase the area required for the semiconductor package.

[0064] In embodiments of this disclosure, a common conductive pattern (e.g., a third conductive pattern) can be provided to supply the same voltage across semiconductor dies with different signal channels. This common conductive pattern can facilitate efficient voltage management by connecting multiple semiconductor dies. Furthermore, the common conductive pattern can be designed to have a thickness greater than a specified minimum, thereby allowing for efficient and reliable voltage transfer.

[0065] Figure 6This is a cross-sectional view showing a semiconductor package according to an embodiment of the present disclosure. (Refer to...) Figure 6 The semiconductor package 1100 according to embodiments of the present disclosure may further include an electronic device 800. The electronic device 800 may be disposed on the substrate 1. Although Figure 6 An electronic device 800 is shown, but the number of electronic devices 800 can be increased. Electronic device 800 may include connection pads 810. Substrate 1 may include an upper pad 17 disposed on its top surface. Connection terminals 880 may be interposed between connection pads 810 and upper pad 17, and may include, for example, solder material. Electronic device 800 can be electrically connected via substrate 1 to first semiconductor dies 100, 200, 300, and 400. Electronic device 800 may be, for example, a memory controller. Alternatively, electronic device 800 may be a capacitor. A molding layer 500 may cover electronic device 800. Unlike the illustrated structure, in this embodiment, electronic device 800 may be attached to the bottom surface of substrate 1.

[0066] Figure 7 This is a plan view illustrating a semiconductor package according to an embodiment of the present disclosure. Figure 8 yes Figure 7 Perspective view. Figure 9 It is along Figure 7 A sectional view taken from line I-I'. Figure 10 It is shown Figure 9 An enlarged view of the "EV3" section.

[0067] Reference Figure 7 , Figure 8 , Figure 9 and Figure 10Insulating patterns 600 may be disposed on the side surfaces of semiconductor dies 100, 200, 300, and 400, respectively. Insulating patterns 600 may include polymer insulating materials. Insulating patterns 600 may include underfill materials or organic materials. For example, insulating patterns 600 may include epoxy resin. Insulating patterns 600 may serve as slope relief structures to reduce the slope of the side surfaces of each of semiconductor dies 100, 200, 300, and 400. First conductive patterns 21, second conductive patterns 22, and third conductive patterns 30 may be spaced apart from the side surfaces of the semiconductor dies, and insulating patterns 600 are interposed between the first conductive patterns 21, second conductive patterns 22, and third conductive patterns 30. Each of the first conductive patterns 21, second conductive patterns 22, and third conductive patterns 30 may be disposed on and in contact with the side surface 600S of the insulating pattern 600. The adhesion of the first conductive pattern 21, the second conductive pattern 22, and the third conductive pattern 30 to the insulating pattern 600 can be stronger than the adhesion of the first conductive pattern 21, the second conductive pattern 22, and the third conductive pattern 30 to the semiconductor substrate (e.g., 220). When viewed in a plan view, the insulating pattern 600 can be a linear pattern extending in the second direction D2. In an embodiment, the insulating pattern 600 can be configured to have a plurality of separate patterns that are locally formed to contact or be adjacent to the first conductive pattern 21, the second conductive pattern 22, and the third conductive pattern 30. Figure 10 As shown, the first angle 600A between the side surface 600S of the insulating pattern 600 and the top surface of the semiconductor die (e.g., 100) can be greater than about 0° and less than about 90°. For example, the first angle 600A can be in the range of about 30° to about 60°, however, it is not limited to this example. The width of the insulating pattern 600 in the first direction D1 can be greater than the height of the insulating pattern 600 in the third direction D3. That is, when viewed in a cross-sectional view, the insulating pattern 600 can have a shape similar to a right triangle with a base longer than its height. Although the side surfaces of the semiconductor dies 100, 200, 300, and 400 have a tilt angle of about 90°, the first conductive pattern 21, the second conductive pattern 22, and the third conductive pattern 30 are prevented from being cut at the steeply tilted areas between the semiconductor dies because an insulating pattern 600 with a gentle tilt angle is also provided. For example, the insulating pattern 600 may contact the side surface 220S of the second semiconductor substrate 220, the side surface of the second insulating layer 230, the side surface of the adhesive layer 40, and the top surface of the first insulating layer 130. In an embodiment, the slope of the side surface of the insulating pattern 600 may be less steep than the slope of the side surface of the second semiconductor die 200. In an embodiment, the insulating pattern 600 does not cover the pads (e.g., 110), thus exposing the pads.

[0068] Figure 11 This is a plan view illustrating a semiconductor package according to an embodiment of the present disclosure. Figure 12 yes Figure 11 Perspective view. Figure 13 It is shown Figure 11 An enlarged view of the "EV4" section. For ease of explanation, previous references can be omitted. Figures 8 to 10 Further description of the components and technologies described.

[0069] Reference Figures 11 to 13 When viewed in a plan view, the third conductive pattern 30 can be a linear pattern extending in a zigzag pattern along the first direction D1. That is, when viewed in a plan view, the third conductive pattern 30 can have multiple curved portions. For example... Figure 13 As shown, the third width 30W of the third conductive pattern 30 can be approximately equal to the first width 21W of the first conductive pattern 21 or the second width 22W of the second conductive pattern 22.

[0070] Figure 14 This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment of the present disclosure.

[0071] refer to Figure 14 A semiconductor die stack ST can be formed on substrate 1. The formation of the semiconductor die stack ST may include sequentially stacking first to fourth semiconductor dies 100, 200, 300, and 400 offset from each other. Next, an insulating pattern 600 can be formed by coating the side surfaces of each of the first to fourth semiconductor dies 100, 200, 300, and 400 with a polymer insulating material (e.g., an underfill material). A container 730 containing conductive material 700 can be prepared. The conductive material 700 can be a solid material in powder form or a fluid liquid material. The conductive material 700 can be sprayed through a first nozzle 710. The conductive material 700 can be sprayed onto the top and side surfaces of the semiconductor dies and can be cured to form the aforementioned conductive pattern. For example, the formation of the conductive pattern may include using inkjet printing technology. For example, silver nanoparticle ink can be printed to form a shape corresponding to the conductive pattern. A sintering process can then be performed, in which case the silver particles in the printed ink can bond to form the conductive pattern. The width of the conductive pattern can be determined by the diameter of the nozzle. For example, a first nozzle 710 connected to container 730 and having a small diameter can be used to form a first conductive pattern 21 and a second conductive pattern 22 having a small width. A third conductive pattern 30 having a large width can be formed by a second nozzle 720 having a diameter larger than that of the first nozzle 710. In an embodiment, the first conductive pattern 21, the second conductive pattern 22, and the third conductive pattern 30 can be formed using nozzles of the same diameter (e.g., see...). Figure 11 , Figure 12 and Figure 13 The first conductive pattern 21, the second conductive pattern 22, and the third conductive pattern 30 can be formed simultaneously or at different times.

[0072] Return to reference Figure 3 The molding layer 500 can be formed after the first conductive pattern 21, the second conductive pattern 22, and the third conductive pattern 30 are formed. External connection terminals 18 can be formed on the lower pad 19 of the substrate 1. As a result, a semiconductor package according to an embodiment of the present disclosure can be formed.

[0073] In the semiconductor package according to embodiments of the present disclosure, by using conductive patterns that connect semiconductor dies to each other, electrical paths can be shortened and the overall height of the package can be reduced. Since semiconductor dies with different signal channels are effectively stacked in a single stack and connected to each other, the package area can be reduced. Furthermore, a common conductive pattern can be used to efficiently perform voltage management within the semiconductor dies. As a result, signal transmission efficiency and reliability in the semiconductor package can be increased.

[0074] Although this disclosure has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims.

[0075] Cross-reference to related applications

[0076] This application claims priority to Korean Patent Application No. 10-2024-0116855, filed on August 29, 2024, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor package, comprising: Substrate; A first semiconductor die is disposed on the substrate; The second semiconductor die is disposed on the first semiconductor die; The third semiconductor die is disposed on the second semiconductor die; First conductive pattern; and Second conductive pattern, The second semiconductor die is stacked on top of the first semiconductor die and offset from the first semiconductor die in a first direction and a second direction perpendicular to each other. The third semiconductor die is stacked on the first semiconductor die and the second semiconductor die and is offset from the first semiconductor die and the second semiconductor die in the first direction. The first semiconductor die includes a first pad and a second pad, which are arranged continuously in the second direction. The second semiconductor die includes a third pad and a fourth pad, which are arranged continuously in the second direction. The third semiconductor die includes a fifth pad and a sixth pad, which are arranged continuously in the second direction. The first conductive pattern connects the first pad and the fifth pad. The second conductive pattern connects the second pad, the fourth pad, and the sixth pad, and The first conductive pattern and the second conductive pattern are spaced apart from the third pad.

2. The semiconductor package according to claim 1, wherein, Each of the first pad, the third pad, and the fifth pad is a signal pad. Each of the second pad, the fourth pad, and the sixth pad is one of a power pad and a ground pad, and The second pad, the fourth pad, and the sixth pad are the same type of pad.

3. The semiconductor package according to claim 1, wherein, The third semiconductor die is disposed at the same position as the first semiconductor die in the second direction.

4. The semiconductor package according to claim 1, wherein, The first pad and the second pad are repeatedly arranged in the second direction with a first pitch, and The second semiconductor die is spaced from the first semiconductor die by a distance less than or equal to half of the first pitch in the second direction.

5. The semiconductor package according to claim 1, wherein, The thickness of the second conductive pattern is greater than the thickness of the first conductive pattern.

6. The semiconductor package according to claim 1, wherein, The first conductive pattern is in contact with the top surface of the second semiconductor die.

7. The semiconductor package according to claim 1, wherein, The first conductive pattern is in contact with the side surface of the second semiconductor die.

8. The semiconductor package according to claim 1, wherein, The first conductive pattern is in contact with the top surface of the second semiconductor die and is spaced apart from the side surface of the second semiconductor die.

9. The semiconductor package according to claim 1, wherein, When viewed in a plan view, the first conductive pattern and the second conductive pattern have a straight line shape extending in the first direction.

10. The semiconductor package according to claim 1, wherein, When viewed in a plan view, the first conductive pattern has a line shape extending in the first direction. The second conductive pattern has a serrated shape extending along the first direction.

11. The semiconductor package according to claim 1, further comprising: An insulating pattern is disposed on the side surface of the second semiconductor die. The first conductive pattern and the second conductive pattern are in contact with the insulating pattern.

12. The semiconductor package of claim 11, wherein, The insulating pattern includes epoxy resin.

13. The semiconductor package of claim 11, wherein, The slope of the side surface of the insulating pattern is not as steep as the slope of the side surface of the second semiconductor die.

14. The semiconductor package according to claim 1, further comprising: A fourth semiconductor die is disposed on the third semiconductor die. The fourth semiconductor die includes a seventh pad and an eighth pad arranged continuously in the second direction; and A third conductive pattern connects the third pad and the seventh pad to each other. The third conductive pattern is disposed between the first conductive pattern and the second conductive pattern. The second conductive pattern is in contact with the eighth pad.

15. The semiconductor package of claim 14, wherein the fourth semiconductor die is stacked on the third semiconductor die and offset from the third semiconductor die in the first direction and the second direction, and The fourth semiconductor die is disposed at the same position as the second semiconductor die in the second direction.

16. A semiconductor package, comprising: Substrate; A first semiconductor die is disposed on the substrate; The second semiconductor die is disposed on the first semiconductor die; First conductive pattern; and Second conductive pattern, The second semiconductor die is stacked on top of the first semiconductor die and offset from the first semiconductor die in a first direction and a second direction perpendicular to each other. The substrate includes a first substrate pad and a second substrate pad spaced apart from each other in the second direction. The first semiconductor die includes a first insulating layer and a first pad exposed from the first insulating layer. The second semiconductor die includes a second pad. The first conductive pattern is disposed between the first substrate pad and the first pad. The second conductive pattern is disposed between the second substrate pad and the second pad. The second conductive pattern is spaced apart from the first conductive pattern, and The second conductive pattern is in contact with the top surface of the first insulating layer.

17. The semiconductor package of claim 16, wherein, The second conductive pattern is in contact with the side surface of the second semiconductor die.

18. The semiconductor package of claim 16, further comprising: An insulating pattern is disposed on the side surface of the second semiconductor die. The second conductive pattern is in contact with the side surface of the insulating pattern.

19. The semiconductor package of claim 18, wherein, The first insulating layer comprises an inorganic insulating material. The insulating pattern comprises polymer insulating material.

20. A semiconductor package, comprising: Substrate; Semiconductor dies are stacked and disposed on the substrate; A molding layer that covers the top and side surfaces of the semiconductor die stack; First conductive pattern; Second conductive pattern; and Third conductive pattern, The semiconductor die stack includes: A first semiconductor die is disposed on the substrate; The second semiconductor die is disposed on the first semiconductor die; A third semiconductor die is disposed on the second semiconductor die; and A fourth semiconductor die is disposed on the third semiconductor die. The second semiconductor die and the fourth semiconductor die are offset from the first semiconductor die in a first direction and a second direction, respectively. The third semiconductor die is offset from the first semiconductor die in the first direction and is positioned at the same location as the first semiconductor die in the second direction. The fourth semiconductor die is offset from the second semiconductor die in the first direction and is positioned at the same location as the second semiconductor die in the second direction. The first semiconductor die includes a first signal pad and a first voltage pad spaced apart from each other in the second direction. The second semiconductor die includes a second signal pad and a second voltage pad spaced apart from each other in the second direction. The third semiconductor die includes a third signal pad and a third voltage pad spaced apart from each other in the second direction. The fourth semiconductor die includes a fourth signal pad and a fourth voltage pad spaced apart from each other in the second direction. The first conductive pattern connects the first signal pad and the third signal pad. The second conductive pattern connects the second signal pad and the fourth signal pad, and The third conductive pattern connects the first voltage pad, the second voltage pad, the third voltage pad, and the fourth voltage pad.

21. A method for forming a semiconductor package, comprising: Semiconductor die stacks are formed by stacking multiple semiconductor dies on a substrate. The semiconductor dies are stacked sequentially and offset from each other; An insulating pattern is formed by coating the side surface of a semiconductor die with a polymer insulating material; Conductive patterns are formed by spraying conductive material onto the top and side surfaces of the semiconductor die using a nozzle and sintering the conductive material.

22. The method according to claim 21, wherein, The conductive material is silver nanoparticle ink, and the sintering combines the silver particles of the silver nanoparticle ink to form the conductive pattern.

23. The method according to claim 21, wherein, The conductive pattern is formed using inkjet printing technology.

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