Wafer back N + layout structure of reverse conducting insulated gate bipolar transistor RC-IGBT

Abstract

The invention discloses a wafer back N + layout structure of a reverse conducting insulated gate bipolar transistor (RC-IGBT). N + doped regions are arranged on the back surface of the wafer, the N + doped regions are arranged according to a periodic hexagonal close packing structure formed by a plurality of regular hexagonal units, and the N + doped regions are formed in the regular hexagonal units and are uniformly distributed on the back surface of the wafer in a regular periodic manner. Through the geometric constraint of the hexagonal unit area and the periodic structure, the area proportion of the N + region and the P + region on the back surface of the wafer is balanced, so that the current diffusion and conduction path of the device in an IGBT mode and a diode mode is improved. According to the layout, the N + / P + proportion can be optimized, the current distribution uniformity is improved, the local current density peak value is reduced, the reverse recovery loss and the turn-on voltage rebound phenomenon are reduced, and the overall conduction characteristic and the device reliability are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing, and specifically to a wafer backside N+ layout structure for a reverse-conducting insulated-gate bipolar transistor (RC-IGBT). Background Technology

[0002] An insulated-gate bipolar transistor (IGBT) is a composite power semiconductor device that combines the characteristics of a metal-oxide-semiconductor field-effect transistor (MOSFET) and a bijunction transistor (BJT). Due to its low drive power consumption, high voltage withstand capability, and excellent conduction performance, it has been widely used in high-voltage, high-power electronic equipment such as inverters, motor drives, power conversion, rail transportation, and new energy vehicles. Traditional IGBTs can only achieve unidirectional conduction during operation. In the gate-off state, it is equivalent to a PNP transistor structure with an open base region, thus it cannot provide a reverse freewheeling path. An external anti-parallel diode is required to meet the reverse current flow requirement in the circuit.

[0003] As modern power electronic systems evolve towards higher power density, miniaturization, and higher efficiency, the traditional dual-chip solution of IGBT + anti-parallel diode has gradually revealed problems such as large package area, high parasitic parameters, and increased losses. To improve overall system performance, a reverse-conducting IGBT (RC-IGBT) that integrates the anti-parallel diode function into the IGBT chip has emerged. This device simultaneously possesses IGBT mode and diode mode on the same silicon chip, achieving automatic switching between forward and reverse current conduction, significantly reducing system cost and improving electrical performance.

[0004] However, despite the more advanced overall structure of RC-IGBTs, their performance remains highly dependent on the layout of the N+ and P+ regions on the back side of the wafer. Existing RC-IGBT devices commonly employ strip-shaped or island-shaped N+ layouts (as shown in the PDF file). Figure 1 , Figure 2 (As shown), however, these traditional structures have limitations in terms of doping depth, dose distribution, and layout geometry, which can easily lead to problems such as uneven current distribution, high local current density, and severe heat accumulation, thereby affecting device reliability. In addition, an unreasonable N+ / P+ ratio may also cause phenomena such as turn-on voltage bounce, increased reverse recovery loss, or high on-state voltage drop, making it difficult for the device to achieve a good balance of characteristics between diode mode and IGBT mode.

[0005] like Figure 1 and Figure 2As shown, existing research has attempted to improve RC-IGBT performance by modifying the geometry and distribution strategy of the N+ region on the back side, such as by adopting alternating periodic layouts and regionalized N+ distributions. However, the following shortcomings still generally exist:

[0006] Strip-shaped or island-shaped structures are prone to current concentration areas, which is not conducive to reducing the peak reverse recovery current;

[0007] Traditional layouts have low shape freedom and are difficult to simultaneously achieve multiple objectives such as conduction voltage drop, softness, and robustness.

[0008] Excessive localized heating can induce lattice damage and accelerate device aging;

[0009] The turn-on conditions of the PN junction on the back side are significantly affected by the N+ geometric ratio, and the existing layout makes it difficult to achieve precise control.

[0010] Therefore, how to adopt a new layout structure in the N+ region on the back side to make the N+ ratio controllable, the current distribution uniform, the doping geometry stable, and at the same time take into account the feasibility of the process has become a key problem that the current RC-IGBT technology urgently needs to overcome. Summary of the Invention

[0011] To address the aforementioned issues, this invention provides a wafer-side N+ layout structure for a reverse-conducting insulated-gate bipolar transistor (RC-IGBT). This structure utilizes a hexagonal close-packed configuration to achieve precise control over the N+ ratio, significantly improve current and heat distribution, and suppress springback effects, thus offering a new structural design approach for enhancing the performance and reliability of RC-IGBTs.

[0012] This invention is achieved through the following technical solution: a wafer backside N+ layout structure for a reverse-conducting insulated-gate bipolar transistor (RC-IGBT), wherein an N+ doped region is provided on the wafer backside.

[0013] The N+ doped regions are arranged in a periodic hexagonal close-packed structure consisting of multiple regular hexagonal units.

[0014] Each of the aforementioned regular hexagonal units forms an N+ doped region inside, and multiple regular hexagonal units are uniformly distributed on the back side of the wafer.

[0015] The area ratio of N+ regions to P+ regions on the back side of the wafer is balanced by using a geometric periodic structure.

[0016] As a preferred technical solution, the side length of the regular hexagonal unit is 0.5–10 micrometers.

[0017] As a preferred technical solution, the spacing between adjacent regular hexagonal units is 0–5 micrometers.

[0018] As a preferred technical solution, the proportion of the N+ region on the back side of the wafer is controlled between 30% and 70% to simultaneously reduce the on-state voltage drop of the RC-IGBT and suppress reverse recovery loss in diode mode.

[0019] As a preferred technical solution, the hexagonal periodic layout makes the current distribution inside the device tend to be uniform, so as to reduce the peak value of local current density and reduce local thermal stress.

[0020] As a preferred technical solution, the hexagonal N+ unit is realized by photolithographic mask patterning and formed by ion implantation or diffusion process.

[0021] As a preferred technical solution, the multiple regular hexagonal units are arranged continuously in a periodic unit ring manner, so that the geometric doping structure on the back side of the wafer presents a periodic repeating unit array.

[0022] As a preferred technical solution, the hexagonal units are arranged in a equidistant distribution relative to any direction of the wafer's main plane, so that the hexagonal periodic structure maintains isotropy throughout the entire wafer area.

[0023] As a preferred technical solution, the N+ regular hexagonal unit is formed by mask patterning in one or more photolithography steps, and the dopant is activated by rapid thermal annealing to maintain the clarity of the doped contour of the hexagonal unit boundary.

[0024] An RC-IGBT device of the present invention includes an emitter region, a gate structure, a drift region, and an electrode structure disposed on the back side of a wafer, wherein the back side of the wafer adopts an N+ hexagonal doped layout structure.

[0025] The beneficial effects of this invention are as follows: This invention employs a periodic close-packed layout composed of multiple regular hexagonal units. By adjusting the area of ​​the hexagonal units and the unit spacing, a stable N+ occupancy region of 30%–70% can be achieved across the entire wafer. Compared to the difficulty in maintaining uniform occupancy due to traditional geometries, the layout of this invention naturally possesses isotropic properties and high fill efficiency, effectively suppressing turn-on voltage bounce caused by deviations in local PN junction turn-on conditions, thereby improving the consistency and controllability between device batches.

[0026] The highly symmetrical arrangement of the hexagonal cells results in a more balanced current-carrying path, allowing electrons and holes to form a more uniform path along the back electrode during conduction. This reduces the effective resistance between the collector and emitter, significantly improving the on-state voltage drop in IGBT mode. Simultaneously, the uniform N+ distribution provides a more controllable current-carrying region in diode mode, helping to reduce peak reverse recovery current and reverse recovery charge, thereby enhancing high-speed switching characteristics.

[0027] Because the hexagonal structure has multi-directional symmetry in the planar direction, its periodic array can ensure that the internal current of the device exhibits an approximately uniform two-dimensional diffusion distribution under reverse freewheeling and high-speed switching conditions. Compared with strip structures, which are prone to current concentration at the edges, this invention can significantly reduce local hot spots and electric field peaks, suppress current crowding effects, and enhance the stability of the device under high-power conditions.

[0028] In traditional back-side layouts, the N+ region often suffers from more severe localized heat generation due to uneven shape or proportion. This invention utilizes a regular hexagonal cell array to achieve a uniform distribution of heat conduction and current carrying paths on the back side of the wafer, resulting in a smoother temperature field on both the chip surface and back side, reducing localized thermal gradients. This effectively reduces lattice damage caused by thermal stress, delays device aging, and improves long-term reliability.

[0029] Uniform doping distribution can effectively reduce local current surges during transient operation. When the device is under harsh conditions such as hard turn-on and hard turn-off under inductive load, the structure of this invention can disperse the peak current density, reduce the risk of triggering parasitic transistors or local thermal breakdown due to transient large current, and improve the device's short-circuit withstand capability and overall robustness.

[0030] The regular boundaries of the hexagonal unit cells make the doping profile formed by ion implantation, diffusion, and subsequent rapid thermal annealing clearer, reducing the problem of blurred doping distribution in traditional irregular structures. This feature not only ensures the accuracy of design parameters but also improves the repeatability of doping depth and concentration, facilitating large-scale production.

[0031] The hexagonal array of this invention can be realized using conventional photolithography masks without the need for special etching or complex patterning processes. The formation of the N+ region is still accomplished through standard ion implantation or diffusion processes, thus exhibiting good process compatibility and manufacturability, helping to reduce manufacturing costs while avoiding additional impacts on the front-end device structure. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of the strip-shaped N+ layout on the back side of an RC-IGBT wafer in the prior art;

[0034] Figure 2This is a schematic diagram of the island-shaped N+ layout on the back side of an RC-IGBT wafer in the prior art;

[0035] Figure 3 This is a schematic diagram of the hexagonal N+ layout on the back side of the RC-IGBT wafer according to an embodiment of the present invention;

[0036] Figure 4 This is an enlarged version of the structure with different hexagonal units and spacing in the hexagonal unit ring layout of the embodiments of the present invention. Figure 1 ;

[0037] Figure 5 This is an enlarged version of the structure with different hexagonal units and spacing in the hexagonal unit ring layout of the embodiments of the present invention. Figure 2 . Detailed Implementation

[0038] All features disclosed in this specification, or all steps in all disclosed methods or processes, may be combined in any way, except for mutually exclusive features and / or steps.

[0039] Any feature disclosed in this specification (including any appended claims, abstract, and drawings) may be replaced by other equivalent or similar features for a similar purpose, unless specifically stated otherwise. That is, unless specifically stated otherwise, each feature is merely one example of a series of equivalent or similar features.

[0040] like Figures 3-5 As shown, this invention provides a wafer backside N+ doped layout structure for a reverse-conducting insulated-gate bipolar transistor (RC-IGBT). By constructing periodically arranged regular hexagonal N+ regions on the wafer backside, comprehensive optimization of the device's conduction characteristics, reverse recovery characteristics, and current distribution is achieved. This embodiment, in conjunction with device structural features, doping design, photolithography patterning process, ion implantation and diffusion steps, and annealing activation details, fully discloses the technical solution of this invention, enabling those skilled in the art to implement this invention.

[0041] In the actual fabrication process, a semiconductor substrate with the main IGBT structure is first provided. The emitter region, gate structure, drift region, gate oxide layer, trench structure, and metal interconnects are formed using conventional front-end processes. This substrate is typically made of silicon, and a drift layer with a specific thickness and doping concentration is pre-formed according to the device's voltage rating to meet the operating requirements of the RC-IGBT under high voltage and high current conditions. After completing the front-end structure, the wafer is flipped to allow for the patterning and doping formation of the N+ region on the back side.

[0042] In order to realize the hexagonal close-packed N+ region layout structure proposed in this invention on the back side of the wafer, photoresist is first coated on the back side of the wafer, and the pre-designed regular hexagonal mask pattern is transferred to the photoresist layer by photolithography equipment.

[0043] The side length of the hexagonal cells is set according to the device current density requirements, typically controlled within the range of 0.5 micrometers to 10 micrometers, ensuring both pattern resolution and sufficient conductive area. The spacing between adjacent hexagonal cells is designed to be 0 to 5 micrometers, thereby adjusting the uniformity of current distribution according to the proportion. The hexagonal cells are arranged at equal intervals, ensuring that the mask pattern exhibits consistent periodicity and isotropy across the entire wafer plane, thus guaranteeing a regular distribution of N+ doped regions on the wafer.

[0044] After the photolithographic pattern is formed, N-type impurities, such as arsenic or phosphorus, are implanted into the exposed area using an ion implantation device to form the desired high-concentration N+ doped structure in the regular hexagonal region.

[0045] The ion implantation energy and dose are determined based on the required doping depth and concentration. Generally, implantation parameters that can achieve a shallow, high-concentration profile are selected to ensure good ohmic contact between the N+ region and the metal electrode on the back side. If further improvement in doping uniformity is required, multiple implantation steps can be used to make the doping transition at the hexagonal pattern boundary smoother.

[0046] This invention supports the formation of hexagonal N+ regions through one or more photolithography steps combined with multiple doping. By segmenting the formation of doping profiles with different depths or concentrations, it helps to further improve the electric field distribution.

[0047] After ion implantation, the wafer undergoes rapid thermal annealing (RTA) in an inert atmosphere, typically at temperatures between 900°C and 1100°C. This short-term high-temperature process activates the implanted impurity atoms, allowing them to occupy lattice positions and recover from the lattice damage caused by the implantation.

[0048] Because this invention uses a regular hexagonal shape, the diffusion behavior after annealing is more controllable, and the hexagonal boundary can be kept clear, which helps to reduce doping profile distortion and avoid the problem of uncontrolled doping diffusion caused by traditional complex patterns.

[0049] With the formation of the hexagonal N+ region, a periodic N+ / P+ distribution structure is formed between the doped and undoped regions. By adjusting the area and spacing of the hexagon, the proportion of the N+ region on the back side of the wafer can be controllably adjusted within the range of 30% to 70%.

[0050] A higher N+ ratio results in a smaller forward voltage drop, while a slightly lower N+ ratio can reduce the reverse recovery charge in diode mode.

[0051] Therefore, this invention uses designable geometric parameters to control the trade-off characteristics of the device between IGBT mode and diode mode, making the device more efficient and stable under high voltage, high frequency and high current environments.

[0052] After forming the hexagonal N+ region, a metal layer is deposited on the back side of the wafer using sputtering or evaporation processes to form the back electrode structure of the device. The metal material can be aluminum, titanium / nickel / silver multilayer structures, or other commonly used ohmic contact metals, so that the metal and the hexagonal N+ region form a low contact resistance interface.

[0053] Because the symmetrical structure of the hexagonal N+ region makes the current distribution under the metal electrode tend to be uniform, local hot spots are less likely to appear on the back side of the device during high current conduction or reverse freewheeling, reducing the risk of thermal stress and local overheating failure.

[0054] In the final RC-IGBT device, the hexagonal N+ layout structure of the present invention serves as a key current channel under the wafer back electrode, and together with the emitter region, gate structure, drift region and P+ back region, constitutes a complete reverse conduction IGBT device.

[0055] Thanks to the isotropic current diffusion capability provided by the hexagonal close-packed structure, the device can achieve a lower forward voltage drop in IGBT mode, a smaller reverse recovery loss in diode mode, and maintain high softness characteristics during high-frequency switching.

[0056] Uniform current and heat distribution further enhance the device's short-circuit capability, shock resistance, and long-term reliability, making the solution of this invention suitable for high-voltage and high-power scenarios such as industrial inverter drives, vehicle power systems, and energy conversion equipment.

[0057] This embodiment uses standard semiconductor processes such as photolithography, ion implantation, diffusion, and annealing to form a periodic regular hexagonal N+ doped structure on the back side of the wafer. The overall structure is simple, highly feasible, and can significantly improve the electrical performance and reliability of RC-IGBT.

[0058] The technical solution of this invention can improve performance without increasing process complexity, and has important engineering application value for RC-IGBT structure design.

[0059] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions conceived without inventive effort should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A wafer backside N+ layout structure for a reverse-conducting insulated-gate bipolar transistor (RC-IGBT), characterized in that: The back side of the wafer has an N+ doped region. The N+ doped regions are arranged in a periodic hexagonal close-packed structure consisting of multiple regular hexagonal units. Each of the aforementioned regular hexagonal units forms an N+ doped region inside, and multiple regular hexagonal units are uniformly distributed on the back side of the wafer. The area ratio of N+ regions to P+ regions on the back side of the wafer is balanced by using a geometric periodic structure.

2. The wafer backside N+ layout structure of the reverse-conducting insulated-gate bipolar transistor RC-IGBT according to claim 1, characterized in that: The side length of the regular hexagonal unit is 0.5–10 micrometers.

3. The wafer backside N+ layout structure of the reverse-conducting insulated-gate bipolar transistor RC-IGBT according to claim 1, characterized in that: The spacing between adjacent regular hexagonal cells is 0–5 micrometers.

4. The wafer backside N+ layout structure of the reverse-conducting insulated-gate bipolar transistor RC-IGBT according to claim 1, characterized in that: The proportion of the N+ region on the back side of the wafer is controlled between 30% and 70% to simultaneously reduce the on-state voltage drop of the RC-IGBT and suppress reverse recovery losses in diode mode.

5. The wafer backside N+ layout structure of the reverse-conducting insulated-gate bipolar transistor RC-IGBT according to claim 1, characterized in that: The hexagonal periodic layout makes the current distribution inside the device more uniform, thereby reducing local current density peaks and local thermal stress.

6. The wafer backside N+ layout structure of the reverse-conducting insulated-gate bipolar transistor RC-IGBT according to claim 1, characterized in that: The hexagonal N+ cells are realized through photolithographic mask patterns and formed through ion implantation or diffusion processes.

7. The wafer backside N+ layout structure of the reverse-conducting insulated-gate bipolar transistor RC-IGBT according to claim 1, characterized in that: Multiple hexagonal units are arranged continuously in a periodic unit ring pattern, so that the geometric doping structure on the back side of the wafer presents a periodic repeating unit array.

8. The wafer backside N+ layout structure of the reverse-conducting insulated-gate bipolar transistor RC-IGBT according to claim 1, characterized in that: The hexagonal units are arranged at equal intervals relative to any direction of the wafer's main plane, so that the hexagonal periodic structure maintains isotropic properties throughout the entire wafer area.

9. The wafer backside N+ layout structure of the reverse-conducting insulated-gate bipolar transistor RC-IGBT according to claim 1, characterized in that: The N+ regular hexagonal cells are formed by mask patterning in one or more photolithography steps, and the dopant is activated by rapid thermal annealing to maintain the clarity of the doped contour of the hexagonal cell boundaries.

10. An RC-IGBT device, comprising an emitter region, a gate structure, a drift region, and an electrode structure disposed on the back side of a wafer, characterized in that, The back side of the wafer adopts an N+ hexagonal doped layout structure as described in any one of claims 1 to 9.

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