Integrated circuit device

Abstract

An integrated circuit device may include: at least one first semiconductor pattern extending in a vertical direction; a first source / drain region connected to an end portion of the at least one first semiconductor pattern in a first horizontal direction; at least one second semiconductor pattern extending in a vertical direction and spaced apart from the at least one first semiconductor pattern in a second horizontal direction; a second source / drain region connected to an end portion of the at least one second semiconductor pattern in the first horizontal direction; and an insulating wall in an insulating wall opening extending in a first horizontal direction, between the at least one first semiconductor pattern and the at least one second semiconductor pattern, and between the first source / drain region and the second source / drain region.

Description

[0001] Cross-references to related applications

[0002] This application is based on Korean Patent Application No. 10-2024-0126166, filed with the Korean Intellectual Property Office on September 13, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] One or more embodiments of this disclosure relate to an integrated circuit device, and more specifically, to an integrated circuit device including a field-effect transistor. Background Technology

[0004] With the increasing demand for miniaturization, multifunctionality, and high performance in electronic products, there is a need for high-capacity integrated circuit devices. To achieve high-capacity integrated circuit devices, increased integration density is required. For example, improving device performance may necessitate finding a new approach by modifying the device's structure. Consequently, integrated circuit devices may need to include transistors with novel structures. Summary of the Invention

[0005] One or more embodiments of this disclosure provide an integrated circuit device having transistors, including multi-gate metal-oxide-semiconductor field-effect transistors (MOSFETs) with improved operating characteristics.

[0006] According to one aspect of this disclosure, an integrated circuit device may include: at least one first semiconductor pattern extending in a vertical direction; a first source / drain region connected to an end of the at least one first semiconductor pattern in a first horizontal direction; at least one second semiconductor pattern extending in a vertical direction and spaced apart from the at least one first semiconductor pattern in a second horizontal direction; a second source / drain region connected to the end of the at least one second semiconductor pattern in the first horizontal direction; and an insulating wall located in an insulating wall opening extending in the first horizontal direction, between the at least one first semiconductor pattern and the at least one second semiconductor pattern, and between the first source / drain region and the second source / drain region. The insulating wall may include: an insulating wall liner on the inner wall of the insulating wall opening; a buried insulating layer on the insulating wall liner; and an insulating wall cover layer located on the upper surface of the insulating wall liner and the upper surface of the buried insulating layer in the insulating wall opening.

[0007] According to another aspect of this disclosure, an integrated circuit device may include: a first active region and a second active region extending in a first horizontal direction; an insulating wall extending in the first horizontal direction between the first active region and the second active region; at least one first semiconductor pattern located on the first active region and extending in a vertical direction; a first source / drain region located on the first active region and connected to the at least one first semiconductor pattern; at least one second semiconductor pattern located on the second active region and extending in a vertical direction; and a second source / drain region located on the second active region and connected to the at least one second semiconductor pattern. The insulating wall may include: a buried insulating layer extending in the first horizontal direction between the at least one first semiconductor pattern and the at least one second semiconductor pattern and between the first source / drain region and the second source / drain region; an insulating wall liner on the sidewall of the buried insulating layer; and an insulating wall cover layer on the upper surface of the insulating wall liner and the upper surface of the buried insulating layer.

[0008] According to another aspect of this disclosure, an integrated circuit device may include: a substrate including a first active region and a second active region; at least one first semiconductor pattern and at least one second semiconductor pattern disposed on the first active region and the second active region, respectively; a first source / drain region and a second source / drain region located on the first active region and the second active region, respectively, and connected to the at least one first semiconductor pattern and the at least one second semiconductor pattern, respectively; and an insulating wall located between the first active region and the second active region, and between the at least one first semiconductor pattern and the at least one second semiconductor pattern. The insulating wall may include: a buried insulating layer; an insulating wall pad on the sidewall of the buried insulating layer; and

[0009] An insulating wall covering layer is located on the upper surface of the insulating wall liner and on the upper surface of the buried insulating layer. Attached Figure Description

[0010] The embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 This is a schematic layout diagram of an integrated circuit device according to an embodiment;

[0012] Figure 2 It is shown Figure 1 A three-dimensional diagram illustrating the schematic structure of an integrated circuit device;

[0013] Figure 3A It is along Figure 1 A cross-sectional view of an integrated circuit device taken by line A-A';

[0014] Figure 3B It is along Figure 1A cross-sectional view of an integrated circuit device taken by line B-B';

[0015] Figure 3C It is along Figure 1 A cross-sectional view of an integrated circuit device taken by line C-C';

[0016] Figure 4A yes Figure 3B A magnified view of region CX1;

[0017] Figure 4B yes Figure 3C A magnified view of region CX2;

[0018] Figure 5A , Figure 5B and Figure 5C This is a cross-sectional view showing an integrated circuit device according to an embodiment; and

[0019] Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10 , Figure 11 , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B , Figure 14C , Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B , Figure 17C , Figure 18A , Figure 18B , Figure 18C , Figure 19A , Figure 19B , Figure 19C , Figure 20A , Figure 20B and Figure 20C This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to an embodiment. Detailed Implementation

[0020] Hereinafter, embodiments of the technical concept of the present invention will be described in detail with reference to the accompanying drawings.

[0021] Figure 1 This is a schematic layout diagram of an integrated circuit device according to an embodiment. Figure 2 It is shown Figure 1 A three-dimensional view illustrating the schematic structure of the integrated circuit device 100. Figure 3A It is along Figure 1 A cross-sectional view of integrated circuit device 100 taken by line A-A'. Figure 3B It is along Figure 1 A cross-sectional view of the integrated circuit device 100 taken by line B-B'. Figure 3C It is along Figure 1 A cross-sectional view of the integrated circuit device 100 taken by line C-C'. Figure 4A yes Figure 3B A magnified view of region CX1. Figure 4B yes Figure 3C A magnified view of region CX2.

[0022] Reference Figure 1 , Figure 2 , Figure 3A , Figure 3B , Figure 3C , Figure 4A and Figure 4B The integrated circuit device 100 may include a plurality of unit transistors CTRs arranged at a first vertical level and a front wiring structure FS arranged at a second vertical level higher than the first vertical level and electrically connected to the plurality of unit transistors CTRs.

[0023] Multiple unit transistors (CTRs) can be used to construct various types of logic cells included in logic circuits. In an embodiment, integrated circuit device 100 can be configured to construct logic cells including multi-bridge channel field-effect transistor (MBCFET) devices.

[0024] The integrated circuit device 100 may include a first active region RX1 and a second active region RX2, which respectively protrude from the upper surface of a substrate 110 and extend in a first horizontal direction X. In an embodiment, the first active region RX1 and the second active region RX2 may protrude from the upper surface of the substrate 110 in a vertical direction Z and extend in the first horizontal direction X. A device isolation layer 112 may be disposed within a device isolation trench 112T extending into the substrate 110, and at least a portion of the sidewalls of the first active region RX1 and the second active region RX2 may contact the device isolation layer 112.

[0025] In one embodiment, the first active region RX1 and the second active region RX2 can be a p-channel metal-oxide-semiconductor (PMOS) transistor region or an n-channel metal-oxide-semiconductor (NMOS) transistor region. In another embodiment, the plurality of unit transistors CTRs disposed on or within the first active region RX1 and the second active region RX2 can include PMOS transistors. In yet another embodiment, the plurality of unit transistors CTRs disposed within the first active region RX1 can include PMOS transistors, and the plurality of unit transistors CTRs disposed within the second active region RX2 can include NMOS transistors.

[0026] In one embodiment, an insulating wall DW extending in the first horizontal direction X can be disposed between the first active region RX1 and the second active region RX2. The insulating wall DW can be disposed within an insulating wall opening DWH extending into the substrate 110 between the first active region RX1 and the second active region RX2. The bottom surface of the insulating wall opening DWH can be disposed at the same vertical height LV0 as the bottom surface of the device isolation trench 112T.

[0027] The insulating wall DW may include an insulating wall liner D10 disposed on the inner wall of the insulating wall opening DWH, a buried insulating layer D20 filling the insulating wall opening DWH on the insulating wall liner D10, and an insulating wall covering layer D30 disposed on the buried insulating layer D20 and the insulating wall liner D10.

[0028] In an embodiment, the insulating wall liner D10 may include a low-k dielectric layer (e.g., a dielectric constant in the range of 2.0 to 3.0). For example, the insulating wall liner D10 may include at least one of silicon oxide carbon, silicon nitride carbon, and silicon oxynitride carbon. In an embodiment, the buried insulating layer D20 may include at least one of silicon nitride, silicon oxide, and silicon oxynitride. In an embodiment, the insulating wall capping layer D30 may include at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0029] In an embodiment, the insulating wall DW may include a first portion DWU1 and a second portion DWU2 having different heights in the vertical direction Z. For example, the first portion DWU1 of the insulating wall DW may have an upper surface disposed at a first vertical height LV1, and the second portion DWU2 of the insulating wall DW may have an upper surface disposed at a second vertical height LV2, which is lower than the first vertical height LV1. For example, the second vertical height LV2 may be lower than the first vertical height LV1 relative to the height LV0 of the bottom surface of the device isolation trench 112T.

[0030] In one embodiment, the upper portion of the insulating wall DW can be removed using a recessing process, which reduces the height of the upper surface of the second portion DWU2 of the insulating wall DW. In this recessing process, a portion of the insulating wall cover layer D30 within the second portion DWU2 of the insulating wall DW can be removed, leaving the insulating wall cover layer D30 only in the first portion DWU1 of the insulating wall DW. As a result, the insulating wall cover layer D30 may not be present in the second portion DWU2 of the insulating wall DW. For example, the upper surface of the insulating wall cover layer D30 within the first portion DWU1 of the insulating wall DW may be located at a first vertical height LV1, while the upper surface of the second portion DWU2 of the insulating wall DW may be located at a second vertical height LV2.

[0031] Multiple unit transistors (CTRs) can be arranged on a first active region RX1 and a second active region RX2, and can be arranged separately from each other in a first horizontal direction X and a second horizontal direction Y. The multiple unit transistors (CTRs) may include multiple semiconductor patterns NS arranged separately from each other in a vertical direction Z, multiple gate structures GS surrounding the multiple semiconductor patterns NS and extending in a second horizontal direction Y, and multiple source / drain regions SD arranged on both sides of the multiple gate structures GS.

[0032] In an embodiment, each of the plurality of semiconductor patterns NS may include a group IV semiconductor such as Si or Ge, a group IV-IV compound semiconductor such as SiGe or SiC, or a group II-IV compound semiconductor such as GaAs, InAs, or InP.

[0033] In an embodiment, each of the plurality of semiconductor patterns NS can be arranged on a sidewall of the insulating wall DW and can be separated from each other in the vertical direction Z on the sidewall of the insulating wall DW. In an embodiment, the plurality of semiconductor patterns NS arranged on the first active region RX1 (or at a position perpendicularly overlapping with the first active region RX1) (here, each of the plurality of semiconductor patterns NS arranged on the first active region RX1 is referred to as the first semiconductor pattern NS1) can be arranged on the first sidewall DWS1 of the insulating wall DW and contact the first sidewall DWS1. In an embodiment, the plurality of semiconductor patterns NS arranged on the second active region RX2 (or at a position perpendicularly overlapping with the second active region RX2) (here, each of the plurality of semiconductor patterns NS arranged on the second active region RX2 is referred to as the second semiconductor pattern NS2) can be arranged on the second sidewall DWS2 of the insulating wall DW opposite to the first sidewall DWS1 of the insulating wall DW and contact the second sidewall DWS2.

[0034] In one embodiment, the end of the first semiconductor pattern NS1 in the second horizontal direction Y can contact the first sidewall DWS1 of the insulating wall DW, and the end of the second semiconductor pattern NS2 in the second horizontal direction Y can contact the second sidewall DWS2 of the insulating wall DW. In another embodiment, the first semiconductor pattern NS1 and the second semiconductor pattern NS2 can be arranged to be separated from each other in the second horizontal direction Y with the insulating wall DW located therebetween, and can contact the sidewall of the insulating wall pad D10.

[0035] In an embodiment, the upper surface of the insulating wall pad D10 included in the first portion DWU1 of the insulating wall DW can be arranged at a higher vertical height than the upper surface of the uppermost semiconductor pattern NS among the plurality of semiconductor patterns NS. The upper surface of the insulating wall pad D10 included in the first portion DWU1 of the insulating wall DW can be arranged at a lower vertical height than the upper surface of the insulating wall cover layer D30 included in the first portion DWU1 of the insulating wall DW. Therefore, the insulating wall pad D10 may not be exposed to the etching atmosphere during the insulating layer formation process for forming the device isolation layer 112 and / or the subsequent etch-back process.

[0036] In an embodiment, a plurality of gate structures GS may extend in the second horizontal direction Y to surround a plurality of semiconductor patterns NS on the first sidewall DWS1 and the second sidewall DWS2 of the insulating wall DW, and may be arranged separately from each other in the first horizontal direction X.

[0037] In an embodiment, each of the plurality of gate structures GS may include a gate electrode 122 and a gate insulating layer 124. For example, the gate electrode 122 may extend in a second horizontal direction Y to surround a plurality of semiconductor patterns NS, and the gate insulating layer 124 may be disposed between the gate electrode 122 and each of the semiconductor patterns NS.

[0038] In some embodiments, the gate insulating layer 124 may be disposed on the upper surface, sidewalls, and bottom surface of a plurality of semiconductor patterns NS, and may conformally extend to the first sidewall DWS1 and the second sidewall DWS2 of the insulating wall DW. In some embodiments, a portion of the gate insulating layer 124 may be disposed on the upper surface of the first portion DWU1 of the insulating wall DW (e.g., the upper surface of the insulating wall capping layer D30). Another portion of the gate insulating layer 124 may be disposed on the upper surface of the first active region RX1, the upper surface of the second active region RX2, and the upper surface of the device isolation layer 112.

[0039] In embodiments, the gate electrode 122 may include doped polysilicon, metal, conductive metal nitride, conductive metal carbide, conductive metal silicide, or combinations thereof. For example, the gate electrode 122 may include, but is not limited to, Al, Cu, Ti, Ta, W, Mo, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, or combinations thereof. In embodiments, the gate electrode 122 may include a work function metal layer and an interstitial metal layer. The work function metal layer may include at least one metal selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. The interstitial metal layer may include a W layer or an Al layer. In embodiments, the gate electrode 122 may include, but is not limited to, a stacked structure of TiAlC / TiN / W layers, a stacked structure of TiN / TaN / TiAlC / TiN / W layers, or a stacked structure of TiN / TaN / TiN / TiAlC / TiN / W layers.

[0040] In an embodiment, the gate insulating layer 124 may include a silicon oxide layer, a silicon oxynitride layer, a high-k dielectric layer having a higher dielectric constant than the silicon oxide layer, or a combination thereof. The high-k dielectric layer may include a metal oxide or a metal oxynitride. For example, the high-k dielectric layer that can be used as the gate insulating layer 124 may include, but is not limited to, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof.

[0041] In one embodiment, the capping layer 126 may extend along a second horizontal direction Y on the upper surface of the gate electrode 122. In another embodiment, the capping layer 126 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), silicon carbonitride (SiC) x N y ), silicon carbonitride (SiO) x C y N z (or a combination thereof).

[0042] In one embodiment, spacer 128 may be further disposed on two sidewalls of the gate structure GS at a height higher than the uppermost semiconductor pattern NS. Spacer 128 may extend along a second horizontal direction Y on the two sidewalls of the gate electrode 122 at a height higher than the uppermost semiconductor pattern NS (or on the sidewalls of the gate insulating layer 124 at a height higher than the uppermost semiconductor pattern NS), and capping layer 126 may be disposed on the upper surface of spacer 128. In some other embodiments, spacer 128 may extend to the two sidewalls of capping layer 126 and the two sidewalls of gate electrode 122.

[0043] In an embodiment, the upper surface of the gate structure GS can be positioned at a vertical height higher than the bottom surface of the insulating wall capping layer D30 of the insulating wall DW. The upper surface of the first portion DWU1 of the insulating wall DW surrounded by the gate electrode 122 can be positioned at a first vertical height LV1, and the upper surface of the first portion DWU1 of the insulating wall DW can have a substantially flat profile.

[0044] The source / drain region SD can be formed on both sides of the gate structure GS. The source / drain region SD can be disposed on the recess RS formed in the first active region RX1 and the second active region RX2, and can be connected to both ends of a plurality of semiconductor patterns NS. The source / drain region SD can have an upper surface disposed at the same height as or higher than the upper surface of the uppermost semiconductor pattern NS.

[0045] In embodiments, the source / drain region SD may include, but is not limited to, a doped SiGe layer, a doped Ge layer, a doped SiC layer, or a doped InGaAs layer. In embodiments, the source / drain region SD may include multiple semiconductor layers with different compositions. For example, the source / drain region SD may include a lower semiconductor layer, an upper semiconductor layer, and a cover semiconductor layer stacked in sequence. For example, the lower semiconductor layer, the upper semiconductor layer, and the cover semiconductor layer may each include SiC and have different Si and C contents.

[0046] In an embodiment, the second portion DWU2 of the insulating wall DW can be arranged between the source / drain region SD (here referred to as the first source / drain region SD1) placed on the first active region RX1 and the source / drain region SD (here referred to as the second source / drain region SD2) placed on the second active region RX2.

[0047] In an embodiment, a portion of the second part of the insulating wall DW disposed between the first source / drain region SD1 and the second source / drain region SD2 can be removed by a recessing process. Therefore, the second part of DWU2 may include a circular upper surface.

[0048] In an embodiment, the first source / drain region SD1 and the second source / drain region SD2 may have upper surfaces at a vertical height higher than the upper surface of the second portion DWU2 of the insulating wall DW disposed therebetween. Furthermore, the upper portions of the first source / drain region SD1 and the second source / drain region SD2 may be arranged to be separated from each other by a relatively small spacing w2 at a vertical height higher than the upper surface of the second portion DWU2 of the insulating wall DW (see...). Figure 16B ).

[0049] In an embodiment, the source / drain region SD may include a lower sidewall SD_L that contacts the second portion DWU2 of the insulating wall DW, and an upper sidewall SD_U that is disposed at a vertical height higher than the lower sidewall SD_L and does not contact the second portion DWU2 of the insulating wall DW. In some embodiments, such as Figure 4A As shown, the upper sidewall SD_U of the source / drain region SD may protrude outward relative to the lower sidewall SD_L of the source / drain region SD. For example, the upper sidewall SD_U of the source / drain region SD may be separated from the lower sidewall SD_L of the source / drain region SD by a first distance d1 in the second horizontal direction Y. In an embodiment, the first distance d1 may be in the range of about 0.1 nanometers to about 5 nanometers.

[0050] In some embodiments, the insulating wall DW may have a first width w1 in the second horizontal direction Y, the first width w1 being in the range of approximately 15 nanometers to approximately 25 nanometers. Therefore, the first source / drain region SD1 and the second source / drain region SD2 may be separated from each other by the insulating wall DW.

[0051] Depending on the conductivity type of the semiconductor pattern NS and / or the conductivity type of the source / drain regions SD, the unit transistor CTR can be an NMOS transistor or a PMOS transistor.

[0052] An etch stop layer 142 covering the upper surface of the source / drain region SD can be disposed between the gate structures GS, and an inter-gate insulating layer 144 filling the space between the gate structures GS can be formed on the etch stop layer 142. The etch stop layer 142 may comprise silicon oxide or silicon oxynitride, and the inter-gate insulating layer 144 may comprise silicon oxide or silicon oxynitride. The etch stop layer 142 may also be conformally disposed on the upper surface of the second portion DWU2 of the insulating wall DW, which is disposed between the first source / drain region SD1 and the second source / drain region SD2.

[0053] A gate dicing insulating layer (GCI) can be disposed along a second horizontal direction Y on the sidewall of the gate structure GS. The GCI can fill the interior of the gate dicing region GCIH formed by removing portions of the gate structure GS, etch stop layer 142, and inter-gate insulating layer 144. In an embodiment, the bottom of the GCI can extend to a height lower than the bottom surface of the gate electrode 122 and can have a downwardly tapering shape. The bottom of the GCI can be surrounded by a device isolation layer 112. The upper surface of the GCI can be arranged to be coplanar with the upper surface of the capping layer 126.

[0054] The upper insulating layer 146 may be disposed on the gate cleaved insulating layer GCI and the inter-gate insulating layer 144. The upper insulating layer 146 may comprise silicon oxide or silicon oxynitride.

[0055] The first contact 152 and the first via 154 can be disposed on the source / drain region SD through the upper insulating layer 146 and the inter-gate insulating layer 144. The second contact 156 and the second via 158 can be disposed on the gate electrode 122 through the upper insulating layer 146 and the capping layer 126. In an embodiment, the first contact 152 and the first via 154 can be formed in a stacked structure, such that the first contact 152 is electrically connected to the source / drain region SD and the first via 154 is disposed on the first contact 152. The second contact 156 and the second via 158 can be formed in a stacked structure, such that the second contact 156 is electrically connected to the gate electrode 122 and the second via 158 is disposed on the second contact 156. In other embodiments, the second via 158 can be omitted, and the upper surface of the first via 154 can be arranged to be coplanar with the upper surface of the second contact 156 and the upper surface of the upper insulating layer 146. In other embodiments, the first through-hole 154 and the second through-hole 158 may be omitted, the first contact 152 may pass through the upper insulating layer 146, and the upper surface of the first contact 152 may be arranged to be coplanar with the upper surface of the second contact 156 and the upper surface of the upper insulating layer 146.

[0056] The front wiring structure FS, electrically connected to the unit transistor CTR, can be disposed on the upper insulating layer 146. The front wiring structure FS may include a front via FSV, a front wiring layer FSW, and a front insulating layer FSI. In an embodiment, the front wiring layer FSW may be a wiring pattern disposed at one vertical height, or it may be a wiring pattern disposed at two or more vertical heights.

[0057] In an embodiment, the front insulating layer FSI may include an oxide layer, a nitride layer, a low-k dielectric layer having a dielectric constant of about 2.2 to about 2.4, or a combination thereof. The front wiring layer FSW may be electrically connected to the first via 154 and the second via 158. The front via FSV may be electrically connected to the front wiring layer FSW, and the sidewalls of the front wiring layer FSW and the front via FSV may be surrounded by the front insulating layer FSI.

[0058] As integrated circuit devices continue to shrink in scale, integrated circuit devices in which semiconductor patterns are arranged with insulating walls between them have been proposed. When the insulating walls are formed first, followed by the semiconductor patterns, residues from the semiconductor patterns may not be completely removed, potentially degrading device performance. To address this issue, a method has been proposed in which insulating walls are formed between the semiconductor patterns after they have been formed first. However, this method may lead to increased width deviations in the semiconductor patterns, which could adversely affect device performance.

[0059] However, in the integrated circuit device 100 according to the embodiment, an insulating wall DW comprising an insulating wall pad D10, a buried insulating layer D20, and an insulating wall capping layer D30 is first formed. Next, a recess process is performed on the upper portion of the insulating wall DW to reduce its height, followed by the growth of the source / drain regions SD. The insulating wall pad D10 may comprise a low-k dielectric material, which helps prevent coupling effects and improves the threshold voltage control characteristics of the integrated circuit device 100. Furthermore, the insulating wall capping layer D30 may cover the upper surface of the insulating wall pad D10, thereby protecting the insulating wall DW from potential loss or damage that may occur when the upper surface of the insulating wall pad D10 is exposed during the formation of the device isolation layer 112. Therefore, the integrated circuit device 100 can have excellent electrical performance. The structure and material of the insulating wall DW in the integrated circuit device 100 eliminate the need for a second wall, as relying solely on a single insulating wall DW solves the prior art challenges associated with wall formation.

[0060] Figure 5A , Figure 5B and Figure 5C This is a cross-sectional view showing an integrated circuit device 100A according to an embodiment.

[0061] Reference Figure 5A , Figure 5B and Figure 5CThe integrated circuit device 100A may include a plurality of unit transistors CTRs arranged at a first vertical height, a front wiring structure FS arranged at a second vertical height higher than the first vertical height and electrically connected to the plurality of unit transistors CTRs, and a back wiring structure BS arranged at a third vertical height lower than the first vertical height and electrically connected to the plurality of unit transistors CTRs.

[0062] The back-side wiring structure BS may include a power delivery network for applying power supply voltage and ground voltage to the unit transistor CTR. The back-side wiring structure BS may include a back-side via BSV, a back-side wiring layer BSW, and a back-side insulating layer BSI.

[0063] In integrated circuit device 100A, substrate 110 can be removed (see...). Figure 3A Furthermore, a substrate insulating layer 116 can be disposed at the location where the substrate 110 is removed. A back contact 160 can be disposed through the substrate insulating layer 116 and electrically connected to the bottom surface of the source / drain region SD. A back wiring structure BS can be disposed on the bottom surface of the substrate insulating layer 116 and the device isolation layer 112, and a back via BSV or back wiring layer BSW can be disposed electrically connected to the back contact 160.

[0064] In some embodiments, a placeholder may be further arranged between the bottom surface of the source / drain region SD and the back contact 160. However, the technical concept of the present invention is not limited thereto.

[0065] Figures 6A to 20C This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device 100 according to an embodiment.

[0066] Specifically, Figure 6A , Figure 7A , Figure 9A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A and Figure 20A Is along Figure 1 The cross-sectional diagram corresponding to the section intercepted by line A-A'. Figure 6B , Figure 7B , Figure 8A , Figure 9B , Figure 10 , Figure 11 , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B and Figure 20B Is along Figure 1 The cross-sectional diagram corresponding to the section intercepted by line B-B', and Figure 6C , Figure 7C , Figure 8B , Figure 13C , Figure 14C , Figure 15C , Figure 16C , Figure 17C , Figure 18C , Figure 19C and Figure 20C Is along Figure 1 The cross-sectional diagram corresponding to the section cut by line C-C'.

[0067] Reference Figures 6A to 6C A sacrificial layer 210 and a semiconductor layer NSL can be alternately and sequentially formed on the upper surface of the substrate 110 to form a semiconductor layer stack NSS. Subsequently, a mask pattern M10 can be formed on the semiconductor layer stack NSS, and a portion of the semiconductor layer stack NSS and a portion of the substrate 110 can be removed to form a device isolation trench 112T and an insulating wall opening DWH extending into the substrate 110.

[0068] In an embodiment, the device isolation trench 112T and the insulating wall opening DWH can be arranged alternately and can extend in the first horizontal direction X.

[0069] In an embodiment, the insulating wall opening DWH may have a first width w01 in the second horizontal direction Y, ranging from about 15 nanometers to about 25 nanometers. The portion of the substrate 110 disposed on the first side of the insulating wall opening DWH is referred to as the first active region RX1, and the portion of the substrate 110 disposed on the second side of the insulating wall opening DWH is referred to as the second active region RX2. Therefore, the first active region RX1 and the second active region RX2 may be arranged to extend in the first horizontal direction X with the insulating wall opening DWH between them.

[0070] In this embodiment, the sacrificial layer 210 and the semiconductor layer NSL can be formed by an epitaxial growth process. In this embodiment, the sacrificial layer 210 and the semiconductor layer NSL can comprise materials that are etch-selective relative to each other. For example, the sacrificial layer 210 and the semiconductor layer NSL can each comprise a single-crystal layer of a group IV semiconductor, a group IV-IV compound semiconductor, or a group III-V compound semiconductor. The sacrificial layer 210 and the semiconductor layer NSL can comprise different materials. For example, the sacrificial layer 210 can comprise SiGe, and the semiconductor layer NSL can comprise single-crystal silicon.

[0071] In the embodiments, the epitaxial process can be vapor phase epitaxy (VPE), chemical vapor deposition (CVD) processes, such as ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy, or a combination thereof. In the epitaxial process, liquid or gaseous precursors can be used as precursors required to form the sacrificial layer 210 and the semiconductor layer NSL.

[0072] Reference Figures 7A to 7C An insulating wall liner layer D10L can be formed on the inner wall of the device isolation trench 112T and the insulating wall opening DWH. The insulating wall liner layer D10L can have a relatively small thickness and can be conformally arranged on the surface of the semiconductor layer stack NSS.

[0073] In this embodiment, the insulating wall liner layer D10L can be formed using a low-k dielectric material via a CVD process or an atomic layer deposition (ALD) process. For example, the insulating wall liner layer D10L can be formed using at least one of silicon carbon oxide, silicon carbon nitride, and silicon carbon oxynitride.

[0074] Reference Figure 8A and Figure 8B An embedded insulating layer D20 can be formed on the inner wall of the insulating wall opening DWH.

[0075] In one embodiment, a buried insulating layer D20 may be formed on an insulating wall liner layer D10L to fill the interior of an insulating wall opening DWH. An etch-back process may be performed on the upper part of the buried insulating layer D20, so that the upper surface of the buried insulating layer D20 may be disposed at a height lower than the upper surface of the semiconductor layer stack NSS.

[0076] In the embodiments, the buried insulating layer D20 can be formed using at least one of silicon nitride, silicon oxide, and silicon oxynitride through a CVD process or an ALD process.

[0077] Reference Figure 9A and Figure 9B The process can be etched back to expose the upper surface of the buried insulating layer D20, thereby leaving the portion of the insulating wall liner layer D10L within the insulating wall opening DWH and re-exposing the surface of the semiconductor layer stack NSS.

[0078] The portion of the insulating wall liner layer D10L that remains within the insulating wall opening DWH can be referred to as the insulating wall liner D10.

[0079] The insulating wall pad D10 may have an upper surface arranged to be coplanar with the upper surface of the buried insulating layer D20. After the etching process, the upper surfaces of the insulating wall pad D10 and the buried insulating layer D20 may be arranged at a height higher than the upper surface of the uppermost semiconductor layer NSL and lower than the upper surface of the uppermost sacrificial layer 210.

[0080] In some embodiments, after the etch-back process, the upper surfaces of the insulating wall pad D10 and the buried insulating layer D20 can be arranged to be coplanar with the upper surface of the uppermost semiconductor layer NSL.

[0081] Reference Figure 10 A capping layer D30L can be formed to cover the semiconductor layer stack NSS. The capping layer D30L can be arranged to cover the upper surface of the insulating wall pad D10 and the buried insulating layer D20 on the upper part of the insulating wall opening DWH. In an embodiment, the capping layer D30L may include at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0082] Reference Figure 11 An etch-back process can be performed on the capping layer D30L to re-expose the surface of the semiconductor layer stack NSS, while leaving only a portion of the capping layer D30L on the upper part of the insulating wall opening DWH.

[0083] In this case, a portion of the cover layer D30L remaining on the upper part of the insulating wall opening DWH can be referred to as the insulating wall cover layer D30. The insulating wall liner D10, the buried insulating layer D20, and the insulating wall cover layer D30 can be arranged within the insulating wall opening DWH to form an integrated wall structure, and can be collectively referred to as the insulating wall DW.

[0084] In an embodiment, the interior of the insulating wall opening DWH may be filled with the insulating wall DW, and the device isolation trench 112T may not be filled.

[0085] Reference Figure 12A and Figure 12B Device isolation layer 112 can be formed within device isolation trench 112T.

[0086] In some embodiments, an insulating layer may be formed on the inner wall of the device isolation trench 112T and on the semiconductor layer stack NSS, and the upper portion of the insulating layer may be etched back to leave the device isolation layer 112 on the inner wall of the device isolation trench 112T. During the process of forming the insulating layer on the semiconductor layer stack NSS and / or the process of etching back the insulating layer, the upper surface of the insulating wall pad D10 may be covered by the insulating wall capping layer D30, thus preventing exposure to the outside or the etching atmosphere. Therefore, damage or loss of the insulating wall pad D10 can be prevented during the process of forming the insulating layer and / or the process of etching back the insulating layer.

[0087] Reference Figures 13A to 13C It can remove the mask pattern M10 (see Figure 12A ).

[0088] During or after removing the mask pattern M10, a portion of the upper part of the insulating wall capping layer D30 can be removed. As a result, the upper surface of the insulating wall capping layer D30 can be arranged at the same height as the upper surface of the semiconductor layer stack NSS (or the upper surface of the uppermost sacrificial layer 210).

[0089] Subsequently, a sacrificial gate structure 230 can be formed on the substrate 110, covering a semiconductor layer stack NSS and extending in the second horizontal direction Y. The sacrificial gate structure 230 may include a sacrificial gate insulating layer 232, a sacrificial gate electrode 234, and a sacrificial capping layer 236. In an embodiment, the sacrificial gate electrode 234 may be formed using polysilicon. The sacrificial capping layer 236 may be formed using silicon nitride.

[0090] In one embodiment, the sacrificial gate insulating layer 232 may comprise silicon oxide obtained by performing a thermal oxidation process on the surface of the semiconductor layer stack NSS. In other embodiments, the sacrificial gate insulating layer 232 may comprise silicon oxide formed by performing a CVD process or an ALD process on the surface of the semiconductor layer stack NSS.

[0091] In one embodiment, after the sacrificial gate structure 230 is formed on the semiconductor layer stack NSS, the sacrificial gate structure 230 can be used as an etch mask to remove the uppermost sacrificial layer 210 and expose the upper surface of the uppermost upper semiconductor layer NSL.

[0092] Reference Figures 14A to 14C Spacers 128 can be formed on the upper surface and sidewalls of the sacrificial gate structure 230. Spacers 128 can be formed using silicon nitride.

[0093] Reference Figures 15A to 15C A recessed process can be performed on the portion of the insulating wall DW that is arranged at a vertical height higher than the top semiconductor layer NSL and protrudes upward from the top semiconductor layer NSL, thereby reducing the height of the upper part of the insulating wall DW.

[0094] In an embodiment, during the recess process, the insulating wall capping layer D30 on the upper part of the insulating wall DW can be removed, resulting in a reduction in the height of the upper surface of the insulating wall DW. The portion of the insulating wall DW whose height is reduced due to the recess process is referred to as the second portion DWU2, and the portion of the insulating wall DW covered by the sacrificial gate structure 230 that has not undergone the recess process and whose height remains the same is referred to as the first portion DWU1. The upper surface of the second portion DWU2 can be arranged at a lower height than the upper surface of the first portion DWU1. For example, the upper surface of the first portion DWU1 covered by the sacrificial gate structure 230 can be arranged at a first vertical height LV1, and the upper surface of the second portion DWU2 can be arranged at a second vertical height LV2, which is lower than the first vertical height LV1.

[0095] Subsequently, a portion of the semiconductor layer stack NSS between the sacrificial gate structures 230 can be removed to form a recess RS. The recess RS can extend into portions of the first active region RX1 and the second active region RX2.

[0096] In the process of removing a portion of the semiconductor layer stack NSS, a portion of the upper part of the insulating wall DW, such as the upper part of the second portion DWU2, can be removed. As a result of this process, the second portion DWU2 may include a circular upper surface, and the upper surface of the second portion DWU2 may be at a lower height than the upper surface of the first portion DWU1. For example, the upper surface of the first portion DWU1, covered by the sacrificial gate structure 230, may be at a first vertical height LV1, and the upper surface of the second portion DWU2 may be at a second vertical height LV2, which is lower than the first vertical height LV1.

[0097] According to the embodiment, because the second portion DWU2 of the insulating wall DW has a relatively small height in the process of removing a portion of the semiconductor layer stack NSS, the process of removing a portion of the semiconductor layer stack NSS within the recess RS can be precisely controlled.

[0098] Reference Figures 16A to 16C Source / drain regions SD can be formed on the upper surface of the substrate 110 exposed on both sides of the sacrificial gate structure 230 to fill the interior of the recessed RS.

[0099] In this embodiment, the source / drain region SD can be formed by epitaxially growing semiconductor material from the surfaces of the sacrificial layer 210, the semiconductor layer NSL, and the substrate 110. The source / drain region SD may include at least one of an epitaxially grown Si layer, an epitaxially grown SiC layer, an epitaxially grown SiGe layer, and an epitaxially grown SiP layer.

[0100] In this embodiment, the source / drain region SD (hereinafter referred to as the first source / drain region SD1) arranged on the first active region RX1 and the source / drain region SD (hereinafter referred to as the second source / drain region SD2) arranged on the second active region RX2 can be separated from each other in the second horizontal direction Y, with the second portion DWU2 of the insulating wall DW located therebetween. The upper portions of the first source / drain region SD1 and the second source / drain region SD2 can be separated from each other by a relatively small gap w2 at a vertical height higher than the upper surface of the second portion DWU2 of the insulating wall DW.

[0101] In an embodiment, the source / drain region SD may include a lower sidewall SD_L that contacts the second portion DWU2 of the insulating wall DW, and an upper sidewall SD_U that is arranged at a vertical height higher than the lower sidewall SD_L and does not contact the second portion DWU2 of the insulating wall DW.

[0102] In some embodiments, the upper sidewall SD_U of the source / drain region SD may protrude outward relative to the lower sidewall SD_L of the source / drain region SD. For example, the upper sidewall SD_U of the source / drain region SD may be separated from the lower sidewall SD_L of the source / drain region SD by a first distance d1 in the second horizontal direction Y. In embodiments, the first distance d1 may be in the range of about 0.1 nanometers to about 5 nanometers.

[0103] In some embodiments, the insulating wall DW may have a first width w1 in the second horizontal direction Y, the first width w1 being in the range of about 15 nanometers to about 25 nanometers. Because the upper sidewall SD_U of the source / drain region SD protrudes outward (or grows laterally) relative to the lower sidewall SD_L by a relatively small first distance d1, the first source / drain region SD1 and the second source / drain region SD2 will not merge with each other during the epitaxial growth process.

[0104] Reference Figures 17A to 17C This can form an etch stop layer 142 and an inter-gate insulating layer 144 covering the source / drain regions SD.

[0105] The etch stop layer 142 can conformally cover the first source / drain region SD1 and the second source / drain region SD2, and a portion of the etch stop layer 142 can be disposed on the upper surface of the second portion DWU2 of the insulating wall DW.

[0106] During or after the formation of the inter-gate insulating layer 144, an insulating structure IB can be formed covering the end of the semiconductor layer stack NSS in the first horizontal direction X.

[0107] Reference Figures 18A to 18C The sacrificial gate structure 230 can be removed, and a gate space GSS can be formed. The sacrificial layer 210 exposed to the gate space GSS can be removed to expose the upper and lower surfaces of the semiconductor layer NSL. The process for removing the sacrificial layer 210 can be a wet etching process that utilizes the etch selectivity between the sacrificial layer 210 and the semiconductor layer NSL.

[0108] In an embodiment, the semiconductor layer NSL exposed after the removal of the sacrificial layer 210 may be referred to as the semiconductor pattern NS. The semiconductor layer NSL included at the end of the semiconductor layer stack NSS along the first horizontal direction X may be referred to as the edge semiconductor pattern NS_E. The edge semiconductor pattern NS_E may be arranged adjacent to the insulating structure IB.

[0109] Reference Figures 19A to 19C It can be done in the space where the sacrificial gate structure 230 has been removed (i.e., Figure 18AA gate insulating layer 124 and a gate electrode 122 are formed in the gate space (GSS) shown. The gate electrode 122, the gate insulating layer 124 and the capping layer 126 can be collectively referred to as the gate structure GS, and can surround a plurality of semiconductor patterns NS that are spaced apart from each other in the vertical direction Z and extend in the second horizontal direction Y.

[0110] Since the spacer 128 is arranged on the uppermost semiconductor pattern NS, the portion of the gate electrode 122 arranged at a height higher than the uppermost semiconductor pattern NS can have a smaller width (e.g., the width in the first horizontal direction X) than the portion of the gate electrode 122 arranged between two adjacent semiconductor patterns NS.

[0111] Subsequently, a capping layer 126 can be formed on the upper surface of the gate electrode 122. In an embodiment, the capping layer 126 can be arranged to contact the sidewall of the inter-gate insulating layer 144.

[0112] Reference Figures 20A to 20C A portion of the gate structure GS can be removed to form the gate cleaved region GCIH, and an insulating layer GCI can be formed within the gate cleaved region GCIH using an insulating material. The bottom of the gate cleaved insulating layer GCI can protrude toward and contact the device isolation layer 112.

[0113] A first contact 152, electrically connected to the source / drain region SD through the inter-gate insulating layer 144 and the etch stop layer 142, can be formed, and a second contact 156, electrically connected to the gate electrode 122 through the capping layer 126, can be formed. Then, an upper insulating layer 146 is formed on the gate structure GS, the gate dicing insulating layer GCI, and the inter-gate insulating layer 144. A first via 154, passing through the upper insulating layer 146 and electrically connected to the first contact 152, can be formed, and a second via 158, passing through the upper insulating layer 146 and electrically connected to the second contact 156, can be formed.

[0114] Refer again Figures 3A to 3C A front-side wiring layer (FSW), a front-side via (FSV), and a front-side insulating layer (FSI) can be formed on the upper insulating layer 146. Therefore, a front-side wiring structure (FS) can be completed.

[0115] Typically, to form an integrated circuit device having a fork structure in which semiconductor patterns are arranged with insulating walls between them, the insulating walls are formed first, followed by the semiconductor patterns. However, in this case, residues from the semiconductor patterns may not be completely removed, leading to device performance degradation. Conversely, a method has been proposed to form insulating walls by etching between the semiconductor patterns after their formation; however, in this method, the width deviation of the semiconductor patterns may increase due to the etching process, further degrading device performance.

[0116] However, in the integrated circuit device 100 according to the embodiment, an insulating wall DW is formed, comprising an insulating wall pad D10, a buried insulating layer D20, and an insulating wall capping layer D30, and a recess process is performed on the upper part of the insulating wall DW to reduce the height of the insulating wall DW, after which the source / drain region SD can be grown. Since the insulating wall pad D10 comprises a low-k dielectric material, coupling effects can be prevented, and the threshold voltage control characteristics of the integrated circuit device 100 can be improved.

[0117] Furthermore, since the insulating wall capping layer D30 covers the upper surface of the insulating wall pad D10, it can prevent loss or damage to the insulating wall DW that may occur when the upper surface of the insulating wall pad D10 is exposed during the process of forming the device isolation layer 112 and / or the etch-back process. Therefore, the integrated circuit device 100 can have excellent electrical performance.

[0118] According to the integrated circuit device conceived in this invention, an insulating wall is formed comprising an insulating wall pad, a buried insulating layer, and an insulating wall capping layer. A recessed process is performed on the upper portion of the insulating wall to reduce its height, and then source / drain regions are grown. Because the insulating wall pad comprises a low-k material, coupling effects can be prevented, and the threshold voltage control characteristics of the integrated circuit device can be improved. Furthermore, because the insulating wall capping layer covers the upper surface of the insulating wall pad, loss or damage to the insulating wall that may occur when the upper surface of the insulating wall pad is exposed during the process of forming the device isolation layer can be prevented. Therefore, the integrated circuit device can have excellent electrical performance.

[0119] The above exemplary embodiments are merely illustrative and should not be construed as restrictive.

[0120] The teachings of this invention can be readily applied to other types of devices. Furthermore, exemplary embodiments are provided.

[0121] The descriptions of the examples are intended to be illustrative, not to limit the scope of the claims, and many alternatives...

[0122] The substitutions, modifications, and changes will be obvious to those skilled in the art.

Claims

1. An integrated circuit device, comprising: At least one first semiconductor pattern extending in the vertical direction; A first source / drain region is connected to an end of the at least one first semiconductor pattern in a first horizontal direction; At least one second semiconductor pattern extends in the vertical direction and is spaced apart from the at least one first semiconductor pattern in the second horizontal direction; A second source / drain region is connected to the end of the at least one second semiconductor pattern in the first horizontal direction; as well as An insulating wall, located in an opening extending in the first horizontal direction, between the at least one first semiconductor pattern and the at least one second semiconductor pattern, and between the first source / drain region and the second source / drain region. The insulating wall includes: An insulating wall liner, which is located on the inner wall of the opening in the insulating wall; An insulating layer is buried on the insulating wall liner; and An insulating wall covering layer is located on the upper surface of the insulating wall liner and the upper surface of the buried insulating layer within the opening in the insulating wall.

2. The integrated circuit device according to claim 1, wherein, The insulating wall includes: The first portion is located between the at least one first semiconductor pattern and the at least one second semiconductor pattern; and The second part is located between the first source / drain region and the second source / drain region. The upper surface of the second part is at a lower height in the vertical direction than the upper surface of the first part.

3. The integrated circuit device according to claim 2, wherein, The upper surface of the second portion of the insulating wall is at a lower height in the vertical direction than the upper surfaces of the first source / drain region and the second source / drain region.

4. The integrated circuit device according to claim 2, wherein, The upper part of the first source / drain region is spaced apart from the upper part of the second source / drain region in the second horizontal direction.

5. The integrated circuit device according to claim 2, wherein, The insulating wall covering is located within the first portion of the insulating wall, and the insulating wall covering is located outside the second portion of the insulating wall.

6. The integrated circuit device according to claim 2, wherein, The at least one first semiconductor pattern has its end in the second horizontal direction in contact with the first sidewall of the insulating wall, and the at least one second semiconductor pattern has its end in the second horizontal direction in contact with the second sidewall of the insulating wall opposite to the first sidewall.

7. The integrated circuit device according to claim 6, wherein, The ends of at least one first semiconductor pattern in the second horizontal direction and the ends of at least one second semiconductor pattern in the second horizontal direction are in contact with the insulating wall liner.

8. The integrated circuit device according to claim 2, further comprising: A gate electrode that surrounds the at least one first semiconductor pattern and the at least one second semiconductor pattern and extends in the second horizontal direction; as well as A gate insulating layer is provided between the at least one first semiconductor pattern and the gate electrode, and between the at least one second semiconductor pattern and the gate electrode. The gate insulating layer extends onto the upper surface of the first portion of the insulating wall.

9. The integrated circuit device according to claim 8, wherein, The gate insulating layer is located on the upper surface of the insulating wall cover layer in the first portion of the insulating wall.

10. The integrated circuit device according to claim 2, wherein, The insulating wall has a width of 15 nanometers to 25 nanometers in the second horizontal direction.

11. The integrated circuit device according to claim 2, wherein, The first source / drain region includes: The lower sidewall, which contacts the second portion of the insulating wall; and The upper sidewall, which is at a higher height than the lower sidewall in the vertical direction, and is spaced apart from the second portion of the insulating wall. The upper sidewall protrudes outward relative to the lower sidewall, and the upper sidewall and the lower sidewall are spaced apart by a first distance of 0.1 nanometers to 5 nanometers in the second horizontal direction.

12. The integrated circuit device according to claim 2, wherein, The upper surface of the insulating wall liner included in the first portion of the insulating wall is at a height higher than the upper surface of the at least one first semiconductor pattern in the vertical direction, and the upper surface of the insulating wall liner included in the first portion of the insulating wall is at a height lower than the upper surface of the insulating wall cover layer included in the first portion of the insulating wall in the vertical direction.

13. An integrated circuit device, comprising: The first active region and the second active region extend in the first horizontal direction; An insulating wall extends along a first horizontal direction between the first active region and the second active region; At least one first semiconductor pattern extends vertically over the first active region; A first source / drain region is located on the first active region and connected to the at least one first semiconductor pattern; At least one second semiconductor pattern is located on the second active region and extends in the vertical direction; as well as A second source / drain region, located on the second active region and connected to the at least one second semiconductor pattern. The insulating wall includes: A buried insulating layer extends along the first horizontal direction between the at least one first semiconductor pattern and the at least one second semiconductor pattern and between the first source / drain region and the second source / drain region; Insulating wall liner, which is located on the sidewall of the buried insulating layer; and An insulating wall covering layer is located on the upper surface of the insulating wall liner and on the upper surface of the buried insulating layer.

14. The integrated circuit device according to claim 13, wherein, The insulating wall pad contacts the at least one first semiconductor pattern, the at least one second semiconductor pattern, the first source / drain region, and the second source / drain region.

15. The integrated circuit device according to claim 13, wherein, The insulating wall capping layer is located between the at least one first semiconductor pattern and the at least one second semiconductor pattern, and is spaced apart from the region between the first source / drain region and the second source / drain region.

16. The integrated circuit device according to claim 13, wherein, The insulating wall includes: The first portion is located between the at least one first semiconductor pattern and the at least one second semiconductor pattern; and The second part is located between the first source / drain region and the second source / drain region. The upper surface of the second part is at a lower height in the vertical direction than the upper surface of the first part.

17. The integrated circuit device according to claim 16, wherein, The upper surface of the second portion of the insulating wall is at a lower height in the vertical direction than the upper surfaces of the first source / drain region and the second source / drain region.

18. The integrated circuit device according to claim 16, wherein, Each of the first source / drain region and the second source / drain region includes: The lower sidewall, which contacts the second portion of the insulating wall; and The upper sidewall, which is at a higher height than the lower sidewall in the vertical direction, and is spaced apart from the second portion of the insulating wall. The upper sidewall protrudes outward relative to the lower sidewall, and the upper sidewall is spaced from the lower sidewall by a first distance of 0.1 nanometers to 5 nanometers in a second horizontal direction intersecting the first horizontal direction.

19. The integrated circuit device according to claim 18, wherein, The upper sidewall of the first source / drain region is spaced apart from the upper sidewall of the second source / drain region in the second horizontal direction.

20. An integrated circuit device, comprising: The substrate includes a first active region and a second active region; At least one first semiconductor pattern and at least one second semiconductor pattern are respectively disposed on the first active region and the second active region; The first source / drain region and the second source / drain region are located on the first active region and the second active region, respectively, and are connected to the at least one first semiconductor pattern and the at least one second semiconductor pattern, respectively. as well as An insulating wall is located between the first active region and the second active region, and between the at least one first semiconductor pattern and the at least one second semiconductor pattern; The insulating wall includes: Bury the insulation layer; Insulating wall liner, which is located on the sidewall of the buried insulating layer; and An insulating wall covering layer is located on the upper surface of the insulating wall liner and on the upper surface of the buried insulating layer.

Images