Array substrate and display panel

Abstract

The invention discloses an array substrate and a display panel, and belongs to the technical field of display, and the array substrate comprises an active layer which is located on a substrate and comprises an active pattern of a thin film transistor, and the active pattern is provided with a source part, a channel part and a drain part which are connected in sequence; the second conductive layer is located on the active layer and comprises a source electrode and a drain electrode of the thin film transistor, the source electrode is connected to the source part, the drain electrode is connected to the drain part, a first opening is formed between the source electrode and the drain electrode, and the first opening is located above the channel part; and the protection layer is located on the second conductive layer and is provided with a second opening, and the second opening is located above the first opening and is communicated with the first opening so as to expose the channel part through the first opening. The width of the first opening can be accurately controlled by using a conventional technological process, so that the width of the channel part in the thin film transistor can be accurately controlled and effectively shortened, and the charging efficiency and the refreshing performance of the display panel can be improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Technology

[0002] Thin film transistor (TFT) devices with back channel etching (BCE) structures are widely used in liquid crystal display (LCD) panels due to their simple manufacturing process and low cost.

[0003] For TFT devices with BCE structure, the width of the channel portion in the TFT device will directly affect the charging efficiency and refresh performance of the LCD panel where the TFT device is located.

[0004] Therefore, how to accurately control and effectively shorten the width of the channel in TFT devices to improve the charging efficiency and refresh performance of LCD panels is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] An array substrate and a display panel are provided to solve the above-mentioned technical problems.

[0006] In a first aspect, an array substrate is provided having thin-film transistors, the array substrate comprising: substrate; A first conductive layer, located on the substrate, includes the gate of the thin-film transistor; An active layer, located on the substrate, includes the active pattern of the thin-film transistor, the active pattern having a source portion, a channel portion, and a drain portion connected in sequence; and The second conductive layer is located on the active layer and includes the source and drain of the thin film transistor. The source is connected to the source portion, the drain is connected to the drain portion, and a first opening is provided between the source and the drain. The array substrate further includes a protective layer located on the second conductive layer and having a second opening located above the first opening and communicating with the first opening to expose the channel portion through the first opening.

[0007] Optionally, the array substrate further includes: an ohmic contact layer, the ohmic contact layer being located between the active layer and the second conductive layer, and including a source contact portion and a drain contact portion, the source electrode being connected to the source portion through the source contact portion, and the drain electrode being connected to the drain electrode through the drain contact portion; The source contact portion and the drain contact portion have a third opening, which is located below the first opening. The second opening exposes the channel portion through the first opening and the third opening in sequence.

[0008] Optionally, the width of the channel portion is equal to the width of the third opening, and / or the third opening is smaller than the width of the first opening, and / or the active layer comprises monocrystalline silicon material.

[0009] Optionally, the second opening directly exposes the channel portion through the first opening.

[0010] Optionally, the width of the channel portion is equal to the width of the first opening, and / or the active layer comprises a metal oxide semiconductor material.

[0011] Optionally, the protective layer is an insulating protective layer.

[0012] Optionally, the protective layer covers the top surfaces of the source and the drain and extends beyond the boundaries of the top surfaces of the source and the drain, such that the second opening is located above the first opening.

[0013] Optionally, the width of the second opening is smaller than the width of the first opening.

[0014] Optionally, the width of the channel portion is less than or equal to the width of the first opening.

[0015] Secondly, embodiments of this application also provide a display panel, including: an array substrate as described above.

[0016] The array substrate in this application, by providing a protective layer on a second conductive layer including the source and drain of thin-film transistors, and providing a second opening in the protective layer, and then providing a first opening between the source and drain that communicates with the second opening and has a width not less than the width of the channel portion in the active layer, can precisely control the width of the first opening using conventional process flow, thereby precisely controlling and effectively shortening the width of the channel portion in the thin-film transistor, and thus improving the charging efficiency and refresh performance of the display panel.

[0017] Furthermore, in this embodiment, the array substrate can reduce the thickness of the second conductive layer by effectively shortening the width of the channel portion in the thin-film transistor, thereby reducing the amount of metal used in the array substrate fabrication process and thus reducing the cost of array substrate fabrication. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0020] Figure 1 This is one of the cross-sectional structural schematic diagrams of an array substrate provided in an exemplary embodiment of this disclosure.

[0021] Figure 2 This is a second cross-sectional view of an array substrate provided in an exemplary embodiment of this disclosure.

[0022] Figure 3 This is one of the flowcharts illustrating an exemplary embodiment of the array substrate fabrication method provided in this disclosure.

[0023] Figures 4a to 4i This is one of the process diagrams for fabricating an array substrate provided in an exemplary embodiment of this disclosure.

[0024] Figure 5 This is a second schematic flowchart illustrating an exemplary embodiment of the array substrate fabrication method provided in this disclosure.

[0025] Figures 6a to 6h This is the second diagram illustrating the fabrication process of the array substrate provided in an exemplary embodiment of this disclosure.

[0026] Figure label: 100: Array substrate; 11: Gate insulating layer; 12: Substrate; 13: Gate; 14: Active pattern; 15: Source portion; 16: Channel portion; 17: Drain portion; 18: Source electrode; 19: Drain electrode; 20: First opening; 21: Protective layer; 22: Second opening; 23: Passivation layer; 24: Planarization layer; 25: Pixel electrode layer; 26: Fourth opening; 27: Ohmic contact layer; 28: Source contact portion; 29: Drain contact portion; 30: Third opening; 31: Active layer; 40: Second conductive layer; 41: First photoresist layer; 42: Sacrificial layer; 43: Second photoresist layer; 44: Sacrificial pillar; 45: Third photoresist layer. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0028] In the embodiments of this application, "at least one" refers to one or more; "multiple" refers to two or more. In the description of this application, the terms "first," "second," "third," etc., are used only for the purpose of distinguishing descriptions and should not be construed as indicating or implying relative importance, nor should they be construed as indicating or implying order.

[0029] References such as “one embodiment” or “some embodiments” as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the terms “comprising,” “including,” “having,” and variations thereof, as used in this specification, mean “including, but not limited to,” unless otherwise specifically emphasized.

[0030] It should be noted that in the embodiments of this application, "and / or" describes the relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after it are in an "or" relationship.

[0031] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0032] It should be noted that with the continuous development of display technology, LCD panels are evolving towards larger sizes, higher refresh rates, and lower power consumption. The pixel charging efficiency and refresh performance of large-size LCD panels are significantly affected by the characteristics of their internal TFT devices.

[0033] BCE structure is a typical fabrication structure for TFT devices. In BCE TFT devices, after forming the source and drain metal patterns, the back side of the channel (i.e., the back side of the active layer) is etched to form the channel. BCE TFT devices have advantages such as simple structure, fewer process steps, and low manufacturing cost, and are therefore widely used in large-size LCD panels.

[0034] For TFTs with a BCE structure, the shorter the channel width in the TFT device, the lower the channel resistance and the larger the conduction current under the same gate driving voltage. This allows more charge to be provided to the pixel capacitor within a limited line scan time, achieving higher charging efficiency. Conversely, if the channel width in the TFT device is longer, the TFT conduction current is limited, the pixel charging time is prolonged, resulting in incomplete charging and difficulty in supporting high refresh rate displays.

[0035] Experiments have shown that, under the same manufacturing process conditions, reducing the channel width in a BCE-structured TFT device from 3.2 μm to 1.8 μm can improve the charging efficiency of large-size LCD panels containing these TFT devices by approximately 15%, and increase the refresh rate from 60 Hz to 120 Hz. Furthermore, the reduced channel width in the BCE-structured TFT device also allows for thinning of the source / drain metal layers, thereby reducing metal usage and the manufacturing cost of the TFT device.

[0036] Therefore, the design of the channel width in BCE structure TFT devices is of great significance for improving the charging efficiency and refresh performance of LCD panels.

[0037] The Halt Tone process, commonly used in related technologies, forms both transparent and semi-transparent areas on the same photomask to create the channel portion in a TFT device. However, the lithographic resolution of the Halt Tone process is limited by the control of light intensity and exposure uniformity in the semi-transparent area of ​​the mask. When the designed width of the channel portion in the TFT device is less than 3μm, the energy distribution in the semi-transparent area is difficult to control precisely, easily leading to problems such as blurred edges of the lithographic pattern, linewidth deviation, and channel overlap errors.

[0038] Furthermore, alignment errors between the metal and active layers in the stacked structure further amplify dimensional deviations. Therefore, the Halt Tone mask process has inherent limitations in channel miniaturization, making it difficult to stably and accurately form short (e.g., less than 3 μm) channels in BCE-structured TFT devices.

[0039] Therefore, how to accurately control and effectively shorten the width of the channel in TFT devices to improve the charging efficiency and refresh performance of display panels is a technical problem that urgently needs to be solved in this field.

[0040] Figure 1 This is one of the structural schematic diagrams of an array substrate provided in an exemplary embodiment of this disclosure. Figure 2 This is a second schematic diagram of the array substrate provided as an exemplary embodiment of this disclosure. Please refer to... Figure 1 and Figure 2The array substrate 100 has thin-film transistors and includes: a substrate 12; a first conductive layer located on the substrate 12, including a gate 13 of the thin-film transistor; an active layer located on the substrate 12, including an active pattern 14 of the thin-film transistor, the active pattern 14 having a source portion 15, a channel portion 16 and a drain portion 17 connected in sequence; and a second conductive layer located on the active layer, including a source 18 and a drain 19 of the thin-film transistor, the source 18 being connected to the source portion 15 and the drain 19 being connected to the drain portion 17, and a first opening 20 being provided between the source 18 and the drain 19.

[0041] The array substrate 100 further includes a protective layer 21, which is located on the second conductive layer and has a second opening 22. The second opening 22 is located above the first opening 20 and communicates with the first opening 20 to expose the channel portion 16 through the first opening 20.

[0042] Optionally, in this embodiment, the substrate 12 can be made of materials such as glass, quartz, or polyimide.

[0043] Optionally, in this embodiment, the thin-film transistor can be an N-type thin-film transistor or a P-type thin-film transistor.

[0044] Along the thickness direction of the array substrate 100, a first conductive layer is disposed on the substrate 12. The first conductive layer may include the gate 13 and scan lines of the thin-film transistor. A gate insulating layer 11 is deposited covering the entire gate 13, and an active layer is disposed on the gate insulating layer 11. The gate insulating layer 11 is used to isolate the gate 13 from the active layer.

[0045] Optionally, the material of the first conductive layer in this embodiment may include metals such as Cr (chromium), W (tungsten), Ti (titanium), Ta (tantalum), Mo (molybdenum), Al (aluminum), Cu (copper), or alloys composed of at least two of the above metals.

[0046] Optionally, the material of the gate insulating layer 11 in this embodiment may include a compound composed of nitrogen, silicon and oxygen, or aluminum oxide, such as a single layer of silicon oxide or silicon nitride, or multiple layers of the above-mentioned inorganic film.

[0047] Optionally, the active layer material in this embodiment can be a metal oxide semiconductor, such as IGZO (indium gallium zinc oxide), IGTO (indium gallium tin oxide), Ln-IZO (lanthanide indium zinc oxide), ITZO (indium tin zinc oxide), ITGZO (indium tin gallium zinc oxide), HIZO (hafnium indium zinc oxide), IZO (indium zinc oxide), ZnO:F (fluorine-doped zinc oxide), In2O3:Sn (tin-doped indium oxide), In2O3:Mo (molybdenum-doped indium oxide), Cd2SnO4 (cadmium stannate), ZnO:Al (aluminum-doped zinc oxide), TiO2:Nb (niobium-doped titanium dioxide), Cd-Sn-O (cadmium tin oxide), or other metal oxides.

[0048] Optionally, the active layer in this embodiment may also include amorphous silicon.

[0049] A second conductive layer is disposed on the active layer along the thickness direction of the array substrate 100. The second conductive layer may include a source 18, a drain 19, and data lines in a thin-film transistor. The source 18 is disposed on and connected to a source portion 15 in the active layer. The drain 19 is disposed on and connected to a drain portion 17 in the active layer. A first opening 20 between the source 18 and the drain 19 is located on a channel portion 16 in the active layer. The width of the first opening 20 is not less than the width of the channel portion 16.

[0050] Optionally, in this embodiment, the first opening 20 can directly expose the channel portion 16; in this embodiment, the first opening 20 can also expose the channel portion 16 through openings in other layers.

[0051] Optionally, the material of the second conductive layer in this embodiment may include metals such as Cr (chromium), W (tungsten), Ti (titanium), Ta (tantalum), Mo (molybdenum), Al (aluminum), Cu (copper), or alloys composed of at least two of the above metals.

[0052] Along the thickness direction of the array substrate 100, a protective layer 21 is disposed on the second conductive layer and has a second opening 22 communicating with the first opening 20.

[0053] Optionally, in this embodiment, the protective layer 21 is an insulating protective layer. The material of the protective layer 21 can be silicon nitride or silicon oxide.

[0054] Optionally, in this embodiment, the first opening 20 and the second opening 22 are coaxially arranged along the thickness direction of the array substrate 100.

[0055] Optionally, in this embodiment, the width of the first opening 20 is greater than the width of the second opening 22.

[0056] It should be noted that, in this embodiment, the array substrate 100 has a protective layer 21 on the second conductive layer. During the fabrication process of the array substrate 100, steps such as forming sacrificial metal pillars, planarizing photoresist, wet etching, and resist removal can be performed on the protective layer 21. This allows for the formation of a second opening 22 of a target width below the sacrificial metal pillars in the protective layer 21, and the formation of the gate 13 and drain 19 of the thin-film transistor, as well as a first opening 20 between the gate 13 and drain 19, on the first conductive layer. Furthermore, the position of the second opening 22 in the protective layer 21 can be controlled by controlling the position of the sacrificial metal pillars; the width of the second opening 22 can be precisely controlled by controlling the width of the sacrificial metal pillars; and the width of the first opening 20 can be precisely controlled by controlling the process parameters of the wet etching process. This allows for precise control and effective shortening of the width of the channel portion 16.

[0057] The width of the sacrificial layer metal pillars can be predefined based on the design parameters of the array substrate 100.

[0058] In this embodiment, the array substrate has a protective layer on a second conductive layer including the source and drain of thin-film transistors, a second opening on the protective layer, and a first opening between the source and drain that communicates with the second opening and has a width not less than the width of the channel portion in the active layer. The width of the first opening can be precisely controlled using conventional process flow, thereby precisely controlling and effectively shortening the width of the channel portion in the thin-film transistor, and thus improving the charging efficiency and refresh performance of the display panel.

[0059] Furthermore, in this embodiment, the array substrate 100 can reduce the thickness of the second conductive layer by effectively shortening the width of the channel portion 16 in the thin film transistor, thereby reducing the amount of metal used in the fabrication process of the array substrate 100 and thus reducing the cost of fabricating the array substrate 100.

[0060] Please see Figure 1 As one embodiment of the array substrate 100 provided in this application, the array substrate 100 further includes: an ohmic contact layer 27, which is located between the active layer and the second conductive layer, and includes a source contact portion 28 and a drain contact portion 29. The source electrode 18 is connected to the source portion 15 through the source contact portion 28, and the drain electrode 19 is connected to the drain electrode 19 through the drain contact portion 29.

[0061] There is a third opening 30 between the source contact portion 28 and the drain contact portion 29. The third opening 30 is located below the first opening 20. The second opening 22 exposes the channel portion 16 through the first opening 20 and the third opening 30 in sequence.

[0062] In this embodiment, the array substrate has an ohmic contact layer in the active layer and the second conductive layer. The source contact portion in the ohmic contact layer connects the source portion and the source electrode, and the drain portion in the ohmic contact layer contacts the drain portion and the drain electrode. The width of the third opening between the drain contact portion and the source contact portion can be precisely controlled using conventional process flow, thereby enabling precise control and further shortening of the width of the channel portion in the thin film transistor.

[0063] As an optional embodiment, the protective layer 21 is an insulating protective layer.

[0064] In this embodiment, the protective layer is an insulating protective layer that can form an insulating barrier on the second conductive layer, effectively preventing damage to the second conductive layer by subsequent processes and ensuring the reliability of the thin-film transistor. Furthermore, through the second opening in the protective layer, the first opening in the second conductive layer can be formed using processes such as wet etching, and the width of the first opening can be precisely controlled by controlling the process parameters. This transforms the channel width control problem into control of the opening width of the uppermost layer, which is easier to pattern precisely, thereby enabling precise control and effective shortening of the channel width using conventional processes.

[0065] Please see Figure 1 As an optional embodiment, the protective layer 21 covers the top surfaces of the source 18 and the drain 19 and extends beyond the boundaries of the top surfaces of the source 18 and the drain 19, such that the second opening 22 is located above the first opening 20.

[0066] Please see Figure 1 As an optional embodiment, the width of the second opening 22 is smaller than the width of the first opening 20.

[0067] Optionally, the second opening 22 and the first opening 20 are coaxially arranged along the thickness direction of the array substrate 100.

[0068] In this embodiment, the protective layer covers the top surfaces of the source and drain and extends beyond the boundaries of the top surfaces of the source and drain, so that the second opening is located above the first opening. This avoids damage to the sidewalls of the source / drain when the first opening is formed later, and the thickness of the protective layer can be used to form a buffer, enhancing the fault tolerance of subsequent processes.

[0069] As an alternative embodiment, the width of the channel portion 16 is equal to the width of the third opening 30, and / or the third opening 30 is smaller than the width of the first opening 20, and / or the active layer comprises amorphous silicon material.

[0070] In this embodiment, the width of the channel is equal to the width of the third opening. The width of the third opening can be precisely controlled by conventional processes such as dry etching through the first and second openings, thereby achieving precise control and effective shortening of the channel width.

[0071] In this embodiment, the width of the third opening is smaller than that of the first opening, which ensures that the width of the channel is further shortened.

[0072] Amorphous silicon technology offers advantages such as lower cost, more stable processes, and better uniformity; however, amorphous silicon itself has a lower carrier mobility. In this embodiment, the active layer includes amorphous silicon material, which can effectively compensate for the low carrier mobility of amorphous silicon by utilizing a shorter channel width. This significantly increases the on-state current, achieving improved performance of the amorphous silicon thin-film transistor by shortening the channel width while fundamentally altering the material system. This simultaneously controls the manufacturing cost and improves the performance of the thin-film transistor.

[0073] As an alternative embodiment, the ohmic contact layer 27 is made of an N-type semiconductor material.

[0074] In this embodiment, the ohmic contact layer is made of an N-type semiconductor material, which can provide a high concentration of free electrons between the source / drain and the active layer, thereby significantly reducing the contact resistance between the source / drain and the active layer. This not only ensures that the improved driving capability brought about by shortening the channel width can be effectively converted into fast charging of the pixel electrode layer, but also ensures the efficient operation of the thin-film static tube under low voltage.

[0075] Preferably, the width of the channel portion 16, the width of the first opening 20 and the width of the third opening 30 are equal, the channel portion 16, the first opening 20, the second opening 22 and the third opening 30 are coaxially arranged along the thickness direction of the array substrate 100, the ohmic contact layer 27 is made of N-type semiconductor material, and the active layer includes amorphous silicon material.

[0076] Please see Figure 1 As an optional embodiment, the array substrate 100 further includes: a passivation layer 23 located on the protective layer 21, the passivation layer 23 covering the inner surfaces of the first opening 20 and the second opening 22, and a fourth opening 26 provided above the second opening 22.

[0077] In this embodiment, the passivation layer 23 covers the entire protective layer 21, and the passivation layer 23 covers the inner surfaces of the first opening 20, the second opening 22 and the third opening 30 to form a cavity.

[0078] Optionally, the width of the fourth opening 26 is the same as the width of the second opening 22.

[0079] Optionally, the fourth opening 26 exposes the channel portion 16 through the second opening 22, the first opening 20 and the third opening 30 in sequence.

[0080] Preferably, the fourth opening 26, the second opening 22, the third opening 30 and the channel portion 16 have the same width, and the fourth opening 26, the second opening 22, the third opening 30 and the channel portion 16 are coaxially arranged in the thickness direction of the array substrate 100.

[0081] The material of the passivation layer 23 may be a compound composed of nitrogen, silicon and oxygen, such as a single layer of silicon oxide film or a silicon oxide-silicon nitride stacked structure.

[0082] In this embodiment, a passivation layer is also provided on the protective layer, which can provide insulation and barrier for the thin film transistor, effectively preventing damage to the thin film transistor by subsequent processes. It can ensure the stability and reliability of the overall film structure while realizing the efficient transfer of the driving current of the thin film transistor to the pixel electrode layer.

[0083] Please see Figure 1 As an optional embodiment, the array substrate 100 further includes a planarization layer 24; the planarization layer 24 fills the cavity.

[0084] Optionally, if the passivation layer 23 is not covered on the protective layer 21, the planarization layer 24 may be disposed on the protective layer 21. See also... Figure 1 When the protective layer 21 is covered with a passivation layer 23, a planarization layer 24 can be disposed on the passivation layer 23, and the passivation layer 23 is used to isolate the protective layer 21 and the planarization layer 24.

[0085] Optionally, the planarization layer 24 has a recess above the fourth opening 26. The sidewall of the recess is inclined along the thickness direction of the array substrate 100, such that the cross-section of the recess is an isosceles trapezoid with a top area larger than the bottom area.

[0086] In this embodiment, the cavity formed by the passivation layer covering the inner surfaces of the first, second, and third openings is filled with a planarization layer, which eliminates the deep holes formed by the superposition of multiple openings. This provides a flat and uniform surface for the formation of the upper pixel dot layer, ensuring the consistency of electrical performance in the array substrate and improving the product yield and display uniformity of the array substrate.

[0087] Please see Figure 1 As an optional embodiment, the array substrate 100 further includes a pixel electrode layer 25.

[0088] Optionally, if the passivation layer 23 is not covered on the protective layer 21, the pixel electrode layer 25 can sequentially pass through the planarization layer 24 and the via on the protective layer 21 to be electrically connected to the source 18 or the drain 19. (See also...) Figure 1When the protective layer 21 is covered with a passivation layer 23, the pixel electrode layer 25 can pass through the planarization layer 24, the passivation layer 23 and the via on the protective layer 21 in sequence to be electrically connected to the source 18 or the drain 19.

[0089] Alternatively, the pixel electrode layer 25 can be made of transparent indium tin oxide (ITO).

[0090] In this embodiment, this application also proposes a method for fabricating an array substrate 100. Please refer to [link to relevant documentation]. Figure 3 as well as Figures 4a to 4i . Figure 3 This is one of the flowcharts illustrating a method for fabricating an array substrate 100 provided in an exemplary embodiment of this disclosure. Figures 4a to 4i This is one of the fabrication process diagrams of the array substrate 100 provided in an exemplary embodiment of this disclosure. See also... Figure 3 The method for fabricating the array substrate 100 includes: S301, providing a substrate 12, and sequentially forming a first conductive layer, a gate insulating layer 11, an active layer 31, an ohmic contact layer 27, a second conductive layer 40, and a first photoresist layer 41 on the substrate 12.

[0091] Specifically, see Figure 4a In this embodiment, thin film deposition and photolithography techniques can be used to sequentially form a first conductive layer including a gate 13 and a gate insulating layer 11 on the substrate 12.

[0092] After forming a first conductive layer including a gate 13 and a gate insulating layer 11 on the substrate 12, an active layer 31 covering the entire gate insulating layer 11 can be formed on the gate insulating layer 11, an ohmic contact layer 27 covering the entire active layer 31 can be formed on the active layer 31, and a second conductive layer 40 covering the entire ohmic contact layer 27 can be formed on the ohmic contact layer 27. Then, a first photoresist layer 41 of a first width is formed in the middle of the projection area of ​​the gate 13 of the thin film transistor in the second conductive layer 40.

[0093] The first width is equal to the sum of the widths of the source portion 15, the channel portion 16, and the drain portion 17 in the thin-film transistor of the second conductive layer 40. The first width can be determined based on the design parameters of the array substrate 100.

[0094] Please see Figure 4bAfter forming a first conductive layer, a gate insulating layer 11, an active layer 31, an ohmic contact layer 27, a second conductive layer 40, and a first photoresist layer 41 on the substrate 12, wet etching can be used to remove the area of ​​the second conductive layer 40 not covered by the first photoresist layer 41. Dry etching can be used to remove the area of ​​the ohmic contact layer 27 other than the projection area of ​​the first photoresist layer 41. Dry etching can also be used to remove the area of ​​the active layer 31 other than the projection area of ​​the first photoresist layer 41. Then, a resist removal process can be used to remove the first photoresist layer 41. The resist removal process can include wet resist removal and dry resist removal.

[0095] S302, a protective layer 21 and a sacrificial layer 42 are sequentially formed on the second conductive layer 40, and a second photoresist layer 43 with a second width is formed in the middle of the projection area of ​​the active layer 31 on the sacrificial layer.

[0096] Please see Figure 4c In this embodiment, a thin film deposition process can be used to sequentially form a protective layer 21 and a sacrificial layer 42 on the second conductive layer 40.

[0097] Preferably, in this embodiment, chemical vapor deposition (CVD) can be used to form a protective layer 21 covering the top surface of the gate insulating layer 11, the side surfaces of the active layer 31 and the ohmic contact layer 27, and the top surface of the second conductive layer 40. In this embodiment, physical vapor deposition (PVD) can be used to form a sacrificial layer 42 on the protective layer 21.

[0098] Please see Figure 4c The protective layer 21 covers the top surface of the gate insulating layer 11, the sides of the active layer 31 and the ohmic contact layer 27, and the top surface of the second conductive layer 40. The sacrificial layer 42 covers the entire protective layer 21.

[0099] After the sacrificial layer 42 is formed on the protective layer 21, a second photoresist layer 43 with a second width can be formed in the center of the projection area of ​​the active layer 31 onto the sacrificial layer 42. The second width is the same as the width of the second opening 22. The second width can be determined based on the design parameters of the array substrate 100.

[0100] S303. After removing the sacrificial layer 42 that is not covered by the second photoresist layer 43, the second photoresist is removed, and sacrificial pillars 44 are formed on the protective layer 21.

[0101] Please see Figure 4d In this embodiment, an etching (ETCH) process can be used to remove the sacrificial layer 42 that is not covered by the second photoresist layer 43.

[0102] After removing the sacrificial layer 42 that is not covered by the second photoresist layer 43, the second photoresist layer 43 can be removed using a photoresist removal process, and a sacrificial pillar 44 of the second width can be formed in the middle of the projection area of ​​the active layer 31 in the protective layer 21.

[0103] S304, forming a third photoresist layer 45 on the top surface of the protective layer 21 and the side surface of the sacrificial pillar 44.

[0104] Please see Figure 4e After forming a sacrificial pillar 44 of a second width in the middle of the projection area of ​​the active layer 31 in the protective layer 21, a third photoresist layer 45 is further formed covering the top surface of the protective layer 21 and the side surface of the sacrificial pillar 44. Specifically, a photoresist layer covering the top surface of the protective layer 21 and the top surface of the sacrificial pillar 44 can be formed first, and then the photoresist layer can be thinned to form the third photoresist layer 45.

[0105] S305, Remove the sacrificial pillar 44 to form the second opening 22 in the protective layer 21, the first opening 20 in the second conductive layer 40, and the third opening 30 in the ohmic contact layer 27.

[0106] Please see Figure 4f In this embodiment, the sacrificial pillar 44 can be removed by wet etching to form the fifth opening 37.

[0107] The second opening 22 of the second width can be formed in the protective layer 21 by using a dry etching process through the fifth opening.

[0108] The first opening 20 can be formed in the second conductive layer 40 by using a wet etching process through the second opening 22.

[0109] A third opening 30 of a second width can be formed in the ohmic contact layer 27 through the first opening 20 using a dry etching process.

[0110] Correspondingly, the width of the channel portion 16 in the active layer 31 is the second width.

[0111] S306. Remove the third photoresist layer 45 and form an inner surface on the protective layer 21 that covers the protective layer 21, the first opening 20, the second opening 22 and the third opening 30, and a passivation layer 23 having a fourth opening 26 above the second opening 22.

[0112] Please see Figure 4g In this embodiment, the third photoresist layer 45 can be removed by a photoresist removal process.

[0113] Please see Figure 4hAfter removing the third photoresist layer 45, a passivation layer 23 covering the protective layer 21, the first opening 20, the second opening 22 and the third opening 30 can be formed on the protective layer 21 using a chemical vapor deposition process, and a passivation layer 23 having a fourth opening 26 above the second opening 22.

[0114] S307. A planarization layer 24 and a pixel electrode layer 25 are sequentially formed on the passivation layer 23.

[0115] Please see Figure 4i After the passivation layer 23 is formed, a planarization layer 24 can be formed on the passivation layer 23 by chemical vapor deposition. This planarization layer 24 can fill the cavity formed by the inner surfaces of the passivation layer 23 covering the first opening 20, the second opening 22 and the third opening 30.

[0116] After the planarization layer 24 is formed, the pixel electrode layer 25 can be formed on the planarization layer 24 using thin film deposition, dry etching and photolithography processes.

[0117] In this embodiment, the array substrate 100 has an ohmic contact layer 27 between the active layer 31 and the second conductive layer 40. The ohmic contact layer 27 includes a source contact 28 for connecting the source electrode 18 and the source portion 15, and a drain contact 29 for connecting the drain electrode 19 and the drain portion 17. The ohmic contact layer 27 has a third opening 30 between the source contact 28 and the drain contact 29. The second opening 22 exposes the channel portion 16 through the first opening 20 and the third opening 30 in sequence. The width of the first opening 20 and the third opening 30 can be precisely controlled using conventional process flow, thereby enabling precise control and effective shortening of the width of the channel portion 16 in the thin film transistor.

[0118] Please see Figure 2 In another embodiment of the array substrate 100 provided in this application, the second opening 22 directly exposes the channel portion 16 through the first opening 20.

[0119] As an optional embodiment, the protective layer 21 is an insulating protective layer.

[0120] In this embodiment, the protective layer is an insulating protective layer that can form an insulating barrier on the second conductive layer, effectively preventing damage to the second conductive layer by subsequent processes and ensuring the reliability of the thin-film transistor. Furthermore, through the second opening in the protective layer, the first opening in the second conductive layer can be formed using processes such as wet etching, and the width of the first opening can be precisely controlled by controlling the process parameters. This transforms the channel width control problem into control of the opening width of the uppermost layer, which is easier to pattern precisely, thereby enabling precise control and effective shortening of the channel width using conventional processes.

[0121] Please see Figure 2As an optional embodiment, the protective layer 21 covers the top surfaces of the source 18 and the drain 19 and extends beyond the boundaries of the top surfaces of the source 18 and the drain 19, such that the second opening 22 is located above the first opening 20.

[0122] In this embodiment, the protective layer covers the top surfaces of the source and drain and extends beyond the boundaries of the top surfaces of the source and drain, so that the second opening is located above the first opening. This avoids damage to the sidewalls of the source / drain when the first opening is formed later, and the thickness of the protective layer can be used to form a buffer, enhancing the fault tolerance of subsequent processes.

[0123] Please see Figure 2 As an optional embodiment, the width of the second opening 22 is smaller than the width of the first opening 20.

[0124] In this embodiment, the width of the second opening is smaller than the width of the first opening. By reducing the width of the second opening, the protective layer can be better utilized to avoid damage to the sidewalls of the source / drain electrodes when the first opening is formed later. The thickness of the protective layer can also be better utilized to form a buffer, further enhancing the fault tolerance of subsequent processes.

[0125] Optionally, the second opening 22 and the first opening 20 are coaxially arranged along the thickness direction of the array substrate 100.

[0126] Please see Figure 2 As an optional embodiment, the width of the channel portion 16 is equal to the width of the first opening 20, and / or the active layer 31 comprises a metal oxide semiconductor material.

[0127] Preferably, the width of the channel portion 16 is equal to the width of the first opening 20, and the channel portion 16, the first opening 20 and the second opening 22 are coaxially arranged along the thickness direction of the array substrate 100, and the active layer 31 includes a metal oxide semiconductor material.

[0128] Preferably, the active layer 31 comprises IGTO (indium gallium tin oxide) semiconductor material.

[0129] In this embodiment, the width of the channel is equal to the width of the first opening. The width of the first opening can be precisely controlled through the second opening using conventional processes such as wet etching, thereby achieving precise control and effective shortening of the channel width.

[0130] In this embodiment, the active layer includes a metal oxide semiconductor material, which can organically combine the inherent high carrier mobility of the metal oxide semiconductor material with the precise control of the channel width. This allows for the achievement of extremely high on-state current to significantly improve pixel charging rate and refresh rate, while maintaining the extremely low off-state current characteristics of the metal oxide transistor. This not only meets the stringent requirements of high-resolution, high dynamic range displays for fast charging, but also significantly reduces the basic static power consumption of the array.

[0131] Please see Figure 2 As an optional embodiment, the array substrate 100 further includes: a passivation layer 2323 located on the protective layer 21, the passivation layer 23 covering the inner surfaces of the first opening 20 and the second opening 22, and forming a fourth opening 26 above the second opening 22.

[0132] In this embodiment, the passivation layer 23 covers the entire protective layer 21, and the passivation layer 23 covers the inner surfaces of the first opening 20 and the second opening 22 to form a cavity.

[0133] The material of the passivation layer 23 may be a compound composed of nitrogen, silicon and oxygen, such as a single layer of silicon oxide film or a silicon oxide-silicon nitride stacked structure.

[0134] In this embodiment, a passivation layer is also provided on the protective layer, which can provide insulation and barrier for the thin film transistor, effectively preventing damage to the thin film transistor by subsequent processes. It can ensure the stability and reliability of the overall film structure while realizing the efficient transfer of the driving current of the thin film transistor to the pixel electrode layer.

[0135] Please see Figure 2 As an optional embodiment, the array substrate 100 further includes a planarization layer 2424; the planarization layer 24 fills the cavity.

[0136] Optionally, the width of the fourth opening 26 is the same as the width of the second opening 22, and they are coaxially arranged in the thickness direction of the array substrate 100.

[0137] Optionally, if the passivation layer 23 is not covered on the protective layer 21, the planarization layer 24 may be laid covering the entire protective layer 21. See also... Figure 2 When the protective layer 21 is covered with the passivation layer 23, the planarization layer 24 can be laid to cover the entire passivation layer 23. The passivation layer 23 is used to isolate the protective layer 21 and the planarization layer 24.

[0138] Optionally, the planarization layer 24 has a recess above the fourth opening 26. The sidewall of the recess is inclined along the thickness direction of the array substrate 100, such that the cross-section of the recess is an isosceles trapezoid with a top area larger than the bottom area.

[0139] In this embodiment, the cavity formed by the passivation layer covering the inner surfaces of the first and second openings is filled with a planarization layer, which eliminates the deep holes formed by the superposition of multiple openings. This provides a flat and uniform surface for the formation of the upper pixel dot layer, ensuring the consistency of electrical performance in the array substrate and improving the product yield and display uniformity of the array substrate.

[0140] Please see Figure 2 As an optional embodiment, the array substrate 100 further includes a pixel electrode layer 2525.

[0141] The pixel electrode layer 25 can pass through vias in the planarization layer 24, passivation layer 23 and protective layer 21 in sequence, and be electrically connected to the source 18 or drain 19.

[0142] Alternatively, the pixel electrode layer 25 can be made of transparent indium tin oxide (ITO).

[0143] Alternatively, if the planarization layer 24 has a recess above the fourth opening 26, the pixel electrode layer 25 fills the recess.

[0144] Optionally, the sidewalls of the recessed portion in the pixel electrode layer 25 are inclined downward along the thickness direction of the array substrate 100, so that the cross-section of the recessed portion is trapezoidal.

[0145] In this embodiment, this application also proposes a method for fabricating an array substrate 100. Please refer to [link to relevant documentation]. Figure 5 as well as Figures 6a to 6h . Figure 5 This is a second schematic flowchart illustrating a method for fabricating an array substrate 100 provided in an exemplary embodiment of this disclosure. Figures 6a to 6h This is a second diagram illustrating the fabrication process of the array substrate 100 provided in an exemplary embodiment of this disclosure. (See also...) Figure 5 The method for fabricating the array substrate 100 includes the following steps: S501, providing a substrate 12, and sequentially forming a first conductive layer, a gate insulating layer 11, an active layer 31, a second conductive layer 40, and a protective layer 21 on the substrate 12.

[0146] Specifically, see Figure 6a In this embodiment, thin film deposition and photolithography techniques can be used to sequentially form a first conductive layer including a gate 13 and a gate insulating layer 11 on the substrate 12.

[0147] After forming a first conductive layer including a gate 13 and a gate insulating layer 11 on the substrate 12, an active layer 31 covering the entire gate insulating layer 11 can be formed on the gate insulating layer 11, an ohmic contact layer 27 covering the entire active layer 31 can be formed on the active layer 31, and a second conductive layer 40 covering the entire ohmic contact layer 27 can be formed on the ohmic contact layer 27. Then, a first photoresist layer 41 of a first width is formed in the middle of the projection area of ​​the gate 13 of the thin film transistor in the second conductive layer 40.

[0148] The first width is equal to the sum of the widths of the source portion 15, the channel portion 16, and the drain portion 17 in the thin-film transistor of the second conductive layer 40. The first width can be determined based on the design parameters of the array substrate 100.

[0149] After forming a first conductive layer, a gate insulating layer 11, an active layer 31, an ohmic contact layer 27, a second conductive layer 40, and a first photoresist layer 41 on the substrate 12, wet etching can be used to remove the area of ​​the second conductive layer 40 not covered by the first photoresist layer 41. Dry etching can be used to remove the area of ​​the ohmic contact layer 27 other than the projection area of ​​the first photoresist layer 41. Dry etching can also be used to remove the area of ​​the active layer 31 other than the projection area of ​​the first photoresist layer 41. Then, a resist stripping process can be used to remove the first photoresist layer 41. The resist stripping process can include wet resist stripping and dry resist stripping.

[0150] In this embodiment, a protective layer 21 can be formed on the second conductive layer 40 using a thin film deposition process.

[0151] Preferably, in this embodiment, chemical vapor deposition (CVD) can be used to form a protective layer 21 covering the top surface of the gate insulating layer 11, the side surfaces of the active layer 31 and the ohmic contact layer 27, and the top surface of the second conductive layer 40.

[0152] S502, A sacrificial layer 42 is formed on the protective layer 21, and a second photoresist layer 43 of a second width is formed in the middle of the projection area of ​​the active layer 31 on the sacrificial layer 42.

[0153] Please see Figure 6b In this embodiment, a sacrificial layer 42 can be formed on the protective layer 21 using a thin-film deposition process. The protective layer 21 covers the top surface of the gate insulating layer 11, the side surface of the active layer 31, and the top surface of the second conductive layer 40. The sacrificial layer 42 completely covers the protective layer 21.

[0154] In this embodiment, physical vapor deposition (PVD) can be used to form a sacrificial layer 42 on the protective layer 21.

[0155] After the sacrificial layer 42 is formed on the protective layer 21, a second photoresist layer 43 with a second width can be formed in the center of the projection area of ​​the active layer 31 onto the sacrificial layer 42. The second width is the same as the width of the second opening 22. The second width can be determined based on the design parameters of the array substrate 100.

[0156] S503. After removing the sacrificial layer 42 that is not covered by the second photoresist layer 43, the second photoresist is removed, and sacrificial pillars 44 are formed on the protective layer 21.

[0157] Please see Figure 6c In this embodiment, an etching (ETCH) process can be used to remove the sacrificial layer 42 that is not covered by the second photoresist layer 43.

[0158] After removing the sacrificial layer 42 that is not covered by the second photoresist layer 43, the second photoresist layer 43 can be removed using a photoresist removal process, and a sacrificial pillar 44 of the second width can be formed in the middle of the projection area of ​​the active layer 31 in the protective layer 21.

[0159] S504, forming a third photoresist layer 45 on the top surface of the protective layer 21 and the side surface of the sacrificial pillar 44.

[0160] Please see Figure 6d After a second-width sacrificial pillar 44 is formed in the middle of the projection area of ​​the active layer 31 in the protective layer 21, a third photoresist layer 45 is further formed covering the top surface of the protective layer 21 and the side surface of the sacrificial pillar 44.

[0161] S505, Remove the sacrificial pillar 44 to form a second opening 22 in the protective layer 21 and a first opening 20 in the second conductive layer 40.

[0162] Please see Figure 6e In this embodiment, the sacrificial pillar 44 can be removed by wet etching to form the fifth opening 37.

[0163] Please see Figure 6f A second opening 22 of a second width can be formed in the protective layer 21 through the fifth opening using a dry etching process. A first opening 20 can be formed in the second conductive layer 40 through the second opening 22 using a wet etching process.

[0164] Correspondingly, the width of the channel portion 16 in the active layer 31 is the first width.

[0165] S506. Remove the third photoresist layer 45, and form an inner surface on the protective layer 21 that covers the protective layer 21, the first opening 20, the second opening 22 and the third opening 30, and a passivation layer 23 having a fourth opening 26 above the second opening 22.

[0166] Please see Figure 6g In this embodiment, the third photoresist layer 45 can be removed by a photoresist removal process.

[0167] Please see Figure 6h After removing the third photoresist layer 45, a passivation layer 23 covering the protective layer 21, the first opening 20, the second opening 22 and the third opening 30 can be formed on the protective layer 21 using a chemical vapor deposition process, and a passivation layer 23 having a fourth opening 26 above the second opening 22.

[0168] S507, A planarization layer 24 and a pixel electrode layer 25 are sequentially formed on the passivation layer 23.

[0169] Please see Figure 6h After the passivation layer 23 is formed, a planarization layer 24 can be formed on the passivation layer 23 by chemical vapor deposition. This planarization layer 24 can fill the cavity formed by the inner surfaces of the first opening 20 and the second opening 22 covered by the passivation layer 23.

[0170] Please see Figure 6h After the planarization layer 24 is formed, the pixel electrode layer 25 can be formed on the planarization layer 24 using thin film deposition process, dry etching process and photolithography process.

[0171] In this embodiment, the array substrate 100 has a second opening 22 that exposes the channel portion 16 between the first openings 20. The width of the first opening 20 can be precisely controlled using conventional process flow, thereby enabling precise control and effective shortening of the width of the channel portion 16 in the thin-film transistor.

[0172] As one embodiment, a display panel includes: an array substrate 100 as described above.

[0173] The display panel in this embodiment includes any of the array substrates 100 mentioned above, and can improve the charging efficiency and refresh performance of the display panel based on the thin-film transistors with smaller channel widths 16 in the array substrate 100.

[0174] The specific structure of the array substrate 100 described above can be found in the descriptions of the above embodiments, and will not be repeated in the embodiments of this invention.

[0175] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0176] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. An array substrate having thin-film transistors, characterized in that, The array substrate includes: substrate; A first conductive layer, located on the substrate, includes the gate of the thin-film transistor; An active layer, located on the substrate, includes the active pattern of the thin-film transistor, the active pattern having a source portion, a channel portion, and a drain portion connected in sequence; and The second conductive layer is located on the active layer and includes the source and drain of the thin film transistor. The source is connected to the source portion, the drain is connected to the drain portion, and a first opening is provided between the source and the drain. The array substrate further includes a protective layer located on the second conductive layer and having a second opening located above the first opening and communicating with the first opening to expose the channel portion through the first opening.

2. The array substrate according to claim 1, characterized in that, Also includes: An ohmic contact layer is located between the active layer and the second conductive layer, and includes a source contact portion and a drain contact portion. The source electrode is connected to the source portion through the source contact portion, and the drain electrode is connected to the drain electrode through the drain contact portion. The source contact portion and the drain contact portion have a third opening, which is located below the first opening. The second opening exposes the channel portion through the first opening and the third opening in sequence.

3. The array substrate according to claim 2, characterized in that, The width of the channel portion is equal to the width of the third opening, and / or the third opening is smaller than the width of the first opening, and / or the active layer comprises monocrystalline silicon material.

4. The array substrate according to claim 1, characterized in that, The second opening directly exposes the channel portion through the first opening.

5. The array substrate according to claim 4, characterized in that, The width of the channel portion is equal to the width of the first opening, and / or the active layer comprises a metal oxide semiconductor material.

6. The array substrate according to any one of claims 1-5, characterized in that, The protective layer is an insulating protective layer.

7. The array substrate according to any one of claims 1-5, characterized in that, The protective layer covers the top surfaces of the source and the drain, and extends beyond the boundaries of the top surfaces of the source and the drain, such that the second opening is located above the first opening.

8. The array substrate according to any one of claims 1-5, characterized in that, The width of the second opening is smaller than the width of the first opening.

9. The array substrate according to any one of claims 1 to 5, characterized in that, The width of the channel is less than or equal to the width of the first opening.

10. A display panel, characterized in that, include: The array substrate as described in any one of claims 1 to 9.

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