Test layout structure of semiconductor device, semiconductor layout structure and manufacturing method thereof

Abstract

The invention provides a test layout structure of a semiconductor device, a semiconductor layout structure and a manufacturing method thereof, the test layout structure of the semiconductor device comprises at least one sub-test layout layer, and the sub-test layout layer comprises a connection area layout layer and a test end layout layer; the first end of the connection region layout layer is used for connecting one of a substrate pattern region, a gate pattern region, a source pattern region and a drain pattern region of the semiconductor device, and the test end layout layer is connected with the second end of the connection region layout layer. According to the invention, compatibility of semiconductor devices with at least two architectures is realized, the utilization rate of the test layout structure is effectively improved, and layout resources are saved in typesetting layout.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a test layout structure for a semiconductor device, a semiconductor layout structure, and a method for manufacturing the same. Background Technology

[0002] For semiconductor devices with a COB (Capacitor over Bitline) architecture, the ferroelectric unit (Fe-Cap) is located between the first and second metal layers; for semiconductor devices with a CUB (Capacitor under Bitline) architecture, the ferroelectric unit is located between the active region and the first metal layer.

[0003] In related technologies, two types of wafer acceptability test key structures (WAT Testkey structures) need to be constructed to test the semiconductor devices of the two architectures mentioned above, resulting in a waste of layout resources in the layout.

[0004] In view of the above-mentioned technical problems, the present invention provides a new test layout structure for semiconductor devices, a semiconductor layout structure and a method for manufacturing the same. Summary of the Invention

[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] To address the existing problems, the present invention provides a test layout structure for a semiconductor device, the test layout structure comprising:

[0007] At least one sub-test version layer, the sub-test version layer including a connection area version layer and a test end version layer;

[0008] The first end of the connection area plate layer is used to connect to one of the substrate pattern area, gate pattern area, source pattern area and drain pattern area of ​​the semiconductor device, and the test end plate layer is connected to the second end of the connection area plate layer;

[0009] The connection area plate layer includes a first metal layer, and a contact hole structure and a first through hole zero structure are provided in the first end of the connection area plate layer so that the first metal layer connects to the semiconductor device.

[0010] The test end plate layer includes a second metal layer, and a through-hole structure is provided in the test end plate layer. A second through-hole zero structure is provided in the second end of the connection area plate layer, so that the second metal layer is connected to the first metal layer.

[0011] In some embodiments of this application, a first surface of a first end of the first metal layer is used to connect to the semiconductor device through the contact hole structure, and a first via zero structure is disposed on a second surface of the first end of the first metal layer; the second metal layer is connected to the second end of the first metal layer through the via structure forming a stack of holes and the second via zero structure.

[0012] In some embodiments of this application, the first through-hole zero structure and the contact hole structure are arranged vertically aligned.

[0013] In some embodiments of this application, the connection area layer includes a first dielectric layer and a second dielectric layer, a first surface of the first dielectric layer is used to connect the semiconductor device, and the second dielectric layer is disposed on the second surface of the first dielectric layer; the contact hole structure is disposed within the first dielectric layer, and the first metal layer, the first via zero structure, and the second via zero structure are disposed within the second dielectric layer.

[0014] In some embodiments of this application, the test end plate layer includes a third dielectric layer, the first surface of the third dielectric layer is connected to the second end of the connection area plate layer; the through-hole structure is disposed in the third dielectric layer, and the second metal layer is disposed on the second surface of the third dielectric layer.

[0015] In some embodiments of this application, the first end of the first metal layer is connected to the semiconductor device through the first via zero structure forming a stacked via and the contact hole structure; the second via zero structure is disposed on the first surface of the second end of the first metal layer, and the second metal layer is connected to the second surface of the second end of the first metal layer through the via structure.

[0016] In some embodiments of this application, the second through-hole zero structure and the through-hole structure are arranged vertically aligned.

[0017] In some embodiments of this application, the connection area layer includes a first dielectric layer and a second dielectric layer, a first surface of the first dielectric layer is used to connect the semiconductor device, and the second dielectric layer is disposed on the second surface of the first dielectric layer; the contact hole structure is disposed in the first dielectric layer, the first via zero structure and the second via zero structure are disposed in the second dielectric layer, and the first metal layer is disposed on the second surface of the second dielectric layer.

[0018] In some embodiments of this application, the test end plate layer includes a third dielectric layer, the first surface of the third dielectric layer is connected to the second end of the connection area plate layer; the through-hole structure is disposed in the third dielectric layer, and the second metal layer is disposed on the second surface of the third dielectric layer.

[0019] In another aspect, the present invention provides a semiconductor layout structure, the semiconductor layout structure comprising: a layout structure of a semiconductor device and a test layout structure of the semiconductor device as described above; wherein, the layout structure of the semiconductor device comprises: a substrate pattern area; an active region layout layer, the active region layout layer being disposed on the substrate pattern area; the active region layout layer comprising a gate pattern area, a source pattern area, and a drain pattern area; each connection region layout layer of the test layout structure of the semiconductor device is respectively connected to one of the substrate pattern area, gate pattern area, source pattern area, and drain pattern area of ​​the semiconductor device.

[0020] In another aspect, the present invention provides a method for manufacturing a test layout structure of a semiconductor device. The test layout structure includes at least one sub-test layout layer. The method for manufacturing each sub-test layout layer includes: forming a connection area layout layer, wherein a first end of the connection area layout layer is used to connect to one of a substrate pattern area, a gate pattern area, a source pattern area, and a drain pattern area of ​​the semiconductor device; forming a test end layout layer, wherein the test end layout layer is connected to a second end of the connection area layout layer; wherein the connection area layout layer includes a first metal layer, and a contact hole structure and a first via zero structure are provided in the first end of the connection area layout layer to connect the first metal layer to the semiconductor device; the test end layout layer includes a second metal layer, and a via structure is provided in the test end layout layer, and a second via zero structure is provided in the second end of the connection area layout layer to connect the second metal layer to the first metal layer.

[0021] In some embodiments of this application, forming the connection area layer includes: forming a first dielectric layer, wherein a first surface of the first dielectric layer is connected to the semiconductor device; forming a contact hole structure within the first dielectric layer; forming a first metal layer on a second surface of the first dielectric layer, wherein a first surface of a first end of the first metal layer is connected to the semiconductor device through the contact hole structure; forming a second dielectric layer covering the first dielectric layer and the first metal layer; and forming a first via zero structure and a second via zero structure within the second dielectric layer, wherein the first via zero structure is located on the second surface of the first end of the first metal layer, and the second via zero structure is located on the second surface of the second end of the first metal layer.

[0022] In some embodiments of this application, forming the test end plate layer includes: forming a third dielectric layer, the first surface of which is connected to the second end of the connection area plate layer; forming a via structure in the third dielectric layer, the via structure and the second via zero structure forming a stacked via; forming a second metal layer on the second surface of the third dielectric layer, the second metal layer being connected to the first metal layer through the stacked via.

[0023] In some embodiments of this application, the first through-hole zero structure and the contact hole structure are arranged vertically aligned.

[0024] In some embodiments of this application, forming the connection area layer includes: forming a first dielectric layer, the first surface of which is connected to the semiconductor device; forming a contact hole structure within the first dielectric layer; forming a second dielectric layer on the second surface of the first dielectric layer; forming a first via zero structure and a second via zero structure within the second dielectric layer, the first via zero structure and the contact hole structure forming a stacked via; forming a first metal layer on the second surface of the second dielectric layer, the first surface of the first end of the first metal layer being connected to the semiconductor device through the stacked via, and the second via zero structure being located on the first surface of the second end of the first metal layer.

[0025] In some embodiments of this application, forming the test end plate layer includes: forming a third dielectric layer, the first surface of which is connected to the second end of the connection area plate layer; forming a through-hole structure in the third dielectric layer; and forming a second metal layer on the second surface of the third dielectric layer, the second metal layer being connected to the first metal layer through the through-hole structure.

[0026] In some embodiments of this application, the second through-hole zero structure and the through-hole structure are arranged vertically aligned.

[0027] In another aspect, the present invention provides a method for manufacturing a semiconductor layout structure, the method comprising: providing a semiconductor device, the layout structure of the semiconductor device including a substrate pattern region and an active region layout layer, the active region layout layer being disposed on the substrate pattern region; the active region layout layer including a gate pattern region, a source pattern region, and a drain pattern region; and forming a test layout structure of the semiconductor device based on the manufacturing method of the test layout structure of the semiconductor device described in any one of the above-mentioned methods, wherein each connection region layout layer of the test layout structure of the semiconductor device is respectively connected to one of the substrate pattern region, the gate pattern region, the source pattern region, and the drain pattern region of the semiconductor device.

[0028] The test layout structure, semiconductor layout structure and manufacturing method of the semiconductor device disclosed in this application achieve compatibility with at least two semiconductor device architectures, effectively improve the utilization rate of the test layout structure, and save layout resources in terms of layout. Attached Figure Description

[0029] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0030] In the attached image:

[0031] Figure 1 A cross-sectional schematic diagram of a semiconductor device based on the COB architecture in the related art is shown;

[0032] Figure 2 A cross-sectional schematic diagram of a semiconductor device based on the CUB architecture in the related art is shown;

[0033] Figure 3 A cross-sectional schematic diagram of a wafer acceptability test bond structure constructed using semiconductor devices with a COB architecture in related technologies is shown.

[0034] Figure 4 This diagram shows a top view of the wafer acceptability test bond structure constructed using semiconductor devices based on the COB architecture in related technologies.

[0035] Figure 5 A cross-sectional schematic diagram of a wafer acceptability test bond structure constructed using semiconductor devices applicable to the CUB architecture in related technologies is shown.

[0036] Figure 6 The diagram shows a top view of the wafer acceptability test bond structure constructed using semiconductor devices based on the CUB architecture in the related art.

[0037] Figure 7 The diagram shows a top view of a test layout structure including a sub-test layout according to a specific embodiment of the present invention;

[0038] Figure 8 This illustration shows a 3D cross-sectional schematic diagram of a test layout structure constructed using a semiconductor device suitable for a COB architecture according to a specific embodiment of the present invention.

[0039] Figure 9 This diagram shows a 3D cross-sectional view of a test layout structure constructed using a semiconductor device adapted to the CUB architecture according to a specific embodiment of the present invention.

[0040] Figure 10 A top view of a semiconductor layout structure according to a specific embodiment of the present invention is shown. Detailed Implementation

[0041] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.

[0042] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0043] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0044] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0045] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0046] To fully understand this invention, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by this invention. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0047] COB architecture semiconductor devices, such as Figure 1 As shown, this includes the active region (see [reference needed] for details on the active region). Figure 4 The active region (in the image) has a source, a gate, and a drain. The source is connected to the first metal layer (Meat1, or M1) through a contact hole structure. The first metal layer is connected to the ferroelectric unit (Fe-Cap) through an OxidationVia (or Via0, defined as a Fe-CAP interconnect; in COB architecture semiconductor devices, Via0 is the Fe-CAP bottom electrode interconnect; in CUB architecture semiconductor devices, Via0 is the Fe-CAP top electrode interconnect) structure. The ferroelectric unit is connected to the second metal layer (Meat12, or M2) through a via structure. In other words, the ferroelectric unit is located between the first and second metal layers.

[0048] The CUB architecture semiconductor device is shown, including the active region (see [reference needed] for details). Figure 6 The active region is provided with a source, a gate, and a drain. The source is connected to the ferroelectric unit (Fe-Cap) through a contact structure. The ferroelectric unit is connected to the first metal layer (M1) through a zero-voltage (OV) structure. That is, the ferroelectric unit is located between the active region and the first metal layer.

[0049] In related technologies, for the two types of semiconductor devices mentioned above, corresponding wafer acceptability test bond structures are usually designed for testing.

[0050] Specifically, for COB architecture semiconductor devices, the constructed wafer acceptability test bond structure is as follows: Figure 3 and Figure 4 As shown, the device as a whole includes a MOS device region and a metal layer interconnection region. The first metal layer and the second metal layer are connected by a through-hole structure and a through-hole zero structure forming a stacked via. The first metal layer is connected to the substrate, source, gate or drain through a contact hole structure.

[0051] For CUB architecture semiconductor devices, the constructed wafer acceptability test bond structure is as follows: Figure 5 and Figure 6 As shown, the device as a whole includes a MOS device region and a metal layer interconnection region. The first metal layer and the second metal layer are connected through a via structure. The first metal layer is connected to the substrate, source, gate or drain through a via zero structure and a contact hole structure that form a stack of vias.

[0052] The above scheme requires the construction of two wafer acceptability test bond structures to test semiconductor devices of the corresponding architectures, resulting in a waste of layout resources in the layout.

[0053] Therefore, in view of the aforementioned technical problems, this application proposes a test layout structure for a semiconductor device, comprising: at least one sub-test layout layer, the sub-test layout layer including a connection area layout layer and a test terminal layout layer; a first end of the connection area layout layer is used to connect to one of the substrate pattern area, gate pattern area, source pattern area, and drain pattern area of ​​the semiconductor device, and the test terminal layout layer is connected to a second end of the connection area layout layer; wherein, the connection area layout layer includes a first metal layer, and a contact hole structure and a first via zero structure are provided in the first end of the connection area layout layer to connect the first metal layer to the semiconductor device; the test terminal layout layer includes a second metal layer, and a via structure is provided in the test terminal layout layer, and a second via zero structure is provided in the second end of the connection area layout layer to connect the second metal layer to the first metal layer.

[0054] The test layout structure of the semiconductor device according to this application achieves compatibility with at least two architectures of semiconductor devices, effectively improves the utilization rate of the test layout structure, and saves layout resources in terms of layout.

[0055] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0056] The following is for reference. Figures 7-10This application describes a test layout structure of a semiconductor device according to one embodiment of the present application. The test layout structure of a semiconductor device includes: at least one sub-test layout layer 100, which includes a connection area layout layer 110 and a test terminal layout layer 120; the first end of the connection area layout layer 110 is used to connect to one of the substrate pattern area (i.e., Sub), gate pattern area (i.e., Gate), source pattern area (i.e., Source), and drain pattern area (i.e., Drain) of the semiconductor device; the test terminal layout layer 120 is connected to the second end of the connection area layout layer 110; wherein, the connection area layout layer 110 includes a first metal layer (M1), and a contact hole structure and a first via zero structure (OV1) are provided in the first end of the connection area layout layer 110 to connect the first metal layer to the semiconductor device; the test terminal layout layer 120 includes a second metal layer (M2), and a via structure is provided in the test terminal layout layer 120; the second end of the connection area layout layer 110 is provided with a second via zero structure (OV2) to connect the second metal layer to the first metal layer.

[0057] Specifically, for COB architecture semiconductor devices, the first metal layer in the connection area layer 110 can be connected to the semiconductor device through contact hole structures, and the second metal layer in the test end layer 120 can be connected to the first metal layer in the connection area layer 110 through via structures and second via zero structures, thereby enabling wafer acceptability testing of COB architecture semiconductor devices. For CUB architecture semiconductor devices, the first metal layer in the connection area layer 110 can be connected to the semiconductor device through contact hole structures and first via zero structures, and the second metal layer in the test end layer 120 can be connected to the first metal layer in the connection area layer 110 through via structures, thereby enabling wafer acceptability testing of CUB architecture semiconductor devices.

[0058] Therefore, this application provides a test layout structure for semiconductor devices that can test both COB architecture semiconductor devices and CUB architecture semiconductor devices, achieving compatibility with both COB and CUB architecture semiconductor devices, effectively improving the utilization rate of the test layout structure, and saving layout resources in terms of layout.

[0059] Of course, the test layout structure of the semiconductor device in this embodiment is applicable not only to the above-mentioned COB and CUB architectures, but also to other architectures, and is not limited thereto.

[0060] In some embodiments, the number of sub-test layout layers 100 in the test layout structure of a semiconductor device can be set according to actual conditions and is not limited thereto. For example, as... Figure 10 As shown, taking the test layout structure of a semiconductor device as an example, it can include four sub-test layout layers 100. The four sub-test layout layers 100 are respectively connected to the substrate pattern area, gate pattern area, source pattern area and drain pattern area of ​​the semiconductor device.

[0061] In some embodiments, such as Figure 8 and Figure 9 As shown, the connection area layout layer 110 includes a first dielectric layer (ILD, Inter-Layer Dielectric) and a second dielectric layer (IMD0, Inter Metal Dielectric-0). The first surface of the first dielectric layer is used to connect semiconductor devices, and the second dielectric layer is disposed on the second surface of the first dielectric layer. The test end layout layer 120 includes a third dielectric layer (IMD1, Inter Metal Dielectric-1). The first surface of the third dielectric layer is connected to the second end of the connection area layout layer 110.

[0062] The first, second, and third dielectric layers can be formed sequentially by deposition. The specific deposition process can be physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc., and there is no limitation on this.

[0063] In some embodiments, such as Figure 8 As shown, when the test layout structure of a semiconductor device is applicable to a COB architecture semiconductor device, the contact hole structure is disposed in the first dielectric layer, the first metal layer, the first via zero structure, and the second via zero structure are disposed in the second dielectric layer; the via structure is disposed in the third dielectric layer, and the second metal layer is disposed on the second surface of the third dielectric layer.

[0064] The contact hole structure, the first via zero structure, the second via zero structure, and the via structure can be formed within the corresponding dielectric layer through etching processes. Specific etching processes can include dry etching, wet etching, etc., and are not limited thereto. Taking the formation of the contact hole structure within the first dielectric layer using a wet etching process as an example, a photoresist mask layer can first be formed on the second surface of the first dielectric layer. Through exposure and development processes, the photoresist mask layer is patterned to form a mask layer defining the contact hole structure to be formed. Then, an etchant solution can chemically react with the first dielectric layer to remove a portion of the material not covered by the mask layer, forming the contact hole structure within the first dielectric layer. Afterward, the mask layer on the first dielectric layer can be removed using a developer. The specific processes for forming the first and second via zero structures within the second dielectric layer, and for forming the via structure within the third dielectric layer, can be analogous to the description of forming the contact hole structure within the first dielectric layer, and will not be elaborated further here.

[0065] The first and second metal layers can be formed by a combination of deposition and etching. Specific deposition processes can include physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc., and etching processes can include dry etching, wet etching, etc., without any limitation.

[0066] It is worth noting that after each dielectric layer is deposited, a pore structure, metal layer, etc., associated with that dielectric layer can be formed first, and then the next dielectric layer can be deposited. Specifically, a first dielectric layer can be deposited first, and then a contact pore structure can be etched within the first dielectric layer. Then, a first metal layer can be formed on the second surface of the first dielectric layer through a combination of deposition and etching. Next, a second dielectric layer can be deposited, and then a first and second via zero structures can be etched within the second dielectric layer. Then, a third dielectric layer can be deposited, and then a via structure can be etched within the third dielectric layer. Finally, a second metal layer can be formed on the second surface of the third dielectric layer through a combination of deposition and etching.

[0067] Furthermore, such as Figure 8 As shown, the first surface of the first end of the first metal layer is used to connect to a semiconductor device through a contact hole structure, and the first through-hole zero structure is disposed on the second surface of the first end of the first metal layer; the second metal layer is connected to the second end of the first metal layer through a through-hole structure forming a stacked hole and the second through-hole zero structure.

[0068] The through-hole structure and the second through-hole zero structure are arranged vertically aligned, and the lower end of the through-hole structure contacts the upper end of the second through-hole zero structure, so that the through-hole structure and the second through-hole zero structure form a stacked hole.

[0069] Specifically, the first end of the first metal layer is electrically connected to one of the substrate pattern region, gate pattern region, source pattern region, and drain pattern region of the semiconductor device through a contact hole structure. The second metal layer is electrically connected to the second end of the first metal layer through a through-hole structure and a second through-hole zero structure. This allows the semiconductor device and the second metal layer to transmit electrical test signals through the contact hole structure, the first metal layer, the through-hole structure, and the second through-hole zero structure, so that the test layout structure can perform wafer acceptability testing on the semiconductor device.

[0070] It is worth noting that in this embodiment, the first through-hole zero structure is disposed on the second surface of the first end of the first metal layer. Since the upper end of the first through-hole zero structure is not connected to other conductive structures, the first through-hole zero structure can be regarded as being suspended.

[0071] Furthermore, such as Figure 8As shown, the first through-hole zero structure and the contact hole structure are vertically aligned. Because a first metal layer is provided between the first through-hole zero structure and the contact hole structure, the first metal layer isolates the first through-hole zero structure and the contact hole structure, so that although the first through-hole zero structure and the contact hole structure are vertically aligned, they do not form a stacked hole.

[0072] In some embodiments, such as Figure 9 As shown, when the test layout structure of the semiconductor device is applicable to the CUB architecture semiconductor device, the contact hole structure is disposed in the first dielectric layer, the first via zero structure and the second via zero structure are disposed in the second dielectric layer, and the first metal layer is disposed on the second surface of the second dielectric layer; the via structure is disposed in the third dielectric layer, and the second metal layer is disposed on the second surface of the third dielectric layer.

[0073] The contact hole structure, the first via zero structure, the second via zero structure, and the via structure can be formed within the corresponding dielectric layer through etching processes. Specific etching processes can include dry etching, wet etching, etc., and are not limited thereto. Taking the formation of the contact hole structure within the first dielectric layer using a wet etching process as an example, a photoresist mask layer can first be formed on the second surface of the first dielectric layer. Through exposure and development processes, the photoresist mask layer is patterned to form a mask layer defining the contact hole structure to be formed. Then, an etchant solution can chemically react with the first dielectric layer to remove a portion of the material not covered by the mask layer, forming the contact hole structure within the first dielectric layer. Afterward, the mask layer on the first dielectric layer can be removed using a developer. The specific processes for forming the first and second via zero structures within the second dielectric layer, and for forming the via structure within the third dielectric layer, can be analogous to the description of forming the contact hole structure within the first dielectric layer, and will not be elaborated further here.

[0074] The first and second metal layers can be formed by a combination of deposition and etching. Specific deposition processes can include physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc., and etching processes can include dry etching, wet etching, etc., without any limitation.

[0075] It is worth noting that after each dielectric layer is deposited, a pore structure, metal layer, etc., associated with that dielectric layer can be formed first, and then the next dielectric layer can be deposited. Specifically, a first dielectric layer can be deposited first, and then a contact pore structure can be etched within the first dielectric layer. Next, a second dielectric layer can be deposited, and then a first and second via zero structures can be etched within the second dielectric layer. Then, a first metal layer can be formed on the second surface of the second dielectric layer through a combination of deposition and etching. Then, a third dielectric layer can be deposited, and a via structure can be etched within the third dielectric layer. Finally, a second metal layer can be formed on the second surface of the third dielectric layer through a combination of deposition and etching.

[0076] Furthermore, such as Figure 9 As shown, the first end of the first metal layer is used to connect to a semiconductor device through a first through-hole zero structure and a contact hole structure forming a stacked hole; the second through-hole zero structure is disposed on the first surface of the second end of the first metal layer, and the second metal layer is connected to the second surface of the second end of the first metal layer through the through-hole structure.

[0077] The first through-hole zero structure and the contact hole structure are arranged vertically aligned, and the lower end of the first through-hole zero structure contacts the upper end of the contact hole structure, so that the first through-hole zero structure and the contact hole structure form a stacked hole.

[0078] Specifically, the first end of the first metal layer forms an electrical connection with one of the substrate pattern region, gate pattern region, source pattern region, and drain pattern region of the semiconductor device through the first via zero structure and contact hole structure forming a stacked via. The second metal layer forms an electrical connection with the second end of the first metal layer through the via structure. This allows the semiconductor device and the second metal layer to transmit electrical test signals through the first via zero structure and contact hole structure forming a stacked via, the first metal layer, and the via structure, so that the test layout structure can perform wafer acceptability testing on the semiconductor device.

[0079] It is worth noting that in this embodiment, the second through-hole zero structure is disposed on the first surface of the second end of the first metal layer. Since the lower end of the second through-hole zero structure is not connected to other conductive structures, the second through-hole zero structure can be regarded as being suspended.

[0080] Furthermore, such as Figure 9 As shown, the second through-hole zero structure and the through-hole structure are arranged vertically aligned. Because a second metal layer is provided between the second through-hole zero structure and the through-hole structure, the second metal layer isolates the second through-hole zero structure and the through-hole structure, so that although the second through-hole zero structure and the through-hole structure are arranged vertically, they do not form a stacked hole.

[0081] As can be seen from the above description, the semiconductor layout structure in this application, whether applicable to COB architecture semiconductor devices or CUB architecture semiconductor devices, forms a first via zero structure and a second via zero structure. The difference is that, when applicable to COB architecture semiconductor devices, both the first via zero structure and the second via zero structure are located above the first metal layer. In this case, the first via zero structure is suspended, and the first metal layer is connected to the semiconductor device only through contact hole structures. The second metal layer is connected to the first metal layer through via structures forming stacked holes and the second via zero structure. When applicable to CUB architecture semiconductor devices, both the first via zero structure and the second via zero structure are located below the first metal layer. In this case, the second via zero structure is suspended, and the first metal layer is connected to the semiconductor device through the first via zero structure forming stacked holes and contact hole structures. The second metal layer is connected to the first metal layer only through via structures.

[0082] According to another aspect of this application, a semiconductor layout structure is provided. For example... Figure 10 As shown, the semiconductor layout structure includes: a semiconductor device layout structure and a semiconductor device test layout structure; wherein, the semiconductor device layout structure includes: a substrate pattern area; an active area layout layer, the active area layout layer being disposed on the substrate pattern area; the active area layout layer includes a gate pattern area, a source pattern area, and a drain pattern area; each connection area layout layer of the semiconductor device test layout structure is connected to one of the substrate pattern area, gate pattern area, source pattern area, and drain pattern area of ​​the semiconductor device.

[0083] The test layout structure of the semiconductor device can be implemented as described above, and will not be repeated here.

[0084] Specifically, when the semiconductor device's process architecture is a COB (Chip-on-Board) architecture, the first metal layer in the connection area layer of the test layout structure can be connected to the semiconductor device through contact holes. The second metal layer in the test end layer can be connected to the first metal layer in the connection area layer through vias and second via zero structures, thus enabling wafer acceptability testing of the COB architecture semiconductor device. When the semiconductor device's process architecture is a CUB (Chip-on-Board) architecture, the first metal layer in the connection area layer of the test layout structure can be connected to the semiconductor device through contact holes and first via zero structures. The second metal layer in the test end layer can be connected to the first metal layer in the connection area layer through vias, thus enabling wafer acceptability testing of the CUB architecture semiconductor device. Of course, wafer acceptability testing can also be performed using the test layout structure when the semiconductor device's process architecture is other architectures; there are no limitations on this. It is worth noting that in this embodiment, the semiconductor layout structure, whether the semiconductor device process structure is a COB architecture or a CUB architecture, forms a first via zero structure and a second via zero structure. The difference is that when the semiconductor device process structure is a COB architecture, both the first via zero structure and the second via zero structure are located above the first metal layer, and the first via zero structure is suspended. When the semiconductor device process structure is a CUB architecture, both the first via zero structure and the second via zero structure are located below the first metal layer, and the second via zero structure is suspended.

[0085] Therefore, this application provides a semiconductor layout design that is compatible with at least two architectures, which effectively improves the utilization rate of semiconductor layout structure and saves layout resources in terms of typesetting.

[0086] According to another aspect of this application, a method for manufacturing a test layout structure of a semiconductor device is provided. The test layout structure includes at least one sub-test layout layer, and the method for manufacturing each sub-test layout layer includes:

[0087] A connection area layer is formed, the first end of which is used to connect one of the substrate pattern area, gate pattern area, source pattern area and drain pattern area of ​​the semiconductor device;

[0088] Create a test end plate layer, and connect the second end of the test end plate layer to the connection area plate layer;

[0089] The connection area plate layer includes a first metal layer, and a contact hole structure and a first through hole zero structure are provided in the first end of the connection area plate layer so that the first metal layer can connect to the semiconductor device.

[0090] The test end plate layer includes a second metal layer and has a through-hole structure. The second end of the connection area plate layer has a second through-hole structure so that the second metal layer can connect to the first metal layer.

[0091] Specifically, for COB architecture semiconductor devices, the first metal layer in the connection area layout layer can be connected to the semiconductor device through contact via structures. The second metal layer in the test layout layer can be connected to the first metal layer in the connection area layout layer through via structures and second via zero structures, thus enabling wafer acceptability testing of COB architecture semiconductor devices. For CUB architecture semiconductor devices, the first metal layer in the connection area layout layer can be connected to the semiconductor device through contact via structures and first via zero structures. The second metal layer in the test layout layer can be connected to the first metal layer in the connection area layout layer through via structures, thus enabling wafer acceptability testing of CUB architecture semiconductor devices. Of course, when the semiconductor device layout structure is other architectures, wafer acceptability testing can also be performed using the test layout structure; there are no limitations on this.

[0092] Therefore, the manufacturing method based on this application can produce a test layout structure that can test semiconductor devices of at least two architectures, achieving compatibility with semiconductor devices of at least two architectures, effectively improving the utilization rate of the test layout structure, and saving layout resources in terms of layout.

[0093] In some embodiments, the number of sub-test layout layers in the test layout structure of a semiconductor device can be set according to actual conditions and is not limited thereto. For example, as Figure 5 As shown, the test layout structure of a semiconductor device may include four sub-test layout layers. These four sub-test layout layers are respectively connected to the substrate pattern area, gate pattern area, source pattern area, and drain pattern area of ​​the semiconductor device.

[0094] In some embodiments, when forming a connection area layer for a semiconductor device suitable for a COB architecture, the layer may include:

[0095] A first dielectric layer is formed, and a semiconductor device is connected to a first surface of the first dielectric layer;

[0096] A contact hole structure is formed within the first dielectric layer;

[0097] A first metal layer is formed on the second surface of the first dielectric layer, and the first surface of the first end of the first metal layer is connected to a semiconductor device through a contact hole structure.

[0098] A second dielectric layer is formed covering the first dielectric layer and the first metal layer;

[0099] A first via zero structure and a second via zero structure are formed in the second dielectric layer. The first via zero structure is located on the second surface of the first end of the first metal layer, and the second via zero structure is located on the second surface of the second end of the first metal layer.

[0100] The first and second dielectric layers can be formed by deposition. The specific deposition process can be physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc., and there is no limitation on this.

[0101] Contact hole structures, first via numeric structures, and second via numeric structures can be formed within the corresponding dielectric layers through etching processes. Specific etching processes can include dry etching, wet etching, etc., and are not limited to one method. Taking the formation of contact hole structures within the first dielectric layer using a wet etching process as an example, a photoresist mask layer can first be formed on the second surface of the first dielectric layer. Through exposure and development processes, the photoresist mask layer is patterned to form a mask layer defining the contact hole structure to be formed. Then, an etchant solution can chemically react with the first dielectric layer to remove a portion of the material not covered by the mask layer, thus forming the contact hole structure within the first dielectric layer. Afterward, the mask layer on the first dielectric layer can be removed using a developer. The specific process for forming the first via numeric structures and second via numeric structures within the second dielectric layer can be analogous to the description of forming contact hole structures within the first dielectric layer described above, and will not be repeated here.

[0102] The first metal layer can be formed by a combination of deposition and etching. Specific deposition processes can include physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc., and etching processes can include dry etching, wet etching, etc., without any limitation.

[0103] In some embodiments, when forming a test panel layer for a semiconductor device suitable for a COB architecture, it may include:

[0104] A third dielectric layer is formed, and the first surface of the third dielectric layer is connected to the second end of the connecting area plate layer;

[0105] A through-hole structure is formed in the third dielectric layer, and the through-hole structure and the second through-hole zero structure form a stacked hole;

[0106] A second metal layer is formed on the second surface of the third dielectric layer, and the second metal layer is connected to the first metal layer through a stacked via.

[0107] The third medium layer can be formed by deposition, and the specific deposition process can be physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc., without limitation.

[0108] Through-hole structures can be formed within the third dielectric layer through an etching process. Specific etching processes can include dry etching, wet etching, etc., and are not limited to any particular process. The specific process of forming a through-hole structure within the third dielectric layer is analogous to the description of forming a contact hole structure within the first dielectric layer, and will not be elaborated further here.

[0109] The second metal layer can be formed by a combination of deposition and etching. Specific deposition processes can include physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc., and etching processes can include dry etching, wet etching, etc., without any limitation.

[0110] In some embodiments, the first through-hole zero structure and the contact hole structure are vertically aligned. A first metal layer is disposed between the first through-hole zero structure and the contact hole structure, isolating them and preventing them from forming a stacked hole structure despite their vertical alignment.

[0111] In some embodiments, when forming a connection area layer for a semiconductor device applicable to a CUB architecture, the layer may include:

[0112] A first dielectric layer is formed, and a semiconductor device is connected to a first surface of the first dielectric layer;

[0113] A contact hole structure is formed within the first dielectric layer;

[0114] A second dielectric layer is formed on the second surface of the first dielectric layer;

[0115] A first through-hole zero structure and a second through-hole zero structure are formed in the second dielectric layer, and the first through-hole zero structure and the contact hole structure form a stacked hole;

[0116] A first metal layer is formed on the second surface of the second dielectric layer. The first surface of the first end of the first metal layer is connected to a semiconductor device through a via. The second via zero structure is located on the first surface of the second end of the first metal layer.

[0117] The first and second dielectric layers can be formed by deposition. The specific deposition process can be physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc., and there is no limitation on this.

[0118] Contact hole structures, first via numeric structures, and second via numeric structures can be formed within the corresponding dielectric layers through etching processes. Specific etching processes can include dry etching, wet etching, etc., and are not limited to one method. Taking the formation of contact hole structures within the first dielectric layer using a wet etching process as an example, a photoresist mask layer can first be formed on the second surface of the first dielectric layer. Through exposure and development processes, the photoresist mask layer is patterned to form a mask layer defining the contact hole structure to be formed. Then, an etchant solution can chemically react with the first dielectric layer to remove a portion of the material not covered by the mask layer, thus forming the contact hole structure within the first dielectric layer. Afterward, the mask layer on the first dielectric layer can be removed using a developer. The specific process for forming the first via numeric structures and second via numeric structures within the second dielectric layer can be analogous to the description of forming contact hole structures within the first dielectric layer described above, and will not be repeated here.

[0119] The first metal layer can be formed by a combination of deposition and etching. Specific deposition processes can include physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc., and etching processes can include dry etching, wet etching, etc., without any limitation.

[0120] In some embodiments, when forming a test panel layer for a semiconductor device applicable to a CUB architecture, the process may include:

[0121] A third dielectric layer is formed, and the first surface of the third dielectric layer is connected to the second end of the connecting area plate layer;

[0122] A through-hole structure is formed within the third dielectric layer;

[0123] A second metal layer is formed on the second surface of the third dielectric layer, and the second metal layer is connected to the first metal layer through a through-hole structure.

[0124] The third medium layer can be formed by deposition, and the specific deposition process can be physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc., without limitation.

[0125] Through-hole structures can be formed within the third dielectric layer through an etching process. Specific etching processes can include dry etching, wet etching, etc., and are not limited to any particular process. The specific process of forming a through-hole structure within the third dielectric layer is analogous to the description of forming a contact hole structure within the first dielectric layer, and will not be elaborated further here.

[0126] The second metal layer can be formed by a combination of deposition and etching. Specific deposition processes can include physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc., and etching processes can include dry etching, wet etching, etc., without any limitation.

[0127] In some embodiments, the second via zero structure and the via structure are vertically aligned. A second metal layer is provided between the second via zero structure and the via structure, isolating them and preventing them from forming a stacked via, even though they are vertically aligned.

[0128] According to another aspect of this application, a method for manufacturing a semiconductor layout structure is provided, the method comprising:

[0129] A semiconductor device is provided, the layout structure of which includes a substrate pattern area and an active area layout layer, the active area layout layer being disposed in the substrate pattern area; the active area layout layer includes a gate pattern area, a source pattern area, and a drain pattern area;

[0130] A method for manufacturing a test layout structure based on a semiconductor device forms a test layout structure for the semiconductor device. Each connection area layer of the test layout structure of the semiconductor device is connected to one of the substrate pattern area, gate pattern area, source pattern area, and drain pattern area of ​​the semiconductor device.

[0131] The method for forming the test layout structure of a semiconductor device can be implemented as the manufacturing method of the test layout structure of a semiconductor device described above, which can be referred to in the above description and will not be repeated here.

[0132] In summary, the test layout structure, semiconductor layout structure and manufacturing method of the semiconductor device according to the embodiments of this application achieve compatibility with at least two architectures of semiconductor devices, effectively improve the utilization rate of the test layout structure, and save layout resources in terms of layout.

[0133] The present invention has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, those skilled in the art will understand that the present invention is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of the present invention, all of which fall within the scope of protection claimed by the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A test layout structure for a semiconductor device, characterized in that, The test layout structure includes: At least one sub-test version layer, the sub-test version layer including a connection area version layer and a test end version layer; The first end of the connection area plate layer is used to connect to one of the substrate pattern area, gate pattern area, source pattern area and drain pattern area of ​​the semiconductor device, and the test end plate layer is connected to the second end of the connection area plate layer; The connection area plate layer includes a first metal layer, and a contact hole structure and a first through hole zero structure are provided in the first end of the connection area plate layer so that the first metal layer connects to the semiconductor device. The test end plate layer includes a second metal layer, and a through-hole structure is provided in the test end plate layer. A second through-hole zero structure is provided in the second end of the connection area plate layer, so that the second metal layer is connected to the first metal layer.

2. The semiconductor layout structure as described in claim 1, characterized in that, The first surface of the first end of the first metal layer is used to connect the semiconductor device through the contact hole structure, and the first through-hole zero structure is disposed on the second surface of the first end of the first metal layer; The second metal layer is connected to the second end of the first metal layer through the through-hole structure forming the stacked holes and the second through-hole zero structure.

3. The semiconductor layout structure as described in claim 2, characterized in that, The first through-hole zero structure and the contact hole structure are aligned vertically.

4. The semiconductor layout structure as described in claim 2, characterized in that, The connection area layer includes a first dielectric layer and a second dielectric layer. The first surface of the first dielectric layer is used to connect the semiconductor device, and the second dielectric layer is disposed on the second surface of the first dielectric layer. The contact hole structure is disposed within the first dielectric layer, and the first metal layer, the first through-hole zero structure, and the second through-hole zero structure are disposed within the second dielectric layer.

5. The semiconductor layout structure as described in claim 2, characterized in that, The test end plate layer includes a third medium layer, and the first surface of the third medium layer is connected to the second end of the connection area plate layer; The through-hole structure is disposed within the third dielectric layer, and the second metal layer is disposed on the second surface of the third dielectric layer.

6. The semiconductor layout structure as described in claim 1, characterized in that, The first end of the first metal layer is used to connect to the semiconductor device through the first through-hole zero structure forming a stacked hole and the contact hole structure; The second through-hole structure is disposed on the first surface of the second end of the first metal layer, and the second metal layer is connected to the second surface of the second end of the first metal layer through the through-hole structure.

7. The semiconductor layout structure as described in claim 6, characterized in that, The second through-hole zero structure and the through-hole structure are aligned vertically.

8. The semiconductor layout structure as described in claim 6, characterized in that, The connection area layer includes a first dielectric layer and a second dielectric layer. The first surface of the first dielectric layer is used to connect the semiconductor device, and the second dielectric layer is disposed on the second surface of the first dielectric layer. The contact hole structure is disposed within the first dielectric layer, the first through-hole zero structure and the second through-hole zero structure are disposed within the second dielectric layer, and the first metal layer is disposed on the second surface of the second dielectric layer.

9. The semiconductor layout structure as described in claim 2, characterized in that, The test end plate layer includes a third medium layer, and the first surface of the third medium layer is connected to the second end of the connection area plate layer; The through-hole structure is disposed within the third dielectric layer, and the second metal layer is disposed on the second surface of the third dielectric layer.

10. A semiconductor layout structure, characterized in that, The semiconductor layout structure includes: The layout structure of a semiconductor device and the test layout structure of a semiconductor device as described in any one of claims 1 to 9; The layout structure of the semiconductor device includes: Substrate pattern area; An active region pattern layer is disposed on the substrate pattern area; the active region pattern layer includes a gate pattern area, a source pattern area, and a drain pattern area. Each connection area layer of the test layout structure of the semiconductor device is connected to one of the substrate pattern area, gate pattern area, source pattern area, and drain pattern area of ​​the semiconductor device.

11. A method for manufacturing a test layout structure for a semiconductor device, characterized in that, The test layout structure includes at least one sub-test layout layer, and the method for manufacturing each sub-test layout layer includes: A connection area plate layer is formed, wherein the first end of the connection area plate layer is used to connect one of the substrate pattern area, gate pattern area, source pattern area and drain pattern area of ​​the semiconductor device; A test end plate layer is formed, and the test end plate layer is connected to the second end of the connection area plate layer; The connection area plate layer includes a first metal layer, and a contact hole structure and a first through hole zero structure are provided in the first end of the connection area plate layer so that the first metal layer connects to the semiconductor device. The test end plate layer includes a second metal layer, and a through-hole structure is provided in the test end plate layer. A second through-hole zero structure is provided in the second end of the connection area plate layer, so that the second metal layer is connected to the first metal layer.

12. The method for manufacturing the test layout structure as described in claim 11, characterized in that, The formation of the connection area layer includes: A first dielectric layer is formed, and a first surface of the first dielectric layer is connected to the semiconductor device; A contact hole structure is formed within the first dielectric layer; A first metal layer is formed on the second surface of the first dielectric layer, and the first surface of the first end of the first metal layer is connected to the semiconductor device through the contact hole structure. A second dielectric layer is formed covering the first dielectric layer and the first metal layer; A first via zero structure and a second via zero structure are formed within the second dielectric layer. The first via zero structure is located on the second surface of the first end of the first metal layer, and the second via zero structure is located on the second surface of the second end of the first metal layer.

13. The method for manufacturing the test layout structure as described in claim 12, characterized in that, The formation of the test panel layer includes: A third dielectric layer is formed, wherein the first surface of the third dielectric layer is connected to the second end of the connecting area plate layer; A through-hole structure is formed in the third dielectric layer, and the through-hole structure and the second through-hole zero structure form a stacked hole; A second metal layer is formed on the second surface of the third dielectric layer, and the second metal layer is connected to the first metal layer through the stacked vias.

14. The method for manufacturing the test layout structure as described in claim 12, characterized in that, The first through-hole zero structure and the contact hole structure are aligned vertically.

15. The method for manufacturing the test layout structure as described in claim 11, characterized in that, The formation of the connection area layer includes: A first dielectric layer is formed, and a first surface of the first dielectric layer is connected to the semiconductor device; A contact hole structure is formed within the first dielectric layer; A second dielectric layer is formed on the second surface of the first dielectric layer; A first through-hole zero structure and a second through-hole zero structure are formed in the second dielectric layer, and the first through-hole zero structure and the contact hole structure form a stacked hole; A first metal layer is formed on the second surface of the second dielectric layer, and the first surface of the first end of the first metal layer is connected to the semiconductor device through the via. The second via zero structure is located on the first surface of the second end of the first metal layer.

16. The method for manufacturing the test layout structure as described in claim 15, characterized in that, The formation of the test panel layer includes: A third dielectric layer is formed, wherein the first surface of the third dielectric layer is connected to the second end of the connecting area plate layer; A through-hole structure is formed within the third dielectric layer; A second metal layer is formed on the second surface of the third dielectric layer, and the second metal layer is connected to the first metal layer through the through-hole structure.

17. The method for manufacturing the test layout structure as described in claim 16, characterized in that, The second through-hole zero structure and the through-hole structure are aligned vertically.

18. A method for manufacturing a semiconductor layout structure, characterized in that, The manufacturing method includes: A semiconductor device is provided, wherein the layout structure of the semiconductor device includes a substrate pattern area and an active region layout layer, the active region layout layer being disposed on the substrate pattern area; the active region layout layer includes a gate pattern area, a source pattern area, and a drain pattern area; A test layout structure of a semiconductor device is formed based on a manufacturing method of a test layout structure of a semiconductor device as described in any one of claims 12 to 17, wherein each connection area layer of the test layout structure of the semiconductor device is respectively connected to one of the substrate pattern area, gate pattern area, source pattern area and drain pattern area of ​​the semiconductor device.

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