Electrostatic and surge protection device applied to high-speed ADC input port

Abstract

The invention relates to an electrostatic and surge protection device applied to a high-speed ADC input port, and belongs to the technical field of electrostatic and surge protection of integrated circuits. According to the device, a plurality of P traps and a plurality of injection regions are arranged in a deep N trap on a semiconductor substrate, a PNP and NPN structure, a diode structure and transistors are formed based on the P traps and the injection regions, and an SCR structure is formed based on the transistors, so that a composite structure is formed to realize the effects of low-voltage triggering, immune latch-up and bidirectional protection; therefore, the problems that an existing SCR structure cannot be timely started in an ESD / EOS event due to the fact that trigger voltage is too high, latching is caused due to the fact that hysteresis voltage is too low, and the ESD / EOS event from a cathode port cannot be protected through a one-way protection device are solved.

Description

Technical Field

[0001] This invention relates to the field of electrostatic discharge (ESD) and surge protection technology for integrated circuits, and in particular to an ESD and surge protection device for high-speed ADC input ports. Background Technology

[0002] Electrostatic discharge (ESD) and surges are the two most common types of transient electromagnetic interference in electronic systems operating environments, also known as electrical overstress (EOS). These two transient pulses are the main causes of interface failures in electronic devices. ESD is usually caused by charge transfer due to contact, friction, or separation of different materials (triboelectric charging), and it discharges instantaneously when the electric field strength exceeds the dielectric breakdown threshold, with a pulse width typically ranging from 10 to 100 ns. Surges, on the other hand, mainly refer to transient overvoltages or overcurrents of longer duration, usually caused by lightning induction (indirect lightning strikes), power grid switching (such as capacitive load switching), fault transients, etc., with pulse widths ranging from hundreds of nanoseconds to tens of microseconds.

[0003] High-speed analog-to-digital converters (ADCs) are core devices that quickly and accurately convert high-frequency analog signals into digital signals, and are widely used in communications, radar, medical imaging, test and measurement, and industrial control. Due to their precision, high speed, high frequency, and low voltage characteristics, high-speed ADCs are extremely sensitive to transient electromagnetic interference. As electronic devices evolve towards smaller, thinner, and more integrated designs, high-speed ADC input ports, to meet the core requirements of high sampling rates, high bandwidth, and high precision, employ extremely thin gate oxide layers and low operating voltages. Electrostatic discharge (ESD) generated during manufacturing processes and during transportation can directly break down the thin gate oxide layer of the input stage MOSFETs, burn out differential pairs or metal interconnects, leading to permanent failure of the high-speed ADC input port and ultimately rendering the chip unusable. Furthermore, high-speed ADCs contain multiple sensitive nodes, including analog power supplies, digital power supplies, and reference voltages. Even if a power rail disturbance caused by ESD / surges does not directly break down the gate oxide layer, it can cause malfunctions in internal analog circuits (such as sample-and-hold amplifiers, comparators, and reference sources), resulting in performance degradation. Furthermore, the analog input terminals of high-speed analog-to-digital converters (ADCs) are highly sensitive to charge injection. High-frequency transient currents generated by electrostatic discharge (ESD) events can be directly coupled to the input terminals, interfering with the signal integrity at the moment of sampling or causing latch-up effects in the input protection diodes. Therefore, enhancing the ESD / EOS protection capability of the high-speed ADC input ports is an important measure to improve the stability and reliability of high-speed ADCs.

[0004] Common basic ESD / EOS protection units suitable for high-speed ADC input ports include unidirectional diodes, bipolar junction transistors (BJTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and silicon controlled rectifiers (SCRs). Unidirectional diodes are characterized by their simple structure, low turn-on voltage, small parasitic capacitance, and fast turn-on speed. By connecting a low-capacitance diode in parallel between the analog input pin of the high-speed ADC and the power supply or ground, the unidirectional diode is reverse-biased and non-conducting during normal operation, without affecting the signal path. When a transient high voltage occurs, the breakdown voltage of the unidirectional diode is lower than the maximum withstand voltage of the ADC, and the unidirectional diode quickly enters the conducting state, diverting the overvoltage current to the power supply or ground, forming a low-impedance discharge path, thereby protecting the high-speed ADC. However, the forward conduction voltage of the unidirectional diode is relatively low, which may generate leakage current during normal operation. Therefore, multiple unidirectional diodes or additional resistors need to be connected in series, leading to an increase in area and on-resistance. Furthermore, the reverse breakdown current withstand capability of the diode is limited, and it may fail under extreme ESD events. The protection principle of a bipolar junction transistor (BJT) is that when an external electrostatic discharge (ESD) or electromagnetic transient (EOS) occurs, the discharge voltage will first cause the emitter junction to conduct in the forward direction, forming a large current amplification and rapidly introducing the transient energy into the base. Emitter circuit and through collector Reverse breakdown of the base junction directs current to ground or power supply, achieving low-voltage clamping and limiting peak current. However, the base-collector junction capacitance of a bipolar junction transistor (BJT) increases input load and reduces bandwidth in high-speed ADCs, leading to signal distortion. Furthermore, BJTs are limited by temperature and their asymmetric characteristics, potentially causing false triggering / protection failure or increasing layout area and power consumption. A metal-oxide-semiconductor (MOSFET) field-effect transistor has a gate-source breakdown voltage lower than the absolute maximum input voltage of the high-speed ADC. Upon discharge, the MOSFET immediately enters avalanche breakdown, directing charge to ground or power supply, thus protecting the input port of the high-speed ADC. The low on-resistance of the MOSFET provides steady-state current limiting during prolonged overvoltage periods, preventing damage to the high-speed ADC port due to sustained overvoltage. However, the nonlinear input capacitance of the MOSFET varies with voltage, introducing gain error. At high frequencies, the parasitic inductance and resistance of the MOSFET can create damping, causing ringing or signal distortion, affecting sampling accuracy. Controlled rectifier silicon controlled rectifiers (SCRs) achieve protection based on positive feedback. When ESD or EOS occurs, if the instantaneous voltage exceeds the SCR's trigger voltage, the positive feedback immediately pulls the SCR into a low-impedance conduction state. After conduction, the SCR provides a low-impedance discharge path for transient current, limiting the inrush current to a safe level, thereby protecting the high-speed ADC front-end amplifier from breakdown. However, if the trigger voltage of the controlled rectifier silicon controlled rectifier is too high, the protection window will be limited, making low-voltage systems vulnerable to damage. Furthermore, the turn-on speed is relatively slow, and some high-frequency transient voltages can still penetrate the protection layer. There is also a latch-up problem caused by excessive hysteresis, which seriously affects the normal operation of the protected circuit.

[0005] Therefore, there is an urgent need to provide an innovative electrostatic discharge and surge protection device for high-speed ADC input ports to overcome the aforementioned technical deficiencies in existing technologies. Summary of the Invention

[0006] To address the aforementioned problems, this invention provides an electrostatic discharge and surge protection device for the input port of a high-speed ADC, enabling it to achieve low-voltage triggering, latch-up immunity, and high robustness.

[0007] The protective device includes a substrate, a deep N-well, and a metal component, which are arranged sequentially from bottom to top. The substrate is a P-type substrate; Several P-wells, including a first P-well, a second P-well, and a third P-well, are arranged at intervals on the side of the deep N-well away from the substrate. The first P-well, the second P-well, and the third P-well are arranged sequentially along the length of the substrate. The three P-wells do not contact each other, and the first P-well and the third P-well do not contact the edge of the deep N-well either. Furthermore, a first Pb well and a second Pb well are respectively disposed in the first P well and the third P well. The first Pb well is disposed on the side of the first P well away from the substrate and does not contact the two sides of the first P well. The second Pb well is disposed in the third P well at a position symmetrical to the first Pb well about the second P well. Furthermore, a plurality of P+ and N+ implantation regions are disposed inside the deep N-well on the side away from the substrate, including a first P+ implantation region, a first N+ implantation region, a second P+ implantation region, a second N+ implantation region, a third P+ implantation region, a third N+ implantation region, a fourth P+ implantation region, a fourth N+ implantation region, and a fifth P+ implantation region; the plurality of implantation regions are disposed sequentially in the above order, and the plurality of implantation regions are disposed at intervals; Furthermore, the first P+ injection region and the fifth P+ injection region are respectively located on both sides of the deep N-well and do not contact the edge of the deep N-well; Furthermore, the first N+ injection region is disposed in the first Pb well and does not contact the edge of the first Pb well, and the fourth P+ injection region is disposed in the second Pb well and similarly does not contact the edge of the second Pb well. Furthermore, the second P+ injection region is disposed in the first P well and does not contact the edge of the first Pb well and the first P well; the fourth P+ injection region is disposed in the third P well at a position symmetrical to the second P+ injection region about the second P well. Furthermore, the second N+ injection region, the third P+ injection region, and the third N+ injection region are disposed in the second P-well, and the three are spaced apart and do not contact the edge of the second P-well; The metal component includes several metal connecting units and several metals, including a first metal connecting unit, a second metal connecting unit, a third metal connecting unit, a fourth metal connecting unit, a fifth metal connecting unit, a sixth metal connecting unit, a seventh metal connecting unit, an eighth metal connecting unit, a ninth metal connecting unit, a first metal, a second metal, and a third metal; Furthermore, the first metal connector is disposed above the first P+ injection region, the second metal connector is disposed above the first N+ injection region, the third metal connector is disposed above the second N+ injection region, the fourth metal connector is disposed above the second P+ injection region, the fifth metal connector is disposed above the third P+ injection region, the sixth metal connector is disposed above the fourth P+ injection region, the seventh metal connector is disposed above the third N+ injection region, the eighth metal connector is disposed above the fourth N+ injection region, and the ninth metal connector is disposed above the fifth P+ injection region. Furthermore, the first metal is disposed above the first metal connecting unit, the second metal connecting unit, and the third metal connecting unit, and extends outward toward the direction of the first metal connecting unit; The second metal is positioned above the fourth metal connecting unit, the fifth metal connecting unit, and the sixth metal connecting unit; The third metal is positioned above the seventh, eighth, and ninth metal connecting units and extends outward toward the ninth metal connecting unit; Furthermore, the first electrode extending from the first metal connection unit of the first metal serves as the anode of the protective device, and the second electrode extending from the ninth metal connection unit of the third metal serves as the cathode of the protective device. Furthermore, the second N+ injection region, the second P-well, and the third N+ injection region constitute an embedded NPN transistor. Through the internal carrier movement of the emitter-base-collector, the small control current of the base is converted into a large current of the collector, thereby forming a complete current path in the circuit and providing an additional current path for the protection device. Furthermore, when a forward ESD is applied to the anode of the protective device and the cathode is grounded, the first N+ injection region and the first Pb well form a Zener diode, the third P+ injection region and the third N+ injection region form a first diode, and the fourth P+ injection region and the fourth N+ injection region form a second diode. Furthermore, an auxiliary triggering path is formed by a Zener diode, a first diode, and a second diode, where the forward voltage drop of the diode cancels out the voltage drop of the Zener diode, causing the combined threshold of the two to decrease as a whole, thereby reducing the trigger voltage and improving the turn-on speed. Furthermore, because Zener diodes have a better clamping effect, the hysteresis voltage of the protection device is higher, thus avoiding the latch-up effect of the protection device. Furthermore, when the anode of the protective device is connected to a high potential and the cathode is grounded, the first N+ injection region, the second P+ injection region, the fourth P+ injection region, and the fourth N+ injection region constitute a series structure of a Zener diode plus a diode; the first N+ injection region, the second P+ injection region, the third P+ injection region, and the third N+ injection region also constitute a series structure of a Zener diode plus a diode; this series structure forms a series capacitance between the Zener diode and the diode, and the equivalent capacitance is dominated by the small capacitance, thereby reducing the capacitance of the protective device and ensuring the integrity of high-speed signals; Furthermore, when the anode of the protective device is grounded and the cathode is connected to a high potential, the conduction structure of the protective device is the same as when the anode is connected to a high potential and the cathode is grounded, thus providing bidirectional ESD protection. Furthermore, when the anode of the protective device is connected to a high potential and the cathode is grounded, the first P+ injection region, the deep N-well, and the fifth P+ injection region constitute a PNP structure, which serves as a PNP auxiliary path to provide an additional current path. Furthermore, when ESD occurs, the protective device can discharge current through NPN and PNP transistors. Since the paths of the two are different, they can shunt the ESD current, making the device conduction more uniform and effectively improving the robustness of the protective device. Furthermore, the first P+ injection region, the deep N-well, and the second P-well constitute the first transistor; the deep N-well, the second P-well, and the third N+ injection region constitute the second transistor; and the deep N-well, the third P-well, and the fourth N+ injection region constitute the third transistor. The first transistor and the second / third transistor together constitute the SCR structure. Since the collector current of the first transistor provides the base current for the second / third transistor, and the collector current of the second / third transistor, in turn, provides the base current for the first transistor, a closed-loop positive feedback is formed by means of the current amplification effect, which effectively improves the current discharge capability of the overall device and effectively improves the robustness of the electrostatic surge protection circuit.

[0008] The beneficial effects of this invention are: This invention provides a bidirectional electrostatic surge protection device for the input port of a high-speed ADC. It utilizes a plurality of P-wells and injection regions formed within a deep N-well on a semiconductor substrate. These P-wells and injection regions create PNP and NPN structures, providing additional current paths for current shunting and improving robustness. Furthermore, the injection regions form a plurality of diodes, whose series connection reduces capacitance and ensures signal integrity. The diode structure also provides an auxiliary trigger path, lowering the trigger voltage and improving turn-on speed. The clamping diodes further enhance hysteresis voltage, preventing latch-up. Additionally, the device incorporates transistors formed by the injection regions, deep N-wells, and P-wells, with each transistor forming an SCR structure to create a closed-loop positive feedback loop, improving current discharge capability and electrostatic protection robustness. The protective device provided by this invention achieves low-voltage triggering, latch-up immunity, and bidirectional protection through a composite structure composed of a transistor's SDR closed-loop positive feedback structure, PNP, NPN, and diode. This overcomes the problems of existing SCR structures, such as excessively high trigger voltage leading to failure to open in time during ESD / EOS events, excessively low hysteresis voltage causing latch-up, and the inability of unidirectional protective devices to protect against ESD / EOS events from the cathode port. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a three-dimensional structural diagram of a bidirectional electrostatic surge protection device applied to the input port of a high-speed ADC, provided in Embodiment 1 of the present invention. Figure 2 This is an equivalent circuit diagram of a bidirectional electrostatic surge protection device applied to the input port of a high-speed ADC, provided in Embodiment 1 of the present invention. Figure 3 This is a schematic diagram illustrating an application scenario of a bidirectional electrostatic surge protection device for a high-speed ADC input port, as provided in Embodiment 2 of the present invention. The reference numerals in the attached figures are explained as follows: 100 - substrate, 101 - deep N-well, 102 - first P-well, 103 - second P-well, 104 - third P-well, 105 - first Pb-well, 106 - second Pb-well, 107 - first P+ implantation region, 108 - first N+ implantation region, 109 - second P+ implantation region, 110 - second N+ implantation region, 111 - third P+ implantation region, 112 - third N+ implantation region, 113 - fourth P+ implantation region, 114 - fourth N+ implantation region, 1 15-Fifth P+ injection region, 201-First metal connection unit, 202-Second metal connection unit, 203-Third metal connection unit, 204-Fourth metal connection unit, 205-Fifth metal connection unit, 206-Sixth metal connection unit, 207-Seventh metal connection unit, 208-Eighth metal connection unit, 209-Ninth metal connection unit, 210-First metal, 211-Second metal, 212-Third metal, Anode end 301, Cathode end 302. Detailed Implementation

[0011] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0012] Example 1 This embodiment provides a bidirectional electrostatic surge protection device for the input port of a high-speed ADC, such as... Figure 1 As shown, the protective device includes The protective device includes a substrate 100, a deep N-well 101, and a metal component, which are arranged sequentially from bottom to top. Substrate 100 is a P-type substrate; A plurality of P-wells are arranged at intervals on the side of the deep N-well 101 away from the substrate 100, including a first P-well 102, a second P-well 103 and a third P-well 104, wherein the first P-well 102, the second P-well 103 and the third P-well 104 are arranged sequentially along the length direction of the substrate 100, and the three do not contact each other, and the first P-well 102 and the third P-well 104 also do not contact the edge of the deep N-well 101; A first Pb well 105 and a second Pb well 106 are respectively disposed in the first P well 102 and the third P well 104. The first Pb well 105 is disposed on the side of the first P well 102 away from the substrate 100 and does not contact the two sides of the first P well 102. The second Pb well 106 is disposed in the third P well 104 at a position symmetrical to the first Pb well 105 about the second P well 103. A plurality of P+ and N+ implantation regions are disposed inside the deep N-well 101 on the side away from the substrate 100, including a first P+ implantation region 107, a first N+ implantation region 108, a second P+ implantation region 109, a second N+ implantation region 110, a third P+ implantation region 111, a third N+ implantation region 112, a fourth P+ implantation region 113, a fourth N+ implantation region 114, and a fifth P+ implantation region 115; the plurality of implantation regions are arranged sequentially in the above order, and the plurality of implantation regions are arranged at intervals. The first P+ injection region 107 and the fifth P+ injection region 115 are respectively disposed on both sides of the deep N-well 101 and do not contact the edge of the deep N-well 101. The first N+ injection region 108 is disposed in the first Pb well 105 and does not contact the edge of the first Pb well 105; the fourth P+ injection region 113 is disposed in the second Pb well 106 and similarly does not contact the edge of the second Pb well 106. The second P+ injection region 109 is disposed in the first P well 102 and does not contact the edges of the first Pb well 105 and the first P well 102. The fourth P+ injection region 113 is disposed in the third P well 104 at a position symmetrical to the second P+ injection region 109 about the second P well 103. The second N+ injection region 110, the third P+ injection region 111 and the third N+ injection region 112 are disposed in the second P-well 103, and are spaced apart and do not contact the edge of the second P-well 103. The metal component includes several metal connecting units and several metals, including a first metal connecting unit 201, a second metal connecting unit 202, a third metal connecting unit 203, a fourth metal connecting unit 204, a fifth metal connecting unit 205, a sixth metal connecting unit 206, a seventh metal connecting unit 207, an eighth metal connecting unit 208, a ninth metal connecting unit 209, a first metal 210, a second metal 211, and a third metal 212; The first metal connector is disposed above the first P+ injection area 107; the second metal connector unit 202 is disposed above the first N+ injection area 108; the third metal connector unit 203 is disposed above the second N+ injection area 110; the fourth metal connector unit 204 is disposed above the second P+ injection area 109; the fifth metal connector unit 205 is disposed above the third P+ injection area 111; the sixth metal connector unit 206 is disposed above the fourth P+ injection area 113; the seventh metal connector unit 207 is disposed above the third N+ injection area 112; the eighth metal connector unit 208 is disposed above the fourth N+ injection area 114; and the ninth metal connector unit 209 is disposed above the fifth P+ injection area 115. The first metal 210 is disposed above the first metal connecting unit 201, the second metal connecting unit 202 and the third metal connecting unit 203, and extends outward toward the first metal connecting unit 201; The second metal 211 is disposed above the fourth metal connecting unit 204, the fifth metal connecting unit 205 and the sixth metal connecting unit 206; The third metal 212 is disposed above the seventh metal connecting unit 207, the eighth metal connecting unit 208 and the ninth metal connecting unit 209, and extends outward toward the ninth metal connecting unit 209; The first electrode of the first metal 210 extending from the first metal connection unit 201 serves as the anode 301 of the protective device, and the second electrode of the third metal 212 extending from the ninth metal connection unit 209 serves as the cathode 302 of the protective device. The equivalent circuit of this embodiment is as follows: Figure 2 As shown, Wherein, the first P+ injection region, the deep N-well, and the second P-well constitute the first transistor T1; the deep N-well, the second P-well, and the third N+ injection region constitute the second transistor T2; the deep N-well, the third P-well, and the fourth N+ injection region constitute the third transistor T3; the second N+ injection region, the second P-well, and the third N+ injection region constitute the fourth transistor T4; and the first P+ injection region, the deep N-well, and the fifth P+ injection region constitute the fifth transistor T5. The emitter of the first transistor T1 is connected to the anode port 301, and the collector of the first transistor T1 is connected to the collectors of the second transistor T2 and the third transistor T3. The emitters of the second transistor T2 and the third transistor T3 are connected to the cathode port 302, wherein the bases of the second transistor T2 and the third transistor T3 are connected. The collector of the fourth transistor T4 is connected to the anode port 301, the base of the fourth transistor T4 is connected to the second transistor T2 and the third transistor T3, and the emitter of the fourth transistor T4 is connected to the cathode port 302. The emitter of the fifth transistor T5 is connected to the anode port 301, the base of the fifth transistor T5 is connected to the base of the first transistor T1, and the collector of the fifth transistor T5 is connected to the cathode port 302. The anode of the Zener diode ZD is connected to the anode port 301, the cathode of the Zener diode is connected to the base of the second transistor T2, the anode of diode D1 is connected to the base of the second transistor T2, and the cathode of diode D1 is connected to the cathode port 302. The anode of diode D2 is connected to the base of the third transistor T3, and the cathode of diode D2 is connected to the cathode port 302. When a forward ESD is applied to VDD and Vss is grounded, the first N+ injection region 108 and the first Pb well 105 form a Zener diode ZD, the third P+ injection region 111 and the third N+ injection region form a first diode D1, and the fourth P+ injection region and the fourth N+ injection region form a second diode D2. The Zener diode ZD, together with the first diode D1 and the first diode D2, forms an auxiliary trigger path, which improves the turn-on speed and reduces the trigger voltage. Furthermore, because the Zener diode ZD has a good clamping effect, the hysteresis voltage of the device is higher, which effectively avoids the latch-up of the device. The first transistor, together with the second and third transistors, forms an SCR structure. Since the collector current of the first transistor provides the base current for the second and third transistors, and the collector current of the second and third transistors in turn provides the base current for the first transistor, a closed-loop positive feedback is formed by means of the current amplification effect, which effectively improves the current discharge capability of the overall device and the robustness of the electrostatic surge protection circuit. The first P+ injection region 107, the deep N-well 101, and the fifth P+ injection region 115 constitute a PNP structure, while the second N+ injection region 110 and the third N+ injection region 112 constitute an NPN structure. The PNP and NPN structures provide additional current discharge paths, making the conduction more uniform and reducing the hot spot focusing problem, thereby further improving the robustness of the device.

[0013] When the anode 301 is connected to a high potential and the cathode 302 is grounded, the fourth metal connection unit 204, the fifth P+ metal connection unit 205, and the sixth metal connection unit 206 are connected through the second metal 211 to form a surface shunt path, which promotes uniform conduction of the device. When the anode 301 is connected to a high potential and the cathode 302 is grounded, and when the cathode 302 is connected to a high potential and the anode 301 is grounded, the current conduction path is the same, providing bidirectional ESD / EOS protection.

[0014] By utilizing the fast turn-on and voltage clamping characteristics of Zener diodes, and through a composite structure involving PNP, NPN, Zener diodes, and SCRs, a novel ESD / EOS protection device for high-speed ADC input ports is constructed to improve the HBM / CDM protection level of high-speed ADC input ports.

[0015] This embodiment provides a bidirectional electrostatic surge protection device for high-speed ADC input ports, which not only has a fast turn-on speed, low voltage triggering and high clamping effect, but also enhances the overcurrent capability of the device by adjusting the width of the device. At the same time, it can flexibly adopt multi-finger interfaces to further improve the robustness of the invention and improve the HBM / CDM protection level of the high-speed ADC input port.

[0016] Example 2 This embodiment provides a bidirectional electrostatic surge protection method for a high-speed ADC input port. This method is based on the protection device described in Embodiment 1. The method involves applying this protection device to a specific circuit, such as... Figure 3 As shown, it includes the positive analog input terminal AIN_P and the negative analog input terminal AIN_M of the high-speed ADC chip; the anode terminals 301 of the two protection devices are connected to the positive analog input terminal AIN_P and the negative analog input terminal AIN_M of the high-speed ADC chip respectively, and the cathode terminal 302 is grounded.

[0017] This protective device utilizes a first N+ injection region 108 and a first Pb well 105 to form a Zener diode ZD, a third P+ injection region 111 and a third N+ injection region 112 to form a first diode D1, and a fourth P+ injection region 113 and a fourth N+ injection region 114 to form a second diode D2. The Zener diode ZD, the first diode D1 and the second diode D2 form an auxiliary trigger path, which improves the turn-on speed and reduces the trigger voltage. Furthermore, based on the clamping effect of the Zener diode ZD, the hysteresis voltage of the device is increased, thus preventing latch-up of the device. Furthermore, the first transistor T1 in this protective device, together with the second transistor T2 and the third transistor T3, forms an SCR structure. The collector current of the first transistor T1 provides the base current for the second transistor T2 and the third transistor T3, and the collector current of the second transistor T2 and the third transistor T3, in turn, provides the base current for the first transistor T1. With the help of the current amplification effect, a closed-loop positive feedback is formed, which effectively improves the overall current discharge capability of the device and the robustness of the electrostatic surge protection circuit. The PNP structure formed by the first P+ injection 107, the deep N-well 101 and the fifth P+ injection 115, and the NPN structure formed by the second N+ injection 110 and the third N+ injection 112 provide additional current discharge paths.

[0018] The fourth metal connection unit 204, the fifth P+ metal connection unit 205, and the sixth metal connection unit 206 of the protective device are connected through the second metal 211 to form a surface current shunt path, which promotes uniform conduction of the device. Furthermore, regardless of whether the anode 301 of the protective device is connected to a high potential and the cathode 302 is grounded, or the cathode 302 is connected to a high potential and the anode 301 is grounded, the current conduction path is the same, thus achieving bidirectional ESD / EOS protection.

[0019] In this embodiment, the protection circuit is applied to the positive analog input terminal AIN_P and the negative analog input terminal AIN_M of the high-speed ADC to achieve bidirectional ESD / EOS protection for the AIN_P and AIN_M pins, thereby improving the reliability of the high-speed ADC during operation.

[0020] Some steps in the embodiments of the present invention can be implemented using software, and the corresponding software program can be stored in a readable storage medium, such as an optical disc or a hard disk.

[0021] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A bidirectional electrostatic surge protection device for use at the input port of a high-speed ADC, characterized in that, The device includes a substrate (100), a deep N-well (101), and a metal component, which are arranged sequentially from bottom to top. The deep N-well (101) is provided with several P-wells and several injection regions. The device constructs an SCR closed-loop positive feedback structure based on the injection regions, P-wells and deep N-well (101) to achieve electrostatic surge protection for the input port of the high-speed ADC.

2. The device according to claim 1, characterized in that, The plurality of P-wells are disposed inside the deep N-well (101) on the side away from the substrate (100), and the plurality of P-wells include a first P-well (102), a second P-well (103) and a third P-well (104). The first P-well (102), the second P-well (103) and the third P-well (104) are arranged sequentially at intervals along the length direction of the substrate (100). The first P-well (102) and the third P-well (104) are located at both ends inside the deep N-well (101) and do not contact the edge of the deep N-well (101). A first Pb well (105) is provided in the first P well (102). The first Pb well (105) is located inside the first P well (102) on the side away from the substrate (100) and does not contact the two sides of the first P well (102). The third P-well (104) is provided with a second Pb-well (106), which is located in the third P-well (104) at a position symmetrical to the first Pb-well (105) about the second P-well (103).

3. The device according to claim 2, characterized in that, The plurality of injection regions are disposed inside the deep N-well (101) on the side away from the substrate (100), including a first P+ injection region (107), a first N+ injection region (108), a second P+ injection region (109), a second N+ injection region (110), a third P+ injection region (111), a third N+ injection region (112), a fourth P+ injection region (113), a fourth N+ injection region (114), and a fifth P+ injection region (115). The injection regions are arranged at intervals in the above positions. The first P+ injection region (107) and the fifth P+ injection region (115) are respectively located at both ends inside the deep N-well (101) and do not contact the edge of the deep N-well (101).

4. The device according to claim 3, characterized in that, The first N+ injection region (108) is disposed in the first Pb well (105) and does not contact the edge of the first Pb well (105); the fourth P+ injection region (113) is disposed in the second Pb well (106) and does not contact the edge of the second Pb well (106). The second P+ injection region (109) is disposed in the first P well (102) and does not contact the edges of the first Pb well (105) and the first P well (102); the fourth P+ injection region (113) is disposed in the third P well (104) at a position symmetrical to the second P+ injection region (109) about the second P well (103); The second N+ injection region (110), the third P+ injection region (111) and the third N+ injection region (112) are disposed in the second P-well (103), and the three are spaced apart and do not contact the edge of the second P-well (103).

5. The device according to claim 4, characterized in that, The metal component includes several metal connecting units and several metals; The plurality of metal connection units include a first metal connection unit (201), a second metal connection unit (202), a third metal connection unit (203), a fourth metal connection unit (204), a fifth metal connection unit (205), a sixth metal connection unit (206), a seventh metal connection unit (207), an eighth metal connection unit (208), and a ninth metal connection unit (209). The plurality of metals includes a first metal (210), a second metal (211), and a third metal (212).

6. The device according to claim 5, characterized in that, The first metal connection unit (201) is disposed above the first P+ injection area (107), the second metal connection unit (202) is disposed above the first N+ injection area (108), the third metal connection unit (203) is disposed above the second N+ injection area (110), the fourth metal connection unit (204) is disposed above the second P+ injection area (109), the fifth metal connection unit (205) is disposed above the third P+ injection area (111), the sixth metal connection unit (206) is disposed above the fourth P+ injection area (113), the seventh metal connection unit (207) is disposed above the third N+ injection area (112), the eighth metal connection unit (208) is disposed above the fourth N+ injection area (114), and the ninth metal connection unit (209) is disposed above the fifth P+ injection area (115). The first metal (210) is disposed above the first metal connecting unit (201), the second metal connecting unit (202) and the third metal connecting unit (203), and extends outward toward the first metal connecting unit (201); The second metal (211) is disposed above the fourth metal connecting unit (204), the fifth metal connecting unit (205), and the sixth metal connecting unit (206); The third metal (212) is disposed above the seventh metal connecting unit (207), the eighth metal connecting unit (208) and the ninth metal connecting unit (209), and extends outward toward the ninth metal connecting unit (209); The first electrode of the first metal (210) extending from the first metal connection unit (201) serves as the anode (301) of the protective device, and the second electrode of the third metal (212) extending from the ninth metal connection unit (209) serves as the cathode (302) of the protective device.

7. The device according to claim 6, characterized in that, The second N+ injection region (110), the second P-well (103), and the third N+ injection region (112) constitute an embedded NPN transistor. Through the internal carrier movement of the emitter-base-collector, the control current of the base is converted into the current of the collector, thereby forming a current path and providing a current path for the device. The first P+ injection region (107), the deep N-well (101), and the fifth P+ injection region (115) constitute a PNP structure, which serves as a PNP auxiliary path to provide a current path.

8. The device according to claim 7, characterized in that, When the anode (301) of the device is connected to a high potential and the cathode (302) is grounded, the first N+ injection region (108), the second P+ injection region (109), the fourth P+ injection region (113), and the fourth N+ injection region (114) constitute a Zener diode plus a diode series structure; the first N+ injection region (108), the second P+ injection region (109), the third P+ injection region (111), and the third N+ injection region (112) also constitute a Zener diode plus a diode series structure; When the anode (301) of the device is grounded and the cathode (302) is connected to a high potential, the conduction structure of the protection device is the same as when the anode (301) is connected to a high potential and the cathode (302) is grounded.

9. The device according to claim 8, characterized in that, The first N+ injection region (108) and the first Pb well (105) constitute a Zener diode, the third P+ injection region (111) and the third N+ injection region (112) constitute a first diode, and the fourth P+ injection region (113) and the fourth N+ injection region (114) constitute a second diode. The Zener diode, the first diode, and the second diode constitute the auxiliary triggering path of the device.

10. An electrostatic discharge and surge protection system, characterized in that, The system employs the device described in any one of claims 1-9 to achieve electrostatic discharge and surge protection.

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