Class-II superlattice detector and preparation method thereof

Abstract

The invention belongs to the technical field of semiconductors, and particularly relates to a class-II superlattice detector and a preparation method thereof, and the class-II superlattice detector comprises a germanium layer grown on a silicon substrate and a gallium arsenide layer formed on the germanium layer. And III-V group semiconductor compounds are alternately grown on the gallium arsenide layer. After the second-class superlattice material prepared by the method is applied to an infrared detector, a high-resolution image can be formed, and the second-class superlattice material has high-quality and uniform performance.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a type II superlattice detector and its fabrication method. Background Technology

[0002] T2SL (type-2 superlattice) materials grown on GaSb substrates are a novel infrared detection material technology that has seen rapid development internationally in recent years. In particular, nBn-type T2SL infrared detectors offer advantages such as suppressing Auger recombination and reducing tunneling current, maintaining high performance even at high operating temperatures. Based on the numerous advantages and characteristics of type-2 superlattices in infrared detector applications, their material physics, growth techniques, and device fabrication technologies have attracted considerable attention from research institutions. Currently, with the continuous progress and improvement of GaSb-based infrared detectors, there have been significant advancements in device fabrication and material preparation technologies. At this stage, improving the cost and performance of T2SL is paramount. To improve cost and performance, larger diameter wafers are needed to increase throughput, volume, and yield. However, current manufacturing processes for nBn-type T2SL infrared detector materials, both domestically and internationally, can only produce 2-inch and 4-inch epitaxial wafers. Furthermore, due to technological embargoes, China's nBn-type T2SL infrared detector production is still in its early stages, with only the production capacity for 2-inch T2SL materials. Molecular beam epitaxy (MBE) is a complex process with high control difficulty. Large-size epitaxial growth can lead to increased stress due to lattice mismatch and high material defect density, making it unsuitable for device fabrication. Furthermore, traditional GaSb epitaxial wafer fabrication requires a complete substrate removal step, which is quite challenging. As is well known, incomplete substrate removal affects the quantum efficiency of the detector, and current full substrate removal technology is still immature and requires expensive materials. Summary of the Invention

[0003] This invention primarily provides a large-size superlattice infrared material capable of forming high-resolution images and exhibiting high-quality uniformity when fabricated into an infrared detector, as well as a low-cost method for preparing this material. This overcomes the problems of conventional processes in the prior art, which struggle to produce large-size epitaxial wafers and require substrate removal, which is difficult and leads to high production costs and low yields. The technical solution is as follows:

[0004] A type II superlattice material includes a germanium layer grown on a silicon substrate and a gallium arsenide layer formed on the germanium layer; wherein group III-V semiconductor compounds are alternately grown on the gallium arsenide layer.

[0005] Furthermore, the diameter of the silicon substrate is 2 to 6 inches; the thickness of the germanium layer is 600 to 1200 nm; and the thickness of the gallium arsenide layer is 400 to 1000 nm.

[0006] Furthermore, the III-V group compounds include binary, ternary, and quaternary compounds selected from elements of Group IIIA and Group VA.

[0007] A method for preparing the above-mentioned type II superlattice material includes the following steps:

[0008] a. Use a clean silicon wafer as a substrate; in a vacuum environment of 250~350℃, in an atmosphere of hydrogen germanide and hydrogen, perform germanium nucleation on the substrate; after nucleation, heat treat at 800~900℃ for 3~10 min, and then continue to grow the germanium layer;

[0009] b. Clean the substrate with the germanium layer to remove surface contaminants; under vacuum conditions, grow an arsenic layer on the germanium layer at 550~620℃ using an arsenic beam; then in an arsenic-free environment, bond the gallium layer with the arsenic layer using a gallium beam to form a gallium arsenide nucleus; introduce an arsenic beam to continue growth on the gallium arsenide nucleus to form a gallium arsenide layer; after growth, perform high-temperature annealing.

[0010] c. After annealing, grow epitaxial material on the gallium arsenide layer.

[0011] By using a truncated substrate, optimizing initial nucleation conditions, and employing thermal annealing, antiphase domains in molecular beam epitaxy (MBE) growth are suppressed.

[0012] Furthermore, after thoroughly washing the silicon wafer, it is subjected to high-temperature treatment in a reducing atmosphere to remove the surface oxide layer, resulting in a clean silicon wafer.

[0013] Furthermore, the substrate with the grown germanium layer is thoroughly washed to remove organic contaminants, and then heat-treated at 450~550℃ to remove oxides from the surface of the germanium layer.

[0014] Furthermore, UV ozone cleaning is performed, and the natural oxides on the surface of the germanium layer are removed by thermal desorption at a temperature of 500±1℃.

[0015] Furthermore, the vacuum degree in step a is 5~15 mT; the vacuum degree in step b is 10 mT. -10 ~1.5×10 -10 T.

[0016] A detector made of the aforementioned type II superlattice material has a noise equivalent temperature difference of no more than 30 mK.

[0017] A method for fabricating the detector described above includes the following steps: depositing a silicon dioxide hard mask on the surface of the type II superlattice material as described in any one of claims 1 to 3; then performing reactive ion etching in a vacuum under the action of an etching gas; after removing the resist, performing inductively coupled plasma etching at 1 to 10 mT to complete pixel isolation; then continuing to deposit a silicon dioxide passivation layer; and depositing a contact layer after opening the passivation layer.

[0018] Furthermore, the thickness of the hard mask is 200~300nm; the thickness of the passivation layer is 0.5~1.5µm; the etching gas for reactive ion etching is a mixture of carbon tetrafluoride and oxygen, or a mixture of carbon tetrafluoride, trifluoromethane, and oxygen; the etching gas for inductively coupled plasma etching is a mixture of boron chloride and argon, or a mixture of methane, hydrogen, and chlorine.

[0019] By adopting the above scheme, the method of the present invention has the following advantages:

[0020] 1. The method of this invention improves the substrate material by replacing the GaSb substrate with a Si substrate, and growing nbn-type superlattice materials on the Si substrate. Si substrates are significantly cheaper than GaSb substrates, offering a cost advantage, and are also easier to grow larger T2SL materials on. Furthermore, this invention simplifies the device manufacturing process, enabling the fabrication of larger-sized and higher-volume epitaxial wafers.

[0021] 2. The present invention uses Si as the substrate. The physical properties of the Si substrate can eliminate the need for a complete substrate removal process, enabling high-volume production and greatly improving product yield. This solves the problems of high cost of GaSb substrate removal and incomplete removal affecting the quantum efficiency of the detector.

[0022] 3. The method of this invention utilizes molecular beam epitaxy to grow nBn-type superlattice infrared materials on Si substrates. By growing a Ge layer on the Si substrate with a lattice constant very close to that of GaAs, and then using molecular beam epitaxy to grow a GaAs layer, the problems of lattice constant mismatch and thermal expansion coefficient mismatch between the Si substrate and GaAs material, which would result in very large lattice dislocations, are solved. This method successfully fabricates large-size nBn-type superlattice infrared materials, laying the foundation for realizing large-area infrared detectors and greatly reducing the cost of material growth and device fabrication.

[0023] 4. In conventional materials, GaAs is grown on GaSb, which is a lattice-matched growth. However, the GaAs layer of the superlattice material of this invention is grown on Ge material, which is a mismatched growth. The roughness is greater than that of matched growth. However, the roughness control effect of the material prepared by the targeted optimization method of this invention is better and significantly better than the material prepared by the unoptimized method.

[0024] 5. Regardless of whether it is in the middle or at the edge of the wafer, the material of the present invention exhibits high consistency in quality, with a mismatch close to zero, a full width at half maximum (FWHM) of the first-order diffraction peak of about 0.0070, and a period thickness fluctuation of less than 0.3%, which makes the fluctuation of the superlattice detection wavelength at different positions negligible.

[0025] 6. The epitaxial wafer material in the detector preparation method of the present invention does not need to be subjected to acetone, and the material morphology is intact. This solves the problem in the prior art that the epitaxial material on the upper layer of the epitaxial wafer material is completely immersed in the solvent, and long-term immersion in the solvent will damage the material and result in poor mesa morphology. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the structure of the two types of superlattice materials synthesized in Example 1;

[0027] Figure 2 These are optical microscope images of the two types of superlattice materials synthesized in Example 1;

[0028] Figure 3 These are atomic force microscopy images of the two types of superlattice materials synthesized in Example 1;

[0029] Figure 4 This is an atomic force microscope image of the type II superlattice material synthesized in Comparative Example 1;

[0030] Figure 5 These are surface defect morphology diagrams of the two types of superlattice materials synthesized in Example 1;

[0031] Figure 6 The image shows the X-ray diffraction pattern of the type II superlattice material synthesized in Example 1.

[0032] Figure 7 This is a cross-sectional view of the infrared detector prepared in Example 1;

[0033] Figure 8 This is a cross-sectional view of the infrared detector made in Comparative Example 2;

[0034] Figure 9 This is a performance test diagram of the infrared detector prepared in Example 1;

[0035] Figure 10 This is a spectral response curve of the infrared detector prepared in Example 1;

[0036] Figure 11 The image is taken by the infrared detector of Example 1. Detailed Implementation

[0037] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0038] Example 1: (1) Prepare a 6-inch silicon wafer with a flat and smooth surface, perform surface cleaning to remove organic and inorganic substances from the surface; place the cleaned silicon wafer in a vacuum reaction chamber at 900°C and H2 atmosphere for 10 minutes to remove the oxide layer on the surface.

[0039] (2) Place the silicon wafer treated with H2 into the CVD vacuum reaction chamber, maintain the chamber temperature at around 300℃ and the chamber pressure at 10mT, introduce GeH4 and H2, and perform Ge nucleation on the Si surface; immediately after nucleation, perform high-temperature annealing at 850℃ for 5min to reduce surface defects; after annealing, continue to grow at 750℃ to obtain a 1-micron-thick Ge layer;

[0040] (3) The silicon wafer with the deposited Ge layer was first pre-cleaned. The pre-cleaning steps were: immersion in acetone for 5 minutes, ethanol for 2 minutes, isopropanol for 1 minute, and then drying the surface with nitrogen. The cleaned Ge substrate was first subjected to UV ozone cleaning to remove surface contaminants. Then the Ge substrate was placed in the MBE chamber and the oxide on the surface of the Ge layer was removed by thermal desorption at a high temperature of about 500°C. The As beam was turned on first, and the growth temperature was maintained at 600°C to grow a monolayer of As on the Ge surface. Then the As beam was turned off and the Ga beam was turned on in the As-free environment to bond and form GaAs molecules, completing the initial nucleation of GaAs. After nucleation, the As beam was turned on again to grow an 800nm ​​GaAs buffer layer, and the vacuum degree of the growth chamber was maintained at 1×10 -10 T; After GaAs layer growth, perform high-temperature annealing at 600℃ for 5 minutes to reduce dislocation defects; according to Figure 1 The structure is further grown on the gallium arsenide layer to obtain a type II superlattice material epitaxial wafer;

[0041] Figure 2 The material surface was observed using an optical microscope at 1000x magnification, which clearly revealed the microscopic morphology and micro-defects on the material surface. The defect size was approximately 8 μm, and the statistical defect density was 614 cm⁻¹. -2 The surface defects were relatively few when examined under a microscope.

[0042] Figure 3 Atomic force microscopy revealed a smooth material surface with atomic steps visible in a 5μm × 5μm region, exhibiting roughness Rq = 0.115nm and Ra = 0.0891. GaAs grown on GaSb exhibits slightly higher roughness than Ga grown on Ga, due to the increased roughness resulting from the increasing mismatch between the device layer and the substrate material; however, the increase in uniform surface roughness obtained using the optimized method of this invention is extremely limited and perfectly acceptable for device fabrication.

[0043] Figure 5This is a representative image of surface defect density measured and quantified using the Surfscan tool. The Surfscan defect mapping tool can assess material surface morphology. This image shows a low and relatively uniform defect density across the entire material surface, with Surfscan displaying a defect density of 4.64 cm⁻¹ larger than 0.8 μm. -2 .

[0044] The spacing between adjacent test points was controlled at 7 mm along the diameter, and 7 test points were set. X-ray diffraction scans were performed sequentially, and the horizontal axis x in the figure represents the distance between the test point and the center of the wafer. Figure 6 The figures show the mismatch, period thickness, and full width at half maximum (FWHM) of the first-order diffraction peak at different locations of the superlattice device structure. As can be seen from the figures, the material exhibits high quality consistency across both the center and edge of the wafer, with a mismatch close to zero. The FWHM of the first-order diffraction peak is approximately 0.0070, and the period thickness fluctuates by less than 0.3%. This makes the fluctuations in the superlattice detection wavelength at different locations negligible.

[0045] (4) A 250nm silicon dioxide hard mask is deposited on the epitaxial wafer by CVD; a MESA pattern is formed on the surface of the epitaxial wafer by photolithography; at 10mT, a 3:1 mixture of CF4 and O2 is used as the etching gas, and silicon dioxide is etched at 250nm by RIE.

[0046] (5) After removing the adhesive, the epitaxial wafer is immediately subjected to a temperature of 250℃ and 6.8×10⁻⁶. -4 At kPa, ICP etching was performed with 5 sccm BCl3, with an RF power of 270W and an ICP power of 800W. The etching reached a barrier layer depth of 120nm, completing pixel isolation. The entire process did not involve contact with organic solutions.

[0047] (6) A 1-micron silicon dioxide passivation layer is deposited using CVD without removing the SiO2 hard mask. The passivation layer is opened using RIE, and finally Ti / Pt / Au contact layer metal is deposited using electron beam evaporation.

[0048] Figure 7 shows a cross-sectional view, in which it can be seen that the product has a normal shape and a very regular tabletop.

[0049] Comparative Example 1: The difference from Example 1 is that:

[0050] (3) The silicon wafer with the above-deposited Ge layer was first pre-cleaned. The pre-cleaning steps were: soaking in acetone for 5 minutes, ethanol for 2 minutes, isopropanol for 1 minute, and then drying the surface with nitrogen. First, the As beam was turned on, and the growth temperature was maintained at 580℃ to grow a monolayer of As on the Ge surface. Then, the As beam was turned off, and the Ga beam was turned on in the As-free environment to bond and form GaAs molecules, completing the initial nucleation of GaAs. After nucleation, the As beam was turned on again to grow an 800nm ​​GaAs buffer layer, and the vacuum degree of the growth chamber was maintained at 1×10 -10 T; After GaAs layer growth is complete, perform high-temperature annealing at 680℃ for 2 minutes.

[0051] Comparative Example 1, which uses a conventional process, did not undergo UV ozone cleaning or the removal of oxides affecting GaAs deposition on the surface. Furthermore, the annealing temperature was higher and the annealing time was shorter than in Example 1. The resulting material's atomic force microscopy image is shown below. Figure 4 As shown, the roughness Rq=0.162nm and Ra=0.129nm are significantly higher than those of Example 1 obtained by the method of the present invention, indicating that the method of the present invention can overcome the technical problem that increased material mismatch leads to increased roughness.

[0052] Comparative Example 2: (1) A MESA pattern was formed on the surface of an epitaxial wafer using photolithography, and then the epitaxial wafer was subjected to a temperature of 250°C and 6.8 × 10⁻⁶ °C. -4 At kPa, ICP etching was performed with 5 sccm BCl3, with an RF power of 270W and an ICP power of 800W, etching to a barrier layer depth of 120nm to complete pixel isolation.

[0053] (2) After removing the adhesive, deposit Ti / Pt / Au contact layer metal by electron beam evaporation; continue to deposit a 1-micron silicon dioxide passivation layer by CVD;

[0054] (4) At 10 mT, a mixture of CF43 and O2 in a ratio of 3:1 was used as the etching gas to etch silicon dioxide by RIE for 1 micrometer.

[0055] AlAsSb material has a higher etching rate than InAsSb contact and absorber layers. After etching the mesa sidewalls formed in step (1), the sidewalls are exposed to the solution during the resist removal process. The acetone solution corrodes the sidewalls, thus revealing the lateral etching of the AlAsSb barrier. Figure 8 As shown, the lateral etching of the AlAsSb barrier causes the contact layer to protrude, resulting in an irregular morphology and poor controllability. During the SiO2 passivation process, the contact layer and the absorption layer cannot be passivated by SiO2, which leads to excessive leakage current and the detector cannot work properly.

[0056] Example Sample Testing:

[0057] The infrared detector and readout circuit chip, made using the material from Example 1, were flip-soldered together. The back of the flip-soldered readout circuit chip was then attached to the test PCB board using acetal adhesive. Wire bonding was used to connect the test pad and common electrode to the corresponding pad on the PCB board. When testing the dark current, a blind cooling screen was fixed directly above the flip-soldered chip with tape to avoid interference from infrared light. The entire PCB board was then placed in a liquid nitrogen Dewar flask, liquid nitrogen was poured in, and the test instrument leads were attached to different pins on the PCB board to test the dark current of the FPA. Figure 9 and Figure 10 Various performance curves of the infrared detector FPA are presented, showing excellent characteristics up to 150K, demonstrating the high operating temperature (HOT) capability of this material structure, low dark current (<10) at a -0.1 V operating bias. -5 A / cm 2 The spectral response was as expected, ranging from 4.2 to 4.8 μm. Within the temperature range of 90–150 °C, the quantum efficiency remained relatively constant, and the material's quality did not decrease due to dislocations, traps, scattering, or recombination centers.

[0058] Images captured by the infrared detector made using the material of Example 1 are as follows: Figure 11 As shown. Figure 11 This confirms that Example 1 is a high-quality detector material, capable of obtaining high-quality images with good resolution and quality consistency. The infrared detector has an operability of 99% and a NETD of approximately 20 mK.

[0059] For those skilled in the art, various other corresponding changes and modifications can be made based on the technical solutions and concepts described above, and all such changes and modifications should fall within the protection scope of the claims of this invention.

Claims

1. A type-two superlattice material, characterized in that, It includes a germanium layer grown on a silicon substrate and a gallium arsenide layer formed on the germanium layer; the gallium arsenide layer is alternately grown with group III-V semiconductor compounds.

2. The type-II superlattice material according to claim 1, characterized in that, The diameter of the silicon substrate is 2 to 6 inches; the thickness of the germanium layer is 600 to 1200 nm; and the thickness of the gallium arsenide layer is 400 to 1000 nm.

3. The type-two superlattice material according to claim 1, characterized in that, The III-V group compounds include binary, ternary, and quaternary compounds selected from elements of Group IIIA and Group VA.

4. A method for preparing a type II superlattice material according to any one of claims 1 to 3, characterized in that, Includes the following steps: a. Use a clean silicon wafer as a substrate; in a vacuum environment of 250~350℃, in an atmosphere of hydrogen germanide and hydrogen, perform germanium nucleation on the substrate; after nucleation, heat treat at 800~900℃ for 3~10 min, and then continue to grow the germanium layer; b. Clean the substrate with the grown germanium layer to remove surface contaminants; In a vacuum state, at 550~620℃, an arsenic layer is grown on a germanium layer by an arsenic beam. Then, in an arsenic-free environment, a gallium beam is used to bond the arsenic layer to form a gallium arsenide nucleus. An arsenic beam is then introduced to continue growth on the gallium arsenide nucleus to form a gallium arsenide layer. After growth, high-temperature annealing is performed. c. After annealing, grow epitaxial material on the gallium arsenide layer.

5. The method for preparing the type II superlattice material according to claim 4, characterized in that, After thoroughly washing the silicon wafer, it is subjected to high-temperature treatment in a reducing atmosphere to remove the surface oxide layer, resulting in a clean silicon wafer.

6. The method for preparing the second type of superlattice material according to claim 4, characterized in that, After thoroughly washing the substrate with the germanium layer to remove organic contaminants, heat-treat it at 450~550℃ to remove oxides from the surface of the germanium layer.

7. The method for preparing the second type of superlattice material according to claim 4, characterized in that, The vacuum level in step a is 5~15 mT; the vacuum level in step b is 10 mT. -10 ~1.5×10 -10 T.

8. A detector made of a type-II superlattice material as described in any one of claims 1 to 3, characterized in that, The noise equivalent temperature difference is no more than 30mK.

9. A method for manufacturing the detector according to claim 8, characterized in that, The fabrication of the focal plane array of the detector includes the following steps: depositing a silicon dioxide hard mask on the surface of the type II superlattice material as described in any one of claims 1 to 3; then performing reactive ion etching in a vacuum under the action of an etching gas; after removing the resist, performing inductively coupled plasma etching at 1 to 10 mT to complete pixel isolation; then continuing to deposit a silicon dioxide passivation layer; and depositing a contact layer after opening the passivation layer.

10. The method for fabricating a type-II superlattice detector according to claim 8, characterized in that, The thickness of the hard mask is 200~300nm; the thickness of the passivation layer is 0.5~1.5µm; the etching gas for reactive ion etching is a mixture of carbon tetrafluoride and oxygen, or a mixture of carbon tetrafluoride, trifluoromethane, and oxygen; the etching gas for inductively coupled plasma etching is a mixture of boron chloride and argon, or a mixture of methane, hydrogen, and chlorine.

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