Chip packaging body, preparation method thereof and chip packaging structure

Abstract

The invention relates to the technical field of chip packaging, in particular to a chip packaging body, a preparation method thereof and a chip packaging structure. The method comprises the following steps: S1, sequentially carrying out photoetching and etching treatment on the back surface of a wafer to form a cavity, and naturally forming a sharp corner at the joint of the side wall of the cavity and the back surface of the wafer; s2, carrying out etching processing on the whole back surface of the wafer, and converting a sharp corner into a round corner; s3, coating the back surface of the wafer with a first insulating layer; s4, performing photoetching treatment on the first insulating layer to expose the electrode pad; s5, depositing a metal film layer on the first insulating layer, and sequentially performing patterning treatment, electroplating treatment and etching treatment on the metal film layer to form a metal wire; and S6, coating a second insulating layer on the metal wire, carrying out photoetching treatment, and implanting a metal ball on the exposed metal wire to obtain a chip packaging body. According to the method, the problem of electric leakage of the chip can be fundamentally and effectively solved through measures of optimizing the chip structure, forming a relatively thick insulating layer and the like.

Description

Technical Field

[0001] This application relates to the field of chip packaging technology, specifically to a chip package and its preparation method, and a chip packaging structure. Background Technology

[0002] In the semiconductor chip manufacturing field, CMOS image sensors (CIS, Complementary Metal-Oxide-Semiconductor image sensors) and other chips occupy a key position in many industries such as consumer electronics, security monitoring, and automotive electronics due to their excellent performance and wide range of applications. However, in actual applications after chip packaging, leakage current often occurs, posing a serious threat to chip performance and reliability. Leakage current causes the chip to consume extra power during use, greatly increasing its power consumption and reducing the battery life of electronic devices that rely on the chip, thus significantly increasing the cost of use. For applications that are extremely sensitive to power consumption, such as portable devices and field-use devices, high power consumption will seriously affect the normal operation of the device and the user experience. At the same time, leakage current problems will accelerate the aging and damage of the chip's internal circuitry, significantly reducing the chip's lifespan. In extreme cases, severe leakage current may even cause short circuits or burnout of the chip's internal circuitry, leading to the chip being scrapped. With the development of the electronics industry and the increase in market demand, the miniaturization of chip packaging structures has become an inevitable trend in semiconductor technology development, but miniaturized packaging structures make chip leakage current even more severe.

[0003] Currently, the industry has taken some measures to address chip leakage issues. For example, the chip packaging method disclosed in patent application number CN202010641529.7 reduces or overcomes potential leakage problems in the insulating layer by performing plasma repair on the corresponding area. However, this method has extremely limited effectiveness in reducing leakage risk. Patent application number CN201810112737.0 uses a parallel inner and outer insulating layer with a lower dielectric constant to achieve dual protection, improving product insulation and preventing leakage failure. However, this method increases the complexity and manufacturing cost of chip packaging, making large-scale application difficult. Furthermore, using parallel inner and outer insulating layers increases the thickness of the chip packaging structure, hindering its miniaturization. Summary of the Invention

[0004] The purpose of this invention is to provide a chip package and its preparation method, as well as a chip packaging structure, to solve the problem of leakage current that easily occurs during chip use, enhance chip reliability, and extend chip lifespan.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a method for preparing a chip package, comprising the following steps: S1. Obtain a wafer. An electrode pad is provided on the front side of the wafer. Photolithography and etching processes are performed on the back side of the wafer in sequence to form a cavity at the position corresponding to the electrode pad on the back side of the wafer. The sidewall of the cavity naturally forms a sharp corner where it meets the back side of the wafer. The bottom of the cavity extends to the back side of the electrode pad, exposing the back side of the electrode pad. S2. The entire back side of the wafer is etched to reduce the thickness of the wafer by 5μm-10μm, so that the sharp corners at the junction of the sidewall of the cavity and the back side of the wafer are transformed into rounded corners. S3. A first insulating layer is coated on the back side of the wafer and the sidewalls and bottom of the cavity, such that the thickness of the first insulating layer at the rounded corners reaches more than 1 μm. S4. Perform photolithography on the first insulating layer formed on the bottom of the cavity to remove part of the first insulating layer covering the back of the electrode pad, exposing the back of the electrode pad. S5. Deposit a metal film layer on the first insulating layer, and perform patterning and electroplating processes on the metal film layer in sequence to form metal wires on the metal film layer. Then, perform etching processes on the metal film layer to remove the metal film layer not covered by the metal wires. S6. Coat the metal wire with a second insulating layer, perform photolithography on a portion of the second insulating layer on the back side of the wafer to expose the metal wire, implant metal balls on the exposed metal wire to form electrode pins, and obtain a chip package.

[0006] Furthermore, in step S2, the etching process is a dry etching method, the etching atmosphere includes SF6, C4F8 and O2, and the etching rate is any value from 100nm / min to 1000nm / min.

[0007] Further, in step S1, the obtained wafer is a thinned wafer for use, and the thickness of the wafer for use is any value between 300μm and 600μm; the photolithography process includes: coating the back of the wafer with photoresist and forming a photolithographic pattern on the back of the wafer at the position corresponding to the electrode Pad through exposure and development processes; the etching process is to use a dry etching process to etch the back of the wafer to form a cavity at the position of the photolithographic pattern, where the sidewalls meet the back of the wafer at a sharp angle.

[0008] Furthermore, in step S3, the material of the first insulating layer is any one of silicon oxide, polymer material, or insulating adhesive.

[0009] Furthermore, in step S6, the material of the second insulating layer is the same as that of the first insulating layer or is a material with barrier properties no lower than those of the first insulating layer.

[0010] Furthermore, in step S5, the metal film is deposited using a sputtering deposition process, and during the deposition process, the gas pressure is controlled at 3E. -6 Below mbar, the sputtering power is controlled within the range of 300W-1000W; the etching process adopts a wet etching process.

[0011] Furthermore, in step S5, during the electroplating process, the temperature of the electroplating solution is controlled within the range of 20℃-60℃, and the current density is set to 0.1A / dm³. 2 -5A / dm 2 Any value in the range.

[0012] This application also provides a chip package, which is prepared using the above-described preparation method.

[0013] Furthermore, the chip package includes a wafer, a cavity is provided on the back side of the wafer, and a first insulating layer, a metal film layer, a metal wire and a second insulating layer are sequentially stacked on the back side of the wafer, the sidewall of the cavity and the bottom. The thickness of the first insulating layer at the junction of the back side of the wafer and the sidewall of the cavity can reach more than 1 μm. An electrode pad is provided on the front side of the wafer, and the electrode pad is electrically connected to the metal wire.

[0014] This application also provides a chip packaging structure, which includes a packaging substrate and the chip package body described above, wherein the chip package body is electrically connected to the packaging substrate.

[0015] The beneficial effects of this invention are as follows: The chip package fabrication method provided in this application can fundamentally and effectively solve the chip leakage problem by optimizing the chip structure and forming a thicker insulating layer. Specifically, by thinning the back side of the wafer, the sharp corner naturally formed at the junction of the back side of the wafer and the cavity sidewall is transformed into a rounded corner, causing the thickness of the first insulating layer deposited at this location to reach 1 μm or more. This effectively avoids leakage problems caused by electric field concentration at the sharp corners, structurally reducing the risk of leakage, thereby significantly improving the reliability and lifespan of the chip, and effectively solving the leakage problem that frequently occurs in chips such as CMOS image sensors after packaging. At the same time, this chip package fabrication method can also meet the development needs of chip package miniaturization, and has significant advantages in reducing power consumption and ensuring normal device operation. Compared with the prior art, it has better operability and economy.

[0016] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, the preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0017] Figure 1 This is a process flow diagram of a chip package fabrication method according to a preferred embodiment of the present invention; Figure 2 This is a process flow diagram of the chip package fabrication method shown in Embodiment 1 of the present invention; Figure 3 For the present invention Figure 1 Enlarged view of the P-region; Figure label: 1. Wafer; 2. Electrode Pad; 3. Cavity; 4. First insulating layer; 5. Copper metal wire; 6. Second insulating layer; 7. Solder ball. Detailed Implementation

[0018] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0020] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances. Furthermore, the technical features involved in the different embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0021] A preferred embodiment of this application illustrates a method for fabricating a chip package, such as... Figure 1 As shown, it includes the following steps: S1. Obtain a wafer with an electrode pad on the front side. Perform photolithography and etching on the back side of the wafer to form a cavity at the position corresponding to the electrode pad on the back side of the wafer. The sidewall of the cavity naturally forms a sharp corner where it meets the back side of the wafer. The bottom of the cavity extends to the back side of the electrode pad, exposing the back side of the electrode pad. S2. The entire back side of the wafer is etched to reduce the thickness of the wafer by 5μm-10μm, so that the sharp corners where the sidewalls of the cavity meet the back side of the wafer are turned into rounded corners. S3. A first insulating layer is coated on the back side of the wafer and the sidewalls and bottom of the cavity, so that the thickness of the first insulating layer at the rounded corners reaches more than 1 μm. S4. Perform photolithography on the first insulating layer formed on the bottom of the cavity to remove part of the first insulating layer covering the back of the electrode pad, exposing the back of the electrode pad. S5. A metal film layer is deposited on the first insulating layer. The metal film layer is used as a seed layer for subsequent fabrication of metal wires. The seed layer is then patterned and electroplated in sequence to form metal wires. The seed layer is then etched to remove the seed layer that is not covered by the metal wires. S6. Coat a second insulating layer on the metal wires, perform photolithography on a portion of the second insulating layer on the back side of the wafer to expose the metal wires, implant metal balls on the exposed metal wires to form electrode pins, and obtain a chip package.

[0022] In step S1, a clear photolithographic pattern is formed on the back side of the wafer at the location corresponding to the electrode pad using photolithography. Then, etching is performed at the photolithographic pattern location to form a cavity. During the etching process, the etching depth must be strictly controlled to ensure that the bottom of the cavity extends to the back side of the electrode pad, exposing the back side of the electrode pad and preparing for subsequent electrical connections. Simultaneously, the height of the electrode pads on the front side of the wafer should not exceed the height of the front side of the wafer, allowing the wafer to be tightly connected to other components, thereby helping to reduce the size of the chip package structure.

[0023] In step S1, the cavity formed after etching has sharp corners where its sidewalls meet the back side of the wafer. When an insulating layer is subsequently coated on the back side of the wafer and the sidewalls of the cavity, the insulating layer at these sharp corners is very thin, reaching a maximum thickness of only 0.1 μm, far from meeting the requirements for effective insulation. This can lead to leakage problems in the resulting chip package during use. To solve this problem, in step S2, when thinning the back side of the wafer, the area where the cavity sidewall meets the back side of the wafer is subjected to the combined action of etching gases from two directions, accelerating the etching rate at this location and gradually forming rounded corners. When the first insulating layer is subsequently coated on the back side of the wafer and the sidewalls of the cavity, the thickness of the first insulating layer at the rounded corners can reach more than 1 μm, or even more than 2 μm, effectively improving the insulation effect of the first insulating layer and ensuring the stability and reliability of the chip package.

[0024] In step S3, during the wafer-level chip packaging process, since the wafer is a semiconductor material, when fabricating metal wires, i.e., redistribution layers, on the back side of the wafer, an insulating layer, i.e., the first insulating layer in this application, needs to be coated on the back side of the wafer first. This first insulating layer not only serves to stably support other layers on the wafer but also effectively blocks charge migration, preventing leakage and short circuits, thus providing a fundamental guarantee for the stable operation of the chip. When the first insulating layer is coated on the back side of the wafer and the sidewalls of the cavity, the thickness of the first insulating layer at the rounded corners reaches more than 1 μm. This thickness effectively ensures good insulation performance in this area, thereby helping to improve the overall reliability of the chip packaging.

[0025] In step S4, a portion of the first insulating layer covering the back of the electrode pad is removed using a precise photolithography process, leaving electrical contact points for the subsequent connection of the metal wires to the electrode pad, thus ensuring the accuracy and stability of the electrical connection.

[0026] In step S5, depositing a metal film layer (i.e., a seed layer) on the first insulating layer facilitates the subsequent fabrication of metal wires on the back side of the wafer. The specific operations for patterning and electroplating the metal film layer involve first coating the metal film layer with a photoresist layer thicker than the required thickness for the packaging metal wires, providing a foundation for subsequent metal wire pattern formation. Then, through exposure and development processes, a pattern is formed on the metal film layer. Next, an electroplating process is used to electroplat the pattern in the developed area to form metal wires. After electroplating, the wafer undergoes photoresist removal and cleaning to thoroughly remove the photoresist and ensure the cleanliness of the wafer surface. Finally, the metal film layer is etched to remove excess seed layer, ultimately forming independent metal wires.

[0027] In step S6, the second insulating layer coated on the metal wire is used to cover and protect the metal wire, prevent the metal wire from being exposed to the air, prevent electromigration, and block moisture intrusion, thereby effectively improving the overall reliability of the chip package and providing a strong guarantee for the long-term stable operation of the chip.

[0028] In one embodiment, step S2 employs a dry etching process. This dry etching is carried out in an etching atmosphere containing SF6, C4F8, and a small amount of O2, with the etching rate precisely controlled within the range of 100 nm / min to 1000 nm / min. This ensures etching efficiency while minimizing over-etching of the wafer. During the etching process, the etching atmosphere from two directions simultaneously acts on the junction between the cavity sidewall and the back of the wafer, accelerating the etching rate of the sharp corner area. This gradually transforms the sharp corner into a rounded corner, effectively improving the uniformity and insulation effect of the subsequent insulating layer coating.

[0029] In one embodiment, in step S1, the obtained wafer is a thinned wafer, and the thickness of the wafer is controlled within the range of 300μm-600μm. This thickness ensures the mechanical strength of the wafer while facilitating subsequent processing. The photolithography process includes two steps: first, a layer of photoresist is coated on the back side of the wafer; then, a photolithographic pattern is formed on the back side of the wafer at the position corresponding to the electrode pad through exposure and development processes. The etching process uses a dry etching method to etch the back side of the wafer, thereby forming a cavity at the location of the photolithographic pattern. Furthermore, a sharp corner is naturally formed where the sidewall of the cavity meets the back side of the wafer.

[0030] In one embodiment, in step S3, the first insulating layer is made of polyimide, which has excellent insulation and high-temperature resistance. The second insulating layer in step S6 is also made of polyimide, the same material as the first insulating layer. In other embodiments, the first insulating layer can be made of one or more of silicon oxide, silicon nitride, polymer materials, and insulating adhesives. The polymer materials are preferably polyimide, silicone, epoxy resin, etc., which have excellent insulation and high-temperature resistance. The second insulating layer can be made of the same material as the first insulating layer, or it can be made of a material with barrier properties no less than that of the first insulating layer, to better prevent moisture intrusion, protect the underlying metal conductor, and meet the performance requirements of different application scenarios. In terms of manufacturing process, both the first and second insulating layers can be achieved through processes such as spraying and spin coating to ensure interlayer uniformity and adhesion.

[0031] In one embodiment, in step S5, a metal film is deposited on the first insulating layer using a sputtering deposition process. During the metal film deposition process, the gas pressure is controlled at 3E. -6Below mbar, the sputtering power is controlled within the range of 300W-1000W to achieve high-quality deposition of the metal film. In other embodiments, in step S5, other processes such as vacuum evaporation deposition and vacuum ion plating can also be used to deposit the metal film on the first insulating layer. The material selection for the metal film is diverse, including but not limited to elemental metals such as titanium and copper, and their alloys or compounds, such as TiN and TiW, to meet different conductivity requirements. The material of the metal conductor can be copper, aluminum, nickel, gold, etc., to adapt to different conductivity and cost requirements. During the electroplating process, the electroplating solution is preferably a sulfuric acid system solution, which facilitates subsequent waste liquid treatment and reduces environmental pollution. During the electroplating process, the temperature of the electroplating solution needs to be controlled within the range of 20℃-60℃, and the current density is set to 0.1A / dm³. 2 -5A / dm 2 This ensures the uniformity and density of the electroplated layer. When etching excess seed film, wet etching is preferred due to its high efficiency and low cost.

[0032] This application also provides a chip package, which is prepared by the above-described preparation method.

[0033] In one embodiment, the chip package includes a wafer with a cavity on its back side. A first insulating layer, a metal film layer, a metal wire, and a second insulating layer are sequentially stacked on the back side of the wafer, the sidewalls of the cavity, and the bottom. The thickness of the first insulating layer at the junction of the back side of the wafer and the sidewall of the cavity can reach 1 μm or more. An electrode pad is disposed on the front side of the wafer and is electrically connected to the metal wire, thereby enabling electrical connection between the electrode pad on the wafer and the device disposed on the back side of the wafer. This chip package structure, due to the thicker thickness of the first insulating layer at the corners (i.e., where the back side of the wafer meets the sidewall of the cavity), effectively supports the metal wire while preventing leakage.

[0034] Example 1 S1. Obtain a wafer 1 with a thickness of 500μm, such as... Figure 2 As shown in (a), an electrode Pad2 is disposed on the front side of the wafer 1. A layer of photoresist is coated on the back side of the wafer 1, and the back side of the wafer 1 is exposed and developed to form a photolithographic pattern on the back side of the wafer 1. The back side of the wafer 1 is etched at an etching rate of 8 μm / min under an atmosphere of SF6, C4F8 and a small amount of O2, forming a cavity 3 at the location of the photolithographic pattern. The sidewall of the cavity 3 naturally forms a sharp corner where it meets the back side of the wafer 1. The bottom of the cavity 3 extends to the back side of the electrode Pad2, exposing the back side of the electrode Pad2.

[0035] S2. Under an etching atmosphere containing SF6, C4F8, and a small amount of O2, the entire back side of wafer 1 is etched at an etching rate of 500 nm / min, reducing the thickness of wafer 1 by 6 μm. This transforms the sharp corners at the junction of the sidewalls of cavity 3 and the back side of the wafer into rounded corners. The result is as follows: Figure 2 (b) and Figure 3 As shown, forming Figure 3 The rounded corner indicated by the middle arrow.

[0036] S3. Using a spraying process, epoxy insulating adhesive is sprayed onto the back side of wafer 1 and the sidewalls and bottom of cavity 3. After drying, a first insulating layer 4 with a thickness of 2.5μm is formed on the back side of wafer 1 and the sidewalls and bottom of cavity 3. At this time, the thickness of the first insulating layer 4 at the rounded corner position can reach more than 1μm.

[0037] S4. Perform photolithography on the first insulating layer 4 formed on the bottom of the cavity 3 to remove part of the first insulating layer 4 covering the back of the electrode pad, exposing the back of the electrode pad 2.

[0038] S5. Using a titanium target, copper target, or titanium-tungsten alloy target and copper target, deposit a 0.1 μm thick titanium metal film and a 0.5 μm thick copper metal film on the first insulating layer 4 as seed layers for subsequent metal wire fabrication. Then, coat a 15 μm thick photoresist film on the metal film, and then expose and develop the photoresist film to form the metal wire pattern. Then, use copper sulfate as the electroplating solution at 1 A / dm 2 Electroplating was performed at a current density to form copper metal wires 5 on the metal film layer in the exposed area. Subsequently, a wet etching process was used to etch the seed layer, removing the portion of the seed layer not covered by the copper metal wires 5. The result is as follows: Figure 2 As shown in (c).

[0039] S6. Using a spin-coating process, an epoxy-based insulating adhesive is coated onto the back side of wafer 1 and the sidewalls and bottom of cavity 3. After drying, a second insulating layer 6 is formed on the back side of the wafer and the sidewalls and bottom of cavity 3. A portion of the second insulating layer 6 on the back side of the wafer is photolithographically processed to expose copper metal wires 5. Solder balls 7 are then implanted onto the exposed copper metal wires 5 to form electrode leads. The result is as follows: Figure 2 As shown in (d), the chip package is obtained.

[0040] The chip package obtained in Example 1 exhibits good structural stability and a simple fabrication method. It requires no complex and expensive equipment or cumbersome processes and does not increase the thickness of the chip package structure, effectively reducing production costs and improving production efficiency. This is beneficial for large-scale industrial production and the miniaturization of chips. Crucially, the first insulation thickness at the junction of the wafer backside and the cavity sidewall in this chip package can reach 1 μm or more, effectively preventing leakage during chip use. This significantly enhances chip reliability and extends its lifespan. Therefore, it provides an effective solution to the common leakage problem in CMOS image sensors and other chips after packaging, demonstrating broad application prospects and significant practical value.

[0041] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0042] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for preparing a chip package, characterized in that, Includes the following steps: S1. Obtain a wafer. An electrode pad is provided on the front side of the wafer. Photolithography and etching processes are performed on the back side of the wafer in sequence to form a cavity at the position corresponding to the electrode pad on the back side of the wafer. The sidewall of the cavity naturally forms a sharp corner where it meets the back side of the wafer. The bottom of the cavity extends to the back side of the electrode pad, exposing the back side of the electrode pad. S2. The entire back side of the wafer is etched to reduce the thickness of the wafer by 5μm-10μm, so that the sharp corners at the junction of the sidewall of the cavity and the back side of the wafer are transformed into rounded corners. S3. A first insulating layer is coated on the back side of the wafer and the sidewalls and bottom of the cavity, such that the thickness of the first insulating layer at the rounded corners reaches more than 1 μm. S4. Perform photolithography on the first insulating layer formed on the bottom of the cavity to remove part of the first insulating layer covering the back of the electrode pad, exposing the back of the electrode pad. S5. Deposit a metal film layer on the first insulating layer, and perform patterning and electroplating processes on the metal film layer in sequence to form metal wires on the metal film layer. Then, perform etching processes on the metal film layer to remove the metal film layer not covered by the metal wires. S6. Coat the metal wire with a second insulating layer, perform photolithography on a portion of the second insulating layer on the back side of the wafer to expose the metal wire, implant metal balls on the exposed metal wire to form electrode pins, and obtain a chip package.

2. The preparation method according to claim 1, characterized in that, In step S2, the etching process is a dry etching method, the etching atmosphere includes SF6, C4F8 and O2, and the etching rate is any value between 100nm / min and 1000nm / min.

3. The preparation method according to claim 2, characterized in that, In step S1, the obtained wafer is a thinned wafer for use, and the thickness of the wafer for use is any value between 300μm and 600μm. The photolithography process includes: coating the back of the wafer with photoresist and forming a photolithographic pattern on the back of the wafer at the position corresponding to the electrode Pad through exposure and development processes; The etching process involves using a dry etching process to etch the back side of the wafer, forming a cavity at the location of the photolithographic pattern where the sidewall meets the back side of the wafer at a sharp angle.

4. The preparation method according to claim 2, characterized in that, In step S3, the material of the first insulating layer is any one of silicon oxide, polymer material, or insulating adhesive.

5. The preparation method according to claim 4, characterized in that, In step S6, the material of the second insulating layer is the same as that of the first insulating layer or is a material with barrier properties no lower than those of the first insulating layer.

6. The preparation method according to claim 2, characterized in that, In step S5, the metal film is deposited using a sputtering deposition process, and the gas pressure is controlled at 3E during the deposition process. -6 Below mbar, the sputtering power is controlled within the range of 300W-1000W; the etching process adopts a wet etching process.

7. The preparation method according to claim 5, characterized in that, In step S5, during the electroplating process, the temperature of the electroplating solution is controlled within the range of 20℃-60℃, and the current density is set to 0.1A / dm³. 2 -5A / dm 2 Any value in the range.

8. A chip package, characterized in that, It is prepared by the preparation method described in any one of claims 1-7.

9. The chip package as described in claim 8, characterized in that, The chip package includes a wafer with a cavity on its back side. A first insulating layer, a metal film layer, a metal wire, and a second insulating layer are sequentially stacked on the back side of the wafer, the sidewall of the cavity, and the bottom. The thickness of the first insulating layer at the junction of the back side of the wafer and the sidewall of the cavity can reach more than 1 μm. An electrode pad is provided on the front side of the wafer and is electrically connected to the metal wire.

10. A chip packaging structure, characterized in that, It includes a packaging substrate and a chip package as described in claim 8 or 9, wherein the chip package is electrically connected to the packaging substrate.

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