Display panel and display equipment

Abstract

The embodiment of the invention provides a display panel and display equipment. The display panel comprises: a substrate; the light-emitting layer is arranged on the first side of the substrate, the light-emitting layer comprises a plurality of pixel light-emitting devices which are arranged at intervals, and each pixel light-emitting device is provided with a corresponding pixel driving circuit; the pixel driving circuit comprises a data line for providing data voltage for the pixel light-emitting device and a power line for providing a working power supply; wherein a gap area is formed between the data line and the power line, an isolation structure is arranged in at least part of the gap area, and the dielectric constant of the isolation structure is smaller than that of a passivation insulating layer covering the power line and the data line.

Description

Technical Field

[0001] This application relates to the field of display technology, and to, but is not limited to, a display panel and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) display panels are widely used in high-end display devices due to their advantages such as self-illumination, high contrast, and wide viewing angle. In OLED panels, the brightness of each pixel is controlled by the current flowing through that pixel, and the pixel circuit typically includes multiple thin-film transistors (TFTs) and capacitors, which have a complex layout and are prone to parasitic capacitance effects between nodes.

[0003] For example, when the data line of a pixel unit is coupled to the power line (ELVDD), a large voltage jump will occur in the Data line when there are alternating signals such as black and white, black and gray, or gray and white on the screen. This voltage change is coupled to the ELVDD line through the parasitic capacitance, causing current fluctuations at the corresponding jump points, resulting in bright and dark lines on the screen.

[0004] Existing solutions primarily rely on software algorithm compensation, such as setting up dedicated processing logic in the TCON to counteract the effects of voltage fluctuations. However, this approach cannot fundamentally solve the coupling capacitance problem at the hardware level, only providing limited improvement. Furthermore, it is complex to debug, has unstable results, and exhibits significant differences in performance under different scanning directions or panel structures, making it difficult to apply uniformly. Summary of the Invention

[0005] This application provides a display panel and a display device.

[0006] The technical solution of this application embodiment is implemented as follows: This application embodiment provides a display panel, the display panel including: Substrate; A light-emitting layer is disposed on the first side of a substrate, the light-emitting layer including a plurality of pixel light-emitting devices arranged at intervals, and each pixel light-emitting device is configured with a corresponding pixel driving circuit; The pixel driving circuit includes a data line for providing data voltage to the pixel light-emitting device and a power line for providing operating power. The data line and the power line have a gap region, and an isolation structure is provided in at least a portion of the gap region. The dielectric constant of the isolation structure is less than the dielectric constant of the passivation insulation layer covering the power line and the data line.

[0007] This application provides a display device, including... The outer casing has a receiving groove; A display panel is sealed within the receiving groove, the display panel comprising: Substrate; A light-emitting layer is disposed on the first side of the substrate, the light-emitting layer including a plurality of pixel light-emitting devices arranged at intervals, each pixel light-emitting device being configured with a corresponding pixel driving circuit. The pixel driving circuit includes a data line for providing data voltage to the pixel light-emitting device and a power line for providing operating power. The data line and the power line have a gap region, and an isolation structure is provided in at least a portion of the gap region. The dielectric constant of the isolation structure is less than the dielectric constant of the passivation insulating layer covering the power line and the data line. Attached Figure Description

[0008] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0009] Figure 1 A schematic diagram illustrating an inter-line crosstalk provided in the prior art; Figure 2 This is a schematic diagram of the layout structure of an exemplary display panel provided in the prior art; Figure 3 This is a schematic diagram of an exemplary film layer structure of a display panel provided in the prior art; Figure 4 A schematic planar view of an exemplary passivation insulating layer provided in the prior art; Figure 5 A schematic diagram of an exemplary display panel film structure provided in this application embodiment. Figure 1 ; Figure 6 A schematic diagram of an exemplary display panel film structure provided in this application embodiment. Figure 2 ; Figure 7 A schematic plan view of an exemplary passivation insulating layer provided for an embodiment of this application; Figure 8 A schematic diagram of an exemplary display panel film structure provided in this application embodiment. Figure 3 ; Figure 9 A schematic diagram of an exemplary display panel film structure provided in this application embodiment. Figure 4 ; Figure 10Exemplary structural diagrams of the first and second structural portions at different layers provided in embodiments of this application; Figure 11 This is a schematic diagram illustrating the deployment of an exemplary first structural portion and a second structural portion, provided for an embodiment of this application. Detailed Implementation

[0010] Exemplary embodiments of this application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.

[0011] In the following description, numerous details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0012] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0013] In the following description, the terms "first," "second," and "third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first," "second," and "third" may be interchanged in a specific order or sequence where permissible, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein. In the drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0014] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0015] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0016] Currently, OLED panels are current-driven devices, and the current flowing through each pixel determines the brightness of that pixel. The pixel circuit of an OLED itself consists of many TFTs and capacitors, and the layout is very complex. There are parasitic capacitances between each node and adjacent nodes. These coupling capacitances are inevitable and cannot be eliminated. Furthermore, some parasitic capacitances can affect the potential of the gate of the driving transistor, thereby affecting the current of that pixel and thus its brightness.

[0017] like Figure 1 The image shows an example of line-xtalk caused by coupling between the data line and the power line. Figure 1 As can be seen in the vertical direction 11, when the image shows alternating black and white, black and gray, or gray and white signals, the data line experiences significant voltage jumps. Through parasitic capacitance, these voltage changes are coupled to the power line, causing current fluctuations at the corresponding jump points. This can be observed as bright and dark lines on the left side of the image (such as...). Figure 1 (as shown in 13), that is Figure 1 The image shown is a portion of an Excel spreadsheet, with area 14 being white / gray and area 12 being gray / white. The light and dark lines are created because the data lines and power lines in the layout are vertically and continuously distributed (see [link to spreadsheet]). Figure 2 The data line 21 and power line 22 are adjacent to each other and made of the same or similar materials. They will form a coupling capacitor (e.g., parallel plate capacitor, edge field capacitor, etc.). When there is a significant change in brightness in the vertical direction of the screen, the data line 21 will have a large change in the vertical direction, which will cause the voltage of the power line 22 to ripple due to the coupling effect; thus affecting the brightness of the pixels next to the change in brightness.

[0018] like Figure 3 As shown, in the film structure, the data line 21 and the power line 22 overlap in the thickness direction (Z-axis direction) and run vertically through the entire display panel. The insulating layer 31 between them is PV material (inorganic material SiNx, dielectric constant of film material 7.x), so the coupling capacitance is large. Figure 4 The planar structure corresponding to the insulating layer 31 is shown in the figure, and the square through hole 41 in the figure is the through hole corresponding to each pixel.

[0019] In related technologies, compensation mainly relies on software algorithms. However, the software is only slightly optimized, and the effect is very limited. Moreover, the method of this algorithm is highly dependent on the scanning direction, and different settings are required depending on the application of the display panel, which increases the difficulty and time of debugging.

[0020] Based on this, the present application provides a display panel and an electronic device; below, the display panel and electronic device in the embodiments of the present application will be described in detail with reference to the accompanying drawings.

[0021] Before introducing the embodiments of this application, let's define the directions used to describe the three-dimensional structure in the following embodiments. The three directions may include the z-axis (first), x-axis (second), and y-axis (third) directions. The z-axis direction can be the thickness direction of the display panel, and the x-axis and y-axis directions are two perpendicular directions on the plane where the display panel is located.

[0022] This application provides a display panel. Figure 5 A schematic diagram of an exemplary display panel film structure provided in this application embodiment. Figure 1 ,like Figure 5 As shown, the display panel 500 includes: Substrate 501; A light-emitting layer 502 is disposed on the first side of the substrate 501. The light-emitting layer includes a plurality of pixel light-emitting devices 503 disposed at intervals, and each pixel light-emitting device 503 is configured with a corresponding pixel driving circuit 504. The pixel driving circuit 504 includes a data line 21 for providing data voltage to the pixel light-emitting device 503 and a power line 22 for providing operating power. The data line 21 and the power line 22 are separated by a gap region 505. An isolation structure 506 is provided in at least a portion of the gap region 505. The dielectric constant of the isolation structure 506 is less than the dielectric constant of the passivation insulation layer 507 covering the power line 22 and the data line 21.

[0023] In the embodiments of this application, the substrate 501 serves as the basic support structure of the display panel 500. The substrate 501 is typically made of glass or a flexible substrate, and its function is to support various functional layers and circuits within the display panel 500. The light-emitting layer 502 is located on the first side of the substrate 501, i.e., the display surface side. The light-emitting layer 502 contains multiple pixel light-emitting devices 503, arranged in a certain row and column to form a pixel matrix. Each pixel light-emitting device is responsible for the light emission brightness corresponding to a single pixel, thereby constituting the entire display image. The pixel light-emitting devices 503 are spaced apart to avoid mutual interference and improve the overall display effect.

[0024] In the embodiments of this application, a pixel definition layer (PDL) 510 is provided on the upper layer of the planarization layer 508. The PDL layer 510 is provided with a plurality of slots, and one of the RGB sub-pixels is placed in each slot. Each sub-pixel corresponds to at least one TFT transistor.

[0025] In the embodiments of this application, in the display panel 500, data lines 21 are used to transmit data signals from the driver chip to control the grayscale level of the pixels; power lines 22 are used to provide a stable operating voltage to the pixels to ensure that the light-emitting devices emit light normally. Data lines 21 and power lines 22 are typically made of metal materials (such as copper, aluminum, etc.) and are laid on the substrate 501. Data lines 21 and power lines 22 are formed into specific wiring patterns through an etching process. Data lines 21 and power lines 22 are usually arranged in an overlapping manner and are placed adjacent to each other to facilitate signal transmission and power supply efficiency. However, adjacent data lines 21 and power lines 22 will generate coupling capacitance. This coupling capacitance refers to the capacitance formed between two conductors (data lines 21 and power lines 22) due to the presence of dielectric material. The size of the coupling capacitance is related to the area, distance, and dielectric constant between the conductors. The coupling capacitance between data lines 21 and power lines 22 will affect the current of adjacent pixels due to voltage changes, resulting in crosstalk between lines.

[0026] In the embodiments of this application, a gap region 505 is provided between the data line 21 and the power line 22. In related technologies, the gap region 505 is typically covered by a passivation insulating layer 507 to protect the underlying metal lines and provide insulation. It is usually made of materials such as silicon nitride (SiNx) and aluminum oxide (Al2O3) and has a high dielectric constant (about 7.x). In the embodiments of this application, at least a portion of the gap region 505 between the data line 21 and the power line 22 can be provided with an isolation structure 506. The dielectric constant of the isolation structure 506 is less than the dielectric constant of the passivation insulating layer 507 covering the power line 22 and the data line 21. In this way, the coupling capacitance between the data line 21 and the power line 22 will be reduced accordingly, thereby reducing the phenomenon of image crosstalk.

[0027] For example, the isolation structure 506 may be made of a material with a low dielectric constant, such as an organic film (e.g., acrylic resin), silicon oxide (SiOx), etc., which have a dielectric constant of about 3.x to 4.x, much lower than the dielectric constant of the passivation insulating layer.

[0028] In embodiments of this application, the isolation structure 506 may be configured to fill the entire gap region 505 with the isolation structure (e.g., Figure 6 (as shown in 506), or, the isolation structure 506 is filled only in the high coupling area of ​​the data line 21 and the power line 22, or the passivation insulating layer 507 is hollowed out in the thickness direction (third direction) of the display panel 500, or a preset percentage of the thickness direction is hollowed out.

[0029] For example, such as Figure 7 The diagram shows a planar view of the passivation insulating layer. The square blocks represent the vias 41 of each pixel in the passivation insulating layer. The blank area 71 represents the size and extent of the cutout in the gap between the data line 21 and the power line 22. The white and black dotted areas 72 represent the size and extent of the partial cutout in the gap between the data line 21 and the power line 22. The percentage of partial cutout can be 80%, 50%, 40%, etc. In the embodiments of this application, the overlapping area between the data line 21 and the power line 22 is cut out (e.g.,...). Figure 7 (7A in the middle), or the area to be dug can be larger (e.g. Figure 7 (7B in the text), but ensure that the display panel border is not cut out, and the rest is cut out (such as...). Figure 7 In the 7C section, or the area around the bezel of the display panel, a portion of the thickness can be cut out, instead of completely removing it (e.g., ...). Figure 7 7D in the middle).

[0030] For example, such as Figure 6As shown, the upper layer of the passivation insulating layer (PV layer) 507 can be an organic film material. After hollowing out or partially hollowing out the passivation insulating layer 507 that overlaps between the data line 21 and the power line 22 in the thickness direction (third direction) (i.e., the bottom layer of the isolation structure 506 still contains PV layer material), the fluid organic film material will replace the original position of the PV layer 507. The dielectric constant of the organic film material is 3.x, while the dielectric constant of the original inorganic film SiNx of the PV layer 507 is 7.x. Therefore, the coupling capacitance between the data line 21 and the power line 22 can be significantly reduced, with an estimated improvement of 50% based on the dielectric constant. The organic film serves as the isolation structure.

[0031] For example, in the hollowed-out or partially hollowed-out gap area, other insulating materials with a dielectric constant lower than that of the passivation insulating layer can also be provided.

[0032] Thus, by setting a low-dielectric-constant isolation structure between the data line and the power line, the display panel can effectively reduce coupling capacitance, thereby improving image crosstalk. Compared to existing solutions that rely on software algorithm compensation, the display panel provided in this application addresses the coupling capacitance problem at the hardware level, fundamentally improving display quality, while simplifying the debugging process and reducing production costs.

[0033] In some embodiments, the gap region includes a gap region formed by the height difference between the data line and the power line in the thickness direction of the display panel and / or a gap region formed at different positions in the first direction; the isolation structure makes the coupling capacitance between the data line and the power line less than the target threshold.

[0034] In the embodiments of this application, the data line 21 and the power line 22 are typically spatially related in their layout. The gap area can be of two types: one is a vertical gap formed by the height difference between the data line 21 and the power line 22 in the thickness direction (third direction) (see...). Figure 8 The vertical gap 81 shown includes the vertical gap region formed by the misalignment of the two in the thickness direction; another type is the transverse gap formed by the transverse misalignment in the first direction (i.e., the horizontal direction) (see...). Figure 6 The gap region shown in Figure 505, that is, the gap region can refer only to the overlapping area of ​​the minimum interval. The presence of vertical and horizontal gaps will also reduce the coupling capacitance between data line 21 and power line 22 to a certain extent, thereby reducing signal interference.

[0035] In the embodiments of this application, by arranging the data line 21 and the power line 22 at different heights or different lateral positions, direct spatial alignment of the data line 21 and the power line 22 can be effectively avoided, thereby reducing the influence of parallel plate capacitance and edge field capacitance.

[0036] For example, data line 21 is arranged below passivation insulating layer 507 or passivation edge layer, while power line 22 is arranged above passivation insulating layer 507. This creates a height difference, forming a vertical staggered structure, and naturally creates a gap in the thickness direction based on this structure. Specifically, the height difference is the height difference at the end away from the TFT transistor. The insulating layer between data line 21 and power line 22 may not be limited to passivation insulating layer 507; that is, the number of insulator layers may be at least one. Thus, the isolation structure 506 can be a multi-layer insulating structure.

[0037] For example, the data cable 21 and the power cable 22 are arranged at different lateral positions on the same insulation layer (see [link]). Figure 6 In this way, a transverse gap structure is formed, so that the isolation structure 506 can be a low dielectric constant material layer.

[0038] In the embodiments of this application, the target threshold can be a value set according to application requirements and actual scenarios. The specific value of the target threshold is usually determined through experiments or simulations. For example, in the design process for a high-resolution OLED panel, the design may require controlling the coupling capacitance below 0.5 nanofarads to ensure that image quality is not affected.

[0039] In the embodiments of this application, the isolation structure can be implemented in various ways. For example, an organic insulating material can be used to replace the original inorganic insulating material. Since the organic insulating material has a lower dielectric constant, it can effectively reduce the coupling capacitance; or one or more layers of low dielectric constant material can be inserted between the data line 21 and the power line 22 to further suppress the capacitance effect.

[0040] For example, low dielectric constant materials include polyimide (PI), fluorinated polymers (such as PFA, FEP), and certain types of silicone resins. The low dielectric constant material can be disposed between data line 21 and power line 22 as an isolation layer, thereby reducing coupling capacitance.

[0041] For example, a new insulating layer (isolation structure) can be made above and below the film layer (passivation insulating layer) where the power line 22 and data line 21 are located, and the area surrounding the power line 22 and data line 21 can also be isolated using a low dielectric constant. In this way, the size of the field capacitance of the coupling capacitor will be further reduced, in addition to reducing the parallel capacitance in the coupling capacitor.

[0042] In the embodiments of this application, the design of the isolation structure needs to comprehensively consider factors such as material properties, process feasibility, and cost. For example, in the case of high-density wiring, a multi-layer structure combined with a cutout process can be used to achieve effective capacitance suppression within a limited space.

[0043] Thus, by setting a reasonable gap area and isolation structure between the data line 21 and the power line 22, voltage fluctuations caused by signal transitions can be reduced, thereby improving crosstalk between lines in the picture, further enhancing the overall display quality, and reducing the reliance on software compensation algorithms.

[0044] In some embodiments, such as Figure 6 , Figure 9 and Figure 10 As shown, the data line 21 includes a first structural portion 211 extending from the passivation insulating layer 507, and the power line 22 includes a second structural portion 221 extending from the passivation insulating layer 507. The gap region 505 includes a first gap region formed between the first structural portion and the second structural portion. The passivation insulating layer is provided with a first through hole corresponding to the first gap region 505. The aperture of the first through hole is the same as the first width of the first gap region 505 in a first direction, which is the setting direction of the passivation insulating layer 507. The light-emitting layer 502 also includes a planarization layer 508 disposed on the second side of the passivation insulating layer 507 facing away from the substrate 501. The first through hole is filled with the planarization layer 508. The dielectric constant of the planarization layer 508 is less than the dielectric constant of the passivation insulating layer 507, so that the parallel plate capacitance formed between the first structural portion 211 and the second structural portion 222 is less than a first threshold value.

[0045] In the embodiments of this application, the first structural portion 211 refers to the extension of the data line 21 on the passivation insulating layer 507. The shape and size of this portion can be determined according to circuit design requirements. The second structural portion 221 refers to the extension of the power line 22 on the passivation insulating layer 207, and this portion can be optimized according to wiring rules. The distribution between the first structural portion 211 and the second structural portion 221 determines their spatial relationship. This spatial relationship will affect the size of the coupling capacitance.

[0046] In the embodiments of this application, by respectively placing the data line 21 and the power line 22 at different positions on the passivation insulating layer 507, the spacing between the data line 21 and the power line 22 can be effectively controlled. The first gap region refers to the gap region located between the data line 21 and the power line 22 in the first direction. The passivation insulating layer 507 is provided with a first through hole in the first gap region 505. The diameter of the first through hole is the same as the width of the first gap region 505 in the first direction, ensuring that the first through hole can completely cover the first gap region 505. Here, the first direction is a planar direction perpendicular to the thickness direction. For example, it can be the short side direction or the long side direction of the display panel, depending on the arrangement of the pixel array.

[0047] In the embodiments of this application, the planarization layer (PLN) 508 is an organic insulating material. Exemplarily, the material used for the planarization layer 508 can be polyimide or acrylic. The planarization layer 508 has a low dielectric constant (approximately 3.x), resulting in a lower coupling effect compared to the passivation insulating layer 507 (approximately 7.x). The planarization layer 508 is disposed on the back side of the passivation insulating layer 507. The planarization layer 508 is used to smooth the surface, improve the quality of subsequent thin film deposition, and can also serve as a filling material for the first via.

[0048] In the embodiments of this application, by filling the first via with a planarization layer 508 with a low dielectric constant, the parallel plate capacitance between the data line 21 and the power line 22 can be significantly reduced, thereby reducing signal interference and improving image quality. The first threshold is a preset upper limit of capacitance. Exceeding the first threshold may cause significant crosstalk between lines. This ensures that the parallel plate capacitance formed between the first structural portion 211 and the second structural portion 221 is lower than the first threshold, thereby improving image display quality. Alternatively, the first threshold can be the parallel plate capacitance value corresponding to when the passivation insulating layer 507 is filled in the first via. Exemplarily, the first threshold can be set based on actual needs and application scenarios, which is not limited in this application.

[0049] For example, the planarization layer 508 can be an organic film layer, and a first through hole is provided in the passivation insulating layer 507 corresponding to the first gap region 505, and the fluid organic film (PLN) will replace the original position of the PV layer.

[0050] For example, during the manufacturing process, the organic film in the first through-hole corresponding to the passivation insulating layer 507 in the first gap region 505 can be flush with the passivation insulating layer 507 (the first gap region is filled by the planarization layer) or not flush (part of the first gap region is filled by the planarization layer 508). For example, 50% or 80% can be filled. It should be noted that if the filling percentage is 80%, then 20% of the first gap region 505 near the planarization layer 508 is empty, and the remaining 80% is organic material.

[0051] Thus, by introducing a passivation insulating layer and setting vias between data line 21 and power line 22, and then filling them with a planarization layer of low dielectric constant, the coupling capacitance is effectively reduced. This structural approach reduces mutual interference between signals, thereby improving the brightness uniformity of the image and significantly mitigating crosstalk between lines, thus enhancing the overall display performance of the OLED panel.

[0052] In some embodiments, such as Figure 6As shown, the passivation insulating layer 507 is provided with a second through hole corresponding to the first gap region 505, the diameter of the second through hole is smaller than the first width, and the planarization layer 508 fills the second through hole; or, the passivation insulating layer 507 is provided with a first groove corresponding to the first gap region 505, and the planarization layer 508 fills the first groove; or, the passivation insulating layer 507 is provided with a first conical hole corresponding to the first gap region 505, and the planarization layer 508 fills the first conical hole, the maximum diameter of the first conical hole is less than or equal to the first width.

[0053] In the embodiments of this application, a second through hole is provided in the first gap region 505 corresponding to the passivation insulating layer 507, and the planarization layer 508 fills the second through hole. Since the diameter of the second through hole is smaller than the first width, it means that the first gap region includes both the material of the passivation insulating layer and the material of the organic film.

[0054] In embodiments of this application, the second through-hole can be disposed in the middle portion of the first gap region 505, such that the material of the first gap region 505 in the first direction is the material of the passivation insulating layer 507, the material of the planarization layer 508, and the material of the passivation insulating layer 507; or, the second through-hole can be disposed on one side biased towards the first structural portion 211, and the material in the first direction is the material of the passivation insulating layer 507 and the material of the planarization layer 508; or, the second through-hole can be disposed on one side biased towards the second structural portion 221, and the material in the first direction is the material of the planarization layer 508 and the material of the passivation insulating layer 507. Of course, the material in the first through-hole can also be other materials with a dielectric constant lower than that of the passivation insulating layer 507.

[0055] In the embodiments of this application, the first groove is a partially recessed structure deployed in the first gap region 505 of the first passivation insulating layer 507. The shape of the first groove is similar to a U-shaped or V-shaped trench. The opening of the first groove may be the same as or different from the first width. For example, when the opening of the first groove is the same as the first width, the upper layer of the first groove may be an organic film, and the lower layer may be other insulating isolation layers and / or the passivation insulating layer 507. Alternatively, when the opening of the first groove is different from the first width, the lower layer of the first groove may be surrounded by the passivation insulating layer, indicating that the passivation insulating layer in the first gap region is not hollowed out. The depth and width of the first groove can be adjusted according to actual needs to achieve the best capacitance suppression effect.

[0056] In the embodiments of this application, the presence of the first groove disrupts the coupling path between the data line and the power line, thereby reducing the formation of coupling capacitance. After the planarization layer 508 is filled into the first groove, the planarization layer 508 has a low dielectric constant, which enhances the ability to suppress coupling capacitance.

[0057] In the embodiments of this application, the first conical hole is an opening with a conical structure, narrower at the bottom and wider at the top. The purpose of the first conical hole design is to ensure that the planarization layer 508 can smoothly fill the entire hole while minimizing the coupling path, avoiding defects such as voids or cracks. The maximum diameter of the first conical hole does not exceed the first width, ensuring the compactness of the overall structure and thus preventing excessive increase in coupling capacitance.

[0058] In the embodiments of this application, when using the first conical hole structure, the planarization layer 508 can more uniformly cover the hole wall, thereby improving the filling quality. Due to the special shape of the first conical hole, this structure helps guide a more uniform electric field distribution, thereby reducing the impact of edge field effects on device performance. By adopting the first conical hole structure and processing the planarization layer 508 to more uniformly cover the hole wall, the coupling capacitance suppression efficiency can be improved, while also further enhancing the product's production yield and process stability.

[0059] Thus, in some embodiments of the display panel manufacturing method, by setting different types of structures (such as second through holes, first grooves, and first conical holes) on the passivation insulating layer and filling these structures on the passivation insulating layer with a low dielectric constant material, the method can effectively reduce the coupling capacitance between data lines and power lines, significantly reduce line-xtalk phenomenon, thereby improving the display quality of the OLED panel and achieving higher image stability and screen consistency.

[0060] In some embodiments, the passivation insulating layer 507 is further provided with a first hollow area 212 corresponding to the first structural portion 211 and / or a second hollow area 222 corresponding to the second structural portion 221, and the planarization layer 508 fills the first hollow area 212 and / or the second hollow area 222; and / or, the first gap region 505 is further filled with a first insulating layer, and the dielectric constant of the first insulating layer is less than the dielectric constant of the passivation insulating layer 507.

[0061] In the embodiments of this application, the first structural portion 211 and the second structural portion 221 refer to the portions of the data line 21 and the power line 22 located in the passivation insulating layer 507. Since the passivation insulating layer 507 is designed to cover the first structural portion 211 and the second structural portion 221, the thickness of this portion is less than the thickness of the passivation insulating layer 507.

[0062] In the embodiments of this application, the excavation direction of the first excavation area 212 and the second excavation area 222 is the side region close to the upper planarization layer 508. It should be noted that the first excavation area 212 and the second excavation area 222 can excavate the first structural part 211 and the second structural part 221 to a partial or complete extent.

[0063] For example, such as Figure 9 As shown, if the first excavation area 212 and the second excavation area 222 can partially expose the first structural part 211 and the second structural part 221, then the exposed location is the area on one side near the upper planarization layer 508.

[0064] For example, such as Figure 9 As shown, if the first cutout area 212 and the second cutout area 222 can completely expose the first structural portion 211 and the second structural portion 221, then a portion of the lower insulating layer of the passivation insulating layer 507 containing the first structural portion 211 and the second structural portion 221 will also be removed. This removed portion can be filled by the planarization layer 508, or it can be filled by the first insulating layer, whose dielectric constant is less than that of the passivation insulating layer 507. In this way, not only is the parallel capacitance reduced between the data line 21 and the power line 22, but the field capacitance is also reduced.

[0065] For example, in addition to filling the planarization layer 508, the first through hole, second through hole, first groove, or first conical hole provided in the first gap region 505 corresponding to the passivation insulating layer 507 may also be filled with the first insulating layer.

[0066] For example, the first gap region 505 may be provided with a through hole, which may be filled with a planarization layer 508. Correspondingly, the first cutout region 212 and the second cutout region 222 may be filled with a first insulating layer; or, the through hole provided in the first gap region 505 may be filled with a first insulating layer, and correspondingly, the first cutout region 212 and the second cutout region 222 may also be filled with a first insulating layer; or, the through hole provided in the first gap region 505 may be filled with a first insulating layer, and correspondingly, the first cutout region 212 and the second cutout region 222 may also be filled with a planarization layer 508.

[0067] For example, if the first excavated area 212 and the second excavated area 222 are further enlarged in the first direction, and the first excavated area 212 and the second excavated area 222 are connected in the first direction, such as... Figure 9 As shown, they can be set to the same material, for example, the material of the planarization layer 508 or the material of the first insulating layer.

[0068] In this way, by reducing the capacitance of the two parts (parallel plate capacitance and field capacitance), the coupling capacitance between the data line and the power line is minimized, thereby improving the crosstalk phenomenon between lines at its source.

[0069] In some embodiments, the data line 21 includes a first structural portion 211 extending from the passivation insulating layer 507, and the power line 22 includes a second structural portion 221 extending from the passivation insulating layer 507; the gap region includes a first gap region 505 formed in a first direction between the first structural portion 211 and the second structural portion 221, and the passivation insulating layer 507 is provided with a third through hole corresponding to the first gap region 505, the diameter of the third through hole being the same as the first width of the first gap region in the first direction, the first direction being the setting direction of the passivation insulating layer 507; the third through hole is filled with a second insulating layer, the dielectric constant of the second insulating layer being less than the dielectric constant of the passivation insulating layer 507; and / or, the surfaces of the first structural portion 211 and the second structural portion 221 are provided with a third insulating layer, the dielectric constant of the third insulating layer being less than the dielectric constant of the passivation insulating layer 507, and the dielectric constant of the third insulating layer being the same as or different from the dielectric constant of the second insulating layer.

[0070] In the embodiments of this application, the third via is an opening drilled in the passivated insulating layer 507. The purpose of the third via is to reduce the coupling capacitance between the data line 21 and the power line 22. The diameter of the third via is the same as the width of the first gap region in the first direction, ensuring that the third via can completely cover the first gap region 505. The first gap region 505 is filled with a low dielectric constant material, the second insulating layer, to reduce the capacitive effect.

[0071] In the embodiments of this application, the second insulating layer is an insulating material with a low dielectric constant, such as an organic film (e.g., PMMA, PI, etc.). The dielectric constant of the second insulating layer is about 3.x, which is much lower than that of the passivation insulating layer 507 (about 7.x), or lower than the dielectric constant of the material of the passivation insulating layer 507. By filling the third via with a second insulating layer with a low dielectric constant, the coupling capacitance between the data line 21 and the power line 22 can be significantly reduced.

[0072] In the embodiments of this application, the third insulating layer is an insulating layer covering the surfaces of the data line 21 and the power line 22. The function of the third insulating layer is to further reduce the edge field capacitance between the data line 21 and the power line 22. The dielectric constant of the third insulating layer is lower than that of the passivation insulating layer 507. The same material as the second insulating layer can be used as the third insulating layer, or a different material can be used, depending on the specific manufacturing process conditions and product performance requirements.

[0073] In the embodiments of this application, by adding a third insulating layer to the surfaces of data line 21 and power line 22, both parallel plate capacitance and edge field capacitance can be reduced simultaneously, thereby more comprehensively suppressing coupling effects. Specifically, the thickness and material of the third insulating layer can be adjusted according to actual needs to achieve the best capacitance control effect.

[0074] For example, if the third through hole provided in the first gap region 505 can be filled with the second insulating layer, then the first structural portion 211 and the second structural portion 221 can be surrounded by the third insulating layer on their upper and lower surfaces in the thickness direction. In this way, the area adjacent to the first structural portion 211 and the second structural portion 221 will be filled with the second insulating layer, and the upper and lower surfaces will be filled with the third insulating layer.

[0075] Therefore, by setting a third via between the data line and the power line and filling it with a second insulating layer with a low dielectric constant, and by setting a third insulating layer on the surface of the data line and the power line, the coupling capacitance between the data line and the power line can be significantly reduced, thereby effectively improving the crosstalk phenomenon between lines. This fundamentally solves the problem of screen brightness fluctuations caused by coupling capacitance, thereby improving the screen quality of the OLED display panel, reducing debugging time and production costs, and improving product consistency and reliability.

[0076] In some embodiments, such as Figure 9 As shown, the data line 21 includes a first structural portion 211 extending in a first direction and a third structural portion 213 extending in the thickness direction toward the substrate. The third structural portion 213 is connected to the source or drain of the first transistor disposed in the gate insulating layer 509 in the light-emitting layer. The power line 22 includes a second structural portion 221 extending in the first direction and a fourth structural portion 223 extending in the thickness direction toward the substrate 501. The fourth structural portion 223 is connected to the anode of the display panel 500 through at least one second transistor disposed in the gate insulating layer 509. The first structural portion 211 is disposed in the passivation insulating layer 507, and the second structural portion 221 is disposed in the planarization layer 508 on the second side of the passivation insulating layer 507 facing away from the substrate 501.

[0077] In the embodiments of this application, the data line 21 consists of two parts: one part extends along a first direction (e.g., laterally), referred to as the first structural portion 211 of the data line 21; the other part extends perpendicular to the first direction and along the thickness direction toward the substrate 501, referred to as the third structural portion 213 of the data line 21. The third structural portion 213 of the data line 21 is used for electrical connection with the source or drain of the first transistor located in the light-emitting layer. The overall structural design consisting of the first structural portion 211 and the third structural portion 213 of the data line 21 helps to optimize wiring space and reduce coupling effects with other lines. Specifically, if the MOS transistor on the PDL is a PMOS, the third structural portion 213 of the data line 21 is used for electrical connection with the source of the first transistor located in the light-emitting layer; if it is an NMOS, the third structural portion 213 of the data line 21 is used for electrical connection with the drain of the first transistor located in the light-emitting layer.

[0078] In the embodiments of this application, by dividing the data line 21 into a first structural portion 211 of the horizontally extending data line 21 and a third structural portion 213 of the vertically extending data line 21, a more compact layout can be achieved, and other signal lines can be effectively isolated, thereby reducing parasitic capacitance and interference and improving the display quality of the OLED panel.

[0079] In the embodiments of this application, the power line 22 also consists of two parts: a second structural portion 221 extending along a first direction and a fourth structural portion 223 extending along the thickness direction. The fourth structural portion 223 of the power line 22 is connected to the anode of the display panel 500 through at least one second transistor, and then connected to the anode of the display panel after passing through one or more other transistors, to ensure that the power supply voltage can be stably delivered to each pixel unit.

[0080] For example, at least one second transistor may be two thin-film transistors (TFTs) and one storage capacitor, or four thin-film transistors and one storage capacitor. The driving TFT (such as LTPS or IGZO) controls the anode current, the switching TFT is responsible for data writing, and the storage capacitor maintains voltage stability.

[0081] For example, at least one second transistor can also be a hybrid of a metal-oxide-semiconductor field-effect transistor (MOSFET) and a TFT. For example, a P-channel MOSFET (such as AO3401) acts as a high-side switch to control the anode voltage switching; an N-channel MOSFET is used for low-side current sinking to optimize power consumption.

[0082] In the embodiments of this application, the power line 22 adopts a similar segmented structure design. This design helps to improve the distribution efficiency of the power line 22. The transistor controls the connection path of the power line 22, which enhances the stability of current transmission and reduces the image distortion problem caused by power fluctuations.

[0083] In the embodiments of this application, the first structural portion 211 of the data line 21 (i.e., the lateral portion of the data line 21) is arranged on the passivation insulating layer 507, while the second structural portion 221 of the power line 22 (i.e., the lateral portion of the power line 22) is arranged above the passivation insulating layer 507 and located in the planarization layer 508. This hierarchical arrangement avoids overlap between the data line 21 and the power line 22 in the thickness direction (third direction), preventing height differences and further reducing the coupling capacitance between the data line 21 and the power line 22.

[0084] In the embodiments of this application, a multilayer insulating layer, such as an inter-layer dielectric (ILD) or an inter-metal dielectric (IMD), is further provided between the passivation insulating layer 507 and the gate insulating layer 509.

[0085] In the embodiments of this application, by placing the data line 21 and the power line 22 in different insulating layers, this design achieves a physically staggered layout, thereby significantly reducing the parallel plate capacitance and edge field capacitance between the data line 21 and the power line 22. This reduction in capacitance fundamentally improves the crosstalk phenomenon between lines, thereby enhancing display uniformity and image quality.

[0086] Thus, the first structural portion of the data line and the second structural portion of the power line are located in different insulating layers and are kept at a certain vertical distance from each other, thereby reducing the capacitive coupling effect between them. Meanwhile, the third structural portion of the data line and the fourth structural portion of the power line are respectively connected to their corresponding transistors, ensuring an effective transmission path for signals and power.

[0087] In some embodiments, such as Figure 10 As shown, the height difference between the second structural portion 221 and the first structural portion 211 in the thickness direction forms a second gap region 101. At least one fourth insulating layer is provided in the second gap region 101, and the dielectric constant of the fourth insulating layer is less than the dielectric constant of the passivation insulating layer 507. And / or, the first structural portion 211 and the fourth structural portion 223 form a third gap region 102 in the first direction, and a fifth insulating layer is provided in the third gap region 102, and the dielectric constant of the fifth insulating layer is less than the dielectric constant of the passivation insulating layer 507.

[0088] In embodiments of this application, the fourth insulating layer refers to an insulating material layer located between the first structural portion 211 and the second structural portion 221, used to fill the third gap region 102 formed by the height difference between the first structural portion 211 and the second structural portion 221. The material of the fourth insulating layer has a low dielectric constant (e.g., SiOx or an organic film with a dielectric constant of approximately 3.x to 4.x), which can effectively reduce the coupling capacitance between adjacent signal lines compared to conventionally used passivation insulating layers 507 (e.g., inorganic film SiNx with a dielectric constant of approximately 7.x). Choosing a low dielectric constant material as the fourth insulating layer can significantly reduce the parallel plate capacitance and field capacitance between data lines and power lines.

[0089] In the embodiments of this application, the second gap region 101 is provided with at least one fourth insulating layer. For example, the height difference between the first structural portion 211 and the second structural portion 221 can be at least one fourth insulating layer. Providing a fourth insulating layer with a low dielectric constant in the second gap region can reduce screen brightness abnormalities caused by current fluctuations and improve the overall display quality. At the same time, it avoids relying on software compensation algorithms, thereby improving debugging efficiency and product consistency.

[0090] In embodiments of this application, the fifth insulating layer refers to an insulating material layer located between the first structural portion 211 and the fourth structural portion, used to fill the third gap region 102 formed by the lateral arrangement between the first structural portion 211 and the fourth structural portion. The fifth insulating layer also uses a low dielectric constant material (such as SiOx or an organic film) to further reduce the coupling capacitance between signal lines.

[0091] For example, the first structural portion 211 and the second structural portion 221 are located in different insulating layers. For instance, the first structural portion is located in the passivation insulating layer 507, and the second structural portion 221 is located in the planarization layer 508. Then, the second gap region 101 formed between the second structural portion 221 and the first structural portion 211 at the height difference is filled with an organic film material, and the third gap region 102 formed between the first structural portion 211 and the fourth structural portion 223 in the first direction is filled with SiOx material.

[0092] Thus, by setting a fifth insulating layer in the third gap region, signal interference in different directions can be effectively controlled, which is especially suitable for complex OLED panel wiring structures. This multi-directional insulation optimization scheme, which sets a fifth insulating layer in the third gap region, helps achieve higher image stability and uniformity, while simplifying the manufacturing process and enhancing product reliability.

[0093] In some embodiments, such as Figure 10As shown, the data line 21 includes a first structural portion 211 extending in a first direction and a third structural portion 213 extending in the thickness direction toward the substrate 501. The third structural portion 213 is connected to the source or drain of a first transistor disposed in the gate insulating layer 509 in the light-emitting layer. The power line 22 includes a second structural portion 221 extending in the first direction and a fourth structural portion 223 extending in the thickness direction toward the substrate 501. The fourth structural portion 223 is connected to the anode of the display panel 500 through at least one second transistor disposed in the gate insulating layer 509. The first structural portion 211 and the second structural portion 221 are disposed in different layers on the first side of the substrate 501. The structural portions of the first structural portion 211 or the second structural portion 221 located in different layers are connected by through holes, and the first structural portion 211 and the second structural portion 221 in the same layer have a specific spacing.

[0094] In the embodiments of this application, in order to reduce the coupling capacitance between the data line 21 and the power line 22, a staggered layer design is adopted. That is, a portion of the first structural part 211 of the data line 21 and a portion of the second structural part 221 of the power line 22 are placed on the same layer, while the other portions are placed on different film layers. The purpose of this is to reduce the overlapping area between the two in the thickness direction, thereby reducing the parallel plate capacitance.

[0095] In the embodiments of this application, such as Figure 11 As shown, when parts of the same structure are located on different layers, electrical connection is achieved through vias 220. Vias are a common interconnect structure used to establish conductive paths between different layers, ensuring signal or current continuity. By rationally designing the location and number of vias, more efficient signal transmission and lower coupling effects can be achieved without increasing overall complexity.

[0096] In the embodiments of this application, the parallel capacitance can be reduced by setting a specific spacing between different structural parts of the same layer. Of course, in the above embodiments, the parallel plate capacitance can also be reduced by increasing the spacing between the first structural part 211 and the second structural part 221 in the first direction, combined with the isolation structure.

[0097] For example, for overlapping regions where the coupling capacitance between the first structural portion 211 and the second structural portion 221 is small, the coupling capacitance between the data line 21 and the power line 22 can be reduced by increasing the spacing (see [link]). Figure 11 (Region 111 in the text), for the overlapping region with a large coupling capacitance between the first structural part 211 and the second structural part 221 (see...) Figure 11 In area 112 of the data line, a staggered arrangement can be used to reduce the coupling capacitance between the data line 21 and the power line 22.

[0098] In this way, by staggering the structural components of the data and power lines, achieving cross-layer connections through vias, and increasing the spacing within the same layer, the coupling capacitance between the data and power lines can be significantly reduced, thereby improving crosstalk. This fundamentally reduces data signal interference caused by coupling capacitance, thus improving the stability and clarity of the displayed image, and ultimately enhancing the user's visual experience when using an OLED display.

[0099] The display panel provided in this application embodiment includes: a substrate; a light-emitting layer disposed on a first side of the substrate, the light-emitting layer including a plurality of pixel light-emitting devices spaced apart, each pixel light-emitting device being configured with a corresponding pixel driving circuit; the pixel driving circuit including a data line for providing data voltage to the pixel light-emitting device and a power line for providing operating power; wherein, there is a gap region between the data line and the power line, and an isolation structure is disposed in at least a portion of the gap region, the dielectric constant of the isolation structure being less than the dielectric constant of the passivation insulating layer covering the power line and the data line. The display panel provided in this application embodiment significantly reduces the coupling capacitance between the data line and the power line by providing an isolation structure with a lower dielectric constant in the gap region between the data line and the power line, replacing the original passivation insulating layer with a higher dielectric constant. Since coupling capacitance is the main cause of line-xtalk phenomenon, this solution effectively suppresses brightness anomalies caused by signal jumps at the hardware level, improves image quality, and simplifies the debugging process and improves overall stability without relying on scanning direction or specific algorithm compensation.

[0100] This application also provides an electronic device, including: The housing has a receiving groove; the display panel is sealed in the receiving groove, and the display panel includes: a substrate; A light-emitting layer is disposed on the first side of a substrate, the light-emitting layer including a plurality of pixel light-emitting devices arranged at intervals, and each pixel light-emitting device is configured with a corresponding pixel driving circuit; The pixel driving circuit includes a data line for providing data voltage to the pixel light-emitting device and a power line for providing operating power. The data line and the power line have a gap region, and an isolation structure is provided in at least a portion of the gap region. The dielectric constant of the isolation structure is less than the dielectric constant of the passivation insulation layer covering the power line and the data line.

[0101] In the embodiments of this application, the display device is a device with a display panel. Exemplarily, the display device can be a laptop, tablet, desktop computer, etc., and the display device is not limited thereto.

[0102] In the several embodiments provided in this application, it should be understood that the disclosed structures and methods can be implemented in a non-target manner. The structural embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the various components shown or discussed are coupled to each other or directly coupled.

[0103] The features disclosed in the several method or structural embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or structural embodiments.

[0104] The above are merely some embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the above-described scope.

Claims

1. A display panel, comprising: Substrate; A light-emitting layer is disposed on the first side of the substrate, the light-emitting layer including a plurality of pixel light-emitting devices arranged at intervals, each pixel light-emitting device being configured with a corresponding pixel driving circuit. The pixel driving circuit includes a data line for providing data voltage to the pixel light-emitting device and a power line for providing operating power. The data line and the power line have a gap region, and an isolation structure is provided in at least a portion of the gap region. The dielectric constant of the isolation structure is less than the dielectric constant of the passivation insulating layer covering the power line and the data line.

2. The display panel according to claim 1, wherein the gap region includes a gap region formed by the height difference between the data line and the power line in the thickness direction of the display panel and / or a gap region formed at different positions in a first direction, wherein the first direction is perpendicular to the thickness direction; The isolation structure ensures that the coupling capacitance between the data line and the power line is less than the target threshold.

3. The display panel according to claim 2, wherein the data line includes a first structural portion extending from the passivated insulating layer, and the power line includes a second structural portion extending from the passivated insulating layer; The gap region includes a first gap region formed between the first structural portion and the second structural portion. The passivation insulating layer is provided with a first through hole corresponding to the first gap region. The diameter of the first through hole is the same as the first width of the first gap region in a first direction. The first direction is the setting direction of the passivation insulating layer. The light-emitting layer further includes a planarization layer disposed on the second side of the passivation insulating layer facing away from the substrate. The first via is filled with the planarization layer. The dielectric constant of the planarization layer is less than the dielectric constant of the passivation insulating layer, so that the parallel plate capacitance formed between the first structural portion and the second structural portion is less than a first threshold.

4. The display panel according to claim 3, wherein, The passivated insulating layer has a second through-hole corresponding to the first gap region, the diameter of the second through-hole being smaller than the first width, and the planarization layer fills the second through-hole; or, The passivation insulating layer has a first groove corresponding to the first gap region, and the planarization layer fills the first groove; or... The passivation insulating layer has a first conical hole corresponding to the first gap region, and the planarization layer fills the first conical hole. The maximum diameter of the first conical hole is less than or equal to the first width.

5. The display panel according to claim 3 or 4, wherein, The passivation insulating layer is provided with a first hollow area corresponding to the first structural part and / or a second hollow area corresponding to the second structural part, and the planarization layer fills the first hollow area and / or the second hollow area. And / or, The first gap region is further filled with a first insulating layer, the dielectric constant of which is less than that of the passivation insulating layer.

6. The display panel according to claim 2, wherein the data line includes a first structural portion extending from the passivated insulating layer, and the power line includes a second structural portion extending from the passivated insulating layer; The gap region includes a first gap region formed in a first direction between the first structural portion and the second structural portion. The passivation insulating layer is provided with a third through hole corresponding to the first gap region. The diameter of the third through hole is the same as the first width of the first gap region in the first direction. The first direction is the setting direction of the passivation insulating layer. The third through hole is filled with a second insulating layer, and the dielectric constant of the second insulating layer is less than that of the passivation insulating layer. And / or, A third insulating layer is provided on the surface of the first structural portion and the second structural portion. The dielectric constant of the third insulating layer is less than that of the passivation insulating layer. The dielectric constant of the third insulating layer may be the same as or different from that of the second insulating layer.

7. The display panel according to claim 2, wherein the data line includes a first structural portion extending in a first direction and a third structural portion extending toward the substrate along the thickness direction, the third structural portion being connected to the source or drain of a first transistor disposed in the gate insulating layer of the light-emitting layer; The power line includes a second structural portion extending in a first direction and a fourth structural portion extending toward the substrate along the thickness direction. The fourth structural portion is connected to the anode of the display panel via at least one second transistor disposed in the gate insulating layer. in, The first structural portion is disposed on the passivation insulating layer, and the second structural portion is disposed on the planarization layer on the second side of the passivation insulating layer facing away from the substrate.

8. The display panel according to claim 7, wherein the height difference between the second structural portion and the first structural portion in the thickness direction forms a second gap region, and at least one fourth insulating layer is disposed in the second gap region, wherein the dielectric constant of the fourth insulating layer is less than the dielectric constant of the passivation insulating layer; And / or, The first structural portion and the fourth structural portion form a third gap region in a first direction, and a fifth insulating layer is disposed in the third gap region. The dielectric constant of the fifth insulating layer is less than that of the passivation insulating layer.

9. The display panel according to claim 2, wherein the data line includes a first structural portion extending in a first direction and a third structural portion extending toward the substrate along the thickness direction, the third structural portion being connected to the source or drain of a first transistor disposed in the gate insulating layer of the light-emitting layer; The power line includes a second structural portion extending in a first direction and a fourth structural portion extending toward the substrate along the thickness direction. The fourth structural portion is connected to the anode of the display panel via at least one second transistor disposed in the gate insulating layer. in, The first structural portion and the second structural portion are disposed on different layers on the first side of the substrate; the structural portions of the first structural portion or the second structural portion located on different layers are connected by through holes, and the first structural portion and the second structural portion on the same layer have a specific spacing.

10. A display device, comprising: The outer casing has a receiving groove; A display panel is sealed within the receiving groove, the display panel comprising: Substrate; A light-emitting layer is disposed on the first side of the substrate, the light-emitting layer including a plurality of pixel light-emitting devices arranged at intervals, each pixel light-emitting device being configured with a corresponding pixel driving circuit. The pixel driving circuit includes a data line for providing data voltage to the pixel light-emitting device and a power line for providing operating power. The data line and the power line have a gap region, and an isolation structure is provided in at least a portion of the gap region. The dielectric constant of the isolation structure is less than the dielectric constant of the passivation insulating layer covering the power line and the data line.

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