Layout of circuit structure and manufacturing method of circuit structure

Abstract

The manufacturing method of the circuit structure comprises the steps of decomposing an original layout into a first layout and a second layout, identifying a first pattern to be cut of the first layout, then determining a first selected block from blocks of the first pattern to be cut, and inserting a first cut pattern into the first selected block. And deducting the first cutting pattern from the first pattern to be cut, outputting a first layout to the first mask, and outputting a second layout and the first cutting pattern to the second mask. A double patterning process is performed using the first mask and the second mask to form a circuit structure on the substrate.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a circuit structure layout and a method for manufacturing the circuit structure using a dual patterning technique. Background Technology

[0002] Integrated circuits (ICs) are devices and interconnects constructed from patterned features formed on a substrate or different film layers. Photolithography is an indispensable technology in IC manufacturing. It involves forming designed layout patterns, such as placement area patterns or circuit structure layout patterns, on a mask. Then, through exposure and development steps, the pattern on the mask is transferred to a photoresist layer on a substrate. This patterned photoresist layer then acts as a shield for ion implantation or etching of the underlying film layers, thereby transferring the designed pattern into the film layers.

[0003] As integrated circuit dimensions shrink, the design of layout patterns becomes increasingly sophisticated, and the spacing between feature patterns is approaching the limits of existing exposure technologies. Based on existing equipment, multiple patterning techniques, such as dual patterning (DPT), have been developed in this field and are widely used in advanced processes to fabricate patterns with minute critical dimensions and / or minute spacing. Multiple patterning technology decomposes an original layout into two or more decomposed layouts, then forms each of these decomposed layouts into a mask, and finally uses these masks in a lithography process to combine them onto a substrate to recreate the desired original layout.

[0004] The aforementioned multi-patterning techniques can effectively solve the problem of fine spacing in the original layout, but they still cannot solve the development anomalies caused by the special shape of the feature patterns themselves, especially in lithography processes using negative tone development (NTD) technology. For example, when the total area of ​​the feature patterns is greater than the area of ​​the development barrier, and the difference in width and / or area between the large and small connected blocks in the feature patterns exceeds the development barrier ratio, the small blocks may suffer from line shrinkage defects. Summary of the Invention

[0005] This invention provides a circuit structure layout and a method for manufacturing the circuit structure using a dual patterning technique. The method involves inserting a cutting pattern into a selected area of ​​a risk feature pattern, dividing the feature pattern into two separate parts, each with a width ratio and / or area ratio that does not approach or exceed the development barrier. This solves the problem of development abnormalities.

[0006] An embodiment of the present invention provides a method for manufacturing a circuit structure, comprising decomposing an original layout into a first layout and a second layout, the first layout and the second layout each including a plurality of feature patterns. Next, a first pattern to be cut is identified in the first layout, the first pattern to be cut including a plurality of consecutively connected blocks. Then, according to a selection rule, a first selected block is determined from the plurality of blocks of the first pattern to be cut, and a first cutting pattern is inserted into the first selected block. Next, after subtracting the first cutting pattern from the first pattern to be cut, the first layout is output to a first mask, and the second layout and the first cutting pattern are output to a second mask. Then, a dual patterning process is performed using the first mask and the second mask to form a circuit structure on a substrate.

[0007] Another embodiment of the present invention provides a circuit structure layout, including a first pattern including a first end and a second end, the first end including a first width and the second end including a second width; a second pattern including a third end and a fourth end, wherein the third end and the second end are disposed opposite to each other along a first direction and separated from each other, the third end including the second width and the fourth end including a third width, the third width being smaller than the second width and the second width being smaller than the first width; and a stitching pattern located between the second end and the third end, wherein the first pattern and the second pattern have a first color for output to a first mask, and the stitching pattern has a second color for output to a second mask. Attached Figure Description

[0008] Figure 1 This is a flowchart illustrating the steps of a method for manufacturing a circuit structure according to an embodiment of the present invention.

[0009] Figures 2 to 11 This is a schematic diagram of a method for manufacturing a circuit structure according to an embodiment of the present invention, wherein... Figures 2 to 6 Explain the steps for breaking down the original layout and modifying the broken-down layout. Figures 7 to 11 This describes the steps for a dual patterning process using two masks, including a modified decomposed layout. Detailed Implementation

[0010] To enable those skilled in the art to further understand the present invention, preferred embodiments of the present invention are described below, and the composition and desired effects of the present invention are explained in detail with reference to the accompanying drawings.

[0011] The figures in this invention are schematic diagrams and not drawn to scale. The dimensions of some components may be enlarged for clarity. Where features in the figures are common or similar, they are usually represented by the same reference numerals for ease of drawing and description. Spatial terms used herein, such as "below," "low," "under," "above," "above," "top," "bottom," etc., are understood by those skilled in the art to describe the relative relationship between one component or feature and another component (or more) in the figures. Rotation at any angle (e.g., 90 degrees or other orientations) will still conform to the spatial descriptions herein. Some figures indicate reference directions, such as a first direction X and a second direction Y, for spatial description purposes, wherein the first direction X and the second direction Y are perpendicular to each other.

[0012] The terms "equal to," "equivalent to," "identical to," or "approximately" are generally interpreted as being within 20% of a given value or range, or within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range. A certain degree of error may exist between any two values ​​or directions used for comparison.

[0013] Please refer to Figure 1 The circuit structure manufacturing method 100 first performs step 102, receiving an original layout of the circuit structure, and then decomposing the original layout into a first layout and a second layout. Next, it performs step 104, identifying a first pattern to be cut in the first layout. In some embodiments, step 104 further includes identifying a second pattern to be cut in the second layout.

[0014] Figure 2 and Figure 3 This is a schematic diagram of steps 102 and 104. (See attached diagram.) Figure 2As shown, the original layout ML includes feature patterns 12, 14, 16, 18, 20, 22, 24, and 26, each composed of multiple connected rectangular blocks. The number, shape, and position of the feature patterns shown in the figure are merely examples and are not intended to limit the invention. The dimensions of the feature patterns are not drawn to scale for ease of drawing and illustration. The original layout ML includes at least one feature pattern that approaches or exceeds a development barrier, such as feature pattern 12, which is composed of multiple blocks A, B, C, D, E, and F continuously connected along a first direction X. In this document, the length of a block is defined as its dimension along the first direction, the width of a block is defined as its dimension along a second direction, and the area of ​​a block is defined as the product of its length and width. The lengths and widths of these blocks may be the same or different. In some embodiments, the blocks are connected in order of decreasing width, i.e., block A has the largest width and block F has the smallest width. In some embodiments, the ratio of the width of block F to the width of block A is less than 3 / 100, or less than 2 / 100, or less than 1 / 100. In some embodiments, the width of block F is approximately 40 nm, the width of block A is approximately 4000 nm, and the widths of blocks B, C, D, and E are between 40 nm and 4000 nm, but are not limited thereto. In some embodiments, the ratio of the area of ​​block F to the total area of ​​the other blocks A, B, C, D, and E is less than 1 / 1600 or less than 1 / 2000. Block F may also be referred to as the smallest block.

[0015] In some embodiments, the original layout ML also includes another feature pattern that approaches or exceeds the development barrier, such as feature pattern 14, which may be composed of multiple blocks P, Q, and R connected continuously along the first direction X in an order of decreasing width. The proportional relationship between the width and area of ​​block R and block P can be referred to the relevant description of blocks F and A of feature pattern 12, and will not be repeated here. Block R may also be referred to as the minimum block.

[0016] It should be noted that feature patterns 12, 14, 16, 18, 20, 22, 24, and 26 can be independent patterns separate from other feature patterns, or connected to other feature patterns, or belong to a part of a continuous feature pattern. For example, blocks A and F of feature pattern 12 can be the ends of the pattern or connected to another block. Similarly, blocks P and R of feature pattern 14 can be the ends of the pattern or connected to another block. In this embodiment, blocks A, B, C, D, E, and F are divided by the edge turning points of feature pattern 12, and blocks P, Q, and R are divided by the edge turning points of feature pattern 14. In other embodiments, other methods can be used to divide the blocks.

[0017] like Figure 3As shown, the original layout ML is decomposed into a first layout ML1 and a second layout ML2. The first layout ML1 may include feature patterns 12, 18, 20, and 24, while the second layout ML2 may include feature patterns 14, 16, 22, and 26. To facilitate differentiation between the first layout ML1 and the second layout ML2, the feature patterns of the first layout ML1 are colored with a first color (represented by a white background in the figure), and the feature patterns of the second layout ML2 are colored with a second color (represented by a background texture in the figure). The method for decomposing the original layout ML is designed based on design specifications and process tolerances, and will not be detailed here. Next, the first layout ML1 and the second layout ML2 are inspected separately to identify feature patterns with a risk of developing defects. Feature patterns 12 and 14, due to their special configurations, are identified as pattern-to-cut patterns in the first layout ML1 and the second layout ML2, respectively.

[0018] Please refer to Figure 1 The circuit structure manufacturing method 100 then proceeds to step 106, which determines a first selected block from a plurality of blocks of a first pattern to be cut according to a selection rule. In some embodiments, step 106 further includes determining a second selected block from a plurality of blocks of a second pattern to be cut according to the selection rule. In some embodiments, the selection rule includes a spacing rule, wherein the distance between adjacent feature patterns of the same layout is less than a first predetermined value, and the distance between adjacent feature patterns of another layout is greater than a second predetermined value, wherein the first predetermined value is less than the second predetermined value. In some embodiments, the selection rule further includes a dimension rule, wherein blocks with longer lengths are preferred, and blocks with smaller widths are preferred. In some embodiments, the selection rule further includes excluding the smallest block.

[0019] Figure 4 This is a schematic diagram of step 106. (See diagram below.) Figure 4As shown, more specifically, the step of determining the selected blocks from blocks A, B, C, D, and E of the feature pattern 12 (i.e., the first pattern to be cut) of the first layout ML1 includes checking the spacing S1 between the feature pattern 12 and the adjacent feature patterns of the first layout ML1 in the second direction Y, and the spacing S2 between the feature pattern 12 and the adjacent feature patterns of the second layout ML2 in the second direction Y. Then, the blocks are further divided into smaller blocks according to different spacings S1 and S2. For example, block B is further divided into blocks B1, B2, B3, and B4 according to different spacings S2; block D is further divided into blocks D1 and D2 according to different spacings S2; and block E is further divided into blocks E1 and E2 according to different spacings S1 and S2. Next, blocks that meet the rule that spacing S1 is less than a first predetermined value and spacing S2 is greater than a second predetermined value are selected. For example, blocks A, B1, B2, E1, and E2 are excluded because they violate the rule that the spacing S1 must be less than a first predetermined value. Blocks B4 and D2 are excluded because they violate the rule that the spacing S2 must be greater than a second predetermined value. According to one embodiment of the present invention, the first predetermined value is approximately 70 nm, and the second predetermined value is approximately 90 nm, but is not limited thereto. Through the above selection steps, one or more blocks that meet the above spacing selection rules can be found, such as blocks B3, C, and D1. Then, according to the size selection rules, block D1 is preferentially selected from blocks B3, C, and D1.

[0020] Similarly, the step of determining the selected block from blocks A, B, C, D, and E of the feature pattern 14 (i.e., the second pattern to be cut) of the second layout ML2 includes checking the spacing S1 between feature pattern 14 and the adjacent feature pattern of the first layout ML1 in the second direction Y, and the spacing S2 between feature pattern 12 and the adjacent feature pattern of the second layout ML2 in the second direction Y. Then, based on the different spacings S1 and S2, the blocks are further divided into smaller blocks. For example, block Q is divided into Q1, Q2, Q3, Q4, Q5, Q6, and Q7. Next, according to the rule that spacing S1 must be less than a first predetermined value and spacing S2 must be greater than a second predetermined value, blocks Q3, Q5, and Q7 are selected. Then, according to the size selection rule, the longer block Q7 is preferentially selected.

[0021] Please refer to Figure 1 The circuit structure manufacturing method 100 then proceeds to step 108, inserting a first cutting pattern into a first selected block. In some embodiments, step 108 further includes inserting a second cutting pattern into a second selected block.

[0022] Figure 5 This is a schematic diagram of step 108. (See diagram below.) Figure 5As shown, after determining the selected block D1 (first selected block) of feature pattern 12 in step 106, a cutting pattern 32 (first cutting pattern) is then inserted into block D1, so that feature pattern 12 can be divided into two separate parts after deducting the portion overlapping with cutting pattern 32. Similarly, a cutting pattern 34 (second cutting pattern) is also inserted into the selected block Q7 (second selected block) of feature pattern 14, so that feature pattern 14 can be divided into two separate parts after deducting the portion overlapping with cutting pattern 34. The shape and size of cutting pattern 32 and cutting pattern 34 can be adjusted according to design requirements. In some embodiments, cutting pattern 32 and cutting pattern 34 are respectively rectangular in shape, and their length and width must conform to the specifications of the first layout ML1 and the second layout ML2.

[0023] Please refer to Figure 1 The circuit structure manufacturing method 100 then proceeds to step 110, subtracting a first cutting pattern from a first pattern to be cut, and then proceeds to step 112, outputting a first layout to a first mask, and outputting a second layout and the first cutting pattern to a second mask. In some embodiments, step 110 further includes subtracting a second cutting pattern from a second pattern to be cut, and step 112 further includes outputting a second cutting pattern to a first mask.

[0024] Figure 6 This is a schematic diagram of steps 110 and 112. (See attached diagram.) Figure 6 As shown, feature pattern 12, after subtracting cut pattern 32, becomes two separate feature patterns 12a and 12b, which are then output to the first mask 302 together with feature patterns 18, 20, and 24 of the first layout ML1. In some embodiments, feature pattern 14, after subtracting cut pattern 34, becomes two separate feature patterns 14a and 14b, which are then output to the second mask 304 together with feature patterns 16, 22, and 26 of the second layout ML2. Notably, cut pattern 32 is colored with a second color and output to the second mask 304, while cut pattern 34 is colored with a first color and output to the first mask 302. Before being output to the mask, the feature patterns and cut patterns can be modified by optical proximity correction (OPC), such as right-angle rounding, end enlargement / reduction, and linewidth increase / reduction. In some embodiments, the lengths of the two ends of the cutting pattern 32 and the cutting pattern 34 are extended along the first direction X to obtain a cutting pattern 32' that partially overlaps with feature patterns 12a and 12b, and a cutting pattern 34' that partially overlaps with feature patterns 14a and 14b. The cutting patterns 32' and 34' are then output to the second mask 304 and the first mask 302, respectively.

[0025] Please refer to Figure 1The circuit structure manufacturing method 100 then proceeds to step 114, using a first mask and a second mask to perform a dual patterning process to form a circuit structure on the substrate.

[0026] Figures 7 to 10 This is a schematic diagram of step 114, where the upper part of each figure is a cross-sectional view and the lower part is a planar view, illustrating the use of a first mask 302 and a second mask 304 for a dual patterning process to form a circuit structure M1 on a substrate 202. The first mask 302 includes an opaque region 302a and a clear region 302b, wherein the feature patterns 12a, 12b, 18, 20, 24 and the cut pattern 34 (or cut pattern 34') are opaque regions 302a on the first mask 302. The second mask 304 includes an opaque region 304a and a clear region 304b, wherein the feature patterns 14a, 14b, 16, 22, 26 and the cut pattern 32 (or cut pattern 32') are opaque regions 304a on the second mask 304. The circuit structure M1 can be, for example, a wire structure fabricated in a dielectric layer DL on the substrate 202, but is not limited to this.

[0027] It should be specifically noted that the dual patterning process in this embodiment uses positive-type photoresist combined with negative tone development (NTD), and includes a double exposure, double development, and etching process (2P2D2E) using two photoresist layers. In other embodiments of the present invention, the dual patterning process may also use a single or double photoresist layer for a double exposure, double development, and single etching process (2P2D1E), but is not limited thereto. Furthermore, Figures 7 to 10 Therefore Figure 6 The upper feature patterns 12a, 12b and cutting pattern 32' illustrate the steps of the dual patterning process, and those skilled in the art will understand that the same description also applies to feature patterns 14a, 14b and cutting pattern 34'.

[0028] In detail, such as Figure 7As shown, a dielectric layer DL is first formed on a substrate 202, and then a first photoresist layer 210 is formed on the dielectric layer DL. The substrate 202 is, for example, a silicon substrate, a silicon-coated insulating substrate, a group III-V semiconductor substrate, etc., but is not limited thereto. The substrate 202 may contain pre-fabricated components, such as transistors, capacitors, resistors, wires, dielectric layers, etc., but is not limited thereto. For simplicity, these components are not shown in the figure. The dielectric layer DL may have a multilayer structure, sequentially including dielectric layer 204, dielectric layer 206, and dielectric layer 208 from bottom to top. The materials of dielectric layer 204 and dielectric layer 208 may include silicon oxide (SiO2) or a low-k dielectric material. Low-k dielectric materials may include, but are not limited to, fluorinated silica glass (FSG), silicon carbide oxide (SiCOH), spin-on glass, porous low-k dielectric material, or organic polymer dielectric materials. The material of dielectric layer 206 differs from that of dielectric layer 204, and may include, for example, silicon nitride (SiN), silicon carbonitride (SiCN), or silicon oxynitride (SiON), but is not limited to these. The layers of dielectric layer DL described above are merely examples, and the invention is not limited thereto. In other embodiments, dielectric layer DL may include different numbers of layers or have a single-layer structure. The first photoresist layer 210 may include any suitable positive photoresist. Next, a patterning process is performed on the first photoresist layer 210, including using the first mask 302 to perform a first exposure and negative development on the first photoresist layer 210, removing the unexposed portion of the first photoresist layer 210, thereby transferring the pattern of the opaque area 302a of the first mask 302 to the first photoresist layer 210, forming feature patterns 12a and 12b in the first photoresist layer 210.

[0029] like Figure 8 As shown, the etching process is then performed using the first photoresist layer 210 as a shield, removing the dielectric layer 208 not covered by the first photoresist layer 210 until the dielectric layer 206 is exposed. This transfers the pattern of the first photoresist layer 210 further down into the dielectric layer 208, forming trenches R1 and R2 defined by feature patterns 12a and 12b, respectively, in the dielectric layer 208. The dielectric layer 206 can serve as an etch stop layer during the etching process to control the trenches R1 and R2 to have a more consistent depth. After forming trenches R1 and R2, the remaining portion of the first photoresist layer 210 is removed.

[0030] like Figure 9As shown, a planarization layer 209 is then formed to completely cover the dielectric layer 208 and trenches R1 and R2. A second photoresist layer 212 is then formed on the planarization layer 209. Next, a patterning process is performed on the second photoresist layer 212, including a second exposure and negative development using a second mask 304. This removes the unexposed portions of the second photoresist layer 212, thereby transferring the pattern of the opaque region 304a of the second mask 304 to the second photoresist layer 212, forming an opening OP defined by the cutting pattern 32' in the second photoresist layer 212. The planarization layer 209 may include an organic dielectric layer (ODL), an optical planarization layer (OPL), a spin-on hard mask (SOH), and / or an advanced patterning film (APF). Its material must have a high etch selectivity with respect to dielectric layers 208 and 206 to achieve trench R3 (reference). Figure 10 The planarization layer 209 was then removed using a selective etching process.

[0031] like Figure 10 As shown, the etching process is then performed using the second photoresist layer 212 as a shield, removing the planarization layer 209 exposed from the opening OP and the dielectric layer 208 between trenches R1 and R2 until the dielectric layer 206 is exposed, allowing the two ends of trenches R1 and R2 to connect and form a continuous trench R3. Then, the remaining second photoresist layer 212 and planarization layer 209 are removed. Trench R3 has a pattern defined by feature pattern 12. In some embodiments, during etching through the opening OP, due to the different etching rates between the planarization layer 209 and the dielectric layer 208, a groove 206a will be left in the dielectric layer 206. Figure 9 As can be seen, the location of the indentation 206a is approximately the area where feature patterns 12a and 12b overlap with the cutting pattern 32'.

[0032] like Figure 11 As shown, a conductive material 220 is then formed to completely cover the dielectric layer 208 and fill the trench R3. A removal process, such as etching or chemical mechanical polishing, is then performed to remove the conductive material 220 outside the trench R3, resulting in a circuit structure 12M located within the trench R3. The conductive material 220 may include a metallic material, such as copper (Cu), but is not limited to this.

[0033] The circuit structure manufacturing method provided by the present invention cuts the feature pattern into two separate parts by inserting a cutting pattern into a selected area of ​​the feature pattern (i.e., subtracting the cutting pattern from the feature pattern). The cut feature pattern and the cutting pattern are then output to two masks, and a dual patterning process is performed using these two masks to combine the desired original layout on the substrate. Since the width ratio and / or area ratio of each cut feature pattern will not approach or exceed the development barrier, the problem of development abnormalities can be solved.

[0034] This invention also provides a circuit structure layout. Please refer to... Figure 6 The upper part of the layout includes a first pattern 12a, a second pattern 12b, and a stitching pattern 32' located between the first pattern 12a and the second pattern 12b. The first pattern 12a includes a first end Aa and a second end D1a, with the first end Aa having a first width W1 and the second end D1a having a second width W2. The second pattern 12b includes a third end D1b and a fourth end Fa, with the second end D1a having a second width W2 and being disposed opposite to and separated from the third end D1b along a first direction X. The fourth end Fa has a third width W3, wherein the third width W3 is smaller than the second width W2, and the second width W2 is smaller than the first width W1. The first pattern 12a and the second pattern 12b have a first color for output to a first mask 302, and the stitching pattern 32' has a second color for output to a second mask 304.

[0035] In some embodiments, the first mask 302 and the second mask 304 are used for a dual patterning process, wherein the total area of ​​the first pattern 12a, the second pattern 12b and the stitching pattern 32' in the layout is greater than the area of ​​a development barrier in the dual patterning process.

[0036] In some embodiments, the width of the first pattern 12a gradually decreases from the first end Aa to the second end D1a, and the width of the second pattern 12b gradually decreases from the third end D1b to the fourth end Fa.

[0037] In some embodiments, the ratio of the third width W3 to the first width W1 is less than 1 / 100. In some embodiments, the third width is less than 40 nm, and the first width is greater than 4000 nm.

[0038] In some embodiments, the ratio of the area of ​​the second pattern 12b to the area of ​​the first pattern 12a is less than 1 / 2000.

[0039] In some embodiments, the stitching pattern 32' partially overlaps with the second end D1a of the first pattern 12a and the third end D1b of the second pattern 12b. In some embodiments, the edges of the second end D1a, the stitching pattern 32', and the third end D1b are aligned along the first direction X.

[0040] In some embodiments, the layout of the circuit structure further includes a plurality of third patterns 18, 20, 24 having a first color, wherein the stitching pattern 32' is adjacent to the third pattern 20 and the spacing is S1 (reference). Figure 4 It is less than the minimum spacing between the third pattern 18, 20, and 24.

[0041] In some embodiments, the layout of the circuit structure further includes a plurality of fourth patterns 16, 22, 26 having a second color, wherein the stitching pattern 32' is adjacent to the fourth pattern 16 and the spacing S2 is greater than a minimum spacing between the fourth patterns 16, 22, 26.

[0042] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0043] [Symbol Explanation]

[0044] 12: Characteristic Pattern

[0045] 14: Characteristic Patterns

[0046] 16: Featured pattern, fourth pattern

[0047] 18: Feature pattern, third pattern

[0048] 20: Feature pattern, third pattern

[0049] 22: Featured pattern, fourth pattern

[0050] 24: Feature pattern, third pattern

[0051] 26: Featured pattern, fourth pattern

[0052] 32: Cutting pattern

[0053] 34: Cutting Pattern

[0054] 100: Manufacturing Method

[0055] 102: Steps

[0056] 104: Steps

[0057] 106: Steps

[0058] 108: Steps

[0059] 110: Steps

[0060] 112: Steps

[0061] 114: Steps

[0062] 202: Base

[0063] 204: Dielectric layer

[0064] 206: Dielectric layer

[0065] 206a: Dent

[0066] 208: Dielectric layer

[0067] 209: Planarization layer

[0068] 210: First photoresist layer

[0069] 212: Second photoresist layer

[0070] 220: Conductive materials

[0071] 302: First Mask

[0072] 304: Second Mask

[0073] 12a: Characteristic pattern, first pattern

[0074] 12M: Circuit Structure

[0075] 12b: Characteristic pattern, second pattern

[0076] 14a: Characteristic Pattern

[0077] 14b: Characteristic Pattern

[0078] 302a: Opaque area

[0079] 302b: Translucent area

[0080] 304a: Opaque area

[0081] 304b: Translucent area

[0082] 32': Cutting pattern

[0083] 34': Cutting pattern

[0084] A: Block

[0085] Aa: First end

[0086] B: Block

[0087] B1: Block

[0088] B2: Block

[0089] B3: Block

[0090] B4: Block

[0091] C: Block

[0092] D: Block

[0093] D1: Block

[0094] D1a: Second end

[0095] D1b: Third end

[0096] D2: Block

[0097] DL: Dielectric layer

[0098] E: Block

[0099] E1: Block

[0100] E2: Block

[0101] F: Block

[0102] Fa: Fourth end

[0103] ML: Original Layout

[0104] ML1: First layout

[0105] ML2: Second Layout

[0106] OP: Opening

[0107] P: Block

[0108] Q: Block

[0109] Q1: Block

[0110] Q2: Block

[0111] Q3: Block

[0112] Q4: Block

[0113] Q5: Block

[0114] Q6: Block

[0115] Q7: Block

[0116] R: Block

[0117] R1: Trench

[0118] R2: Trench

[0119] R3: Trench

[0120] S1: Spacing

[0121] S2: Spacing

[0122] W1: First width

[0123] W2: Second width

[0124] W3: Third Width

[0125] X: First direction

[0126] Y: Second direction

Claims

1. A method for manufacturing a circuit structure, comprising: An original layout is decomposed into a first layout and a second layout, wherein the first layout and the second layout each include multiple feature patterns; Identify a first pattern to be cut in the first layout, the first pattern to be cut comprising a plurality of consecutively connected blocks; According to a selection rule, a first selection block is determined from the plurality of blocks of the first pattern to be cut; Insert a first cutting pattern into the first selected area; After subtracting the first cutting pattern from the first pattern to be cut, the first layout is output to a first mask, and the second layout and the first cutting pattern are output to a second mask; as well as A dual patterning process is performed using the first mask and the second mask to form a circuit structure on a substrate.

2. The method for manufacturing a circuit structure as described in claim 1, wherein the total area of ​​the first pattern to be cut is greater than the area of ​​a development barrier in the dual patterning process.

3. The method for manufacturing a circuit structure as described in claim 1, wherein the plurality of blocks of the first pattern to be cut are connected in order of decreasing width.

4. The method for manufacturing the circuit structure as described in claim 3, wherein the ratio of a minimum width to a maximum width of the first pattern to be cut is less than 1 / 100.

5. The method for manufacturing the circuit structure according to claim 4, wherein the minimum width is less than 40 nm and the maximum width is greater than 4000 nm.

6. The method of manufacturing the circuit structure as described in claim 3, wherein the ratio of the area of ​​the smallest block of the plurality of blocks to the total area of ​​the other blocks of the plurality of blocks is less than 1 / 2000.

7. The method for manufacturing the circuit structure as described in claim 1, wherein the selection rules include: The distance between adjacent feature patterns with the same layout must be less than a first predetermined value; and The distance between adjacent feature patterns of another layout must be greater than a second predetermined value, wherein the first predetermined value is less than the second predetermined value.

8. The method for manufacturing the circuit structure as described in claim 7, wherein the selection rule further includes: Prioritize selecting blocks that are longer.

9. The method for manufacturing the circuit structure as described in claim 7, wherein the selection rule further includes: Prioritize selecting blocks with smaller widths.

10. The method for manufacturing the circuit structure as described in claim 1, further comprising: Identify a second pattern to be cut in the second layout; According to the selection rules, a second selection block of the second pattern to be cut is determined; Insert a second cutting pattern into the second selected area; as well as After subtracting the second cutting pattern from the second pattern to be cut, the second layout is output to the second mask, and the first layout and the second cutting pattern are output to the first mask.

11. A circuit structure layout, comprising: A first pattern includes a first end and a second end, the first end including a first width and the second end including a second width; A second pattern includes a third end and a fourth end, wherein the third end and the second end are disposed opposite to each other along a first direction and are separated from each other, the third end includes a second width, the fourth end includes a third width, the third width being smaller than the second width, and the second width being smaller than the first width; and A stitching pattern is located between the second end and the third end, wherein the first pattern and the second pattern have a first color for output to a first mask, and the stitching pattern has a second color for output to a second mask.

12. The layout of the circuit structure as claimed in claim 11, wherein the first mask and the second mask are used for a dual patterning process, and the total area of ​​the first pattern, the second pattern and the stitching pattern is greater than the area of ​​a development barrier in the dual patterning process.

13. The layout of the circuit structure as claimed in claim 11, wherein the width of the first pattern gradually decreases from the first end to the second end, and the width of the second pattern gradually decreases from the third end to the fourth end.

14. The layout of the circuit structure as claimed in claim 11, wherein the ratio of the third width to the first width is less than 1 / 100.

15. The layout of the circuit structure as claimed in claim 14, wherein the third width is less than 40 nm and the first width is greater than 4000 nm.

16. The layout of the circuit structure as claimed in claim 11, wherein the ratio of the area of ​​the second pattern to the area of ​​the first pattern is less than 1 / 2000.

17. The layout of the circuit structure as claimed in claim 11, wherein the stitching pattern partially overlaps with the second end and the third end.

18. The layout of the circuit structure as claimed in claim 11, wherein the edges of the second end, the stitching pattern, and the third end are aligned along the first direction.

19. The circuit layout as described in claim 11, further comprising: A plurality of third patterns having the first color, wherein the stitching pattern is adjacent to one of the plurality of third patterns and the spacing between them is less than a minimum spacing between the plurality of third patterns.

20. The circuit layout of claim 11, further comprising: A plurality of fourth patterns having the second color, wherein the stitching pattern is adjacent to one of the plurality of fourth patterns and the spacing between them is greater than a minimum spacing between the plurality of fourth patterns.

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