Semiconductor structure and integrated assembly

Abstract

The embodiment of the invention provides a semiconductor structure. The semiconductor structure comprises a first surface and a second surface which are opposite; the first connecting pad and the second connecting pad are arranged on the first surface; the third connecting pad, the fourth connecting pad and the fifth connecting pad are arranged on the second surface; the memory cell region is arranged between the first surface and the second surface, the memory cell region comprises a first semiconductor device and a second semiconductor device which are arranged along a first direction, the first connecting pad and the fourth connecting pad are connected with the first semiconductor device, and the second connecting pad and the fifth connecting pad are connected with the second semiconductor device; the memory cell region further includes a first connection portion connected to at least one of the first semiconductor device and the second semiconductor device, the first connection portion being connected to the third connection pad. The semiconductor structure provided by the embodiment of the invention has a higher integration level.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor structure and integrated assembly. Background Technology

[0002] Memory is used to store data in modern computing architectures. Dynamic random access memory (DRAM) has the advantages of simple structure, low cost and high speed, and is widely used in personal computers, servers and various electronic devices as main memory.

[0003] As data continues to grow rapidly, the increase in DRAM density is slowing down, leading to a widening gap between memory demand and DRAM capacity. Increasing packaging density to improve integration and thus obtain higher storage capacity has become an important goal of integrated circuit manufacturing at this stage, and memory with tight packaging urgently needs to be developed. Summary of the Invention

[0004] This disclosure provides a semiconductor structure with higher integration.

[0005] The technical spirit of this disclosure aims to solve problems not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0006] An exemplary embodiment of this disclosure provides a semiconductor structure including a first surface and a second surface opposite to each other; a first connection pad and a second connection pad disposed on the first surface; a third connection pad, a fourth connection pad, and a fifth connection pad disposed on the second surface; a memory cell region disposed between the first surface and the second surface, the memory cell region including a first semiconductor device and a second semiconductor device arranged along a first direction, the first connection pad and the fourth connection pad connecting the first semiconductor device, the second connection pad and the fifth connection pad connecting the second semiconductor device, the memory cell region further including a first connection portion connected to at least one of the first semiconductor device and the second semiconductor device, the first connection portion connecting to the third connection pad.

[0007] According to an example embodiment of this disclosure, in a direction parallel to the first surface, the maximum width of at least one of the first connecting pad and the second connecting pad is greater than the maximum width of at least one of the third connecting pad, the fourth connecting pad, and the fifth connecting pad.

[0008] According to one example embodiment of this disclosure, in a direction parallel to the first surface, the minimum spacing between the first connecting pad and the second connecting pad is greater than the minimum spacing between the third connecting pad, the fourth connecting pad, and the fifth connecting pad.

[0009] According to an example embodiment of the present disclosure, the semiconductor structure further includes: an interconnect layer disposed adjacent to a first surface; a wiring layer disposed adjacent to a second surface; a first connection pad and a second connection pad being connected to a first semiconductor device and a second semiconductor device respectively via the interconnect layer; a third connection pad being connected to a first connection portion via the wiring layer; and a fourth connection pad and a fifth connection pad being connected to the first semiconductor device and the second semiconductor device respectively via the wiring layer, wherein the metal density of the wiring layer is greater than the metal density of the interconnect layer.

[0010] According to an example embodiment of the present disclosure, the semiconductor structure further includes a second connection portion and a third connection portion, the second connection portion being connected to a first semiconductor device, the third connection portion being connected to a second semiconductor device, a first connection pad and a fourth connection pad being connected to the second connection portion, the second connection pad and a fifth connection pad being connected to the third connection portion, the second connection portion, the third connection portion and the first connection portion being isolated from each other, and the wiring layer including a first wiring layer, the first connection portion, the second connection portion and the third connection portion being connected to the first wiring layer.

[0011] According to an example embodiment of the present disclosure, a sixth connecting pad is further provided on the first surface, and a seventh connecting pad is further provided on the second surface, with the sixth connecting pad connecting to the seventh connecting pad.

[0012] According to an example embodiment of the present disclosure, the semiconductor structure further includes a fourth connection portion located in the memory cell region and in the region between the first semiconductor device and the second semiconductor device. An eighth connection pad is also disposed on the first surface, and a ninth connection pad is also disposed on the second surface. The fourth connection portion connects the eighth connection pad and the ninth connection pad.

[0013] According to an example embodiment of the present disclosure, the wiring layer further includes a second wiring layer, and the fourth connection portion is connected to the second wiring layer.

[0014] According to an example embodiment of this disclosure, another semiconductor structure is provided, including: a first surface and a second surface opposite to each other; a first connection pad and a second connection pad disposed on the first surface; a third connection pad, a fourth connection pad, and a fifth connection pad disposed on the second surface; a memory cell region disposed between the first surface and the second surface, including a first memory cell array and a second memory cell array arranged at intervals, the first memory cell array including a plurality of first semiconductor devices arranged along a first direction, and the second memory cell array including a plurality of second semiconductor devices arranged along the first direction; the first connection pad and the fourth connection pad are connected to the first semiconductor devices, and the second connection pad and the fifth connection pad are connected to the second semiconductor devices; the memory cell region further includes a first connection portion, the first connection portion being connected to at least one of the first semiconductor device and the second semiconductor device, and the third connection pad being connected to the first connection portion.

[0015] According to an example embodiment of the present disclosure, a first memory cell array includes a second connection portion, a second memory cell array includes a third connection portion, the second connection portion is connected to a first semiconductor device, the third connection portion is connected to a second semiconductor device, a first connection pad and a fourth connection pad are connected to the second connection portion, and the second connection pad and a fifth connection pad are connected to the third connection portion.

[0016] According to an exemplary embodiment of this disclosure, a plurality of first semiconductor devices arranged along a first direction form a plurality of first sub-rows. Each first sub-row includes a first sub-row connector connecting the plurality of first semiconductor devices along the first direction. A plurality of second semiconductor devices arranged along the first direction form a second sub-row. Each second sub-row includes a second sub-row connector connecting the plurality of second semiconductor devices along the first direction. A first connecting pad and a fourth connecting pad are connected to the first sub-row connector via a second connecting pad. A second connecting pad and a fifth connecting pad are connected to the second sub-row connector via a third connecting pad. The first sub-row connector and the second sub-row connector extend along the first direction and are spaced apart from each other. The first memory cell array further includes a plurality of first semiconductor devices arranged along a second direction, and the second memory cell array further includes a plurality of second semiconductor devices arranged along a second direction. The plurality of first semiconductor devices arranged along the second direction form a plurality of first sub-rows, and the plurality of second semiconductor devices arranged along the second direction form a plurality of second sub-rows. Each first sub-row includes a first sub-row connection portion connecting the plurality of first semiconductor devices in the second direction, and each second sub-row includes a second sub-row connection portion connecting the plurality of second semiconductor devices in the second direction. The first sub-row connection portion and the second sub-row connection portion extend and are arranged along the second direction. The first connection portion is connected to at least one of the first sub-row connection portion and the second sub-row connection portion.

[0017] According to an example embodiment of the present disclosure, the first storage cell array includes a plurality of first sub-column connection portions and a plurality of first sub-row connection portions, the number of first sub-column connection portions being greater than the number of first sub-row connection portions; the second storage cell array includes a plurality of second sub-column connection portions and a plurality of second sub-row connection portions, the number of second sub-column connection portions being greater than the number of second sub-row connection portions.

[0018] According to an example embodiment of the present disclosure, the memory cell region further includes a third sub-column connection portion extending along a first direction, the third sub-column connection portion extending from the first memory cell array to the second memory cell array, the third sub-connection portion connecting a plurality of first semiconductor devices and a plurality of second semiconductor devices extending along the first direction.

[0019] According to an example embodiment of the present disclosure, both the first semiconductor device and the second semiconductor device include a gate and a drain. A first sub-row connection portion is connected to the gate of the first semiconductor device, a second sub-row connection portion is connected to the gate of the second semiconductor device, a first sub-column connection portion is connected to the drain of the first semiconductor device, a second sub-column connection portion is connected to the drain of the second semiconductor device, and a third sub-column connection portion is connected to the drain of both the first semiconductor device and the second semiconductor device.

[0020] According to an example embodiment of the present disclosure, a sixth connecting pad is further provided on the first surface, and a seventh connecting pad is further provided on the second surface, with the sixth connecting pad connecting to the seventh connecting pad.

[0021] An integrated assembly according to an example embodiment of the present disclosure includes: a first semiconductor structure, the first semiconductor structure including a first surface, the first surface having a first connection pad and a second connection pad disposed thereon, the first semiconductor structure further including a memory cell region disposed below the first surface, the memory cell region including a first semiconductor device and a second semiconductor device, the first connection pad connecting the first semiconductor device, the second connection pad connecting the second semiconductor device, and a first connection portion between the first semiconductor device and the second semiconductor device; a second semiconductor structure, the second semiconductor structure having a first bonding surface bonded to the first surface of the first semiconductor structure, the second semiconductor structure including a third semiconductor device and a fourth semiconductor device, the third semiconductor device and the first semiconductor device being connected to the first connection pad via the first bonding surface, the fourth semiconductor device and the second semiconductor device being connected to the second connection pad via the first bonding surface, the second semiconductor structure further having a common connection portion, the common connection portion connecting at least the third semiconductor device or the fourth semiconductor device; the first semiconductor structure further includes a second surface, the second surface having a third connection pad, a fourth connection pad, a fifth connection pad, and a sixth connection pad disposed thereon, the third connection pad connecting to the first connection portion, the fourth connection pad connecting to the first connection pad, the fifth connection pad connecting to the second connection pad, and the sixth connection pad connecting to the common connection portion.

[0022] According to an example embodiment of the present disclosure, the first semiconductor structure further includes an interconnect layer located between the first surface and the second surface and disposed adjacent to the first surface, and the second semiconductor structure further includes a connection layer disposed adjacent to the first bonding surface, and the third semiconductor device and the fourth semiconductor device are interconnected with the first semiconductor device and the second semiconductor device through the connection layer.

[0023] According to an example embodiment of the present disclosure, a third semiconductor structure is further included, one surface of which is bonded to a second surface of the first semiconductor structure. The third semiconductor structure includes a fifth semiconductor device. The first semiconductor structure also includes a wiring layer disposed adjacent to the second surface. The third semiconductor structure includes a wiring layer disposed adjacent to the second surface. The first semiconductor device, the second semiconductor device, the third semiconductor device, and the fourth semiconductor device are interconnected with the fifth semiconductor device through the wiring layer.

[0024] The semiconductor structure provided in this embodiment has connection channels on both the first and second surfaces that connect to the first and second semiconductor devices. This design allows for more flexible layout and design of the semiconductor devices in the memory cell array, further reducing the area of ​​the memory cell region and providing a more compact semiconductor structure. Attached Figure Description

[0025] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure.

[0026] Figures 1-4 This is a schematic diagram of a semiconductor structure provided in some embodiments of this disclosure;

[0027] Figure 5 This is a schematic diagram of a semiconductor structure provided in some embodiments of this disclosure;

[0028] Figure 6 This is a schematic diagram of another semiconductor structure provided in some embodiments of this disclosure;

[0029] Figure 7 This is a schematic diagram of the structure of an integrated assembly provided in some embodiments of this disclosure;

[0030] The accompanying drawings have illustrated specific embodiments of the present disclosure, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the present disclosure in any way, but rather to illustrate the concepts of the present disclosure to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0031] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are merely for explaining the relevant disclosure and not for limiting the disclosure. It should also be noted that, for ease of description, only relevant parts are shown in the accompanying drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to limit this disclosure. In the following description, references to "some embodiments" describe a subset of all possible embodiments; however, it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict. It should be noted that the terms "first, second, third" involved in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described.

[0032] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0033] Figure 1 A semiconductor structure 1a is provided, which includes a first surface A and a second surface B opposite to each other. The first surface A is provided with a first connection pad 110 and a second connection pad 120, and the second surface B is provided with a third connection pad 210, a fourth connection pad 220 and a fifth connection pad 230.

[0034] The first surface A and the second surface B can be the upper and lower surfaces of the semiconductor structure 1a for bonding with other semiconductor structures, or they can be independent upper and lower surfaces of the semiconductor structure 1a. The first connecting pad 110 and the second connecting pad 120 can have a portion extending below the first surface A and a surface portion exposed to the first surface A. The third connecting pad 210, the fourth connecting pad 220, and the fifth connecting pad 230 can have a portion extending below the second surface B and a surface portion exposed to the second surface B. In some embodiments, the first connecting pad 110 and the second connecting pad 120 can be connecting pads for bonding with other semiconductor structures, and the third connecting pad 210, the fourth connecting pad 220, and the fifth connecting pad 230 can be connecting pads for bonding with other semiconductor structures.

[0035] In some embodiments, the first connecting pad 110, the second connecting pad 120, the third connecting pad 210, the fourth connecting pad 220, and the fifth connecting pad 230 can be conductive pads of the same material type, for example, conductive pads containing copper, aluminum, or other metals or alloys thereof. In other embodiments, the first connecting pad 110 and the second connecting pad 120 can be conductive pads of the same material type, and the third connecting pad 210, the fourth connecting pad 220, and the fifth connecting pad 230 can be conductive pads of the same material type, but the first connecting pad 110 is different from the third connecting pad 210. For example, the first connecting pad 110 is a copper-containing conductive pad, and the third connecting pad 210 is an aluminum-containing conductive pad.

[0036] In some embodiments, the first connecting pad 110, the second connecting pad 120, the third connecting pad 210, the fourth connecting pad 220, and the fifth connecting pad 230 are functional connecting pads, and the first surface A and the second surface B are also provided with non-functional connecting pads. The depth of the non-functional connecting pads extending below the first surface A and the second surface B is less than the extension depth of each functional connecting pad, such as... Figure 1 As shown. In some embodiments, non-functional connection pads may be disposed on only one surface of the semiconductor structure 1a, for example, only on the second surface B, while the connection pads disposed on the first surface A are all functional connection pads. In some embodiments, functional and non-functional connection pads are evenly distributed on each surface.

[0037] In some embodiments, taking a direction parallel to the first surface as a cross-section, the widths of the first connecting pad 110 and the second connecting pad 120 in this cross-section may be the same or substantially the same; in some embodiments, the widths of the first connecting pad 110 and the second connecting pad 120 in this cross-section may be different, for example, the width of the first connecting pad 110 may be greater than the width of the second connecting pad 120, and the width of the second connecting pad 120 may also be greater than the width of the first connecting pad 110. Similarly, the widths of the third connecting pad 210, the fourth connecting pad 220, and the fifth connecting pad 230 may also be the same or different from each other. In some embodiments, the maximum width of at least one of the first connecting pad 110 and the second connecting pad 120 is greater than the maximum width of at least one of the third connecting pad 210, the fourth connecting pad 220, and the fifth connecting pad 230.

[0038] In some embodiments, a cross section is taken along a direction parallel to the first surface, on which the first connecting pad 110 and the second connecting pad 120 have a minimum spacing between each other, the third connecting pad 210, the fourth connecting pad 220 and the fifth connecting pad 230 have a minimum spacing between each other, and the minimum spacing between the first connecting pad 110 and the second connecting pad is greater than the minimum spacing between each of the third connecting pad 210, the fourth connecting pad 220 and the fifth connecting pad 230.

[0039] In some embodiments, the minimum spacing between the first connecting pad 110 and the second connecting pad 120 includes the width of the first connecting pad 110 and the distance between the outer edges of the first connecting pad 110 and the second connecting pad 120. In other embodiments, the minimum spacing between the first connecting pad 110 and the second connecting pad 120 is the distance between the outer edges of the first connecting pad 110 and the second connecting pad 120.

[0040] The semiconductor structure 1a further includes a memory cell region 3, which is disposed between the first surface A and the second surface B. The memory cell region 3 includes a first semiconductor device 310 and a second semiconductor device 320, which are arranged along a first direction. The first direction can be parallel to the first surface A or perpendicular to the first surface A. The first semiconductor device 310 and the second semiconductor device 320 are memory devices, such as DRAM memory cells or NAND memory cells.

[0041] The storage cell region 3 also includes a first connection portion 30, which is used to connect at least one of the first semiconductor device 310 and the second semiconductor device 320. For example, in some embodiments, the first connection portion 30 connects both the first semiconductor device 310 and the second semiconductor device 320 simultaneously; that is, the first connection portion 30 can be a common connection portion between the first semiconductor device 310 and the second semiconductor device 320, such as... Figure 1 As shown. At this time, the first semiconductor device 310 and the second semiconductor device 320 are connected to the third connecting pad 210 via the first connecting portion 30. In some embodiments, the first direction is a direction perpendicular to the first connecting portion.

[0042] In some embodiments, the first connection portion 30 may also be connected separately to the first semiconductor device 310 or separately to the second semiconductor device 320, such as... Figure 2 As shown, Figure 2 A semiconductor structure 1a is shown in which a first connection portion 30 is individually connected to a first semiconductor device 310, and a second semiconductor device 320 is individually connected to another connection portion 30'. In this case, the first semiconductor device 310 is connected to a third connection pad 210 via the first connection portion 30, and the second semiconductor device 320 is connected to another connection pad 210' on the second surface B via the other connection portion 30'.

[0043] The region between the first semiconductor device 310 and the second semiconductor device 320 is a region with an insulating dielectric layer, and no semiconductor device may be disposed in this region. The first connection portion 30 may be located in the region between the first semiconductor device 310 and the second semiconductor device 320, or it may be located on one side of the first semiconductor device 310 or the second semiconductor device 320. The first connection portion 30 and the other connection portion 30' may be located on one side of the first semiconductor device 310 or the second semiconductor device 320, or they may be located between the first semiconductor device 310 and the second semiconductor device 320. The first semiconductor device 310 also has an end connected to the first connection pad 110 and the fourth connection pad 220, and the second semiconductor device 320 also has an end connected to the second connection pad 120 and the fifth connection pad 230. In the semiconductor structure 1a, the first semiconductor device 310 and the second semiconductor device 320 form connection channels through the connection pads disposed on the first surface A and the first surface B, respectively. The additional connection channels allow for more flexible layout and design of the first semiconductor device 310 and the second semiconductor device 320, thereby reducing the area of ​​the memory cell region and providing a more compact semiconductor structure.

[0044] In some embodiments, the first connection portion 30 is disposed relatively closer to the second surface B, see [reference] Figure 3 ,and Figure 1 and Figure 2 The difference is, Figure 3 In the semiconductor structure 1a shown, the first connection portion 30 is relative to Figure 1 and Figure 2 The first connection portion 30 is disposed closer to the second surface B. The first connection portion 30 connects the first semiconductor device 310 and the second semiconductor device 320, and is located in the area near the bottom of the memory cell region 3.

[0045] In some embodiments, the first semiconductor device 310 and the second semiconductor device 320 may be DRAM memory devices. Figures 1-3A schematic diagram of the structure of the first semiconductor device 310 and the second semiconductor device 320 using the same type of DRAM memory cell is shown. The basic units include transistors and capacitors. The transistor in the first semiconductor device 310 includes a source 3102 and a drain 3101, which are arranged vertically. A channel region exists between the source 3102 and the drain 3101, and a gate 3103 is disposed around the channel region. Similarly, the transistor in the second semiconductor device 320 includes a source 3202 and a drain 3201 arranged vertically, and a channel region located between the source 3202 and the drain 3201. A gate 3203 is disposed around the channel region. The capacitor in the first semiconductor device 310 includes an electrode portion 3104 connected to the source 3102, and the capacitor in the second semiconductor device 320 also includes an electrode portion 3204 connected to the source 3202; the first semiconductor device 310 further includes an electrode portion 3105, and the electrode portions 3104 and 3105 constitute the upper and lower electrodes of the capacitor in the first semiconductor device 310; the second semiconductor device 320 further includes an electrode portion 3205, and the electrode portions 3204 and 3205 constitute the upper and lower electrodes of the capacitor in the second semiconductor device 320. In some embodiments, such as Figure 1 As shown, the first connection portion 30 connects the gate 3103 of the first semiconductor device 310 and the gate 3203 of the second semiconductor device 320; in some embodiments, such as Figure 2 As shown, the first connection portion 30 is connected to the gate 3103 of the first semiconductor device 310, and the connection portion 30' is connected to the gate 3203 of the second semiconductor device 320; in some embodiments, such as Figure 3 As shown, the first connection portion 30 connects the drain 3101 of the first semiconductor device 310 and the drain 3201 of the second semiconductor device 320. In some embodiments, the connection portion connected to the gate can be referred to as a word line, and the connection portion connected to the drain can be referred to as a bit line.

[0046] See also Figures 1-3In some embodiments, the semiconductor structure 1a further includes an interconnect layer 1 disposed adjacent to the first surface A and a wiring layer 2 disposed adjacent to the second surface B. The first connection pad 110 and the second connection pad 120 are respectively connected to the first semiconductor device 310 and the second semiconductor device 320 through the interconnect layer 1, the fourth connection pad 220 and the fifth connection pad 230 are respectively connected to the first semiconductor device 310 and the second semiconductor device 320 through the wiring layer 2, and the third connection pad 210 is connected to the first connection portion 30 through the wiring layer. Interconnect layer 1 comprises at least one layer of conductive interconnects, and wiring layer 2 comprises at least one layer of conductive wiring. For example, interconnect layer 1 may include two layers of conductive interconnects, interconnected by interlayer vias, and the conductive interconnects are interconnected with the first connecting pad 110 and the second connecting pad 120 by interlayer vias. Wiring layer 2 may include two or more conductive wiring layers, such as four conductive wiring layers, interconnected by interlayer vias, and the third connecting pad 210, the fourth connecting pad 220, and the fifth connecting pad 230 are interconnected with the conductive wiring layers by interlayer vias. In some embodiments, the metal density in wiring layer 2 is greater than the metal density in interconnect layer 1. Metal density refers to the volume or mass percentage of a metal component within a specific volume; that is, the metal density of the interconnect layer refers to the volume or mass percentage of the metal interconnects in the interconnect layer, and the metal density of the wiring layer refers to the volume or mass percentage of the metal wiring in the wiring layer. In these embodiments, by providing interconnect layers and wiring layers with different metal densities on opposite sides of the memory cell region, not only can the interconnect density requirements on different surfaces be met, but the warpage of the semiconductor structure can also be improved, reducing the deformation between the middle and edge portions of the first and second surfaces of the semiconductor structure, and enabling subsequent packaging integration.

[0047] In the embodiments of this disclosure, there is no clear distinction between the interconnect layer 1, the storage cell region 3, and the wiring layer 3; there may be overlapping areas between them. This disclosure does not imply... Figures 1 to 3 The structures shown are limited.

[0048] See also Figures 1 to 3 The semiconductor structure 1a further includes a second connection portion 31 and a third connection portion 32. The second connection portion 31 is connected to one end of the first semiconductor device 310, the third connection portion 32 is connected to one end of the second semiconductor device 320, and the first connection portion 30 is connected to the other end of the first semiconductor device 310 and the second semiconductor device 320. The second connection portion 31 can be a common connection portion of one end of the first semiconductor device 310, and the third connection portion 32 can be a common connection portion of one end of the second semiconductor device 320. In some embodiments, such as Figure 1As shown, the first connection portion 30 is connected to both the gate of the first semiconductor device 310 and the gate of the second semiconductor device 320, the second connection portion 31 is connected to the drain 3101 of the first semiconductor device 310, and the third connection portion 32 is connected to the drain 3201 of the second semiconductor device 320; in some embodiments, such as Figure 2 As shown, the first connection portion 30 is connected to the gate 3103 of the first semiconductor device 310, the second connection portion 31 is connected to the drain 3101 of the first semiconductor device 310, and the third connection portion 32 is connected to the drain 3201 of the second semiconductor device 320; in some embodiments, such as Figure 3 As shown, the first connection portion 30 is connected to the drain 3101 of the first semiconductor device 310 and the drain 3201 of the second semiconductor device 320. The second connection portion 31 is connected to the gate 3103 of the first semiconductor device 310, and the third connection portion 32 is connected to the gate 3203 of the second semiconductor device 320. In this case, the first connection portion 30 is disposed closer to the first surface B than the second connection portion 31 and the third connection portion 32. The connection relationship between each connection portion and each semiconductor device is not limited to this. In other embodiments, other connection methods may be used. In some embodiments, the first direction is a direction parallel to the second connection portion 31 and the second connection portion 32.

[0049] The first connecting portion 30, the second connecting portion 31, and the third connecting portion 32 are isolated from each other, that is, an insulating dielectric layer is provided between each connecting portion to prevent short circuits between the connecting portions. The second connecting portion 31 is connected to the first connecting pad 110 to realize the connection between the first semiconductor device 310 and the first connecting pad 110, and the third connecting portion 32 is connected to the second connecting pad 120 to realize the connection between the second semiconductor device 320 and the second connecting pad 120.

[0050] In some embodiments, the second connection portion 31 is interconnected with the first connection pad 110 via the interconnect structure 34, and the third connection portion 32 is interconnected with the second connection pad 120 via the interconnect structure 35. The interconnect structure 34 and the interconnect structure 35 may be conductive structures that vertically pass through the memory cell region 3, or they may be conductive structures interconnected through multilayer wiring.

[0051] See also Figures 1 to 3 The wiring layer 2 also includes a first wiring layer 21 disposed adjacent to the storage cell region 3, and a first connection portion 30, a second connection portion 31, and a third connection portion 32 connected to the first wiring layer 21. The first wiring layer 21 and each connection portion are interconnected through interlayer vias. In some embodiments, the height of the interlayer via connecting the first wiring layer 21 and the first connection portion 30 is greater than the height of the interlayer via connecting the first wiring layer 21 and the second connection portion 31 or the third connection portion 32.

[0052] In some embodiments, the second connecting portion 31 and the third connecting portion 32 have different lengths in a direction parallel to the first surface A.

[0053] See also Figures 1 to 3 In some embodiments, a sixth connection pad 130 is further disposed on the first surface A, and a seventh connection pad 240 is further disposed on the second surface B, with the sixth connection pad 130 and the seventh connection pad 240 connected together. In some embodiments, the sixth connection pad 130 and the seventh connection pad 240 are connected via an interconnect structure 36 that penetrates the memory cell region 3. In some embodiments, the interconnect structure 36 may be a multilayer metal wire disposed in the memory cell region 3. In some embodiments, the interconnect structure 36 is connected to a first wiring layer 21, and the seventh connection pad 240 is connected to the interconnect structure 36 via the first wiring layer 21.

[0054] See also Figures 1 to 3 In some embodiments, the memory cell region 3 further includes a fourth connection portion 33, which is located in the region between the first semiconductor device 310 and the second semiconductor device 320. The region between the first semiconductor device 310 and the second semiconductor device 320 may be a region with an insulating dielectric layer, and this region does not contain any semiconductor devices. In some embodiments, the fourth connection portion 33 is disposed closer to the interconnect layer 1 than the first connection portion 30. In other embodiments, the top surface of the fourth connection portion 33 is higher than the top surfaces of the source electrode 3102 of the first semiconductor device 310 and the source electrode 3202 of the second semiconductor device 320, but lower than the top surfaces of the electrode portions 3104 and 3204. In still other embodiments, the top surface of the fourth connection portion 33 is not higher than the top surfaces of the source electrode 3102 of the first semiconductor device 310 and the source electrode 3202 of the second semiconductor device 320.

[0055] In some embodiments, the electrode portion 3104 of the first semiconductor device 310 and / or the electrode portion 3204 of the second semiconductor device 320 can be directly connected to the source electrode 3102 of the first semiconductor device 310 and / or the source electrode 3202 of the second semiconductor device 320, or interconnected via contact plugs. In some embodiments, the material of the electrode portion 3104 of the first semiconductor device 310 and / or the electrode portion 3204 of the second semiconductor device 320 includes polycrystalline silicon, metals (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), metal compounds (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or silicides (e.g., cobalt silicide, nickel silicide, etc.). The material of the source electrode 3102 of the first semiconductor device 310 and / or the source electrode 3202 of the second semiconductor device 320 includes polycrystalline silicon, doped single-crystal silicon, or metal silicides, etc.

[0056] In some embodiments, the fourth connection portion 33 is formed in the same process step as the electrode portion 3104 of the first semiconductor device 310 and / or the electrode portion 3204 of the second semiconductor device 320, and is isolated from each other. In some embodiments, the fourth connection portion 33 is made of the same material as the electrode portions 3104 and 3204.

[0057] In some embodiments, the fourth connection portion 33 is formed in the same process step as the source 3102 of the first semiconductor device 310 and / or the source 3202 of the second semiconductor device 320, and is isolated from each other. In some embodiments, the fourth connection portion 33 has the same material as the source 3102 and the source 3202, for example, a silicon-containing metal compound.

[0058] In some embodiments, the fourth connection portion 33 may be formed during the process of forming the contact plug.

[0059] In some embodiments, the first surface A is further provided with an eighth connecting pad 140, and the second surface B is further provided with a ninth connecting pad 250. The eighth connecting pad 140 and the ninth connecting pad 250 are connected to the fourth connecting portion 33, thereby forming a passage from the first surface A to the second surface B. In some embodiments, such as Figure 1 and Figure 2 As shown, the fourth connection portion 33 is connected to the eighth connection pad 140 and the ninth connection pad 250 via the interconnection structure 39. In some embodiments, such as Figure 3 As shown, due to Figure 3 and Figure 1 and Figure 2 The interconnection structure 39 connecting the fourth connector 33 and the ninth connector pad 250, which employs a different wiring design, is not shown in this cross section.

[0060] In these embodiments, by providing a fourth connection portion in the region between the first semiconductor device and the second semiconductor device, the process of forming the connection channel between the eighth connection pad 140 and the ninth connection pad 250 can be simplified, reducing process difficulty and improving yield.

[0061] The first semiconductor device 310 and the second semiconductor device 320 further include a connecting portion 37 and a connecting portion 38, respectively. The connecting portions 37 and 38 may be located above the first semiconductor device 310 and the second semiconductor device 320, respectively, and are connected to the electrode portion 3105 in the first semiconductor device 310 and the electrode portion 3205 in the second semiconductor device 320, respectively. The connecting portions 37 and 38 may be connected to each other or not connected. In some embodiments, the fourth connecting portion 33 is not connected to the connecting portion 37 or the connecting portion 38. In other embodiments, the fourth connecting portion is connected to the first semiconductor device 310 and the second semiconductor device 320 respectively through the connecting portions 37 and 38, or is simultaneously connected to the first semiconductor device 310 and the second semiconductor device 320 through the connecting portions 37 and 38.

[0062] In some embodiments, the semiconductor structure 1a further includes a fifth connection portion 40, such as Figure 4 As shown, the fifth connection portion 40 is disposed closer to the interconnect layer 1 than the fourth connection portion 40. The fifth connection portion 40 is connected to the fourth connection portion 33 through the interconnect structure 39. That is, a conductive channel is formed between the eighth connection pad 140 and the ninth connection pad 250, including the fourth connection portion 33 and the fifth connection portion 40. In some embodiments, the fifth connection portion 40 may not be connected to the connection portions 37 and 38, may be connected to the connection portions 37 and 38 alone, or may be connected to the connection portions 37 and 38 simultaneously. The fifth connection portion 40 may be located in the region between the connection portions 37 and 38, and the fifth connection portion 40 may be fabricated using the same metalworking process as the connection portions 37 and 38.

[0063] In some embodiments, wiring layer 2 further includes a second wiring layer 22, which is disposed closer to the second surface B than the first wiring layer 21. A fourth connection portion 33 is connected to the second wiring layer 22 via an interconnect structure 39. The fourth connection portion 33 can be directly connected to the second wiring layer 22 via the interconnect structure 39, or it can be connected to the second wiring layer 22 via the first wiring layer 21.

[0064] The first wiring layer 21 and the second wiring layer 22 can be conductive layers disposed in an insulating dielectric layer. Signal transmission between the first wiring layer 21 and the second wiring layer 22 is achieved through via structures at specific locations. In some embodiments, the first wiring layer 21 and the second wiring layer 22 are formed using metal fabrication processes, such as damascus steel. The first wiring layer 21 and the second wiring layer 22 can be one or more combinations of metals such as copper, copper alloys, tungsten, tungsten alloys, aluminum, and aluminum alloys.

[0065] The wiring layer 2 also includes other conductive wiring layers disposed between the second wiring layer 22 and the second surface B. The number of other conductive wiring layers can be 1, 2, 3, 4 or other numbers.

[0066] In some embodiments, the memory cell region in the semiconductor structure 1a includes a plurality of first semiconductor devices 310 and a plurality of second semiconductor devices 320, combined with Figures 1-4 as well as Figure 5 A plurality of first semiconductor devices 310 constitute a first memory cell array 4, and a plurality of second semiconductor devices 320 constitute a second memory cell array 5. The first memory cell array 4 and the second memory cell array 5 are arranged at intervals. The first memory cell array 4 includes a plurality of first semiconductor devices 310 arranged along a first direction and a plurality of first semiconductor devices 310 arranged along a second direction. The second memory cell array 5 includes a plurality of second semiconductor devices 320 arranged along the first direction and a plurality of second semiconductor devices 320 arranged along the second direction. The first direction and the second direction are perpendicular to each other, and both the first direction and the second direction can be parallel to the first surface A and the second surface B.

[0067] In some embodiments, the first memory cell array 4 includes a first connection portion 30 connected to a plurality of first semiconductor devices 310, the first connection portion 30 being connected to one end of the plurality of first semiconductor devices in a second direction. In the first direction, a second connection portion 31 is provided between the plurality of first semiconductor devices 310 in the first memory cell array 4, the second connection portion 31 being connected to one end of the plurality of first semiconductor devices 310 in the first direction. Similarly, in the second memory cell array 5, one end of a plurality of second semiconductor devices 320 in the second direction is connected to another connection portion 30', and one end of a plurality of second semiconductor devices 320 in the first direction is connected to a third connection portion 32.

[0068] In some embodiments, see Figure 3 The first connection portion 30 can also be simultaneously connected to one end of a plurality of first semiconductor devices 310 and one end of a plurality of second semiconductor devices 320 in the first direction. In this case, the second connection portion 31 and the third connection portion 33 are respectively connected to the plurality of first semiconductor devices 310 and the plurality of second semiconductor devices 320 in the second direction. The connection relationship between the first connection portion 30, the second connection portion 31, and the third connection portion 32 and the semiconductor devices in each memory cell array is not limited to... Figure 5 The situation shown.

[0069] In the above embodiments, a plurality of first semiconductor devices 310 and a plurality of second semiconductor devices 320 respectively form connection channels extending to the second surface B through a first connection portion 30 and a third connection pad 210, and a connection portion 30' and a connection pad 210'. The plurality of first semiconductor devices 310 and a plurality of second semiconductor devices 320 also form connection channels extending from the first surface A to the second surface B through a second connection portion 31 and a third connection portion 32, respectively. For example, the second connection portion 31 is connected to the first connection pad 110 in the first surface A and the fourth connection pad 220 in the second surface B, establishing a connection channel extending between the first semiconductor devices 310 and the second surface B. The third connection portion 32 is connected to the second connection pad 120 in the first surface A and the fifth connection pad 230 in the second surface B, establishing a connection channel extending between the second semiconductor devices 320 and the first surface A and the second surface B. This design allows for more flexible layout and design of the semiconductor devices in the memory cell array, further reducing the area of ​​the memory cell region and providing a more compact semiconductor structure.

[0070] See also Figure 5 In the first memory cell array 4, multiple first semiconductor devices 310 arranged along a first direction form multiple first sub-columns 42. A common end of each first semiconductor device 310 in each first sub-column 42 is connected to a first sub-column connection portion 43. A second connection portion 31 is connected to the first sub-column connection portion 43, thus connecting the second connection portion 31 to the first semiconductor device 310. In the second memory cell array 5, multiple second semiconductor devices 320 arranged along a first direction form multiple second sub-columns 52. A common end of each second semiconductor device 320 in each second sub-column 52 is connected to a second sub-column connection portion 53. A third connection portion 32 is connected to the second sub-column connection portion 53, thus connecting the third connection portion 32 to the second semiconductor device 320. In some embodiments, the first sub-column connection portion 43 and the second sub-column connection portion 53 are isolated from each other. The second connection portion 31 and the second connection portion 32 can be respectively disposed on the same side of the first memory cell array 4 and the second memory cell array 5, or they can be respectively disposed on different sides of the first memory cell array 4 and the second memory cell array 5. The second connecting portion 31 and the second connecting portion 32 can be integrally formed with the first sub-row connecting portion 43 and the second sub-row connecting portion 53, respectively, or they can be connecting structures formed by separate processes and connected to the first sub-row connecting portion 43 and the second sub-row connecting portion 53. In some embodiments, the second connecting portion 31 and the second connecting portion 32 can be the end regions of the first sub-row connecting portion 43 and the second sub-row connecting portion 53, respectively.

[0071] Multiple first semiconductor devices 310 arranged along a second direction form multiple first sub-rows 44. A common end of each first semiconductor device 310 in each first sub-row 42 is connected to a first sub-row connection portion 45. In the second memory cell array 5, multiple second semiconductor devices 320 arranged along the second direction form multiple second sub-rows 54. A common end of each second semiconductor device 320 in each second sub-row 54 is connected to a second sub-row connection portion 55. A first connection portion 30 is connected to at least the first sub-row connection portion 45 or the second sub-row connection portion 55. In some embodiments, the first connection portion 30 may be a structure integrally formed with the first sub-row connection portion 45 and the second sub-row connection portion 55, or it may be a connection structure connected to the first sub-row connection portion 45 and / or the second sub-row connection portion 55 using a separate process. In some embodiments, the first connection portion may be the end region of the first sub-row connection portion 45 and / or the second sub-row connection portion 55.

[0072] In some embodiments, the first storage cell array 4 includes a plurality of first sub-column connection portions 43 and a plurality of first sub-row connection portions 45, wherein the number of first sub-column connection portions 43 is greater than the number of first sub-row connection portions 45. In some embodiments, the number of first sub-column connection portions 43 in the first storage cell array 4 may be more than twice the number of first sub-row connection portions 45. The second storage cell array 5 includes a plurality of second sub-column connection portions 53 and a plurality of second sub-row connection portions 55, wherein the number of second sub-column connection portions 53 is greater than the number of second sub-row connection portions 55. In some embodiments, the number of first sub-column connection portions 43 in the first storage cell array 4 may be more than twice the number of first sub-row connection portions 45.

[0073] In some embodiments, at least one first sub-column connector 43 extends in a first direction for a length less than the length of at least one first sub-row connector 45 extends in a second direction; similarly, at least one second sub-column connector 53 extends in a first direction for a length less than the length of at least one second sub-row connector 55 extends in a second direction.

[0074] In some embodiments, the first memory cell array 4 and the second memory cell array 5 further include a third sub-array connection portion 60, which extends along a first direction from the first memory cell array 4 into the second memory cell array 5. The third sub-array connection portion 60 connects the same end of a plurality of first semiconductor devices 310 and a plurality of second semiconductor devices 320 extending along the first direction. In some embodiments, the third sub-array connection portion 60 is spaced apart from the first sub-array connection portion 43 and the second sub-array connection portion 53 along a second direction.

[0075] In some embodiments, the first surface A and / or the second surface B further have a connecting pad connected to the third sub-row connection portion 60, forming a transmission channel that extends one end of a plurality of first semiconductor devices and a plurality of second semiconductor devices extending in the first direction to the surface of the semiconductor structure.

[0076] In some embodiments, the first sub-column connection portion 43, the second sub-column connection portion 53, and the third sub-column connection portion 60 are respectively connected to the same end of the first semiconductor device 310 and the second semiconductor device 320, and the first sub-row connection portion 45 and the second sub-row connection portion 55 are respectively connected to the other end of the first semiconductor device 310 and the second semiconductor device 320.

[0077] In some embodiments, see Figures 1 to 4 As described, both the first semiconductor device 310 and the second semiconductor device 320 include a gate and a drain. A first sub-row connection portion 43 is connected to the drains of a plurality of first semiconductor devices 310 in a first direction in the first memory cell array 4. A second sub-row connection portion 53 is connected to the drains of a plurality of second semiconductor devices 320 in a first direction in the second memory cell array 5. A first sub-row connection portion 45 is connected to the gates of a plurality of first semiconductor devices 310 in a second direction in the first memory cell array 4. A second sub-row connection portion 55 is connected to the gates of a plurality of second semiconductor devices 320 in a second direction in the second memory cell array 5. A third sub-row connection portion 60 is connected to the drains of a plurality of first semiconductor devices 310 and a plurality of second semiconductor devices 320 in a first direction in both the first memory cell array 4 and the second memory cell array 5.

[0078] In some embodiments, each sub-row connection portion may also be connected to the gate of each semiconductor device, and each sub-row connection portion may also be connected to the drain of each semiconductor device.

[0079] In some embodiments, see continue to see Figure 5 A sixth connecting pad 130 and a seventh connecting pad 240 are respectively provided in the first surface A and the second surface B, and the sixth connecting pad 130 and the seventh connecting pad 240 have an interconnection structure extending through the storage cell region 3.

[0080] In some embodiments, see Figures 1-4 Each first semiconductor device 310 in the first memory cell array 4 also has an electrode portion 3104, and each semiconductor device 310 also has a source electrode. The electrode portion 3104 is connected to the source electrode of each semiconductor device, and each semiconductor device also has an electrode portion 3105 connected to each other. Figure 5(Not shown); Each second semiconductor device 320 in the second memory cell array 5 has an electrode portion 3204, and each semiconductor device 320 also has a source electrode. The electrode portion 3204 is connected to the source electrode of each semiconductor device, and each semiconductor device also has an electrode portion 3205 connected to each other. Figure 5 (Not shown). Figure 5 The connection relationship between the electrode portions 3105 and 3205 of each semiconductor device in the semiconductor structure shown can be found in the first surface A and the second surface B. Figures 1-4 The description will not be repeated here.

[0081] In the above embodiments, there can be multiple first memory cell arrays 4 and second memory cell arrays 5. Each memory cell array can be the smallest collection unit of a semiconductor device array, such as a MAT (Memory Array Tile).

[0082] In some embodiments, the semiconductor structure 1a further includes an interconnect layer 1 and a wiring layer 2, the interconnect layer 1 being disposed adjacent to a first surface A, the wiring layer 2 being disposed adjacent to a second surface B, and a memory cell region 3 being disposed between the interconnect layer 1 and the wiring layer 2. Figure 5 The interconnect layer 1 and wiring layer 2 in the semiconductor structure 1a shown can be found in [reference]. Figures 1-4 The description will not be repeated here.

[0083] This disclosure also provides an integrated assembly, see [link to embodiment]. Figure 7 The integrated assembly includes a first semiconductor structure 1a and a second semiconductor structure 1b. The first semiconductor structure 1a can be found in the aforementioned semiconductor structure 1a and... Figures 1-5 The structure shown is illustrated. The composition of the second semiconductor structure 1b can be found in [reference needed]. Figure 6As shown, the second semiconductor structure 1b has a first bonding surface C, which can be an exposed surface of the second semiconductor structure 1b for bonding with the first semiconductor structure 1a. The second semiconductor structure 1b also includes a memory cell region having a third semiconductor device 710 and a fourth semiconductor device 720. The third semiconductor device 710 and the fourth semiconductor device 720 can be identical semiconductor devices located in the same memory cell array, or identical semiconductor devices located in different memory cell arrays, for example, both being DRAM memory cells. The third semiconductor device 710 includes a drain 7101, a source 7102, and a gate 7103 located between the source and drain. The third semiconductor device 710 also includes an electrode portion 7104 and an electrode portion 7105. The electrode portion 7104 is connected to the source 7102, and the electrode portion 7104 and the electrode portion 7105 constitute the two electrodes of a capacitor. Similarly, the fourth semiconductor device 720 includes a drain 7201, a source 7202, and a gate 7203 located between the drain 7201 and the source 7207. The fourth semiconductor device 720 also includes an electrode portion 7204 and an electrode portion 7205. The electrode portion 7204 is connected to the source 7202, and the electrode portion 7204 and the electrode portion 7205 form the two electrodes of a capacitor.

[0084] The second semiconductor structure 1b further includes a connection portion 71 connected to the third semiconductor device 710 and a connection portion 72 connected to the fourth semiconductor device 720. In some embodiments, the connection portion 71 is connected to the drain 7101 of the third semiconductor device 710, and the connection portion 72 is connected to the drain 7201 of the fourth semiconductor device 720. In other embodiments, the connection portion 71 is connected to the gate of the third semiconductor device 710, and the connection portion 72 is connected to the gate of the fourth semiconductor device 720. The second semiconductor structure 1b also includes a common connection portion 70 connected to the third semiconductor device 710 and / or the fourth semiconductor device 720. In some embodiments, the common connection portion 70 is connected to the gate of the third semiconductor device 710 and / or the fourth semiconductor device 720. In other embodiments, the common connection portion 70 may also be connected to the drain of the third semiconductor device 710 and / or the fourth semiconductor device 720. The second semiconductor structure 1b further includes a connection portion 77 connected to the third semiconductor device 710 and a connection portion 78 connected to the fourth semiconductor device 720. In some embodiments, the connection portion 77 is connected to the electrode portion 7105 of the third semiconductor device 710, and the connection portion 78 is connected to the electrode portion 7205 of the fourth semiconductor device 720. In some embodiments, the connection portion 77 and the connection portion 78 may be interconnected.

[0085] The second semiconductor structure 1b further includes a first bonding surface C, which may be an exposed surface of the second semiconductor structure 1b. The first bonding surface C is provided with a plurality of connection pads for bonding with each connection pad in the first surface A of the first semiconductor structure 1a. An interconnect layer 6 is also provided between the first bonding surface C and the third semiconductor device 710 and the fourth semiconductor device 720. The interconnect layer 6 includes at least one metal interconnect layer for establishing connection channels between each connection pad in the first bonding surface C and the third semiconductor device 710 and the fourth semiconductor device 720. In some embodiments, the number of metal interconnect layers in the interconnect layer 6 is the same as the number of conductive interconnect layers in the interconnect layer 1 of the first semiconductor structure 1a, for example, both being two layers. In some embodiments, the first bonding surface C is also provided with virtual connection pads for non-electrical connections. The first bonding surface C may be a surface used for hybrid bonding or fusion bonding.

[0086] The following is combined Figure 6 and Figure 7 Briefly describe the connection relationships between each connecting pad in the second semiconductor structure 1b and the third semiconductor device 710 and the fourth semiconductor device 720, as well as the connection relationships between the first semiconductor structure 1a and the second semiconductor structure 1b.

[0087] In the second semiconductor structure 1b, a connecting pad 610 is connected to a connecting portion 71 of the third semiconductor device 710, a connecting pad 620 is connected to a connecting portion 72 of the fourth semiconductor device 720, and a connecting pad 630 is connected to the connecting portion 70, thereby enabling one end of the third semiconductor device 710 and / or one end of the fourth semiconductor device 720 to be connected to the connecting pad 630. The first bonding surface C also includes a connecting pad 640, which is connected to the connecting portion 77 and / or the connecting portion 78.

[0088] After the first bonding surface C and the first surface A are bonded, the connecting pad 610 is bonded to the first connecting pad 110, the connecting pad 620 is bonded to the second connecting pad 120, and the connecting pad 640 is bonded to the eighth connecting pad 140. This forms a signal transmission channel between the first semiconductor device 310 and the third semiconductor device 710, and a signal transmission channel between the second semiconductor device 320 and the fourth semiconductor device 720, between the first semiconductor structure 1a and the second semiconductor structure 1b. In some embodiments, these signal transmission channels include a connection channel between the drain of the first semiconductor device 310 and the drain of the third semiconductor device 710, such as the channel between the connecting pad 610 and the first connecting pad 110; and a connection channel between the drain of the second semiconductor device 320 and the drain of the fourth semiconductor device 720, such as the channel between the connecting pad 620 and the second connecting pad 120. The signal transmission channel also includes a channel between the connecting pad 640 and the eighth connecting pad 140, which may be a connection channel between the electrode portion 3105 of the first semiconductor device 310 and / or the electrode portion 3205 of the second semiconductor device 320 and the electrode portion 7105 of the third semiconductor device 710 and / or the electrode portion 7205 of the fourth semiconductor device 720.

[0089] After the first bonding surface C and the first surface A are bonded together, the connecting pad 630 and the sixth connecting pad 130 are bonded together to form a signal transmission channel connecting the first semiconductor structure 1a and the second semiconductor structure 1b. In some embodiments, these signal transmission channels may be signal transmission channels of the gate of the third semiconductor device 710 and / or the gate of the fourth semiconductor device 720.

[0090] The integrated assembly provided in this disclosure also includes a third semiconductor structure 1c bonded to the second surface B of the first semiconductor structure 1a. The bonding between the first semiconductor structure 1a and the third semiconductor structure 1c is either hybrid bonding or fusion bonding. Please continue to the next step. Figure 7 The third semiconductor structure 1c includes a fifth semiconductor device 810. A wiring layer 7 is disposed above the fifth semiconductor device 810. The wiring layer 7 is disposed between the second surface B and the fifth semiconductor device 810 and is used to connect the fifth semiconductor device 810 to each connection pad on the second surface B, thereby establishing a signal transmission channel between the third semiconductor structure and the first and second semiconductor structures, and realizing the interconnection between each semiconductor device.

[0091] In some embodiments, the wiring layer 7 includes multiple layers of metal wiring, and the number of metal wiring layers in the wiring layer 7 is greater than the number of conductive wiring layers in the wiring layer of the first semiconductor structure.

[0092] In some embodiments, the first, second, third, and fourth semiconductor devices are the same semiconductor device, such as DRAM memory devices, while the fifth semiconductor device is different from the first semiconductor device and can be a logic device. In some embodiments, the first and second semiconductor structures can be memory structures composed of DRAM memory cells, NAND memory cells, or other memory cells. The first and second semiconductor structures include arrays of memory cells that can use transistors as switching and selection devices. The third semiconductor structure can be any suitable digital, analog, and / or mixed-signal circuit structure used to facilitate the operation of the memory structure.

[0093] It should be noted that, Figure 7 The first semiconductor structure 1a in Figure 1 Taking the first semiconductor structure shown as an example, the first semiconductor structure can also be Figures 2-4 The connection relationship between the first semiconductor structure shown, the second semiconductor structure, and the third semiconductor structure is clear to those skilled in the art after reading the foregoing description.

[0094] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, comprising: The first and second surfaces are opposite to each other; A first connecting pad and a second connecting pad are disposed on the first surface; The third, fourth, and fifth connecting pads are disposed on the second surface; The storage cell region is disposed between the first surface and the second surface. The storage cell region includes a first semiconductor device and a second semiconductor device arranged along a first direction. A first connection pad and a fourth connection pad are connected to the first semiconductor device. A second connection pad and a fifth connection pad are connected to the second semiconductor device. The storage cell region also includes a first connection portion, which is connected to at least one of the first semiconductor device and the second semiconductor device. The first connection portion is connected to the third connection pad.

2. The semiconductor structure according to claim 1, characterized in that, In a direction parallel to the first surface, the maximum width of at least one of the first connecting pad and the second connecting pad is greater than the maximum width of at least one of the third connecting pad, the fourth connecting pad, and the fifth connecting pad.

3. The semiconductor structure according to claim 1, characterized in that, In a direction parallel to the first surface, the minimum distance between the first connecting pad and the second connecting pad is greater than the minimum distance between the third connecting pad, the fourth connecting pad, and the fifth connecting pad.

4. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: An interconnect layer disposed adjacent to the first surface; A wiring layer disposed adjacent to the second surface; The first connection pad and the second connection pad are respectively connected to the first semiconductor device and the second semiconductor device through the interconnect layer. The third connection pad is connected to the first connection portion through the wiring layer. The fourth connection pad and the fifth connection pad are respectively connected to the first semiconductor device and the second semiconductor device through the wiring layer. The metal density of the wiring layer is greater than the metal density of the interconnect layer.

5. The semiconductor structure according to claim 4, characterized in that, The semiconductor structure further includes a second connection portion and a third connection portion, the second connection portion being connected to the first semiconductor device, the third connection portion being connected to the second semiconductor device, the first connection pad and the fourth connection pad being connected to the second connection portion, the second connection pad and the fifth connection pad being connected to the third connection portion, the second connection portion, the third connection portion and the first connection portion being isolated from each other, and the wiring layer including a first wiring layer, the first connection portion, the second connection portion and the third connection portion being connected to the first wiring layer.

6. The semiconductor structure according to claim 1, characterized in that, A sixth connecting pad is also provided on the first surface, and a seventh connecting pad is also provided on the second surface, wherein the sixth connecting pad is connected to the seventh connecting pad.

7. The semiconductor structure according to claim 4, characterized in that, The semiconductor structure further includes a fourth connection portion located in the memory cell region and in the region between the first semiconductor device and the second semiconductor device. An eighth connection pad is also provided on the first surface, and a ninth connection pad is also provided on the second surface. The fourth connection portion connects the eighth connection pad and the ninth connection pad.

8. The semiconductor structure according to claim 7, characterized in that, The wiring layer further includes a second wiring layer, and the fourth connection portion is connected to the second wiring layer.

9. A semiconductor structure, comprising: The first and second surfaces are opposite to each other; A first connecting pad and a second connecting pad are disposed on the first surface; The third, fourth, and fifth connecting pads are disposed on the second surface; The storage cell region is disposed between the first surface and the second surface, and includes a first storage cell array and a second storage cell array arranged at intervals. The first storage cell array includes a plurality of first semiconductor devices arranged along a first direction, and the second storage cell array includes a plurality of second semiconductor devices arranged along the first direction. The first connection pad and the fourth connection pad are connected to the first semiconductor device, the second connection pad and the fifth connection pad are connected to the second semiconductor device, the memory cell region further includes a first connection portion, the first connection portion is connected to at least one of the first semiconductor device and the second semiconductor device, and the third connection pad is connected to the first connection portion.

10. The semiconductor structure according to claim 9, characterized in that, The first memory cell array includes a second connection portion, the second memory cell array includes a third connection portion, the second connection portion is connected to the first semiconductor device, the third connection portion is connected to the second semiconductor device, the first connection pad and the fourth connection pad are connected to the second connection portion, and the second connection pad and the fifth connection pad are connected to the third connection portion.

11. The semiconductor structure according to claim 10, characterized in that, Multiple first semiconductor devices arranged along the first direction form multiple first sub-columns. Each first sub-column includes a first sub-column connector connecting the multiple first semiconductor devices along the first direction. Multiple second semiconductor devices arranged along the first direction form a second sub-column. Each second sub-column includes a second sub-column connector connecting the multiple second semiconductor devices along the first direction. A first connector pad and a fourth connector pad are connected to the first sub-column connector via the second connector. A second connector pad and a fifth connector pad are connected to the second sub-column connector via the third connector. The first sub-column connector and the second sub-column connector extend along the first direction and are isolated from each other. The memory cell array further includes a plurality of first semiconductor devices arranged along a second direction, and the second memory cell array further includes a plurality of second semiconductor devices arranged along the second direction. The plurality of first semiconductor devices arranged along the second direction form a plurality of first sub-rows, and the plurality of second semiconductor devices arranged along the second direction form a plurality of second sub-rows. Each first sub-row includes a first sub-row connection portion connecting the plurality of first semiconductor devices in the second direction, and each second sub-row includes a second sub-row connection portion connecting the plurality of second semiconductor devices in the second direction. The first sub-row connection portion and the second sub-row connection portion extend along the second direction, and the first connection portion is connected to at least one of the first sub-row connection portion and the second sub-row connection portion.

12. The semiconductor structure according to claim 11, characterized in that, The first storage cell array includes multiple first sub-column connection sections and multiple first sub-row connection sections, and the number of first sub-column connection sections is greater than the number of first sub-row connection sections. The second storage cell array includes multiple second sub-column connection sections and multiple second sub-row connection sections, and the number of second sub-column connection sections is greater than the number of second sub-row connection sections.

13. The semiconductor structure according to claim 11, characterized in that, The storage cell region further includes a third sub-column connection portion extending along a first direction, the third sub-column connection portion extending from the first storage cell array to the second storage cell array, the third sub-connection portion connecting a plurality of first semiconductor devices and a plurality of second semiconductor devices extending along the first direction.

14. The semiconductor structure according to claim 13, characterized in that, Both the first semiconductor device and the second semiconductor device include a gate and a drain. The first sub-row connection portion is connected to the gate of the first semiconductor device, the second sub-row connection portion is connected to the gate of the second semiconductor device, the first sub-column connection portion is connected to the drain of the first semiconductor device, the second sub-column connection portion is connected to the drain of the second semiconductor device, and the third sub-column connection portion is connected to the drains of the first semiconductor device and the second semiconductor device.

15. The semiconductor structure according to claim 9, characterized in that, The first surface is further provided with a sixth connecting pad, and the second surface is further provided with a seventh connecting pad, wherein the sixth connecting pad is connected to the seventh connecting pad.

16. An integrated assembly comprising: A first semiconductor structure includes a first surface, on which a first connection pad and a second connection pad are disposed. The first semiconductor structure also includes a memory cell region disposed below the first surface. The memory cell region includes a first semiconductor device and a second semiconductor device. The first connection pad is connected to the first semiconductor device, and the second connection pad is connected to the second semiconductor device. A first connection portion is provided between the first semiconductor device and the second semiconductor device. A second semiconductor structure has a first bonding surface that is bonded to a first surface of the first semiconductor structure. The second semiconductor structure includes a third semiconductor device and a fourth semiconductor device. The third semiconductor device and the first semiconductor device are connected to the first connection pad through the first bonding surface. The fourth semiconductor device and the second semiconductor device are connected to the second connection pad through the first bonding surface. The second semiconductor structure also has a common connection portion that connects at least the third semiconductor device or the fourth semiconductor device. The first semiconductor structure further includes a second surface, on which a third connection pad, a fourth connection pad, a fifth connection pad, and a sixth connection pad are disposed. The third connection pad is connected to the first connection portion, the fourth connection pad is connected to the first connection pad, the fifth connection pad is connected to the second connection pad, and the sixth connection pad is connected to the common connection portion.

17. The assembly according to claim 16, characterized in that, The first semiconductor structure further includes an interconnect layer located between the first surface and the second surface and disposed adjacent to the first surface. The second semiconductor structure further includes a connection layer disposed adjacent to the first bonding surface. The third semiconductor device and the fourth semiconductor device are interconnected with the first semiconductor device and the second semiconductor device through the connection layer.

18. The assembly according to claim 16, characterized in that, It also includes a third semiconductor structure, one surface of which is bonded to a second surface of the first semiconductor structure. The third semiconductor structure includes a fifth semiconductor device. The first semiconductor structure also includes a wiring layer disposed adjacent to the second surface. The third semiconductor structure includes a wiring layer disposed adjacent to the second surface. The first semiconductor device, the second semiconductor device, the third semiconductor device, and the fourth semiconductor device are interconnected with the fifth semiconductor device through the wiring layer.

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