Semiconductor packaging structure and manufacturing method thereof

Abstract

The invention relates to a semiconductor package structure and a method for manufacturing the same. The semiconductor package structure includes a redistribution structure and an impedance matching device. The redistribution structure includes a first surface, a second surface opposite the first surface, and a circuitry-free region extending from the first surface to the second surface. The impedance matching device is disposed on the redistribution structure and includes at least one impedance matching circuit aligned with the circuitry-free region.

Description

[0001] Information related to divisional application

[0002] This application is a divisional application of the invention patent application filed on December 31, 2020, with application number "202011620903.1" and invention title "Semiconductor Packaging Structure and Manufacturing Method Thereof". Technical Field

[0003] This disclosure relates to a semiconductor package structure and a manufacturing method, and to a semiconductor package structure including at least one redistribution structure for electrical connection and impedance matching, and a method for manufacturing the semiconductor package structure. Background Technology

[0004] With the rapid advancement of semiconductor processing technology, semiconductor devices are integrated with an increasing number of electronic components to achieve better electrical performance and more functionality. Consequently, semiconductor devices have more input / output (I / O) connections. To manufacture semiconductor packages that include semiconductor devices with an increased number of I / O connections, the number of circuit layers on the semiconductor substrates that carry the semiconductor devices correspondingly increases. Therefore, the overall thickness of the semiconductor substrate increases accordingly, and impedance matching operations for the semiconductor devices become more difficult. Summary of the Invention

[0005] In some embodiments, a semiconductor package structure includes a redistribution structure and an impedance matching device. The redistribution structure includes a first surface, a second surface opposite to the first surface, and a circuitless region extending from the first surface to the second surface. The impedance matching device is disposed on the redistribution structure and includes at least one impedance matching circuit aligned with the circuitless region.

[0006] In some embodiments, a semiconductor package structure includes a conductive structure, a lower resolution impedance matching device, a higher resolution impedance matching device, and at least one electrical component. The conductive structure has an upper surface and a lower surface opposite to the upper surface. The lower resolution impedance matching device is disposed on the conductive structure and includes a redistribution structure and a first electronic component disposed on the redistribution structure. The higher resolution impedance matching device is disposed on the conductive structure. The electrical component is disposed on the lower surface of the conductive structure.

[0007] In some embodiments, a method for manufacturing a semiconductor package structure includes: providing a conductive structure including a ground plane; and placing a first impedance-matching device on the conductive structure to align with the ground plane. Attached Figure Description

[0008] When read in conjunction with the accompanying drawings, various aspects of some embodiments of this disclosure can be readily understood from the following detailed description. It should be noted that the various structures may not be drawn to scale, and the dimensions of the various structures may be arbitrarily increased or decreased for clarity of explanation.

[0009] Figure 1 Cross-sectional views showing semiconductor package structures according to some embodiments of this disclosure.

[0010] Figure 2 A top view showing a semiconductor package structure according to some embodiments of the present disclosure.

[0011] Figure 3 Show along Figure 2 A cross-sectional view of the CC line.

[0012] Figure 4 show Figure 3 A magnified view of area "A".

[0013] Figure 5 show Figure 3 A magnified view of area "B".

[0014] Figure 6 Cross-sectional views showing semiconductor package structures according to some embodiments of this disclosure.

[0015] Figure 7 show Figure 6 A magnified view of area "D".

[0016] Figure 8 Cross-sectional views showing semiconductor package structures according to some embodiments of this disclosure.

[0017] Figure 9 Cross-sectional views showing semiconductor package structures according to some embodiments of this disclosure.

[0018] Figure 10 Cross-sectional views showing semiconductor package structures according to some embodiments of this disclosure.

[0019] Figure 11 Cross-sectional views showing semiconductor package structures according to some embodiments of this disclosure.

[0020] Figure 12 This disclosure shows one or more stages of some embodiments of the method for manufacturing semiconductor package structures.

[0021] Figure 13 This disclosure shows one or more stages of some embodiments of the method for manufacturing semiconductor package structures.

[0022] Figure 14 This disclosure shows one or more stages of some embodiments of the method for manufacturing semiconductor package structures.

[0023] Figure 15 This disclosure shows one or more stages of some embodiments of the method for manufacturing semiconductor package structures.

[0024] Figure 16 This disclosure shows one or more stages of some embodiments of the method for manufacturing semiconductor package structures.

[0025] Figure 17 This disclosure shows one or more stages of some embodiments of the method for manufacturing semiconductor package structures.

[0026] Figure 18 This disclosure shows one or more stages of some embodiments of the method for manufacturing semiconductor package structures.

[0027] Figure 19 This disclosure shows one or more stages of some embodiments of the method for manufacturing semiconductor package structures.

[0028] Figure 20 This disclosure shows one or more stages of some embodiments of the method for manufacturing semiconductor package structures.

[0029] Figure 21 This disclosure shows one or more stages of some embodiments of the method for manufacturing semiconductor package structures.

[0030] Figure 22 This disclosure shows one or more stages of some embodiments of the method for manufacturing semiconductor package structures.

[0031] Figure 23 This disclosure shows one or more stages of some embodiments of the method for manufacturing semiconductor package structures.

[0032] Figure 24 This disclosure shows one or more stages of some embodiments of the method for manufacturing semiconductor package structures.

[0033] Figure 25 This disclosure shows one or more stages of some embodiments of the method for manufacturing semiconductor package structures.

[0034] Figure 26 This disclosure shows one or more stages of some embodiments of the method for manufacturing semiconductor package structures.

[0035] Figure 27 This disclosure shows one or more stages of some embodiments of the method for manufacturing semiconductor package structures.

[0036] Figure 28 This disclosure shows one or more stages of some embodiments of the method for manufacturing semiconductor package structures.

[0037] Figure 29 This disclosure shows one or more stages of some embodiments of the method for manufacturing semiconductor package structures.

[0038] Figure 30 This disclosure shows one or more stages of some embodiments of the method for manufacturing semiconductor package structures.

[0039] Figure 31 This disclosure shows one or more stages of some embodiments of the method for manufacturing semiconductor package structures.

[0040] Figure 32 This disclosure shows one or more stages of some embodiments of the method for manufacturing semiconductor package structures.

[0041] Figure 33 This disclosure shows one or more stages of some embodiments of the method for manufacturing semiconductor package structures.

[0042] Figure 34 This disclosure shows one or more stages of some embodiments of the method for manufacturing semiconductor package structures.

[0043] Figure 35 This disclosure shows one or more stages of some embodiments of the method for manufacturing semiconductor package structures.

[0044] Figure 36 This disclosure shows one or more stages of some embodiments of the method for manufacturing semiconductor package structures. Detailed Implementation

[0045] Common reference numerals are used throughout the accompanying drawings and detailed description to indicate the same or similar components. Embodiments of this disclosure will be more readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0046] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to illustrate certain aspects of this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed or disposed in direct contact, and may also include embodiments where additional features may be formed or disposed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0047] Figure 1 A cross-sectional view of a semiconductor package structure 1, illustrating some embodiments of the present disclosure, is shown. The semiconductor package structure 1 includes a redistribution structure 10, an impedance matching device (including, for example, a transformer 30 (or a transducer or converter)), at least one semiconductor device 21, an encapsulant 41, a shielding layer 91, at least one first electrical contact (including, for example, contacts 94 and 94a), a plurality of second electrical contacts 95, and a plurality of third electrical contacts 96. In some embodiments, the semiconductor package structure 1 may be an impedance-matchable device.

[0048] The redistribution structure 10 includes a first surface 11, a second surface 12 opposite to the first surface 11, a peripheral surface 13 extending between the first surface 11 and the second surface 12, a dielectric structure 14, a circuitless region 15, a redistribution layer 16, a plurality of inner vias 18, and an impedance-matchable circuit 19. The dielectric structure 14 may include a first dielectric layer 141 and at least one second dielectric layer 142. The second dielectric layer 142 may be disposed on the top surface of the first dielectric layer 141. The first dielectric layer 141 and the second dielectric layer 142 may be made of a curable photoimageable dielectric (PID) material, such as epoxy resin or polyimide (PI) including photoinitiators.

[0049] The circuitless region 15 may extend from the first surface 11 (i.e., the top surface of the dielectric structure 14) to the second surface 12 (i.e., the bottom surface of the dielectric structure 14). That is, the thickness t1 of the circuitless region 15 is substantially equal to the thickness t2 of the redistribution structure 10 from the first surface 11 to the second surface 12. In some embodiments, the circuitless region 15 may include a portion of the first dielectric layer 141 and a portion of the second dielectric layer 142. The redistribution layer 16 may be embedded in the dielectric structure 14 and may include a plurality of circuit layers 162. The redistribution layer 16 may be disposed outside the circuitless region 15. That is, the circuit layers 162 may not extend into the circuitless region 15. There may be no circuit layers in the circuitless region 15. The circuit layers 162 may be fan-out circuit layers, and the line width / line space (L / S) of the circuit layers 162 may be less than or equal to 2 μm / 2 μm, or less than or equal to 1.8 μm / 1.8 μm. The material of circuit layer 162 can be, for example, copper. Internal vias 18 can electrically connect at least one circuit layer 162 of the redistribution layer 16 or two adjacent circuit layers 162. Additionally, the internal via 18 can gradually narrow towards the second surface 12. Figure 1As shown, the topmost second dielectric layer 142 may cover the topmost circuit layer 162 and may define multiple openings to expose portions of the topmost circuit layer 162. Impedance-matching circuit 19 may be electrically connected to the circuit layer 162 of the redistribution layer 16. In some embodiments, impedance-matching circuit 19 may be part of circuit layer 162. In some embodiments, from a top view, impedance-matching circuit 19 may have a spiral shape.

[0050] To reduce the skin effect, which can cause high-frequency currents to flow primarily at the surface of the conductor (e.g., the circuit layer), the thickness of each of the circuit layers 162 may be greater than or equal to about 8 µm, or greater than or equal to about 10 µm. That is, the thickness of the second dielectric layer 142 may be greater than 8 µm to cover the circuit layer 162. In some embodiments, the thickness of the second dielectric layer 142 may be greater than or equal to about 10 µm, greater than or equal to about 12 µm, or greater than or equal to about 14 µm. In some embodiments, the thickness of the second dielectric layer 142 may be between about 10 µm and about 14 µm.

[0051] Impedance matching devices (including, for example, transformer 30) are mounted on and electrically connected to the redistribution structure 10. In some embodiments, the impedance matching devices (including, for example, transformer 30) may be spaced apart from the non-circuit region 15 by a first electrical contact (including, for example, electrical contact 94 and electrical contact 94a).

[0052] In some embodiments, the impedance matching device (including, for example, a transformer 30) may include a base 31, at least one impedance matching circuit (including, for example, a first impedance matching circuit 32 and a second impedance matching circuit 33), a plurality of connection pads (including, for example, a first connection pad 34, a second connection pad 35, and a third connection pad 36), at least one conductive via 37, and at least one protective layer (including, for example, a first protective layer 38 and a second protective layer 39). The base 31 may be made of, for example, FR4, polypropylene (PP), or bismaleimide-triazine (BT). The base 31 has a top surface 311 and a bottom surface 312 opposite to the top surface 311.

[0053] The first impedance matching circuit 32 may be, for example, a coil structure. The first impedance matching circuit 32 may be positioned adjacent to the bottom surface 312 of the base 31 and aligned with the circuitless region 15 of the redistribution structure 10. In some embodiments, the first impedance matching circuit 32 may be spaced apart from the circuitless region 15 of the redistribution structure 10 by first electrical contacts (including, for example, contacts 94 and 94a). Furthermore, the first electrical contacts (including, for example, contacts 94 and 94a) may not overlap with the first impedance matching circuit 32. That is, the projection area of ​​the first electrical contacts (including, for example, contacts 94 and 94a) may not overlap with the projection area of ​​the first impedance matching circuit 32. Therefore, the first impedance matching circuit 32 and the circuitless region 15 of the redistribution structure 10 may constitute part of an inductor. In some embodiments, the projection area of ​​the first impedance matching circuit 32 may fall within the circuitless region 15 of the redistribution structure 10. In some embodiments, the thickness of the first impedance matching circuit 32 may be greater than the thickness of the circuit layer 162. In some embodiments, the thickness of the first impedance matching circuit 32 may be greater than 10 μm, 15 μm, or 20 μm.

[0054] The second impedance matching circuit 33 may be, for example, a coil structure. The second impedance matching circuit 33 may be positioned adjacent to the top surface 311 of the base 31 and aligned with the circuitless region 15 of the redistribution structure 10. In some embodiments, the second impedance matching circuit 33 may be spaced apart from the circuitless region 15 of the redistribution structure 10 by a first electrical contact (including, for example, electrical contacts 94 and 94a). Furthermore, the first electrical contact (including, for example, electrical contacts 94 and 94a) may not overlap with the second impedance matching circuit 33. That is, the projected area of ​​the first electrical contact (including, for example, electrical contacts 94 and 94a) may not overlap with the projected area of ​​the second impedance matching circuit 33. Therefore, the second impedance matching circuit 33 and the circuitless region 15 of the redistribution structure 10 may constitute part of an inductor. In some embodiments, the projected area of ​​the second impedance matching circuit 33 may fall within the circuitless region 15 of the redistribution structure 10. In some embodiments, the thickness of the second impedance matching circuit 33 may be greater than the thickness of the circuit layer 162. In some embodiments, the thickness of the second impedance matching circuit 33 may be greater than 10 μm, 15 μm or 20 μm.

[0055] The first connecting pad 34 and the second connecting pad 35 may be positioned adjacent to the bottom surface 312 of the base 31 and spaced apart from each other. The first connecting pad 34 may be engaged to one of the exposed portions of the topmost circuit layer 162 of the overlay layer 16 via a first electrical contact 94a. The second connecting pad 35 may be connected to the first impedance matching circuit 32 and engaged to one of the exposed portions of the topmost circuit layer 162 of the overlay layer 16 via the first electrical contact 94. Therefore, the first impedance matching circuit 32, the second connecting pad 35, and the first electrical contact 94 may constitute the first electrical path P1 of an impedance matching device (including, for example, a transformer 30).

[0056] The third connecting pad 36 can be positioned adjacent to the top surface 311 of the base 31 and connected to the second impedance matching circuit 33. A via 37 can penetrate the base 31 and is positioned between the third connecting pad 36 and the first connecting pad 34 to electrically connect the third connecting pad 36 and the first connecting pad 34. Therefore, the second impedance matching circuit 33, the third connecting pad 36, the via 37, the first connecting pad 34, and the first electrical contact 94a can constitute the second electrical path P2 of the impedance matching device (including, for example, a transformer 30).

[0057] The first protective layer 38 may be, for example, a solder mask. The first protective layer 38 may be disposed on the bottom surface 312 of the base 31 to cover the first impedance matching circuit 32, the first connection pad 34, and the second connection pad 35. In some embodiments, a portion of the first protective layer 38 may be located between the first impedance matching circuit 32 and the circuitless region 15 of the redistribution structure 10. Therefore, the first impedance matching circuit 32, a portion of the first protective layer 38, and the circuitless region 15 may constitute part of an inductor. In some embodiments, the thickness t1 of the circuitless region 15 may be greater than the thickness t3 of the first protective layer 38.

[0058] The second protective layer 39 may be, for example, a solder mask. The second protective layer 39 may be disposed on the top surface 311 of the base 31 to cover the second impedance matching circuit 33 and the third connection pad 36.

[0059] Semiconductor device 21 may be, for example, a power amplifier. In some embodiments, semiconductor device 21 may be disposed on redistribution structure 10 and electrically connected to impedance matching circuit 19 of redistribution structure 10. Additionally, semiconductor device 21 may be electrically connected to impedance matching devices (including, for example, transformer 30) via impedance matching circuit 19 of redistribution structure 10. Therefore, impedance matching circuit 19 of redistribution structure 10 can perform fine-tuning of circuit impedance after coarse tuning via impedance matching devices (including, for example, transformer 30). Semiconductor device 21 has a lower surface 212 and includes a plurality of bonding pads 214. The bonding pads 214 may be positioned adjacent to the lower surface 212 and bonded to some of the exposed portions of the topmost circuit layer 162 of the overlay layer 16 via second electrical contacts 95 (e.g., solder balls), the second electrical contacts 95 being positioned between the bonding pads 214 of the semiconductor device 21 and the exposed portions of the topmost circuit layer 162 of the overlay layer 16.

[0060] Package 41 is disposed on the redistribution structure 10 to seal the semiconductor device 21 and impedance matching device (including, for example, a transformer 30). The material of package 41 may be a molding compound with or without fillers. In some embodiments, a portion of package 41 may be disposed between the first impedance matching circuit 32 and a circuitless region 15 of the redistribution structure 10, and no bonding materials (e.g., solder balls or solder bumps) are disposed in this portion of package 41. Package 41 has a top surface 411, a bottom surface 412 opposite to the top surface 411, and a peripheral surface 413 extending between the top surface 411 and the bottom surface 412. In some embodiments, the peripheral surface 13 of the redistribution structure 10 may be substantially coplanar with the peripheral surface 413 of package 41.

[0061] The shielding layer 91 covers the package 41 (e.g., top surface 411 and peripheral surface 413) and the peripheral surface 13 of the redistribution structure 10 to reduce radio frequency interferences. In some embodiments, the shielding layer 91 may be electrically connected to the redistribution structure 10.

[0062] A third electrical contact 96 (e.g., a solder ball) is mounted on the rework structure 10 for external connection. In some embodiments, the third electrical contact 96 may be electrically connected to an internal via 18 of the rework structure 10.

[0063] By reducing the thickness of the circuit layer 162, the thickness of the first dielectric layer 141, and the thickness of the second dielectric layer 142, the thickness of the redistribution structure 10 can be significantly reduced to below 150 µm. Therefore, the overall thickness of the semiconductor package structure 1 can be further reduced to below 350 µm. Additionally, the impedance matching device (including, for example, a transformer 30) can fine-tune the circuit impedance for matching the semiconductor device 21 by adjusting the distance between the impedance matching circuit (including, for example, the first impedance matching circuit 32 and the second impedance matching circuit 33) and the circuitless region 15 of the redistribution structure 10, the thickness of the first dielectric layer 141, or the thickness of the second dielectric layer 142.

[0064] Figure 2 A top view showing a semiconductor package structure 2 according to some embodiments of the present disclosure. Figure 3 Show along Figure 2 A cross-sectional view of the CC line. Figure 4 show Figure 3 An enlarged view of region "A". The semiconductor package structure 2 includes a conductive structure 50, a lower resolution impedance-matchable device 4, a higher resolution impedance-matchable device 6, at least one impedance-matchable device 72, an encapsulant 43, at least one semiconductor device, an encapsulant 44, at least one electrical element 98, and a shielding cover 93. The lower resolution impedance-matchable device 4 may also be referred to as the "first impedance-matchable device". The higher resolution impedance-matchable device 6 may also be referred to as the "second impedance-matchable device". That is, the resolution of the first impedance-matchable device may be different from the resolution of the second impedance-matchable device.

[0065] refer to Figure 3and Figure 4 The conductive structure 50 may be, for example, a redistribution structure or a substrate. The conductive structure 50 has an upper surface 51, a lower surface 52 opposite to the upper surface 51, and a peripheral surface 53 extending between the upper surface 51 and the lower surface 52. In some embodiments, the conductive structure 50 may include a dielectric structure 54, a redistribution layer 55, a conductive layer 56, and a plurality of inner vias 57. The dielectric structure 54 may include a first dielectric layer 541 and at least one second dielectric layer 542. The second dielectric layer 542 may be disposed on the top surface of the first dielectric layer 541. The first dielectric layer 541 and the second dielectric layer 542 may be made of a curable photoimageable dielectric (PID) material, such as epoxy resin or polyimide (PI) including photoinitiators. The redistribution layer 55 may contact the dielectric structure 54 and may include a plurality of circuit layers 552. Circuit layer 552 may be a fan-out circuit layer, and the linewidth / spacing (L / S) of circuit layer 552 may be less than or equal to 2 μm / 2 μm, or less than or equal to 1.8 μm / 1.8 μm. Conductive layer 56 may contact dielectric structure 54 and serve as a ground plane. In some embodiments, conductive layer 56 may be exposed from the upper surface 51 of conductive structure 50. In some embodiments, conductive layer 56 may be part of circuit layer 552 of redistribution layer 55. Internal via 57 may electrically connect at least one circuit layer 552 or two adjacent circuit layers 552 of redistribution layer 55. Additionally, internal via 57 may gradually narrow towards lower surface 52. Figure 4 As shown, the topmost second dielectric layer 542 can cover the topmost circuit layer 552 and can define multiple openings to expose portions of the topmost circuit layer 552.

[0066] A lower resolution impedance matching device 4 is disposed on and electrically connected to the conductive structure 50. In some embodiments, the lower resolution impedance matching device 4 may be... Figure 1The semiconductor package structure 1 may include a redistribution structure 10, a first electronic component (including, for example, an impedance matching device, such as a transformer 30), a second electronic component (including, for example, a semiconductor device 21, such as a power amplifier), a first encapsulant 41, and a first shielding layer 91. The accuracy of the circuit impedance modulated by the lower resolution impedance matching device 4 in the semiconductor package structure 2 may be greater than or equal to ±5% or ±10%.

[0067] In some embodiments, Figure 3 and Figure 4 The re-layout structure 10 can be combined with Figure 1 The redistribution structure is the same as 10. Additionally, Figure 3 and Figure 4 The redistribution structure 10 can be electrically connected to the conductive structure 50 via multiple electrical contacts 96 (e.g., solder balls). That is, the impedance matching circuit 19 of the redistribution structure 10 can be spaced apart from the conductive layer 56 (i.e., the ground plane) via the electrical contacts 96. In some embodiments, the electrical contacts 96 may not overlap with the impedance matching circuit 19 of the redistribution structure 10. In other words, the projected area of ​​the electrical contacts 96 may not overlap with the projected area of ​​the impedance matching circuit 19 of the redistribution structure 10.

[0068] Figure 3 and Figure 4 The first electronic component (including, for example, an impedance matching device, such as transformer 30) can be connected with Figure 1 The impedance matching device, including transformer 30, is the same. Figure 3 and Figure 4 The second electronic component (including, for example, semiconductor device 21, such as a power amplifier) ​​can be connected to Figure 1 The semiconductor device 21 (such as a power amplifier) ​​is the same. Figure 3 and Figure 4 The first package 41 can be with Figure 1 The same as the package 41. Figure 3 and Figure 4 The first shielding layer 91 can be with Figure 1 The shielding layer 91 is the same.

[0069] A first shielding layer 91 is disposed on the first package 41 to cover the first package 41 (e.g., top surface 411 and peripheral surface 413) and the peripheral surface 13 of the redistribution structure 10 to reduce radio frequency interference. In some embodiments, the first shielding layer 91 may be electrically connected to the redistribution structure 10.

[0070] A higher resolution impedance matching device 6 is disposed on and electrically connected to the conductive structure 50. In some embodiments, the higher resolution impedance matching device 6 may include a redistribution structure 60, an impedance-matching circuit, at least one electronic component 71, a second encapsulant 42, and a second shielding layer 92. The higher resolution impedance matching device 6 modulates the circuit impedance of the semiconductor package structure 2 with an accuracy less than or equal to ±2% or ±1%.

[0071] Figure 5 show Figure 3 A magnified view of area "B". (Reference) Figure 3 and Figure 5 The redistribution structure 60 is disposed adjacent to the upper surface 51 of the conductive structure 50 and electrically connected to the conductive structure 50 via a plurality of electrical contacts 97 that can be mounted on the redistribution structure 60. The redistribution structure 60 has an upper surface 61, a lower surface 62 opposite to the upper surface 61, and a peripheral surface 63 extending between the upper surface 61 and the lower surface 62. In some embodiments, the redistribution structure 60 may include a dielectric structure 64, a redistribution layer 66, a plurality of internal vias 68, and an impedance-matching circuit 69. The dielectric structure 64 may include a first dielectric layer 641 and at least one second dielectric layer 642. The second dielectric layer 642 may be disposed on the top surface of the first dielectric layer 641. The first dielectric layer 641 and the second dielectric layer 642 may be made of a curable photoimageable dielectric (PID) material, such as an epoxy resin or polyimide (PI) including a photoinitiator. The redistribution layer 66 may be embedded in the dielectric structure 64 and may include a plurality of circuit layers 662. Circuit layer 662 can be a fan-out circuit layer, and the linewidth / spacing (L / S) of circuit layer 662 can be less than or equal to 2 μm / 2 μm, or less than or equal to 1.8 μm / 1.8 μm. The material of circuit layer 662 can be, for example, copper. Internal via 68 can electrically connect at least one circuit layer 662 of the redistribution layer 66 or two adjacent circuit layers 662. Additionally, internal via 68 can gradually narrow towards the lower surface 62. Figure 5As shown, the topmost second dielectric layer 642 may cover the topmost circuit layer 662 and may define multiple openings to expose portions of the topmost circuit layer 662. An impedance matching circuit 69 may be electrically connected to the circuit layer 662 of the redistribution layer 66. In some embodiments, the impedance matching circuit 69 may be part of the circuit layer 662. In some embodiments, the impedance matching circuit 69 may be spiral-shaped when viewed from a top view. Additionally, the impedance matching circuit 69 may be spaced apart from the ground plane (i.e., the conductive layer 56) by an electrical contact 97. In some embodiments, the electrical contact 97 may not overlap with the impedance matching circuit 69 of the redistribution structure 60. That is, the projected area of ​​the electrical contact 97 may not overlap with the projected area of ​​the impedance matching circuit 69 of the redistribution structure 60.

[0072] To reduce the skin effect, the thickness of each of the circuit layers 662 may be greater than or equal to about 8 µm. That is, the thickness of the second dielectric layer 642 may be greater than 8 µm to cover the circuit layer 662. In some embodiments, the thickness of the second dielectric layer 642 may be greater than or equal to about 10 µm. In some embodiments, the thickness of the second dielectric layer 642 may be between about 10 µm and about 14 µm.

[0073] In some embodiments, the circuit layer 662 of the redistribution layer 66 may be an impedance matching circuit. That is, the impedance matching circuit may be placed in the redistribution structure 60.

[0074] Electronic component 71 is disposed on the redistribution structure 60 and electrically connected to the redistribution structure 60 via, for example, solder balls or solder bumps. In some embodiments, electronic component 71 may be electrically connected to an impedance matching circuit 69 of the redistribution structure 60. Therefore, the impedance matching circuit 69 of the redistribution structure 60 can be finely tuned after modulation by electronic component 71. In some embodiments, electronic component 71 may include a filter. The filter may be, for example, a surface acoustic wave (SAW) filter or a bulk acoustic wave (BAW) filter.

[0075] A second package 42 is disposed on the resilient structure 60 to seal the resilient structure 60 and the electronic component 71. The material of the second package 42 may be a molding compound with or without fillers. The second package 42 has a top surface 421, a bottom surface 422 opposite to the top surface 421, and a peripheral surface 423 extending between the top surface 421 and the bottom surface 422. In some embodiments, the peripheral surface 63 of the resilient structure 60 may be substantially coplanar with the peripheral surface 423 of the second package 42.

[0076] A second shielding layer 92 is disposed on the second package 42 to cover the second package 42 (e.g., top surface 421 and peripheral surface 423) and the peripheral surface 63 of the redistribution structure 60 to reduce radio frequency interference. In some embodiments, the second shielding layer 92 may be electrically connected to the redistribution structure 60.

[0077] The impedance matching device 72 can be, for example, an inductor, a resistor, or a capacitor. The impedance matching device 72 can be disposed on and electrically connected to the conductive structure 50. In some embodiments, the resolution of the impedance matching device 72 can be between a lower resolution impedance matching device 4 and a higher resolution impedance matching device 6.

[0078] Package 43 is disposed on conductive structure 50 to seal lower resolution impedance matching device 4, higher resolution impedance matching device 6, and impedance matching device 72. That is, a first shielding layer 91 may be disposed between the first package 41 and package 43, and a second shielding layer 92 may be disposed between the second package 42 and package 43. Additionally, a portion of package 43 may be disposed between conductive layer 56 and the circuitless region 15 of the redistribution structure 10. The material of package 43 may be a molding compound with or without fillers. Package 43 has a top surface 431, a bottom surface 432 opposite to the top surface 431, and a peripheral surface 433 extending between the top surface 431 and the bottom surface 432. In some embodiments, the peripheral surface 53 of conductive structure 50 may be substantially coplanar with the peripheral surface 433 of package 43.

[0079] Semiconductor devices (including, for example, semiconductor devices 22 and 23) may be, for example, controllers, low-noise amplifiers, or switches. Controllers may include mobile industry processor interfaces (MIPI) or general purpose input / output (GPIO). In some embodiments, semiconductor devices (including, for example, semiconductor devices 22 and 23) may be disposed on the lower surface 52 of conductive structure 50 and electrically connected to conductive structure 50. Semiconductor devices (including, for example, semiconductor devices 22 and 23) have bottom surfaces (including, for example, bottom surfaces 221 and 231).

[0080] Package 44 is disposed on the lower surface 52 of conductive structure 50 to seal a semiconductor device (including, for example, semiconductor device 22 and semiconductor device 23). The material of package 44 may be a molding compound with or without fillers. Package 44 has a top surface 441, a bottom surface 442 opposite to the top surface 441, and a peripheral surface 443 extending between the top surface 441 and the bottom surface 442. Additionally, package 44 may define at least one opening 445 through package 44 to expose a portion of conductive structure 50 (e.g., a portion of internal via 57). In some embodiments, the bottom surface (including, for example, bottom surface 221 and bottom surface 231) of the semiconductor device (including, for example, semiconductor device 22 and semiconductor device 23) may be substantially coplanar with the bottom surface 442 of package 44. Additionally, the peripheral surface 53 of conductive structure 50 may be substantially coplanar with the peripheral surface 443 of package 44.

[0081] An electrical component 98 (e.g., a solder ball) is disposed on the lower surface 52 of the conductive structure 50. In some embodiments, the electrical component 98 may be disposed in an opening 445 of the package 44 and on an exposed portion of the conductive structure 50 (i.e., an exposed portion of the internal via 57) for external connection. In some embodiments, the package 44 may seal the upper portion of the electrical component 98, and the lower portion of the electrical component 98 may protrude downward from the bottom surface 442 of the package 44.

[0082] A shielding cover 93 is disposed on the package 43 to cover the package 43 (e.g., top surface 431 and peripheral surface 433), the peripheral surface 53 of the conductive structure 50, and the peripheral surface 443 of the package 44 to reduce radio frequency interference. In some embodiments, the shielding cover 93 may be electrically connected to the conductive structure 50.

[0083] By reducing the thickness of the lower-resolution impedance matching device 4, the higher-resolution impedance matching device 6, and the conductive structure 50, the overall thickness of the semiconductor package structure 2 can be significantly reduced to below 600 µm. Furthermore, the lower-resolution impedance matching device 4 and the higher-resolution impedance matching device 6 can fine-tune or coarse-tune the circuit impedance of the semiconductor package structure 2 to improve its electrical performance.

[0084] Figure 6 A cross-sectional view of a semiconductor package structure 2a according to some embodiments of the present disclosure is shown. Figure 7 show Figure 6 A magnified view of region "D". Semiconductor package structure 2a is similar to... Figures 2 to 5The semiconductor package structure 2 shown differs in the configuration of the conductive layer 56a. The conductive layer 56a can be embedded in the dielectric structure 54 of the conductive structure 50. Therefore, the distance between the conductive layer 56a and the circuitless region 15 of the redistribution structure 10 can be increased accordingly to adjust the inductance value of the inductor and fine-tune the impedance matching. Figure 7 As shown, a portion of the dielectric structure 54 of the conductive structure 50 (e.g., the second dielectric layer 542) may be located between the conductive layer 56a and the circuitless region 15 of the redistribution structure 10 to adjust the dielectric constant between the impedance matching element 30 and the conductive layer 56a.

[0085] Figure 8 A cross-sectional view of a semiconductor package structure 2b, illustrating some embodiments of the present disclosure, is shown. The semiconductor package structure 2b is similar to... Figure 3 The semiconductor package structure 2 shown differs in the configuration of the shielding cover 93a. A portion of the shielding cover 93a extends into the package body 43 to connect to the first shielding layer 91. Therefore, heat generated by the second electronic component (including, for example, a semiconductor device 21, such as a power amplifier) ​​during operation can be easily dissipated through the first shielding layer 91 and the shielding cover 93a.

[0086] Figure 9 A cross-sectional view of a semiconductor package structure 2c, representing some embodiments of the present disclosure, is shown. The semiconductor package structure 2c is similar to... Figure 3 The semiconductor package structure 2 shown differs in the configuration of the first shielding layer 91a. The first shielding layer 91a may extend downward to connect to the conductive structure 50. Therefore, heat generated by the second electronic component (including, for example, a semiconductor device 21, such as a power amplifier) ​​during operation can be easily dissipated through the first shielding layer 91a and the conductive structure 50.

[0087] Figure 10 A cross-sectional view of a semiconductor package structure 3 according to some embodiments of the present disclosure is shown. The semiconductor package structure 3 includes a conductive structure 8, an impedance matching device, at least one first semiconductor device 21a, at least one electronic component 71a, at least one impedance matching device 72a, at least one second semiconductor device, a package body 40, at least one electrical component 98a, and a shielding cover 93b. In some embodiments, the conductive structure 8 may include a first circuit portion 50a, a second circuit portion 10a, an adhesive layer 81, and at least one conductive via 82.

[0088] Figure 10 The first circuit section 50a can be connected with Figure 3and Figure 4 The conductive structure is the same as that of 50.

[0089] The second circuit portion 10a can be bonded to the first circuit portion 50a via an adhesive layer 81 disposed between the first circuit portion 50a and the second circuit portion 10a. In some embodiments, the size of the second circuit portion 10a may be larger than the size of the relay structure 10 and substantially equal to the size of the first circuit portion 50a. Figure 10 The second circuit section 10a can be connected with Figure 3 and Figure 4 The re-lay structure is the same as 10.

[0090] A via 82 passes through the adhesive layer 81 to electrically connect the first circuit portion 50a to the second circuit portion 10a. In some embodiments, the via 82 may pass through the first circuit portion 50a and the adhesive layer 81 to electrically connect the second circuit portion 10a. Alternatively, the via 82 may pass through a portion of the dielectric structure 14 (e.g., the first dielectric layer 141) to electrically connect to or contact the bottommost circuit layer 162 of the redistribution layer 16.

[0091] An impedance matching device (including, for example, a transformer 30a) is disposed on and electrically connected to the second circuit section 10a. In some embodiments, Figure 10 Impedance matching devices (including, for example, transformer 30a) can be used with Figure 3 and Figure 4 The impedance matching devices (including, for example, transformer 30) are the same.

[0092] A first semiconductor device 21a is disposed on a second circuit portion 10a and electrically connected to an impedance matching device (including, for example, a transformer 30a). That is, the first semiconductor device 21a can be electrically connected to an impedance matching device (including, for example, a transformer 30a) via the second circuit portion 10a. In some embodiments, Figure 10 The first semiconductor device 21a can be connected with Figure 3 The semiconductor device 21 (such as a power amplifier) ​​is the same.

[0093] Electronic component 71a is disposed on second circuit portion 10a and electrically connected to second circuit portion 10a via, for example, solder balls or solder bumps. In some embodiments, electronic component 71a may include a filter. The filter may be, for example, a surface acoustic wave (SAW) filter or a bulk acoustic wave (BAW) filter.

[0094] The impedance matching device 72a can be, for example, an inductor, a resistor, or a capacitor. The impedance matching device 72a can be disposed on the second circuit section 10a and electrically connected to the second circuit section 10a.

[0095] The second semiconductor device (including, for example, second semiconductor device 22a and second semiconductor device 23a) may be, for example, a controller, a low-noise amplifier, or a switch. The controller may include a Mobile Industry Processor Interface (MIPI) or a General Purpose Input / Output (GPIO). In some embodiments, the second semiconductor device (including, for example, second semiconductor device 22a and second semiconductor device 23a) may be disposed on the lower surface 52 of the first circuit portion 50a and electrically connected to the first circuit portion 50a. The second semiconductor device (including, for example, second semiconductor device 22a and second semiconductor device 23a) has a bottom surface (including, for example, bottom surface 221a and bottom surface 231a).

[0096] Package 40 seals a first circuit portion 50a, a second circuit portion 10a, an impedance matching device (including, for example, a transformer 30a), a first semiconductor element 21a, an electronic component 71a, an impedance matching device 72a, and a second semiconductor device (including, for example, a second semiconductor device 22a and a second semiconductor device 23a). The material of package 40 may be a molding compound with or without fillers. Package 40 may include a lower portion below the first circuit portion 50a and an upper portion above the second circuit portion 10a. Package 40 may define at least one opening 405 through the lower portion of package 40 to expose a portion of the first circuit portion 50a (e.g., a portion of an internal via 57). Additionally, package 40 may define at least one throughhole 407 through the upper portion of package 40 to expose a portion of the second circuit portion 10a (e.g., a portion of the first surface 11). In some embodiments, the bottom surface (including, for example, bottom surface 221a and bottom surface 231a) of the second semiconductor device (including, for example, second semiconductor device 22a and second semiconductor device 23a) may be substantially coplanar with the bottom surface 402 of the package 40. Additionally, the peripheral surface 53 of the first circuit portion 50a may be substantially coplanar with the peripheral surface 403 of the package 40.

[0097] An electrical component 98a (e.g., a solder ball) is disposed on the lower surface 52 of the first circuit portion 50a. In some embodiments, the electrical component 98a may be disposed in the opening 405 of the package 40 and on the exposed portion of the first circuit portion 50a (i.e., the exposed portion of the internal via 57) for external connection. In some embodiments, the package 40 may seal the upper portion of the electrical component 98a, and the lower portion of the electrical component 98a may protrude downward from the bottom surface 402 of the package 40.

[0098] A shielding cover 93b is disposed on the package 40 to cover the package 40 (e.g., top surface 401 and peripheral surface 403), the peripheral surface 53 of the first circuit portion 50a, the peripheral surface 13 of the second circuit portion 10a, and the peripheral surface of the adhesive layer 81 to reduce radio frequency interference. In some embodiments, the shielding cover 93b may be electrically connected to the first circuit portion 50a. Additionally, a portion of the shielding cover 93b may extend into a through-hole 407 of the package 40 to contact an exposed portion of the second circuit portion 10a (i.e., an exposed portion of the first surface 11).

[0099] Figure 11 A cross-sectional view of a semiconductor package structure 3a, representing some embodiments of the present disclosure, is shown. The semiconductor package structure 3a is similar to... Figure 10 The semiconductor package structure 3 shown differs in the configuration of the conductive layer 56b. The conductive layer 56b can be embedded in the dielectric structure 54 of the first circuit portion 50a. Therefore, the distance between the conductive layer 56b and the circuitless region 15 of the second circuit portion 10a can be correspondingly increased to adjust the inductance value of the inductor and fine-tune the impedance matching. Figure 11 As shown, a portion of the dielectric structure 54 of the first circuit portion 50a (e.g., the second dielectric layer 542) may be located between the conductive layer 56b and the non-circuit region 15 of the second circuit portion 10a to adjust the dielectric constant between the impedance matching device (including, for example, the transformer 30a) and the conductive layer 56b.

[0100] Figures 12 to 16 This disclosure illustrates one or more stages of some embodiments of a method for manufacturing a semiconductor package structure. In some embodiments, the method is used to manufacture, for example, Figure 1 The semiconductor package structure shown is 1.

[0101] refer to Figure 12 A re-fabricated structure 10 is provided. The re-fabricated structure 10 is attached to a release layer 85 formed or disposed on a carrier 84.

[0102] The redistribution structure 10 includes a first surface 11, a second surface 12 opposite to the first surface 11, a dielectric structure 14, a circuit-free region 15, a redistribution layer 16, and a plurality of internal vias 18. The dielectric structure 14 may include a first dielectric layer 141 and at least one second dielectric layer 142. The second dielectric layer 142 may be disposed on the top surface of the first dielectric layer 141.

[0103] The circuitless region 15 extends from the first surface 11 (i.e., the top surface of the dielectric structure 14) to the second surface 12 (i.e., the bottom surface of the dielectric structure 14). That is, the thickness t1 of the circuitless region 15 is substantially equal to the thickness t2 of the redistributed structure 10 from the first surface 11 to the second surface 12. In some embodiments, the circuitless region 15 may include a portion of the first dielectric layer 141 and a portion of the second dielectric layer 142. The redistributed layer 16 may be embedded in the dielectric structure 14 and may include a plurality of circuit layers 162. The redistributed layer 16 may be disposed outside the circuitless region 15. That is, the circuit layers 162 may not extend into the circuitless region 15. An internal via 18 may electrically connect at least one circuit layer 162 or two adjacent circuit layers 162 of the redistributed layer 16. Additionally, the internal via 18 may gradually narrow towards the second surface 12. Figure 12 As shown, the topmost second dielectric layer 142 can cover the topmost circuit layer 162 and can define multiple openings to expose portions of the topmost circuit layer 162.

[0104] refer to Figure 13 The impedance matching device (including, for example, transformer 30) and at least one semiconductor device 21 are electrically connected to the redistribution structure 10. In some embodiments, the impedance matching device (including, for example, transformer 30) may be spaced apart from the non-circuit region 15 by at least one first electrical contact (including, for example, electrical contact 94 and electrical contact 94a).

[0105] In some embodiments, Figure 13 Impedance matching devices (including, for example, transformer 30) can be used with Figures 1 to 4 The impedance matching devices (including, for example, transformer 30) are the same.

[0106] Figure 13 The semiconductor device 21 (e.g., a power amplifier) ​​can be used with Figures 1 to 4 The semiconductor device 21 (e.g., a power amplifier) ​​is the same.

[0107] See Figure 14 A package 41 is formed to seal the semiconductor device 21 and impedance matching devices (including, for example, a transformer 30). The material of the package 41 may be a molding compound with or without fillers. In some embodiments, a portion of the package 41 may be disposed between the first impedance matching circuit 32 and the circuitless region 15 of the redistribution structure 10, and no bonding materials (e.g., solder balls or solder bumps) are disposed in this portion of the package 41. The package 41 has a top surface 411 and a bottom surface 412 opposite to the top surface 411.

[0108] See Figure 15The carrier 84 and release layer 85 are removed, and a plurality of third electrical contacts 96 are formed or disposed on the re-fabricated structure 10 for external connection. In some embodiments, the third electrical contacts 96 may be electrically connected to the internal through-holes 18 of the re-fabricated structure 10.

[0109] refer to Figure 16 Simultaneously, a single-layer package 41 and a re-layout structure 10 are formed to create the peripheral surface 13 of the re-layout structure 10 and the peripheral surface 413 of the package 41. Subsequently, a shielding layer 91 is formed to cover the package 41 (e.g., top surface 411 and peripheral surface 413) and the peripheral surface 13 of the re-layout structure 10 to obtain... Figure 1 The semiconductor package structure 1. In some embodiments, the shielding layer 91 may be electrically connected to the redistribution structure 10. In some embodiments, the peripheral surface 13 of the redistribution structure 10 may be substantially coplanar with the peripheral surface 413 of the package body 41.

[0110] Figures 17 to 26 This disclosure illustrates one or more stages of some embodiments of a method for manufacturing a semiconductor package structure. In some embodiments, the method is used to manufacture, for example, Figure 3 Semiconductor packaging structure 2 is shown.

[0111] See Figure 17 A conductive structure 50 is provided. The conductive structure 50 is attached to a release layer 87 formed or disposed on a carrier 86. Figure 17 The conductive structure 50 can be with Figure 3 and Figure 4 The conductive structure is the same as that of 50.

[0112] refer to Figure 18 A first impedance matching device 4, a second impedance matching device 6, and at least one impedance matching device 72 are disposed on the conductive structure 50. In some embodiments, the resolution of the first impedance matching device 4 may be different from the resolution of the second impedance matching device 6. In addition, the first impedance matching device 4 may be aligned with the conductive layer 56 (i.e., the ground plane) of the conductive structure 50. Figure 18 The first impedance matching device 4 can be with Figure 3 and Figure 4 The lower resolution impedance matching device 4 is the same. Figure 18 The second impedance matching device 6 can be connected with Figure 3 and Figure 4 The higher resolution impedance matching device 6 is the same. Figure 18 The impedance matching device 72 can be used with Figure 3 The impedance matching device 72 is the same.

[0113] refer to Figure 19An encapsulation 43 is formed on the conductive structure 50 to seal the first impedance matching device 4, the second impedance matching device 6, and the impedance matching device 72. That is, the first shielding layer 91 can be disposed between the first encapsulation 41 and the encapsulation 43, and the second shielding layer 92 can be disposed between the second encapsulation 42 and the encapsulation 43. In some embodiments, Figure 19 The package 43 can be with Figure 3 and Figure 4 The same as the package 43.

[0114] refer to Figure 20 The carrier 86 and release layer 87 are removed, and at least one semiconductor device (including, for example, semiconductor device 22 and semiconductor device 23) is disposed on the lower surface 52 of the conductive structure 50. In some embodiments, Figure 20 The semiconductor device (including, for example, semiconductor device 22 and semiconductor device 23) can be used with Figure 3 and Figure 4 The semiconductor devices (including, for example, semiconductor devices 22 and 23) are the same.

[0115] refer to Figure 21 An encapsulation 44 is formed on the lower surface 52 of the conductive structure 50 to seal the semiconductor device (including, for example, semiconductor device 22 and semiconductor device 23).

[0116] refer to Figure 22 A portion of the package 44 is removed, for example, by grinding, to expose the bottom surface (including, for example, bottom surface 221 and bottom surface 231) of the semiconductor device (including, for example, semiconductor device 22 and semiconductor device 23). In some embodiments, the bottom surface (including, for example, bottom surface 221 and bottom surface 231) of the semiconductor device (including, for example, semiconductor device 22 and semiconductor device 23) may be substantially coplanar with the bottom surface 442 of the package 44.

[0117] refer to Figure 23 At least one opening 445 is formed through the package 44 to expose a portion of the conductive structure 50 (e.g., a portion of the internal via 57).

[0118] refer to Figure 24 Solder material 88 is formed in the opening 445 and on the exposed portion of the conductive structure 50 (i.e., the exposed portion of the internal via 57). In some embodiments, the bottom surface of the solder material 88 may be substantially coplanar with the bottom surface 442 of the package 44.

[0119] refer to Figure 25Reflow soldering material 88 is used to form at least one electrical element 98 in the opening 445 and the exposed portion of the conductive structure 50 (i.e., the exposed portion of the internal via 57) for external connection. In some embodiments, the lower portion of the electrical element 98 may protrude downward from the bottom surface 442 of the package 44.

[0120] refer to Figure 26 Simultaneously, the package 43, package 44, and conductive structure 50 are separately formed to create the peripheral surface 433 of the package 43, the peripheral surface 53 of the conductive structure 50, and the peripheral surface 443 of the package 44. Subsequently, a shielding cover 93 is formed to cover the package 43 (e.g., top surface 431 and peripheral surface 433), the peripheral surface 53 of the conductive structure 50, and the peripheral surface 443 of the package 44 to obtain... Figure 3 2. Semiconductor packaging structure.

[0121] Figures 27 to 36 This disclosure illustrates one or more stages of some embodiments of a method for manufacturing a semiconductor package structure. In some embodiments, the method is used to manufacture, for example, Figure 10 Semiconductor packaging structure 3 is shown.

[0122] refer to Figure 27 A first circuit portion 50a is provided, and an adhesive layer 81 is formed or disposed on the first circuit portion 50a. The first circuit portion 50a is attached to a release layer 87' formed or disposed on a carrier 86'. Figure 27 The first circuit section 50a can be connected with Figure 10 The first circuit portion 50a is the same. In some embodiments, an adhesive layer 81 may be formed or disposed on the upper surface 51 of the first circuit portion 50a. In addition, the adhesive layer 81 may cover the conductive layer 56 (i.e., the ground plane).

[0123] refer to Figure 28 The second circuit portion 10a is bonded to the first circuit portion 50a by an adhesive layer 81 disposed between the first circuit portion 50a and the second circuit portion 10a. In some embodiments, Figure 28 The second circuit section 10a can be connected with Figure 10 The second circuit section 10a is the same.

[0124] refer to Figure 29 The carrier 86' and release layer 87' are removed, and at least one via 82 is formed to electrically connect the first circuit portion 50a to the second circuit portion 10a. Therefore, the first circuit portion 50a, the second circuit portion 10a, the adhesive layer 81, and the via 82 can constitute a conductive structure 8. In some embodiments, Figure 29 The via 82 can be connected to Figure 10 The same as the through hole 82.

[0125] refer to Figure 30 An impedance matching device (including, for example, a transformer 30a), at least one first semiconductor device 21a, at least one electronic component 71a, and at least one impedance matching device 72a are disposed on the second circuit section 10a, and at least one second semiconductor device (including, for example, a second semiconductor device 22a and a second semiconductor device 23a) is disposed on the first circuit section 50a. Figure 30 Impedance matching devices (including, for example, transformer 30a) can be used with Figure 10 The impedance matching devices (including, for example, transformer 30a) are the same. Figure 30 The first semiconductor element 21a can be with Figure 10 The first semiconductor element 21a is the same. Figure 30 The electronic component 71a can be used with Figure 10 The electronic component 71a is the same. Figure 30 The impedance matching device 72a can be used with Figure 10 The impedance matching device 72a is the same. Figure 30 The second semiconductor device (including, for example, second semiconductor device 22a and second semiconductor device 23a) can be coupled with Figure 10 The second semiconductor device (including, for example, the second semiconductor device 22a and the second semiconductor device 23a) is the same.

[0126] refer to Figure 31 A package 40 is formed to seal a first circuit portion 50a, a second circuit portion 10a, an impedance matching device (including, for example, a transformer 30a), a first semiconductor element 21a, an electronic component 71a, an impedance matching device 72a, and a second semiconductor device (including, for example, a second semiconductor device 22a and a second semiconductor device 23a). In some embodiments, the package 40 may include a lower portion below the first circuit portion 50a and an upper portion above the second circuit portion 10a.

[0127] refer to Figure 32 A portion of the package 40 (e.g., a portion of the lower portion) is removed by, for example, grinding to expose the bottom surface (e.g., bottom surface 221a and bottom surface 231a) of the second semiconductor device (e.g., second semiconductor device 22a and second semiconductor device 23a). In some embodiments, the bottom surface (e.g., bottom surface 221a and bottom surface 231a) of the second semiconductor device (e.g., second semiconductor device 22a and second semiconductor device 23a) may be substantially coplanar with the bottom surface 402 of the package 40.

[0128] refer to Figure 33At least one opening 405 is formed through the lower portion of the package 40 to expose a portion of the first circuit portion 50a (e.g., a portion of the internal via 57), and at least one through hole 407 is formed through the upper portion of the package 40 to expose a portion of the second circuit portion 10a (e.g., a portion of the first surface 11).

[0129] refer to Figure 34 Solder material 88a is formed in the opening 405 and on the exposed portion of the first circuit portion 50a (i.e., the exposed portion of the internal via 57). In some embodiments, the bottom surface of the solder material 88a may be substantially coplanar with the bottom surface 402 of the package 40.

[0130] refer to Figure 35 Reflow soldering material 88a is used to form at least one electrical component 98a in the opening 405 and on the exposed portion of the first circuit portion 50a (i.e., the exposed portion of the internal via 57) for external connection. In some embodiments, the lower portion of the electrical component 98a may protrude downward from the bottom surface 402 of the package 40.

[0131] refer to Figure 36 Simultaneously, a single-component package 40, a first circuit portion 50a, and a second circuit portion 10a are formed to create a peripheral surface 403 of the package 40, a peripheral surface 53 of the first circuit portion 50a, and a peripheral surface 13 of the second circuit portion 10a. Subsequently, a shielding cover 93b is formed to cover the package 40 (e.g., top surface 401, peripheral surface 403, and through-hole 407), the peripheral surface 53 of the first circuit portion 50a, and the peripheral surface 13 of the second circuit portion 10a, to obtain... Figure 10 3. Semiconductor packaging structure.

[0132] Unless otherwise stated, spatial descriptions such as “above,” “below,” “up,” “left,” “right,” “lower,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “above,” “below,” “upper,” “above,” “below,” etc., indicate relative to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged in space in any orientation or manner, the limitation being that the advantage of the embodiments of this disclosure is not affected by such arrangement.

[0133] As used herein, the terms “approximately,” “generally,” “substantially,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms can refer to examples where the event or situation clearly occurred and examples where the event or situation is very close to occurring. For example, when used in conjunction with numerical values, the terms can refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two numerical values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two numerical values ​​can be considered “substantially” the same or equal.

[0134] If the displacement between two surfaces is no greater than 5 µm, 2 µm, 1 µm, or 0.5 µm, then the two surfaces are considered to be coplanar or substantially coplanar. If the displacement between the highest and lowest points of a surface is no greater than 5 µm, 2 µm, 1 µm, or 0.5 µm, then the surface is considered to be substantially flat.

[0135] As used herein, unless the context clearly indicates otherwise, the singular terms “a” and “the” may include multiple indicators.

[0136] As used herein, the terms “conductive,” “electrically conductive,” and “electrical conductivity” refer to the ability to conduct electric current. Conductive materials are generally those that exhibit very little or no resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Typically, conductive materials have a conductivity greater than approximately 10. 4 S / m (e.g., at least 10) 5 S / m or at least 10 6 A material with an electrical conductivity of (S / m). The electrical conductivity of the material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of the material is measured at room temperature.

[0137] Additionally, quantities, ratios, and other values ​​are sometimes presented in range format in this document. It should be understood that such range format is for convenience and brevity and should be interpreted flexibly to include not only values ​​explicitly specified as range limits, but also all individual values ​​or subranges covered within the range, as if each value and subrange were explicitly specified.

[0138] While this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions for equivalents may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Due to manufacturing processes and tolerances, the process reproduction in this disclosure may differ from actual equipment. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of the invention. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the invention. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of this disclosure.

Claims

1. A semiconductor package structure comprising: Conductive structure; A first impedance matching device is disposed on the conductive structure; and A second impedance matching device is disposed on the conductive structure and includes a redistribution structure and a first electronic element electrically connected to the redistribution structure.

2. The semiconductor packaging structure according to claim 1, wherein the first electronic component comprises a surface acoustic wave filter or a bulk acoustic wave filter.

3. The semiconductor package structure according to claim 1, wherein the first impedance matching device includes an inductor, a resistor, or a capacitor.

4. The semiconductor package structure according to claim 1, wherein the accuracy of the first impedance matching device in modulating the circuit impedance of the semiconductor package structure is within a first range, and the accuracy of the second impedance matching device in modulating the circuit impedance of the semiconductor package structure is within a second range, wherein the first range is greater than the second range.

5. The semiconductor package structure according to claim 1, wherein the resolution of the first impedance matching device in modulating the circuit impedance of the semiconductor package structure is less than the resolution of the second impedance matching device in modulating the circuit impedance of the semiconductor package structure.

6. The semiconductor packaging structure according to claim 1, further comprising: A first package is disposed on the resilient structure to seal the resilient structure and the electronic components.

7. The semiconductor packaging structure according to claim 6, further comprising: An encapsulation is disposed on the conductive structure to seal the first impedance-matching device and the first encapsulation.

8. The semiconductor packaging structure according to claim 1, wherein the redistribution structure is electrically connected to the conductive structure through a plurality of electrical contacts.

9. A semiconductor package structure comprising: The first redistribution structure includes a circuitless region; A first impedance matching device is placed on the circuitless area of ​​the first redistribution structure; and A first electronic component is disposed on the first re-layout structure and electrically connected to the first impedance matching device via the first re-layout structure; and A shielding layer covers the first electronic component and is electrically connected to the first reconstituted structure.

10. The semiconductor package structure of claim 9, wherein the first electronic component comprises a power amplifier.

11. The semiconductor package structure according to claim 9, wherein the first impedance matching device comprises a transformer.

12. The semiconductor packaging structure according to claim 9, further comprising: The substrate is stacked perpendicularly to the first overlapping structure. and The second electronic component is disposed below the substrate and the first repetitive structure.

13. The semiconductor packaging structure according to claim 12, further comprising: The package is placed below the first revegetated structure to seal the second electronic component.

14. The semiconductor packaging structure according to claim 13, further comprising: Electrical components are housed within an opening in the package for external connection.

15. The semiconductor packaging structure according to claim 9, further comprising: The first package seals the first impedance matching device and the first electronic component.

16. A semiconductor package structure comprising: The redistribution structure includes the first and second zones; and An impedance matching device is disposed above the first region and the second region, wherein the first region is used to adjust the inductance value of the impedance matching device, and the second region is used to electrically connect the impedance matching device via electrical contacts.

17. The semiconductor package structure of claim 16, wherein the electrical contacts do not overlap the second region.

18. The semiconductor packaging structure according to claim 16, further comprising: The substrate is stacked perpendicularly to the impedance matching device of the redistribution structure. and Multiple electrical contacts electrically connect the substrate to the redistribution structure, wherein the multiple electrical contacts do not overlap perpendicularly with the first region.

19. The semiconductor packaging structure according to claim 18, further comprising: A first package seals the surface of the substrate, wherein the side of the first package is flush with the side of the substrate; and The second package seals the surface of the resilient structure, wherein the side of the second package is flush with the side of the resilient structure, wherein the first package and the second package are horizontally stacked, and wherein the width of the first package is different from the width of the second package.

20. The semiconductor packaging structure of claim 16, wherein the line density in the second region is greater than the line density in the first region.

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