Packaging structure and preparation method thereof

Abstract

The invention provides a packaging structure and a preparation method thereof, and the method comprises the steps: providing a substrate provided with a plurality of vertical conductive columns, providing a middle interconnection structure which comprises a middle interconnection layer, a top dielectric layer and a plurality of top conductive columns, and carrying out the inverted bonding of the middle interconnection structure on the substrate, thereby obtaining an interconnection substrate structure; forming a solder mask layer on two opposite surfaces of the interconnection substrate structure, and forming a first contact hole and a second contact hole in the solder mask layer; forming first conductive connecting parts and second conductive connecting parts, wherein the distance between two adjacent first conductive connecting parts is smaller than the distance between two adjacent second conductive connecting parts; and providing a first type of chip and bonding the first type of chip on the first conductive connection part. According to the invention, while the cost is reduced and the process is simplified, stable, high-density and high-speed interconnection between the chip and the packaging substrate is realized. In addition, the package substrate provided by the invention effectively reduces the power impedance by providing a direct connection power supply path.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing technology, and relates to a packaging structure and its preparation method. Background Technology

[0002] Currently, advanced packaging solutions for achieving high-density interconnects mostly rely on structures such as silicon interposers and embedded interconnect bridges to realize the electrical connection between the chip and the substrate, such as TSMC's CoWoS, Intel's EMIB, and Samsung's I-Cube technologies. Although these technologies can achieve good 2.5D / 3D integration effects, they still have obvious limitations: First, the silicon interposer process is complex and extremely expensive; second, existing interconnect structures have stringent requirements for process precision and material performance, making it difficult for traditional packaging substrate manufacturers to adapt quickly; third, signal integrity and thermal management face challenges in multi-layer stacked architectures.

[0003] Therefore, how to provide a packaging structure and its fabrication method to achieve stable, high-density, and high-speed interconnection between the chip and the packaging substrate while reducing costs and simplifying the process has become an important problem that needs to be solved by those skilled in the art.

[0004] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a packaging structure and its preparation method to solve the problems of complex high-density interconnect packaging process and extremely high cost in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a method for preparing an encapsulation structure, comprising the following steps:

[0007] A substrate is provided, the substrate including a core layer and a multilayer substrate add-on layer covering two opposite sides of the core layer and electrically connected to the core layer. The upper surface of the core layer includes a first region and a second region surrounding the first region. The multilayer substrate add-on layer covering the upper surface of the core layer includes a first portion located on the first region and a second portion located on the second region. A plurality of vertical conductive pillars are disposed in the outermost layer of the substrate add-on layer in the first portion. The vertical conductive pillars penetrate the outermost layer of the substrate add-on layer in the first portion and are electrically connected to the next adjacent layer of the substrate add-on layer.

[0008] An intermediate interconnect structure is provided, the intermediate interconnect structure including an intermediate interconnect layer, a top dielectric layer and a plurality of top conductive pillars, the top dielectric layer being located on the intermediate interconnect layer, and the top conductive pillars penetrating the top dielectric layer and being electrically connected to the intermediate interconnect layer;

[0009] The intermediate interconnect structure is flip-chip bonded to the outermost substrate layer of the first part, so that the top conductive pillar is connected to the vertical conductive pillar, thereby obtaining an interconnect substrate structure.

[0010] A solder resist layer is formed on both sides of the interconnect substrate structure, and a first contact hole is formed in the solder resist layer to expose the conductive portion of the intermediate interconnect structure and a second contact hole is formed to expose the outermost conductive portion of the substrate addition layer of the second part.

[0011] A first conductive connection portion is formed within the first contact hole and extending to the surface of the solder resist layer, and a second conductive connection portion is formed within the second contact hole and extending to the surface of the solder resist layer, wherein the spacing between two adjacent first conductive connection portions is smaller than the spacing between two adjacent second conductive connection portions.

[0012] A first type of chip is provided, and the first type of chip is bonded to the first conductive connection portion.

[0013] Optionally, the core board layer includes a core board and a core board circuit layer. The core board includes a first surface and a second surface disposed opposite to each other. The core board has a plurality of core board through holes, which are spaced apart and penetrate the core board. The core board circuit layer includes core board conductive lines located on the first surface and the second surface of the core board and core board conductive pillars filled in the core board through holes.

[0014] Optionally, each substrate addition layer includes an addition dielectric layer and an addition circuit layer. Addition blind vias are formed in the addition dielectric layer, and the addition circuit layer includes addition conductive lines located on the upper surface of the addition dielectric layer and addition conductive pillars filling the addition blind vias.

[0015] Optionally, the substrate has a groove of a predetermined depth, the bottom of which exposes the vertical conductive post. Forming the groove includes the following steps:

[0016] A substrate to be slotted is provided, the substrate to be slotted includes the substrate and a preset sacrificial dielectric layer covering the outermost substrate layer of the first portion;

[0017] The preset sacrificial dielectric layer is dry-etched to form the groove in the multilayer substrate add-in layer on the upper surface side of the core board layer.

[0018] Optionally, the intermediate interconnect structure is flip-bonded in the groove, and the side of the intermediate interconnect structure away from the bottom surface of the groove is not lower than the top of the sidewall of the groove.

[0019] Optionally, before forming the solder resist layer, the following steps are further included:

[0020] A bottom filler layer is formed, which fills the gap between the intermediate interconnect structure and the groove.

[0021] Optionally, the intermediate interconnect structure is flip-bonded in the groove, and the side of the intermediate interconnect structure away from the bottom surface of the groove is lower than the top of the sidewall of the groove.

[0022] Optionally, before forming the solder resist layer, the following steps are further included:

[0023] A conductive interconnect layer is formed, the conductive interconnect layer including conductive interconnect lines and a dielectric layer covering the conductive interconnect lines. The conductive interconnect lines include conductive interconnect plugs and conductive interconnect metal layers connected sequentially from bottom to top. The bottom end of the conductive interconnect plug is exposed outside the dielectric layer and electrically connected to the intermediate interconnect structure and the outermost substrate layer of the second part. The dielectric layer fills the groove and covers the intermediate interconnect structure.

[0024] Optionally, the intermediate interconnect layer includes multiple intermediate dielectric layers and multiple intermediate conductive lines embedded in the multiple intermediate dielectric layers, and multiple intermediate conductive plugs, wherein the intermediate conductive plugs are located between two adjacent intermediate conductive lines to electrically connect the two adjacent intermediate conductive lines.

[0025] Optionally, forming the intermediate interconnect structure includes the following steps:

[0026] A support substrate is provided, and a temporary bonding layer is formed on the support substrate;

[0027] A first dry film layer is formed, and the dry film layer is patterned to obtain the first intermediate conductive circuit layer.

[0028] A first intermediate dielectric layer is formed to cover the first intermediate conductive circuit layer, and the blind via is formed in the first intermediate dielectric layer;

[0029] A second intermediate conductive circuit layer is formed on the first intermediate dielectric layer, and the portion of the second intermediate conductive circuit layer filled into the blind via serves as the intermediate conductive plug between the first intermediate conductive circuit layer and the second intermediate conductive circuit layer.

[0030] Repeat the fabrication steps of forming the first intermediate dielectric layer, the blind via, the second intermediate conductive line, and the intermediate conductive plug until the required number of intermediate interconnect layers are completed;

[0031] The top dielectric layer is formed on the topmost intermediate conductive line layer of the intermediate interconnect layer, and a top blind via is formed in the top dielectric layer to expose the topmost intermediate conductive line layer.

[0032] A top-layer conductive pillar is formed in the top-layer blind via, and the top surface of the top-layer conductive pillar is exposed on the upper surface of the top-layer dielectric layer.

[0033] Optionally, before flip-bonding the intermediate interconnect structure to the outermost substrate layer of the first portion, the method further includes forming an NCF layer on the side of the intermediate interconnect structure layer where the top conductive pillar is located.

[0034] Optionally, before forming the first conductive connection portion and the second conductive connection portion, the method further includes forming a third contact hole within the solder resist layer to expose the topmost substrate additive conductive portion located on the lower surface of the core board layer.

[0035] Optionally, the method further includes the step of providing a second type of chip and flip-bonding the second type of chip to the second conductive connection portion, wherein the solder joint density of the second type of chip is less than that of the first type of chip.

[0036] The present invention also provides a packaging structure, comprising:

[0037] The substrate includes a core layer and a multilayer substrate add-on layer covering two opposite sides of the core layer and electrically connected to the core layer. The upper surface of the core layer includes a first region and a second region surrounding the first region. The multilayer substrate add-on layer covering the upper surface of the core layer includes a first portion located on the first region and a second portion located on the second region. The outermost layer of the substrate add-on layer of the first portion does not have conductive lines.

[0038] Multiple vertical conductive pillars, which penetrate the outermost layer of the substrate layer in the first part and are electrically connected to the next adjacent layer of the substrate layer.

[0039] An intermediate interconnect structure includes an intermediate interconnect layer, a top dielectric layer, and a plurality of top conductive pillars. The top dielectric layer is located on the intermediate interconnect layer. The top conductive pillars penetrate the top dielectric layer and are electrically connected to the intermediate interconnect layer. The intermediate interconnect structure is flip-chip bonded to the outermost substrate add-in layer of the first part, such that the top conductive pillars are correspondingly connected to the vertical conductive pillars.

[0040] A solder resist layer is located on opposite sides of the interconnect substrate structure, and a first contact hole is formed in the solder resist layer to expose the conductive part of the intermediate interconnect structure and a second contact hole is formed to expose the outermost conductive part of the substrate addition layer of the second part.

[0041] A first conductive connection portion and a second conductive connection portion, wherein the first conductive connection portion is located in the first contact hole and extends to the surface of the solder resist layer, and the second conductive connection portion is located in the second contact hole and extends to the surface of the solder resist layer, wherein the spacing between two adjacent first conductive connection portions is smaller than the spacing between two adjacent second conductive connection portions.

[0042] A first type of chip is bonded to the first conductive connection portion.

[0043] Optionally, the intermediate interconnect structure layer has an NCF layer on the side where the top conductive pillar is located, and the NCF layer completely fills the gap between the intermediate interconnect structure layer and the substrate add-in layer.

[0044] Optionally, the number of substrate layers in the first part is less than the number of substrate layers in the second part, so as to form a groove with a predetermined depth in the multilayer substrate layers on the upper surface side of the core board layer.

[0045] Optionally, the intermediate interconnect structure is flip-bonded in the groove, and the side of the intermediate interconnect structure away from the bottom surface of the groove is not lower than the top of the sidewall of the groove.

[0046] Optionally, the intermediate interconnect structure is flip-bonded in the groove, and the side of the intermediate interconnect structure away from the bottom surface of the groove is lower than the top of the sidewall of the groove.

[0047] Optionally, it also includes a second type of chip, which is flip-chip bonded to the second conductive connection portion, and the solder joint density of the second type of chip is less than that of the first type of chip.

[0048] As described above, the method for fabricating the packaging structure of the present invention includes the following steps: providing a substrate, the substrate including a core layer and a multilayer substrate layer covering two opposite sides of the core layer and electrically connected to the core layer, the multilayer substrate layer covering the upper surface of the core layer including a first part and a second part, a plurality of vertical conductive pillars being disposed in the outermost substrate layer of the first part, the vertical conductive pillars penetrating the outermost substrate layer of the first part and electrically connected to the next adjacent substrate layer; providing an intermediate interconnect structure, the intermediate interconnect structure including an intermediate interconnect layer, a top dielectric layer and a plurality of top conductive pillars; flip-chip bonding the intermediate interconnect structure to the outermost substrate layer of the first part to obtain an interconnect substrate structure; forming a solder resist layer on two opposite sides of the interconnect substrate structure, and forming a first contact hole and a second contact hole in the solder resist layer; forming a first conductive connection portion located in the first contact hole and extending to the surface of the solder resist layer and a second conductive connection portion located in the second contact hole and extending to the surface of the solder resist layer, the spacing between two adjacent first conductive connection portions being smaller than the spacing between two adjacent second conductive connection portions; providing a chip and bonding the chip to the first conductive connection portion. The packaging structure fabrication method of this invention uses an intermediate interconnect structure instead of a silicon interposer, which has advantages such as simple fabrication process, easy independent fabrication, and low production cost. By flip-chip bonding / embedding / burying the intermediate interconnect structure with multi-layer conductive metal interconnects onto a substrate with multi-layer substrate build-up, vertical electrical interconnection between the intermediate layer and the packaging substrate is achieved. The reverse side of the intermediate interconnect structure is connected to the flip chip, realizing high-density interconnection between two or more chips. At the same time, this packaging structure fabrication method can reduce the need for through-silicon vias (TSVs) and custom silicon embedded layers, packaging chips from different process nodes together into a single processor, realizing heterogeneous integration, and effectively reducing chip complexity and cost. In addition, the intermediate interconnect structure and the substrate provide a direct power supply path through the vertical conductive pillars, effectively reducing power supply impedance, eliminating voltage drop problems, and thus achieving a system upgrade to high-density heterogeneous integration. Attached Figure Description

[0049] Figure 1 The diagram shows a process flow chart of the method for preparing the packaging structure of the present invention.

[0050] Figure 2 The diagram shows a schematic of the substrate provided in Example 1, which illustrates the method for preparing the packaging structure of the present invention.

[0051] Figure 3 The diagram shown is a schematic diagram of the intermediate interconnect structure provided in Example 1, which illustrates the preparation method of the packaging structure of the present invention.

[0052] Figure 4 The diagram shown is a schematic of the structure obtained after providing a supporting substrate and forming a temporary bonding layer in Example 1, which illustrates the preparation method of the packaging structure of the present invention.

[0053] Figure 5 The diagram shown is a schematic diagram of the structure obtained after the formation of the first intermediate metal seed layer and the first dry film pattern transfer in Example 1, which is the preparation method of the packaging structure of the present invention.

[0054] Figure 6 The diagram shown illustrates the structure obtained by forming the first intermediate conductive line layer and the first intermediate conductive seed layer after flashing the non-patterned region in Example 1, which is a method for preparing the packaging structure of the present invention.

[0055] Figure 7 The diagram shown is a schematic diagram of the structure obtained after forming the first intermediate dielectric layer in Example 1, which is a method for preparing the packaging structure of the present invention.

[0056] Figure 8 The diagram shown is a schematic of the structure obtained after forming blind vias in the first intermediate dielectric layer in the method for preparing the packaging structure of the present invention in Example 1.

[0057] Figure 9 The diagram shown is a schematic diagram of the structure obtained after forming the second intermediate metal seed layer and the second dry film pattern transfer in Example 1, which is a method for preparing the packaging structure of the present invention.

[0058] Figure 10 The diagram shown is a schematic diagram of the structure obtained after forming the second intermediate conductive line layer in Example 1, which is a method for preparing the packaging structure of the present invention.

[0059] Figure 11 The diagram shown illustrates the structural method for preparing the packaging structure of the present invention, specifically in Example 1, which involves forming the required number of intermediate interconnect layers and the top dielectric layer.

[0060] Figure 12 The diagram shown is a schematic diagram of the structure obtained after forming the top dielectric layer and the top blind via in Example 1, which is the preparation method of the packaging structure of the present invention.

[0061] Figure 13 The diagram shown is a schematic diagram of the structure obtained after forming the top conductive pillar in Example 1, which is the preparation method of the packaging structure of the present invention.

[0062] Figure 14 The diagram shown is a schematic diagram of the structure obtained after forming the NCF layer in Example 1, which is the preparation method of the packaging structure of the present invention.

[0063] Figure 15 The diagram shown illustrates the structure obtained by flip-chip bonding the intermediate interconnect structure to the outermost substrate layer of the first part in Example 1, which is a method for preparing the packaging structure of the present invention.

[0064] Figure 16The diagram shown is a schematic diagram of the structure obtained after forming a solder resist layer, a first contact hole, and a second contact hole in Example 1, which is a method for preparing the packaging structure of the present invention.

[0065] Figure 17 The diagram shown is a schematic diagram of the structure obtained after forming the first conductive connection portion and the second conductive connection portion in Example 1, which is the preparation method of the packaging structure of the present invention.

[0066] Figure 18 The diagram shown is a schematic representation of the structure obtained by bonding a first type chip to a first conductive connection portion in Example 1, which illustrates the preparation method of the packaging structure of the present invention.

[0067] Figure 19 The diagram shown is a schematic representation of the substrate to be slotted in Example 2, illustrating the method for preparing the packaging structure of the present invention.

[0068] Figure 20 The diagram shows a substrate with a groove formed in Example 2, which is a method for preparing the packaging structure of the present invention.

[0069] Figure 21 The diagram shown illustrates the method for preparing the packaging structure of the present invention in Example 2, where an intermediate interconnect structure is flip-bonded onto the outermost substrate layer of the second part, and a bottom filling adhesive layer, a solder resist layer, a first contact hole, and a second contact hole are formed.

[0070] Figure 22 The diagram shown is a schematic diagram of the structure obtained after forming the first conductive connection portion and the second conductive connection portion in Example 2, which is the preparation method of the packaging structure of the present invention.

[0071] Figure 23 The diagram shown is a schematic representation of the structure obtained by bonding a first type chip to a first conductive connection portion in Example 2 of the method for preparing the packaging structure of the present invention.

[0072] Figure 24 The diagram shows a substrate with a groove formed in Example 3, which is a method for preparing the packaging structure of the present invention.

[0073] Figure 25 The diagram shown illustrates the structure obtained in Example 3 of the packaging structure fabrication method of the present invention, where the intermediate interconnect structure is flip-bonded onto the outermost substrate layer of the third part and a bottom filling adhesive layer is formed.

[0074] Figure 26 The diagram shown is a schematic diagram of the structure obtained after forming a conductive interconnect layer in Example 3, which is the preparation method of the packaging structure of the present invention.

[0075] Figure 27The diagram shown is a schematic diagram of the structure obtained after forming the solder resist layer, the first contact hole, and the second contact hole in Example 3, which is a method for preparing the packaging structure of the present invention.

[0076] Figure 28 The diagram shown is a schematic diagram of the structure obtained after forming the first conductive connection portion and the second conductive connection portion in Example 3, which is the preparation method of the packaging structure of the present invention.

[0077] Figure 29 The diagram shown is a schematic representation of the structure obtained by bonding a first type chip to a first conductive connection portion in Example 3 of the method for preparing the packaging structure of the present invention.

[0078] Explanation of reference numerals in the attached figures

[0079] 1 substrate 1a substrate to be slotted 11 Core layer 111 Core board 112 Core board circuit layer 1121 Core board conductive circuit 1122 Core board conductive pillars 12 Substrate Addition 12a Part One 12b Part Two 121 Addition dielectric layer 121a Preset sacrificial medium layer 122 Add-on circuit layer 1221 Added conductive circuit 1222 Addition conductive pillar 13 Vertical conductive pillar 14 Conductive pillar pads 15 groove 16 Bottom filler layer 17 conductive interconnect layer 171 Conductive interconnects 1711 Conductive interconnect plugs 1712 Conductive interconnect metal layer 172 Dielectric layer 2 Intermediate interconnect structure 21 Intermediate interconnect layer 211 Intermediate conductive layer 211a dry film layer 212 Intermediate conductive plug 213 Intermediate layer 214 Intermediate conductive seed layer 214a Intermediate metal seed layer 22 Top Dielectric Layer 23 Top conductive pillar 24 Top conductive seed layer 25 Top solder balls 26 NCF layer 3 Support substrate 4 Temporary bonding layer 5 blind hole 5a Top-level blind hole 5b First contact hole 5c Second contact hole 5d Third contact hole 6 solder mask 7 First conductive connection part 71 First conductive post 72 First solder ball 8 Second conductive connection part 81 Second conductive post 82 Second solder ball 9 Type 1 chip I First District II Second Zone L1 Spacing between two adjacent first conductive connections L2 Spacing between two adjacent second conductive connections S1~S6 step Detailed Implementation

[0080] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0081] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0082] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0083] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0084] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0085] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0086] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0087] Example 1

[0088] This embodiment provides a method for preparing a packaging structure. Please refer to [link / reference]. Figure 1 The diagram shows the process flow of this method, which includes the following steps:

[0089] S1: A substrate is provided, the substrate including a core layer and a multilayer substrate add-on layer covering two opposite sides of the core layer and electrically connected to the core layer, the upper surface of the core layer including a first region and a second region surrounding the first region, the multilayer substrate add-on layer covering the upper surface of the core layer including a first portion located on the first region and a second portion located on the second region, a plurality of vertical conductive pillars are disposed in the outermost layer of the substrate add-on layer in the first portion, the vertical conductive pillars penetrate the outermost layer of the substrate add-on layer in the first portion and are electrically connected to the next adjacent layer of the substrate add-on layer;

[0090] S2: Provide an intermediate interconnect structure, the intermediate interconnect structure including an intermediate interconnect layer, a top dielectric layer and a plurality of top conductive pillars, the top dielectric layer being located on the intermediate interconnect layer, and the top conductive pillars penetrating the top dielectric layer and being electrically connected to the intermediate interconnect layer;

[0091] S3: The intermediate interconnect structure is flip-bonded to the outermost substrate layer of the first part, so that the top conductive pillar is connected to the vertical conductive pillar, thereby obtaining an interconnect substrate structure.

[0092] S4: A solder resist layer is formed on both sides of the interconnect substrate structure, and a first contact hole is formed in the solder resist layer to expose the conductive part of the intermediate interconnect structure and a second contact hole is formed to expose the outermost conductive part of the substrate layer added to the second part.

[0093] S5: A first conductive connection portion is formed within the first contact hole and extends to the surface of the solder resist layer, and a second conductive connection portion is formed within the second contact hole and extends to the surface of the solder resist layer, wherein the spacing between two adjacent first conductive connection portions is smaller than the spacing between two adjacent second conductive connection portions.

[0094] S6: Provide a first type of chip and bond the first type of chip to the first conductive connection portion.

[0095] The following section, using a structural diagram, details the specific implementation methods for each of the above steps.

[0096] First, please refer to Figure 2 Step S1 is performed as follows: A substrate 1 is provided. The substrate 1 includes a core layer 11 and a multilayer substrate layer 12 covering two opposite sides of the core layer 11 and electrically connected to the core layer 11. The upper surface of the core layer 11 includes a first region I and a second region II surrounding the first region I. The multilayer substrate layer 12 covering the upper surface of the core layer 11 includes a first portion 12a located on the first region I and a second portion 12b located on the second region II. A plurality of vertical conductive pillars 13 are disposed in the outermost layer of the substrate layer 12 in the first portion 12a. The vertical conductive pillars 13 penetrate the outermost layer of the substrate layer 12 in the first portion 12a and are electrically connected to the next adjacent layer of the substrate layer 12. The spacing between the conductive pillars in the first portion 12a region is smaller than the spacing between the conductive pillars in the second portion 12b region.

[0097] As an example, the core board layer 11 includes a core board 111 and a core board 111 circuit layer 112. The core board 111 includes a first surface and a second surface disposed opposite to each other. The core board 111 has a plurality of core board 111 through holes, which are spaced apart and penetrate the core board 111. The core board 111 circuit layer 112 includes core board 111 conductive lines 1121 located on the first surface and the second surface of the core board 111 and core board 111 conductive posts 1122 filled in the core board 111 through holes.

[0098] As an example, the core board 111 includes any one of organic core board 111, glass core board 111 and ceramic core board 111.

[0099] As an example, each substrate addition layer 12 includes an addition dielectric layer 121 and an addition circuit layer 122. An addition blind via 5 is formed in the addition dielectric layer 121. The addition circuit layer 122 includes an addition conductive line 1221 located on the upper surface of the addition dielectric layer 121 and an addition conductive post 1222 filled in the addition blind via 5.

[0100] As an example, the top surface of the vertical conductive post 13 is electrically connected to a conductive post pad 14.

[0101] Please see again Figures 3 to 13 Step S2 is performed: an intermediate interconnect structure 2 is provided, the intermediate interconnect structure 2 includes an intermediate interconnect layer 21, a top dielectric layer 22 and a plurality of top conductive pillars 23, the top dielectric layer 22 is located on the intermediate interconnect layer 21, and the top conductive pillars 23 penetrate the top dielectric layer 22 and are electrically connected to the intermediate interconnect layer 21.

[0102] As an example, the intermediate interconnect layer 21 includes multiple intermediate dielectric layers 213 and multiple intermediate conductive lines 211 embedded in the multiple intermediate dielectric layers 213 and a plurality of intermediate conductive plugs 212, wherein the intermediate conductive plugs 212 are located between two adjacent intermediate conductive lines 211 to electrically connect the two adjacent intermediate conductive lines 211.

[0103] As an example, forming the intermediate interconnect structure 2 includes the following steps:

[0104] (1) such as Figure 4 As shown, a support substrate 3 is provided, and a temporary bonding layer 4 is formed on the support substrate 3;

[0105] As an example, the supporting substrate 3 includes any one of organic copper-clad laminate, glass substrate, metal substrate, polymer substrate, ceramic substrate, or semiconductor substrate. The supporting substrate 3 serves a supporting function, and its dimensions are 515mm × 510mm with a thickness ranging from 0.4 to 1.2 mm. In this embodiment, a glass substrate is selected as the supporting substrate 3. Glass substrates are low in cost and readily form a temporary bonding layer 4 on their surface, while also reducing the difficulty of subsequent peeling processes.

[0106] As an example, the material of the temporary bonding layer 4 includes thermoplastic systems, thermosetting systems, laser-degradable types, and chemically soluble types. In this embodiment, the temporary bonding layer 4 can be formed on the glass substrate 3 using a UV-degradable temporary bonding film. Specifically, a layer of temporary bonding film is spin-coated onto the glass substrate surface. The spin-coating parameters are 500 rpm for 5 seconds and 1500 rpm for 5 seconds, and the curing parameters are curing at 300°C in an N2 environment for 200 minutes. Alternatively, in this embodiment, a thermoplastic temporary bonding film can also be used to form the temporary bonding layer 4 on an organic copper-clad laminate. Specifically, a dry film-type temporary bonding material is laminated onto the surface of the organic copper-clad laminate using a laminator.

[0107] (2) such as Figure 5 and Figure 6 As shown, the first intermediate conductive line layer 211 is formed on the temporary bonding layer 4;

[0108] As an example, the first intermediate conductive layer 211 is formed using SAP (Semi-Additive Process) technology, including dry film lamination, exposure, development, patterning electroplating, film stripping, and etching processes. For details, please refer to [link to relevant documentation]. Figure 5 First, after forming the first intermediate metal seed layer 214a and the first dry film layer sequentially on the temporary bonding layer 4, the first dry film layer is exposed and developed to obtain the first patterned dry film layer 211a. Please refer to [further details omitted]. Figure 6 Then, the intermediate metal seed layer 214a that exposes the dry film layer 211a is electroplated to form the first intermediate conductive line layer 211, and then the dry film layer 211a is removed and the unplated intermediate metal seed layer 214a is etched away to form the first intermediate conductive seed layer 214.

[0109] (3) such as Figures 7 to 8 As shown, a first intermediate dielectric layer 213 is formed covering the first intermediate conductive line layer 211, and the blind via 5 is formed in the first intermediate dielectric layer 213;

[0110] (4) such as Figures 9 to 10 As shown, the second intermediate conductive line layer 211 is formed on the first intermediate dielectric layer 213, and the portion of the dry film layer of the second intermediate conductive line layer 211 filled into the blind via 5 serves as the intermediate conductive plug 212 between the first intermediate conductive line layer 211 and the second intermediate conductive line layer 211.

[0111] As an example, the second intermediate conductive layer 211 is formed using SAP (Semi-Additive Process) technology, including dry film lamination, exposure, development, patterning electroplating, film stripping, and etching processes. For details, please refer to... Figure 9 First, a second intermediate metal seed layer 214a and a second dry film layer are sequentially formed on the first intermediate dielectric layer 213. Then, the second dry film layer is exposed and developed to obtain the second patterned dry film layer 211a. Please refer to [further details omitted]. Figure 10 Then, the intermediate metal seed layer 214a that exposes the dry film layer 211a is electroplated to form the second intermediate conductive line layer 211. After that, the dry film layer 211a is removed and the unplated intermediate metal seed layer 214a is etched away to form the second intermediate conductive seed layer 214.

[0112] (5) such as Figure 11As shown, the fabrication steps of forming the first intermediate dielectric layer 213, the blind via 5, the second intermediate conductive line and the intermediate conductive plug 212 are repeated until the required number of intermediate interconnect layers 21 are completed;

[0113] (6) For example Figure 12 As shown, the top dielectric layer 22 is formed on the topmost intermediate conductive line layer 211 of the intermediate interconnect layer 21, and a top blind via 5a is formed in the top dielectric layer 22 to expose the topmost intermediate conductive line layer 211.

[0114] (7) For example Figure 13 As shown, a top conductive pillar 23 is formed in the top blind hole 5a, and the top surface of the top conductive pillar 23 is exposed on the upper surface of the top dielectric layer 22.

[0115] Specifically, intermediate conductive seed layers 214 are formed on the lower surface of the multilayer intermediate conductive circuit layer 211 and on the sidewalls and bottom surfaces of the multiple intermediate conductive plugs 212, and top conductive seed layers 24 are also formed on the sidewalls and bottom surfaces of the top conductive pillar 23.

[0116] Specifically, the intermediate conductive seed layer 214 and the top conductive seed layer 24 are formed using magnetron sputtering technology. The materials of the intermediate conductive seed layer 214 and the top conductive seed layer 24 include at least one of copper, tungsten and titanium. In this embodiment, the intermediate conductive seed layer 214 and the top conductive seed layer 24 each include a 200-nanometer-thick titanium layer and a 500-nanometer-thick copper layer located on the titanium layer.

[0117] As an example, after forming the top conductive pillar 23, the method further includes the step of forming top solder balls 25 on the top conductive pillar 23.

[0118] As an example, the minimum linewidth of the intermediate conductive line layer 211 is ≤2 micrometers, and the minimum spacing of the intermediate conductive line layer 211 is ≤2 micrometers.

[0119] As an example, methods for forming the intermediate dielectric layer 213 include pressing, coating, chemical vapor deposition, physical vapor deposition, or other suitable methods. The thickness of the intermediate dielectric layer 213 ranges from 5 micrometers to 10 micrometers.

[0120] As an example, the blind hole 5 and the top blind hole 5a can be formed by photolithography and etching processes, or by laser drilling or mechanical drilling processes. In this embodiment, laser drilling is preferred.

[0121] As an example, the diameter of the blind hole 5 is in the range of 5 micrometers to 10 micrometers, the roundness is ≥90%, and the taper value is ≥80%.

[0122] As an example, methods for forming any one of the seed layers include chemical vapor deposition, physical vapor deposition, atomic layer deposition, evaporation, magnetron sputtering, electroplating, electroless plating, or other suitable methods. This embodiment preferably employs magnetron sputtering or electroless plating.

[0123] Please see again Figures 14 to 15 Then, perform step S3: flip-chip bond the intermediate interconnect structure 2 to the outermost substrate layer 12 of the first part 12a, so that the top conductive post 23 is connected to the vertical conductive post 13, thereby obtaining an interconnect substrate 1 structure.

[0124] As an example, a top-layer solder ball 25 is also formed on the top-layer conductive pillar 23. After the intermediate interconnect structure 2 is flip-bonded to the outermost substrate layer 12 of the first portion 12a, the top-layer solder ball 25 is connected to the vertical conductive pillar 13.

[0125] Specifically, the steps for forming the top-layer solder balls 25 include: fabricating an Under Bump Metallization (UBM) layer (not shown in the figure) on the surface of the top-layer dielectric layer 22 and inside the top-layer blind via 5a using magnetron sputtering (or vapor deposition, electroless plating) technology. Subsequently, a photosensitive resist layer is laminated, a window is created above the top-layer blind via 5a using exposure and development, and copper-nickel-tin is electroplated. Then, the photosensitive resist layer in non-patterned areas is removed using a stripping solution. Finally, the electroplated tin layer is reflowed to form the top-layer solder balls using a reflow soldering machine. The UBM layer includes an adhesive layer, a barrier layer, a wetting layer, and an antioxidant layer. The adhesive layer metals include chromium, titanium, nickel, tungsten, etc.; the barrier layer metals include chromium, tungsten, titanium, nickel, etc.; the wetting layer metals include copper, nickel, palladium, etc.; and the antioxidant layer is generally a very thin layer of gold. This embodiment uses electroless nickel-palladium-gold plating.

[0126] As an example, such as Figure 14 As shown, before flip-chip bonding the intermediate interconnect structure 2 to the outermost substrate layer 12 of the first portion 12a, the method further includes forming an NCF (Non-Conductive Film) layer 26 on the side of the intermediate interconnect structure 2 where the top conductive pillar 23 is provided. After flip-chip bonding the intermediate interconnect structure 2 to the outermost substrate layer 12 of the first portion 12a, the NCF layer 26 completely fills the gap between the intermediate interconnect structure 2 and the substrate layer 12.

[0127] Specifically, the steps for forming the NCF layer 26 include: precisely pre-attaching the NCF film to the top solder ball surface of the intermediate interconnect structure. At this time, the NCF is in a "semi-cured" state, with only slight adhesion and not yet fully cured. NCF is a material that melts, flows and fills all gaps when heated and pressurized.

[0128] In other embodiments, prior to flip bonding, the process includes cutting the entire intermediate interconnect structure, along with the supporting substrate 3 and the NCF layer, into cell sizes, thereby fabricating multiple intermediate interconnect structures in a single process and saving process steps.

[0129] As an example, the intermediate interconnect structure is flip-chip bonded to the substrate add-in layer 12 using a hot-press bonding process to obtain the interconnect substrate 1 structure.

[0130] Specifically, the NCF layer 26 faces the surface of the uppermost substrate augmentation layer 12 of the first portion 12a and completely fills the gap between the intermediate interconnect structure layer and the substrate augmentation layer 12.

[0131] As an example, the method for fabricating the packaging structure further includes the step of removing the supporting substrate 3.

[0132] Specifically, the supporting substrate 3 is removed before or after flip-chip bonding the intermediate interconnect structure to the build-up dielectric layer 121. For example, a UV-degradable temporary bonding film forms a temporary bonding layer 4 on the glass substrate 3, which is then treated with a UV laser (wavelength 355nm, energy 150Mj / cm²). 2 The temporary bonding film can be irradiated through glass to cause it to dissociate and thus remove the substrate. At the same time, acetone solution can be used to remove residual adhesive. Alternatively, if a temporary bonding layer 4 is formed on an organic copper-clad laminate using a thermoplastic temporary bonding film, the film can be softened and dissociated by heating it to a specific temperature (the dissociation temperature of the temporary bonding film) in an oven, thereby removing the supporting substrate 3.

[0133] Please see again Figure 16 Step S4 is performed: a solder resist layer 6 is formed on both sides of the interconnect substrate 1 structure, and a first contact hole 5b is formed in the solder resist layer 6 to expose the conductive part of the intermediate interconnect structure and a second contact hole 5c is formed in the outermost conductive part of the substrate addition layer 12 to expose the second part 12b.

[0134] As an example, the method also includes forming a third contact hole 5d within the solder resist layer 6 to expose the conductive portion of the topmost substrate addendum 12 located on the lower surface side of the core board layer 11.

[0135] As an example, the material of the solder resist layer 6 includes a dry film type solder resist.

[0136] Specifically, the solder resist layer 6 can be formed on both sides of the substrate 1 by vacuum pressing, and the first contact hole 5b, the second contact hole 5c and the third contact hole 5d can be formed by exposing and developing the solder resist layer 6.

[0137] Please see again Figure 17 Step S5 is performed: a first conductive connection portion 7 is formed within the first contact hole 5b and extends to the surface of the solder resist layer 6, and a second conductive connection portion 8 is formed within the second contact hole 5c and extends to the surface of the solder resist layer 6. The distance L1 between two adjacent first conductive connection portions 7 is smaller than the distance L2 between two adjacent second conductive connection portions 8.

[0138] As an example, the first conductive connection portion 7 includes a first conductive post 71 and a first solder ball 72 connected sequentially from bottom to top, and the second conductive connection portion 8 includes a second conductive post 81 and a second solder ball 82 connected sequentially from bottom to top.

[0139] As an example, before electroplating metal, a plasma treatment step is included in the formation of the first conductive pillar 71 and the first conductive pillar 71 to improve the reliability quality of the first conductive pillar 71 and the first conductive pillar 71. After the formation of the first conductive pillar 71 and the first conductive pillar 71, a flash etching step is included to finish the surface of the first conductive pillar 71 and the first conductive pillar 71 and remove redundant metal.

[0140] Please see again Figure 18 Step S6 is performed: a first type chip 9 is provided, and the first type chip 9 is bonded to the first conductive connection portion 7.

[0141] Specifically, the number of the first type of chips 9 is one or more. Thanks to the small spacing between adjacent first conductive connection portions 7 (i.e., a high density of first conductive connection portions 7) and the intermediate interconnect structure being vertically electrically connected to the substrate 1 via multiple vertical conductive pillars 13, the first type of chips 9 can achieve high-density heterogeneous integration. The higher density distribution of the first conductive connection portions 7 provides more bonding points, and the intermediate interconnect structure and the vertical conductive pillars 13 provide a direct power supply path, effectively reducing power supply impedance and eliminating voltage drop issues. The coexistence of these two factors achieves high-density heterogeneous integration of the first type of chips 9. Furthermore, the first conductive connection portions 7 are electrically connected to the first type of chips 9 via first solder balls 72, achieving localized high-density interconnection between two or more first type of chips 9. This reduces the need for TSVs and custom silicon interposers, effectively reducing the complexity and cost of the first type of chips 9.

[0142] In another example, the method further includes providing a second type of chip (not shown) and flip-bonding the second type of chip to the second conductive connection portion 8. The solder joint density of the second type of chip is lower than that of the first type of chip 9, indicating that the second type of chip and the first type of chip 9 have different integration requirements. The second type of chip requires low-density integration, while the first type of chip 9 requires high-density integration. In other words, both the first conductive connection portion 7 and the second conductive connection portion 8 are bonded to the chip. The first conductive connection portion 7, with its high-density bumps, is more suitable for the first type of chip 9, which has extremely high interconnect bandwidth requirements, such as HBM / CPU / GP and high-end AI accelerators, which require a large number of I / O ports to transmit data. The second conductive connection portion 8, with its relatively low-density bumps, is more suitable for the second type of chip in scenarios with lower bandwidth requirements, such as power management chips and analog / RF chips, thereby meeting the requirement of physically isolating modules with different density requirements while maintaining system collaboration.

[0143] This embodiment provides a method for fabricating a packaging structure. This method achieves high-density heterogeneous chip integration by flip-chip bonding a substrate-free intermediate interconnect structure onto a multilayer substrate. It enables stable, high-density, and high-speed interconnection between the chip and the packaging substrate, while simultaneously meeting the requirement of physically isolating modules with different density requirements while maintaining system synergy. Compared to traditional silicon-based interposer technology, the intermediate interconnect structure in this embodiment reduces costs and simplifies the process, solving the problems of complex and extremely high-cost silicon interposer fabrication. Furthermore, the vertical electrical connection between the intermediate interconnect structure and the substrate via vertical conductive pillars provides a direct power supply path, effectively reducing power supply impedance and eliminating voltage drop issues, thus achieving a systemic upgrade to high-density heterogeneous integration.

[0144] Example 2

[0145] This embodiment provides a method for preparing a packaging structure, such as... Figures 19 to 23 As shown, the preparation method of the packaging structure in this embodiment is basically the same as that of the packaging structure in Embodiment 1, except that:

[0146] The substrate 1 has a groove 15 of a predetermined depth, the bottom of which exposes the vertical conductive post 13. Forming the groove 15 includes the following steps:

[0147] (1) Please refer to Figure 19 A slotted substrate 1a is provided, the slotted substrate 1a includes the substrate 1 and a preset sacrificial dielectric layer 121a covering the outermost substrate addition layer 12 of the first portion 12a;

[0148] (2) Please refer to Figure 20 The preset sacrificial dielectric layer 121a is dry etched to form the groove 15 in the multilayer substrate add-in layer 12 on the upper surface side of the core layer 11. The depth of the groove 15 depends on the thickness of the embedded intermediate interconnect structure 2.

[0149] Specifically, dry etching includes processes such as laser ablation, excimer laser etching, and plasma etching. In this embodiment, plasma etching is used to etch the preset sacrificial dielectric layer 121a. By adjusting the radio frequency power, gas flow type (CF4, CHF3, Ar, O2, etc.) and flow rate, cavity pressure, temperature, and etching time, the technical requirements for etching depth, rate, etching uniformity, and etching morphology are met. The etching rate range is 3 μm / min to 10 μm / min, the etching uniformity is ≤10%, and the etching temperature range is 80 ℃ to 100 ℃.

[0150] Specifically, before flip-bonding the intermediate interconnect structure 2 to the outermost substrate augmentation layer 12 of the first portion 12a, the step of forming an NCF layer 26 on the side of the intermediate interconnect structure layer where the top conductive pillar 23 is provided is not included, that is, there is no NCF layer 26 between the intermediate interconnect structure 2 and the substrate augmentation layer 12.

[0151] As an example, the intermediate interconnect structure is flip-bonded in the groove 15, and the side of the intermediate interconnect structure away from the bottom surface of the groove 15 is not lower than the top of the sidewall of the groove 15.

[0152] As an example, the following steps are included before forming the solder mask layer 6:

[0153] (1) A bottom filling adhesive layer 16 is formed, which fills the gap between the intermediate interconnect structure and the groove 15.

[0154] Specifically, capillary underfill (CUF) is applied around the groove 15 via a dispensing process, following a predetermined path (L or U-shape). The CUF flows through the gap between the intermediate interconnect structure and the substrate 1 using capillary action, filling the groove 15 to form the capillary underfill layer 16. The CUF is then cured in a vacuum pressure oven to form a mechanically stable interconnect packaging substrate. In another embodiment, the gap between the intermediate interconnect structure and the groove 15 can also be filled using a dielectric layer, or with NCF, or with a molded underfill (MUF) or other underfill materials.

[0155] The other steps of the encapsulation preparation method described in this embodiment are the same as the other steps of the encapsulation preparation method described in Embodiment 1. Please refer to Embodiment 1 for details, which will not be repeated here.

[0156] This embodiment provides a method for fabricating a packaging substrate structure. This method achieves high-density heterogeneous integration of chips by flip-chip embedding a substrate-free intermediate interconnect structure into the grooves of a multilayer substrate. It enables stable, high-density, and high-speed interconnection between the chip and the packaging substrate, while simultaneously meeting the requirement of physically isolating modules with different density requirements while maintaining system synergy. Compared to traditional silicon-based interposer technology, the intermediate interconnect structure in this embodiment reduces costs and simplifies the process, solving the problems of complex and extremely high costs associated with silicon interposers. The presence of grooves helps reduce the overall weight of the packaging substrate structure, promoting the miniaturization and lightweighting of chip packaging. Furthermore, the vertical electrical connection between the intermediate interconnect structure and the substrate via vertical conductive pillars provides a direct power supply path, effectively reducing power supply impedance and eliminating voltage drop issues, thereby achieving a systemic upgrade to high-density heterogeneous integration.

[0157] Example 3

[0158] This embodiment provides a method for preparing a packaging structure, such as... Figures 24 to 29 As shown, the preparation method of the encapsulation structure in this embodiment is basically the same as that of the encapsulation structure in Embodiment 2, except that:

[0159] like Figure 21 As shown, the intermediate interconnect structure is flip-bonded in the groove 15, and the side of the intermediate interconnect structure away from the bottom surface of the groove 15 is lower than the top of the sidewall of the groove 15.

[0160] As an example, after forming the bottom filler layer 16, the following steps are also included:

[0161] (1) A conductive interconnect layer 17 is formed, the conductive interconnect layer 17 includes conductive interconnect lines 17 and a dielectric layer 172 covering the conductive interconnect lines 17. The conductive interconnect lines 17 include conductive interconnect plugs 1711 and conductive interconnect metal layers 1712 connected sequentially from bottom to top. The bottom end of the conductive interconnect plugs 1711 is exposed outside the dielectric layer 172 and is electrically connected to the intermediate interconnect structure and the outermost substrate addition layer 12 of the second part 12b. The dielectric layer 172 fills the groove 15 and covers the intermediate interconnect structure.

[0162] Specifically, the bottom end of the conductive interconnect plug 1711 is electrically connected to the intermediate conductive circuit layer 211 and the augmentation circuit layer 122.

[0163] Specifically, the dielectric layer 172 comprises at least one of epoxy resin-based polymer materials, nitrogen-containing polymer materials, ABF, PI, fluoropolymer materials, polymaleimide triazine resin polymers, and polyphenylene ether. This embodiment uses ABF, which has a certain degree of fluidity and can fill voids under vacuum pressure.

[0164] The other steps in the preparation method of the packaging structure described in this embodiment are the same as the other steps in the preparation method of the packaging structure described in Embodiment 2. Please refer to Embodiments 1 and 2 for details, which will not be repeated here.

[0165] This embodiment provides a method for fabricating a packaging substrate structure. This method achieves high-density heterogeneous integration of chips by flip-chip embedding a substrate-free intermediate interconnect structure into a recess. It enables stable, high-density, and high-speed interconnection between the chip and the packaging substrate, while simultaneously meeting the requirement of physically isolating modules with different density requirements while maintaining system synergy. Furthermore, the complete embedding of this intermediate interconnect structure effectively enhances the electromagnetic shielding performance of the packaging substrate structure, reducing interference from external signals and ensuring efficient and stable signal transmission. Simultaneously, the vertical electrical connection between the intermediate interconnect structure and the substrate via vertical conductive pillars provides a direct power supply path, effectively reducing power supply impedance and eliminating voltage drop issues, thus achieving a systemic upgrade to high-density heterogeneous integration.

[0166] Example 4

[0167] like Figure 18As shown, this embodiment provides a packaging structure, which is obtained by the preparation method of Embodiment 1. The packaging structure includes: a substrate 1, a plurality of vertical conductive pillars 13, an intermediate interconnect structure, a solder mask layer 6, a first conductive connection portion 7, a second conductive connection portion 8, and a first type chip 9. The substrate 1 includes a core layer 11 and a multilayer substrate layer 12 covering two opposite sides of the core layer 11 and electrically connected to the core layer 11. The upper surface of the core layer 11 includes a first region I and a second region II surrounding the first region I. The multilayer substrate layer 12 covering the upper surface of the core layer 11 includes a first portion 12a located on the first region I and a second portion 12b located on the second region II. The outermost layer of the substrate layer 12 of the first portion 12a does not have conductive lines. The vertical conductive pillars 13 penetrate the outermost layer of the substrate layer 12 of the first portion 12a and are electrically connected to the next adjacent layer of the substrate layer 12. The intermediate interconnect structure includes an intermediate interconnect layer 21, a top dielectric layer 22, and a plurality of... A top conductive pillar 23 is formed, the top dielectric layer 22 is located on the intermediate interconnect layer 21, the top conductive pillar 23 penetrates the top dielectric layer 22 and is electrically connected to the intermediate interconnect layer 21, and the intermediate interconnect structure is flip-chip bonded to the outermost substrate layer 12 of the first portion 12a, such that the top conductive pillar 23 is correspondingly connected to the vertical conductive pillar 13; a solder mask layer 6 is located on opposite sides of the interconnect substrate 1 structure, and a first contact hole 5b is formed in the solder mask layer 6 to expose the conductive part of the intermediate interconnect structure and a second contact hole 5c to expose the conductive part of the outermost substrate layer 12 of the second portion 12b; a first conductive connection portion 7 is located in the first contact hole 5b and extends to the surface of the solder mask layer 6, and a second conductive connection portion 8 is located in the second contact hole 5c and extends to the surface of the solder mask layer 6, the spacing L1 between two adjacent first conductive connection portions 7 is smaller than the spacing L2 between two adjacent second conductive connection portions 8; a first type chip 9 is bonded to the first conductive connection portion 7.

[0168] As an example, the intermediate interconnect structure layer has an NCF layer 26 on one side where the top conductive pillar 23 is located, and the NCF layer 26 completely fills the gap between the intermediate interconnect structure layer and the substrate addition layer 12.

[0169] As an example, the number of substrate augmentation layers 12 in the first part 12a is less than the number of substrate augmentation layers 12 in the second part 12b, so as to form a groove 15 with a predetermined depth in the multilayer substrate augmentation layer 12 on the upper surface side of the core board layer 11.

[0170] As an example, the intermediate interconnect structure is flip-bonded in the groove 15, and the side of the intermediate interconnect structure away from the bottom surface of the groove 15 is not lower than the top of the sidewall of the groove 15.

[0171] As an example, the intermediate interconnect structure is flip-bonded in the groove 15, and the side of the intermediate interconnect structure away from the bottom surface of the groove 15 is lower than the top of the sidewall of the groove 15.

[0172] As an example, a second type of chip (not shown in the figure) is also included, which is flip-chip bonded to the second conductive connection portion 8, and the solder joint density of the second type of chip is less than that of the first type of chip 9.

[0173] The packaging structure provided in this embodiment avoids the process complexity issues in the fabrication of silicon-based intermediate layers by using a substrate-free intermediate interconnect structure, thus reducing production complexity and costs. Furthermore, this embodiment eliminates the need to form recesses within the core board layer, further simplifying the process flow. In addition, this embodiment achieves high-density heterogeneous integration of the chip, providing stable, high-density, and high-speed interconnection between the chip and the packaging substrate. It also meets the requirement of physically isolating modules with different density requirements while maintaining system synergy. Moreover, the vertical electrical connection between the intermediate interconnect structure and the substrate via vertical conductive pillars provides a direct power supply path, effectively reducing power supply impedance and eliminating voltage drop issues, thereby achieving a systemic upgrade to high-density heterogeneous integration.

[0174] Example 5

[0175] like Figure 23 As shown, this embodiment provides a packaging structure. The packaging substrate 1 structure is obtained by the preparation method of embodiment two, and its structure is basically the same as the packaging structure of embodiment four, except that:

[0176] The packaging substrate 1 further includes a groove 15, which is located in the multilayer substrate add-on layer 12 on the upper surface side of the core board layer 11. Please refer to [further details omitted]. Figure 19 The preset sacrificial dielectric layer 121a of the first portion 12a is formed by dry etching.

[0177] Specifically, the intermediate interconnect structure is flip-bonded in the groove 15, and the side of the intermediate interconnect structure away from the bottom surface of the groove 15 is not lower than the top of the sidewall of the groove 15.

[0178] The packaging substrate structure provided in this embodiment achieves high-density heterogeneous integration of chips by flip-chip embedding a substrate-free interconnect structure layer into a groove. This enables stable, high-density, and high-speed interconnection between the chip and the packaging substrate, while simultaneously meeting the requirement of physically isolating modules with different density requirements while maintaining system collaboration. Furthermore, the presence of the groove helps reduce the overall weight of the packaging substrate structure, promoting the miniaturization and lightweighting of chip packaging. Additionally, the vertical electrical connection between the intermediate interconnect structure and the substrate via vertical conductive pillars provides a direct power supply path, effectively reducing power supply impedance and eliminating voltage drop issues, thus achieving a systemic upgrade to high-density heterogeneous integration.

[0179] Example 6

[0180] like Figure 29 As shown, this embodiment provides a packaging structure. The packaging substrate structure is obtained by the preparation method of Embodiment 2, and its structure is basically the same as the packaging structure of Embodiment 5, except that:

[0181] The intermediate interconnect structure is flip-bonded in the groove 15, and the side of the intermediate interconnect structure away from the bottom surface of the groove 15 is lower than the top of the sidewall of the groove 15.

[0182] As an example, the packaging structure further includes a bottom filler adhesive layer 16 and a conductive interconnect layer 17. The bottom filler adhesive layer 16 fills the gap between the intermediate interconnect structure and the groove 15. The conductive interconnect layer 17 includes conductive interconnect lines 17 and a dielectric layer 172 covering the conductive interconnect lines 17. The conductive interconnect lines 17 include conductive interconnect plugs 1711 and conductive interconnect metal layers 1712 connected sequentially from bottom to top. The bottom end of the conductive interconnect plugs 1711 is exposed outside the dielectric layer 172 and is electrically connected to the intermediate interconnect structure and the outermost substrate addition layer 12 of the second portion 12b. The dielectric layer 172 fills the groove 15 and covers the intermediate interconnect structure.

[0183] The packaging substrate structure provided in this embodiment achieves high-density heterogeneous integration of chips by flip-chip embedding a substrate-free intermediate interconnect structure in a recess. This enables stable, high-density, and high-speed interconnection between the chip and the packaging substrate, while simultaneously meeting the requirement of physically isolating modules with different density requirements while maintaining system synergy. Furthermore, the complete embedding of this intermediate interconnect structure effectively enhances the electromagnetic shielding performance of the packaging substrate structure, reducing interference from external signals and ensuring efficient and stable signal transmission. Simultaneously, the vertical electrical connection between the intermediate interconnect structure and the substrate via vertical conductive pillars provides a direct power supply path, effectively reducing power supply impedance and eliminating voltage drop issues, thus achieving a systemic upgrade to high-density heterogeneous integration.

[0184] In summary, this invention provides a packaging structure and its fabrication method. The fabrication method includes the following steps: providing a substrate, the substrate including a core layer and a multilayer substrate augmentation layer covering two opposite sides of the core layer and electrically connected to the core layer, the upper surface of the core layer including a first region and a second region surrounding the first region, the multilayer substrate augmentation layer covering the upper surface of the core layer including a first portion located on the first region and a second portion located on the second region, the outermost substrate augmentation layer in the first portion having a plurality of vertical conductive pillars disposed therein, the vertical conductive pillars penetrating the outermost substrate augmentation layer in the first portion and electrically connected to the adjacent next substrate augmentation layer; providing an intermediate interconnect structure, the intermediate interconnect structure including an intermediate interconnect layer, a top dielectric layer and a plurality of top conductive pillars, the top dielectric layer being located on the intermediate interconnect layer, the top conductive pillars being... The pillars penetrate the top dielectric layer and are electrically connected to the intermediate interconnect layer; the intermediate interconnect structure is flip-chip bonded to the outermost substrate layer of the first part, so that the top conductive pillars and the vertical conductive pillars are connected to each other, thus obtaining an interconnect substrate structure; a solder resist layer is formed on opposite sides of the interconnect substrate structure, and a first contact hole exposing the conductive part of the intermediate interconnect structure and a second contact hole exposing the conductive part of the outermost substrate layer of the second part are formed in the solder resist layer; a first conductive connection portion is formed in the first contact hole and extends to the surface of the solder resist layer and a second conductive connection portion is formed in the second contact hole and extends to the surface of the solder resist layer, the spacing between two adjacent first conductive connection portions is smaller than the spacing between two adjacent second conductive connection portions; a first type chip is provided, and the first type chip is bonded to the first conductive connection portion. The packaging structure fabrication method of this invention uses an intermediate interconnect structure instead of a silicon interposer, offering advantages such as simple fabrication process, ease of independent fabrication, and low production cost. By flip-chip bonding / embedding / burying the intermediate interconnect structure with multi-layer conductive metal interconnects onto a substrate with multi-layer substrate add-on layers, vertical electrical interconnection between the intermediate layer and the packaging substrate is achieved. The reverse side of the intermediate interconnect structure is connected to the flip chip, realizing high-density interconnection between two or more chips. Simultaneously, this packaging structure fabrication method reduces the need for through-silicon vias (TSVs) and custom silicon embedded layers, allowing chips from different process nodes to be packaged together into a single processor, achieving heterogeneous integration and effectively reducing chip complexity and cost. Furthermore, the vertical electrical connection between the intermediate interconnect structure and the substrate via vertical conductive pillars provides a direct power supply path, effectively reducing power supply impedance and eliminating voltage drop issues, thereby achieving a system upgrade to high-density heterogeneous integration. Finally, this interconnect structure layer is fabricated at the board level, and after fabrication, it can be directly diced into unit sizes, effectively improving material utilization compared to wafer-level fabrication of silicon-based intermediate layers. This invention provides a new approach to heterogeneous integration, which is beneficial to the development of packaging substrate technology and enables FC packaging substrate products to have more powerful capabilities.At the same time, it can promote the expansion of the local high-density interconnect packaging market and give more application scenarios to products based on 2.3D packaging substrates. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial utilization value.

[0185] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing a packaging structure, characterized in that, Includes the following steps: A substrate is provided, the substrate including a core layer and a multilayer substrate add-on layer covering two opposite sides of the core layer and electrically connected to the core layer. The upper surface of the core layer includes a first region and a second region surrounding the first region. The multilayer substrate add-on layer covering the upper surface of the core layer includes a first portion located on the first region and a second portion located on the second region. A plurality of vertical conductive pillars are disposed in the outermost layer of the substrate add-on layer in the first portion. The vertical conductive pillars penetrate the outermost layer of the substrate add-on layer in the first portion and are electrically connected to the next adjacent layer of the substrate add-on layer. An intermediate interconnect structure is provided, the intermediate interconnect structure including an intermediate interconnect layer, a top dielectric layer and a plurality of top conductive pillars, the top dielectric layer being located on the intermediate interconnect layer, and the top conductive pillars penetrating the top dielectric layer and being electrically connected to the intermediate interconnect layer; The intermediate interconnect structure is flip-chip bonded to the outermost substrate layer of the first part, so that the top conductive pillar is connected to the vertical conductive pillar, thereby obtaining an interconnect substrate structure. A solder resist layer is formed on both sides of the interconnect substrate structure, and a first contact hole is formed in the solder resist layer to expose the conductive portion of the intermediate interconnect structure and a second contact hole is formed to expose the outermost conductive portion of the substrate addition layer of the second part. A first conductive connection portion is formed within the first contact hole and extending to the surface of the solder resist layer, and a second conductive connection portion is formed within the second contact hole and extending to the surface of the solder resist layer, wherein the spacing between two adjacent first conductive connection portions is smaller than the spacing between two adjacent second conductive connection portions. A first type of chip is provided, and the first type of chip is bonded to the first conductive connection portion.

2. The method for preparing the packaging structure according to claim 1, characterized in that: The core board layer includes a core board and a core board circuit layer. The core board includes a first surface and a second surface that are arranged opposite to each other. The core board has a plurality of core board through holes that are spaced apart and penetrate the core board. The core board circuit layer includes core board conductive lines located on the first surface and the second surface of the core board and core board conductive pillars filled in the core board through holes.

3. The method for preparing the packaging structure according to claim 1, characterized in that: Each substrate addition layer includes an addition dielectric layer and an addition circuit layer. Addition blind vias are formed in the addition dielectric layer. The addition circuit layer includes addition conductive lines located on the upper surface of the addition dielectric layer and addition conductive pillars filling the addition blind vias.

4. The method for preparing the packaging structure according to claim 1, characterized in that, The substrate has a groove of a predetermined depth, the bottom of which exposes the vertical conductive post. Forming the groove includes the following steps: A substrate to be slotted is provided, the substrate to be slotted includes the substrate and a preset sacrificial dielectric layer covering the outermost substrate layer of the first portion; The preset sacrificial dielectric layer is dry-etched to form the groove in the multilayer substrate add-in layer on the upper surface side of the core board layer.

5. The method for preparing the packaging structure according to claim 4, characterized in that: The intermediate interconnect structure is flip-bonded in the groove, and the side of the intermediate interconnect structure away from the bottom surface of the groove is not lower than the top of the sidewall of the groove.

6. The method for preparing the packaging structure according to claim 5, characterized in that, Before forming the solder resist layer, the following steps are also included: A bottom filler layer is formed, which fills the gap between the intermediate interconnect structure and the groove.

7. The method for preparing the packaging structure according to claim 4, characterized in that: The intermediate interconnect structure is flip-bonded in the groove, and the side of the intermediate interconnect structure away from the bottom surface of the groove is lower than the top of the sidewall of the groove.

8. The method for preparing the packaging structure according to claim 7, characterized in that, Before forming the solder resist layer, the following steps are also included: A conductive interconnect layer is formed, the conductive interconnect layer including conductive interconnect lines and a dielectric layer covering the conductive interconnect lines. The conductive interconnect lines include conductive interconnect plugs and conductive interconnect metal layers connected sequentially from bottom to top. The bottom end of the conductive interconnect plug is exposed outside the dielectric layer and electrically connected to the intermediate interconnect structure and the outermost substrate layer of the second part. The dielectric layer fills the groove and covers the intermediate interconnect structure.

9. The method for preparing the packaging structure according to claim 1, characterized in that: The intermediate interconnect layer includes multiple intermediate dielectric layers and multiple intermediate conductive lines embedded in the multiple intermediate dielectric layers, and multiple intermediate conductive plugs. The intermediate conductive plugs are located between two adjacent intermediate conductive lines to electrically connect the two adjacent intermediate conductive lines.

10. The method for preparing the packaging structure according to claim 9, characterized in that, Forming the intermediate interconnect structure includes the following steps: A support substrate is provided, and a temporary bonding layer is formed on the support substrate; The first intermediate conductive circuit layer is formed on the temporary bonding layer; A first intermediate dielectric layer is formed to cover the first intermediate conductive circuit layer, and the blind via is formed in the first intermediate dielectric layer; A second intermediate conductive circuit layer is formed on the first intermediate dielectric layer, and the portion of the second intermediate conductive circuit layer filled into the blind via serves as the intermediate conductive plug between the first intermediate conductive circuit layer and the second intermediate conductive circuit layer. Repeat the fabrication steps of forming the first intermediate dielectric layer, the blind via, the second intermediate conductive line, and the intermediate conductive plug until the required number of intermediate interconnect layers are completed; The top dielectric layer is formed on the topmost intermediate conductive line layer of the intermediate interconnect layer, and a top blind via is formed in the top dielectric layer to expose the topmost intermediate conductive line layer. A top-layer conductive pillar is formed in the top-layer blind via, and the top surface of the top-layer conductive pillar is exposed on the upper surface of the top-layer dielectric layer.

11. The method for preparing the packaging structure according to claim 1, characterized in that: Before flip-bonding the intermediate interconnect structure to the outermost substrate add-in of the first portion, the method further includes forming an NCF layer on the side of the intermediate interconnect structure layer where the top conductive pillar is provided.

12. The method for preparing the packaging structure according to claim 1, characterized in that: Before forming the first conductive connection portion and the second conductive connection portion, the method further includes forming a third contact hole within the solder resist layer to expose the topmost substrate additive conductive portion located on the lower surface of the core board layer.

13. The method for preparing the packaging structure according to claim 1, characterized in that: It also includes the step of providing a second type of chip and flip-bonding the second type of chip to the second conductive connection portion, wherein the solder joint density of the second type of chip is less than that of the first type of chip.

14. A packaging structure, characterized in that, include: The substrate includes a core layer and a multilayer substrate add-on layer covering two opposite sides of the core layer and electrically connected to the core layer. The upper surface of the core layer includes a first region and a second region surrounding the first region. The multilayer substrate add-on layer covering the upper surface of the core layer includes a first portion located on the first region and a second portion located on the second region. The outermost layer of the substrate add-on layer of the first portion does not have conductive lines. Multiple vertical conductive pillars, which penetrate the outermost layer of the substrate layer in the first part and are electrically connected to the next adjacent layer of the substrate layer. An intermediate interconnect structure includes an intermediate interconnect layer, a top dielectric layer, and a plurality of top conductive pillars. The top dielectric layer is located on the intermediate interconnect layer. The top conductive pillars penetrate the top dielectric layer and are electrically connected to the intermediate interconnect layer. The intermediate interconnect structure is flip-chip bonded to the outermost substrate add-in layer of the first part, such that the top conductive pillars are correspondingly connected to the vertical conductive pillars. A solder resist layer is located on opposite sides of the interconnect substrate structure, and a first contact hole is formed in the solder resist layer to expose the conductive part of the intermediate interconnect structure and a second contact hole is formed to expose the outermost conductive part of the substrate addition layer of the second part. A first conductive connection portion and a second conductive connection portion, wherein the first conductive connection portion is located in the first contact hole and extends to the surface of the solder resist layer, and the second conductive connection portion is located in the second contact hole and extends to the surface of the solder resist layer, wherein the spacing between two adjacent first conductive connection portions is smaller than the spacing between two adjacent second conductive connection portions. A first type of chip is bonded to the first conductive connection portion.

15. The packaging structure according to claim 14, characterized in that: The intermediate interconnect structure layer has an NCF layer on one side where the top conductive pillar is located, and the NCF layer completely fills the gap between the intermediate interconnect structure layer and the substrate add-in layer.

16. The packaging structure according to claim 14, characterized in that: The number of substrate layers in the first part is less than the number of substrate layers in the second part, so as to form a groove with a predetermined depth in the multilayer substrate layers on the upper surface side of the core board layer.

17. The packaging structure according to claim 14, characterized in that: The intermediate interconnect structure is flip-bonded in the groove, and the side of the intermediate interconnect structure away from the bottom surface of the groove is not lower than the top of the sidewall of the groove.

18. The packaging structure according to claim 14, characterized in that: The intermediate interconnect structure is flip-bonded in the groove, and the side of the intermediate interconnect structure away from the bottom surface of the groove is lower than the top of the sidewall of the groove.

19. The packaging structure according to claim 14, characterized in that: It also includes a second type of chip, which is flip-chip bonded to the second conductive connection portion, and the solder joint density of the second type of chip is less than that of the first type of chip.

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