Semiconductor packaging structure and forming method thereof

Abstract

The invention discloses a semiconductor packaging structure and a forming method thereof, and the method comprises the steps: providing a semiconductor substrate which comprises a device region and an edge region surrounding the device region, and comprises a front surface and a back surface which are opposite to each other, and a side surface located between the front surface and the back surface, a plurality of discrete through hole interconnection structures are arranged in the device region; the edge area is etched along the back face, an annular groove is formed in the edge area, and the annular groove penetrates through part of the side face; the annular groove is filled with a buffer layer; etching the back surface of the semiconductor substrate by taking the buffer layer as a mask to expose a part of height of the through hole interconnection structure; and forming a dielectric layer covering the buffer layer and the side wall of the through hole interconnection structure on the back surface of the semiconductor substrate, wherein the dielectric layer exposes the surface of one end, far away from the front surface, of the through hole interconnection structure. According to the forming method, the dielectric layer on the back edge of the semiconductor substrate can be prevented from falling off, and the yield of products is improved.

Description

Technical Field

[0001] This application relates to the field of packaging technology, and in particular to a semiconductor packaging structure and a method for forming the same. Background Technology

[0002] Silicon interposers, or silicon interposer substrates, are widely used in advanced packaging. A typical silicon interposer includes through-silicon vias (TSVs) within the interposer and a wiring layer on the front side of the interposer, which is electrically connected to the TSVs. Existing silicon interposer fabrication processes generally include: providing a silicon substrate; forming via interconnect structures in the silicon substrate; then forming a wiring layer on the front side of the silicon substrate, the wiring layer being electrically connected to the end of the via interconnect structure near the front side; subsequently, performing a backside via reveal (BVR) process on the back side of the silicon substrate, so that the back side of the silicon substrate exposes the end of the via interconnect structure away from the front side of the silicon substrate; next, forming a dielectric layer on the back side of the silicon substrate covering the exposed via interconnect structure, the dielectric layer exposing the end of the via interconnect structure away from the front side of the silicon substrate; and forming pads electrically connected to the via interconnect structure on the dielectric layer.

[0003] However, existing silicon interposers suffer from peeling of the dielectric layer at the back edge, which affects product yield. Summary of the Invention

[0004] The purpose of this application is to provide a semiconductor packaging structure and its formation method to prevent the dielectric layer from peeling off from the back edge of the semiconductor substrate and improve product yield. To achieve the above objectives, this application first provides a method for forming a semiconductor package structure, including: A semiconductor substrate is provided, the semiconductor substrate including a device region and an edge region surrounding the device region, and the semiconductor substrate including opposing front and back sides, and a side surface located between the front and back sides, the device region having a plurality of discrete through-hole interconnect structures; The edge region is etched along the back side to form an annular groove in the edge region, and the annular groove extends through a portion of the side side; A buffer layer is filled into the annular groove; Using the buffer layer as a mask, the back side of the semiconductor substrate is etched to expose a portion of the via interconnect structure; A dielectric layer is formed on the back side of the semiconductor substrate, covering the buffer layer and the sidewalls of the via interconnect structure, the dielectric layer exposing the end surface of the via interconnect structure away from the front side.

[0005] In some embodiments of this application, the material of the buffer layer is different from the material of the medium layer.

[0006] In some embodiments of this application, the material of the buffer layer includes silicon oxide, and the material of the dielectric layer includes one of silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride, or the material of the dielectric layer includes a combination of one of silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride with silicon oxide.

[0007] In some embodiments of this application, filling the annular groove with a buffer layer includes: forming a buffer material layer in the annular groove and on the back side of the semiconductor substrate; removing the buffer material layer outside the annular groove and a portion of the semiconductor substrate using a chemical mechanical polishing process until the end surface of the via interconnect structure away from the front side is exposed, and the remaining buffer material layer in the annular groove serves as the buffer layer.

[0008] In some embodiments of this application, the formation process of the dielectric layer includes: forming a dielectric material layer covering the buffer layer and the via interconnect structure on the back side of the semiconductor substrate; planarizing the dielectric material layer using a chemical mechanical polishing process until the surface of the via interconnect structure away from the front side is exposed, and the remaining dielectric material layer serves as the dielectric layer.

[0009] In some embodiments of this application, before forming the annular groove, the process further includes: planarizing the back surface of the semiconductor substrate using a chemical mechanical polishing process, and removing a portion of the thickness of the semiconductor substrate along the back surface of the semiconductor substrate.

[0010] In some embodiments of this application, the width of the annular groove is equal to the width of the edge region; The bottom surface of the annular groove is lower than the end surface of the through-hole interconnect structure that is away from the front side; Using the buffer layer as a mask, the back side of the semiconductor substrate is etched to expose a portion of the via interconnect structure. The surface of the buffer layer away from the front side is lower than the surface of the via interconnect structure away from the front side.

[0011] In some embodiments of this application, the process of forming the via interconnect structure includes: etching the semiconductor substrate along the front side of the semiconductor substrate to form a plurality of vias in the semiconductor substrate in the device region; and filling the vias with metal to form the via interconnect structure.

[0012] In some embodiments of this application, forming the via interconnect structure further includes: forming a first redistribution layer on the front side of the semiconductor substrate, wherein the first redistribution layer is electrically connected to one end of the via interconnect structure away from the back side.

[0013] In some embodiments of this application, after forming the dielectric layer, the method further includes: forming a second redistribution layer on the surface of the dielectric layer away from the back side, the second redistribution layer being electrically connected to one end of the via interconnect structure away from the front side.

[0014] This application also provides a semiconductor packaging structure, which includes: A semiconductor substrate includes a device region and an edge region surrounding the device region, and the semiconductor substrate includes opposing front and back sides, and a side surface located between the front and back sides, the device region having a plurality of discrete via interconnect structures, and the back side exposing a portion of the via interconnect structures. A buffer layer located on the surface of the edge region of the back side; A dielectric layer located on the back side covers the buffer layer and the sidewall of the via interconnect structure, the dielectric layer exposing the end surface of the via interconnect structure away from the front side.

[0015] In some embodiments of this application, the material of the buffer layer is different from the material of the medium layer.

[0016] In some embodiments of this application, the material of the buffer layer includes silicon oxide, and the material of the dielectric layer includes one of silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride, or the material of the dielectric layer includes a combination of one of silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride with silicon oxide.

[0017] In some embodiments of this application, the surface of the buffer layer away from the front side is lower than the surface of the via interconnect structure away from the front side.

[0018] In some embodiments of this application, a first redistribution layer is further included, located on the front side of the semiconductor substrate, the first redistribution layer being electrically connected to one end of the via interconnect structure away from the back side.

[0019] In some embodiments of this application, a second redistribution layer is further included, located on the surface of the dielectric layer away from the back side, the second redistribution layer being electrically connected to one end of the via interconnect structure away from the front side.

[0020] This application also provides a method for forming a semiconductor package structure, including: A semiconductor substrate is provided, the semiconductor substrate including a device region and an edge region surrounding the device region, and the semiconductor substrate including opposing front and back sides, and a side surface located between the front and back sides, the device region having a plurality of discrete through-hole interconnect structures; The back side of the semiconductor substrate is etched to expose a portion of the via interconnect structure; A ring-shaped transparent glass is attached to the edge region surface of the back side; A first dielectric layer and a second dielectric layer are sequentially formed on the back side of the semiconductor substrate, covering the through-hole interconnect junction and the annular transparent glass. Remove the annular transparent glass and the first and second dielectric layers located on the annular transparent glass together; Planarization removes the second dielectric layer and a portion of the first dielectric layer, exposing the via interconnect structure.

[0021] In some embodiments of this application, the shape of the annular transparent glass is the same as the shape of the edge region.

[0022] In some embodiments of this application, the annular transparent glass is attached to the edge region surface of the back surface using UV adhesive.

[0023] In some embodiments of this application, an annular isolation trench is further formed between the edge region on the back side and the device region; The method of attaching an annular transparent glass to the surface of the edge region on the back side includes attaching an annular transparent glass to the surface of the edge region outside the annular isolation groove.

[0024] In some embodiments of this application, the material of the first dielectric layer includes a nitrogen-containing silicide, and the material of the second dielectric layer includes silicon oxide.

[0025] In some embodiments of this application, a chemical mechanical polishing process is used to planarize and remove the second dielectric layer and a portion of the first dielectric layer.

[0026] In some embodiments of this application, the width of the annular transparent glass attached to the annular transparent glass ranges from 3mm to 6mm.

[0027] In some embodiments of this application, the step of attaching an annular transparent glass to the edge region surface of the back side is performed after the step of etching the back side of the semiconductor substrate to expose a portion of the height of the via interconnect structure.

[0028] In some embodiments of this application, the step of attaching an annular transparent glass to the edge region surface of the back side is performed before the step of etching the back side of the semiconductor substrate to expose a portion of the height of the via interconnect structure; When etching the back side of the semiconductor substrate to expose a portion of the via interconnect structure, the annular transparent glass is used as an etching barrier layer.

[0029] The beneficial effects of this application are: The present application discloses a semiconductor structure and a method for forming the same. The method includes providing a semiconductor substrate comprising a device region and an edge region surrounding the device region, and the semiconductor substrate comprising opposing front and back sides, and a side surface located between the front and back sides. The device region has a plurality of discrete via interconnect structures. The edge region is etched along the back side to form an annular groove in the edge region, the annular groove penetrating a portion of the side surface. A buffer layer is filled in the annular groove. Using the buffer layer as a mask, the back side of the semiconductor substrate is etched to expose a portion of the via interconnect structures. A dielectric layer is formed on the back side of the semiconductor substrate, covering the buffer layer and the sidewalls of the via interconnect structures, the dielectric layer exposing the end surface of the via interconnect structures away from the front side. In this application, an annular groove is formed in the edge region of the back side of a semiconductor substrate, and a buffer layer is formed in the groove. The buffer layer buffers and reduces the stress between the dielectric layer formed on the back side of the semiconductor substrate and the edge region of the back side of the semiconductor substrate, preventing stress concentration in the edge region. Furthermore, the buffer layer improves the adhesion between the dielectric layer and the edge region of the back side of the semiconductor substrate, thereby preventing the dielectric layer from peeling off in the edge region of the back side of the semiconductor substrate and improving product yield. Moreover, since the buffer layer is formed in an annular groove in the edge region, it does not or does not change the film structure of the dielectric layer subsequently formed on the device region of the back side of the semiconductor substrate. Attached Figure Description

[0030] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In addition, in the following drawings, the components are not necessarily drawn to scale, and components with similar related characteristics or features may have the same or similar reference numerals.

[0031] Figure 1This is a flowchart illustrating a method for forming a semiconductor packaging structure provided in some embodiments of this application; Figure 2 This is a schematic diagram of the structure after a semiconductor substrate is provided in the method for forming a semiconductor packaging structure provided in some embodiments of this application; Figure 3 This is a schematic diagram of the structure after forming an annular groove in the method for forming a semiconductor packaging structure provided in some embodiments of this application; Figure 4 This is a schematic diagram of the structure after forming a buffer material layer in the method for forming a semiconductor packaging structure provided in some embodiments of this application; Figure 5 This is a schematic diagram of the structure after the buffer layer is formed in the method for forming a semiconductor packaging structure provided in some embodiments of this application; Figure 6 This is a schematic diagram of the semiconductor substrate when a portion of its thickness is removed along the back side in the method for forming a semiconductor package structure provided in some embodiments of this application; Figure 7 This is a schematic diagram of the structure after the dielectric material layer is formed in the method for forming a semiconductor packaging structure provided in some embodiments of this application; Figure 8 This is a schematic diagram of the structure after the dielectric layer is formed in the method for forming a semiconductor packaging structure provided in some embodiments of this application; Figures 9-13 This is a cross-sectional structural schematic diagram of different stages in the method of forming a semiconductor package structure in other embodiments of this application; Figures 14-19 This is a cross-sectional structural schematic diagram of different stages in the method of forming a semiconductor package structure in other embodiments of this application; Figures 20-24 This is a cross-sectional structural diagram of different stages in the method of forming a semiconductor package structure in other embodiments of this application. Detailed Implementation

[0032] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0034] In the description of this application, it should be noted that the use of terms such as "first" and "second" to define objects (such as elements, components, regions, layers, doping types and / or parts) is merely for the purpose of distinguishing different objects and is not necessarily used to describe a specific order or sequence. Unless the context clearly indicates otherwise, it should be understood that such data can be used interchangeably where appropriate.

[0035] In the description of this application, it should be understood that the singular forms “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “compose” and / or “comprise” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0036] In the description of this application, it should also be noted that when a component is referred to as "on another component," "connected to another component," or "in contact with another component," it can mean not only that a component is directly on, directly connected to, or directly in contact with another component, but also that an intermediate component can be inserted between the two components. Furthermore, "connection" includes not only fixed connections but also detachable connections or integral connections. Similarly, when an element is referred to as "electrically connected," "electrically contacted," "electrically coupled," or "electrically coupled to" another element, the two elements can be in direct electrical contact or point coupling, or they can be in electrical contact or point coupling through an intermediate component.

[0037] In the description of this application, it should also be noted that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is usually based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0038] Furthermore, in the description of this application, spatial relation terms such as "below," "under," "below," "below," "below," "above," "on the upper surface of," "above," etc., can be used to describe the spatial positional relationship between one element or feature shown in the figures and other elements or features. It should be understood that spatial relation terms, in addition to the orientation shown in the figures, also include different orientations of elements or features in use and operation. For example, if an element or feature in the figures is flipped or inverted, an element or feature described as "below" or "below" other elements or features will be oriented "above" other elements or features. Furthermore, elements may also include other orientations (e.g., rotated by an angle or other orientations).

[0039] The structure of the embodiments of this application should not be limited to the specific shape shown in the accompanying drawings, but includes shape deviations due to, for example, manufacturing techniques.

[0040] It is understood that in the accompanying drawings of this application, some adjacent membrane layers with the same processed membrane material are drawn as connected to make them resemble the actual structure.

[0041] In existing silicon interposer manufacturing processes, in order for the dielectric layer to provide good protection and support for the exposed via interconnect structure on the back side of the silicon substrate, the dielectric layer generally adopts a double-layer stacked structure of silicon nitride and silicon oxide layers, with the silicon oxide layer located on top of the silicon nitride layer. However, due to the poor adhesion between silicon nitride and the silicon substrate, and the relatively concentrated stress at the outer edge of the silicon substrate after the silicon nitride layer is deposited, the silicon nitride layer film at the edge is easily detached, affecting the product yield.

[0042] Therefore, embodiments of this application provide a semiconductor packaging structure and a method for forming the same. Figure 1 This is a flowchart illustrating a method for forming a semiconductor packaging structure provided in some embodiments of this application.

[0043] refer to Figure 3 The method for forming the semiconductor package structure includes the following steps: Step S101: Provide a semiconductor substrate, the semiconductor substrate including a device region and an edge region surrounding the device region, and the semiconductor substrate including opposing front and back sides, and a side side located between the front and back sides, the device region having a plurality of discrete through-hole interconnect structures; Step S102: Etch the edge region along the back surface to form an annular groove in the edge region, and the annular groove penetrates a portion of the side surface; Step S103: Fill the annular groove with a buffer layer; Step S104: Using the buffer layer as a mask, etch the back side of the semiconductor substrate to expose a portion of the via interconnect structure. Step S105: A dielectric layer is formed on the back side of the semiconductor substrate, covering the buffer layer and the sidewalls of the via interconnect structure, the dielectric layer exposing the end surface of the via interconnect structure away from the front side.

[0044] The method for forming the semiconductor packaging structure is described in detail below with reference to the accompanying drawings in some embodiments.

[0045] First, refer to Figure 1 In conjunction with references Figure 2 In step S101, a semiconductor substrate 101 is provided. The semiconductor substrate 101 includes a device region 21 and an edge region 22 surrounding the device region 21. The semiconductor substrate 101 includes a front side and a back side opposite to each other, and a side side located between the front side and the back side. The device region 21 has a plurality of discrete through-hole interconnect structures 102.

[0046] The semiconductor substrate 101 is made of a semiconductor material, which may be silicon (Si), germanium (Ge), silicon-germanium (GeSi), or silicon carbide (SiC). In a specific example, the semiconductor substrate 101 is a silicon substrate.

[0047] The semiconductor substrate 101 includes a front side 11 and a back side 12 opposite to each other, and a side surface located between the front side 11 and the back side 12. In one example, as... Figure 2 As shown, the side of the semiconductor substrate 101 that exposes the via interconnect structure 102 is the front side 11, and the side of the semiconductor substrate 101 opposite to the front side is the back side 12. Figure 2 In the attached diagram, front side 11 faces upwards and back side 12 faces downwards. It should be noted that in subsequent manufacturing processes, for ease of illustration, front side 11 may face downwards and back side 12 may face upwards in some of the attached diagrams.

[0048] The semiconductor substrate 101 includes a device region 21 and an edge region 22 surrounding the device region 21. A plurality of discrete via interconnect structures 102 are formed in the device region 21. In some embodiments, a semiconductor device, including passive and / or active devices, may also be formed on the front side 11 of the device region 21. The semiconductor device can be electrically connected to the via interconnect structures 102. In some embodiments, the semiconductor substrate 101 may be circular or square, and correspondingly, the device region 21 may also be circular or square. The edge region 22 is annular and surrounds the device region 21.

[0049] In some embodiments, the formation process of the via interconnect structure 102 includes: forming a patterned mask layer on the front side of the semiconductor substrate 101, the patterned mask layer having a plurality of openings exposing a portion of the front side of the semiconductor substrate 101; using the patterned mask layer as a mask, etching the semiconductor substrate 101 along the front side of the semiconductor substrate 101 to form a plurality of vias in the semiconductor substrate 101 of the device region 21; and filling the vias with a metal material to form the via interconnect structure 102.

[0050] In some embodiments, the via interconnect structure 102 includes a metal layer and a diffusion-blocking layer covering the metal layer. The diffusion-blocking layer prevents metal elements in the metal layer from diffusing outward. Specifically, the diffusion-blocking layer is located on the sidewalls and bottom surface of the trench, and the metal layer is located on the diffusion-blocking layer and fills the trench. The material of the metal layer is Cu, Al, W, Ag, Au, Pt, or Ni; the material of the diffusion-blocking layer is one or more of Ti, TiN, Ta, and TaN.

[0051] In some embodiments, after forming the via interconnect structure 102, a first redistribution layer (not shown) electrically connected to the via interconnect structure 102 may be formed on the front side 11 of the semiconductor substrate 101. The first redistribution layer is electrically connected to the end of the via interconnect structure 102 away from the back side 12. The first redistribution layer includes a first dielectric layer located on the front side 11 of the semiconductor substrate 101 and a first metal wiring located in the first dielectric layer. In one example, the material of the first dielectric layer is one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxycarbide, and silicon carbonitride, and the material of the first metal wiring is one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

[0052] Next, refer to Figure 1 In conjunction with references Figure 3 In step S102, the edge region 22 is etched along the back surface 12 to form an annular groove 103 in the edge region 22, and the annular groove 103 penetrates a portion of the side surface.

[0053] The annular groove 103 is subsequently used to form a buffer layer. The buffer layer can buffer and reduce the stress between the dielectric layer subsequently formed on the back side of the semiconductor substrate 101 and the edge region 22 of the back side 12 of the semiconductor substrate 101, avoiding stress concentration in the edge region 22 of the back side 12. Furthermore, the buffer layer can also improve the bonding force between the dielectric layer and the edge region 22 of the back side 12 of the semiconductor substrate 101, thereby preventing the dielectric layer from peeling off in the edge region 22 of the back side 12 of the semiconductor substrate 101 and improving the product yield.

[0054] The annular groove 103 is annular and surrounds the device region 21. The annular groove 103 penetrates part or all of the back surface of the edge region 22 and also penetrates part of the side surface of the semiconductor substrate 101. In some embodiments, the width of the annular groove 103 is equal to the width of the edge region 22, ensuring that the buffer layer subsequently formed in the annular groove 103 has sufficient width. This allows for better buffering and reduction of stress between the formed dielectric layer and the edge region 22 of the back surface 12 of the semiconductor substrate 101 when a dielectric layer is subsequently formed on the back surface 101, thereby better preventing the dielectric layer from detaching from the edge region 22. In other embodiments, the width of the annular groove 103 may be smaller than the width of the edge region 22.

[0055] In some embodiments, the bottom surface of the annular groove 103 is lower than the end surface of the via interconnect structure 102 away from the front surface 11, so that the surface of the buffer layer formed in the annular groove 103 away from the front surface 11 will be lower than the end surface of the via interconnect structure 102 away from the front surface 11. When the dielectric layer is formed subsequently, the buffer layer will not affect the planarization process when forming the dielectric layer, so that the planarized dielectric layer can not only expose the end surface of the via interconnect structure 102 away from the front surface 11, but also cover the buffer layer.

[0056] In some embodiments, etching the edge region 22 along the back surface 12 can be performed using a dry etching process. Prior to etching, a patterned mask layer is formed on the back surface, the patterned mask layer exposing the area of ​​the edge region 22 of the back surface 13 that needs to be etched.

[0057] In some embodiments, before etching the edge region 22 along the back surface 12 to form the annular groove 103, the process further includes: planarizing the back surface 12 of the semiconductor substrate 101 using a chemical mechanical polishing process, and removing a portion of the thickness of the semiconductor substrate 101 along the back surface 12 of the semiconductor substrate 101. In a specific example, after the chemical mechanical polishing process, the distance between the back surface 12 of the semiconductor substrate 101 and the end surface of the via interconnect structure 102 away from the front surface 11 is a few micrometers (e.g., 1 micrometer to 8 micrometers).

[0058] Next, refer to Figure 1 In conjunction with references Figure 4 and Figure 5 Then proceed to step S103, where a buffer layer 105 is filled into the annular groove 103.

[0059] The buffer layer 105 is used to buffer and reduce the subsequent formation of the dielectric layer 107 on the back side of the semiconductor substrate 101 (see reference). Figure 8 The buffer layer 105 reduces stress concentration between the dielectric layer 107 and the edge region 22 of the back surface 12 of the semiconductor substrate 101, and also enhances the bonding force between the dielectric layer 107 and the edge region 22 of the back surface 12 of the semiconductor substrate 101, thereby preventing the dielectric layer 107 from detaching from the edge region 22 of the back surface 12 of the semiconductor substrate 101 and improving product yield. Furthermore, since the buffer layer 105 is formed in the annular groove 103 in the edge region 22, it does not or will not change the film structure of the dielectric layer subsequently formed on the device region 21 of the back surface 12 of the semiconductor substrate 101.

[0060] The material of the buffer layer 105 and the subsequently formed dielectric layer 107 (see reference) Figure 8 The materials used are different. In some embodiments, the buffer layer 105 is made of silicon oxide. The elastic modulus of silicon oxide is only 70-80 GPa (far lower than the 280-350 GPa of silicon nitride and the 130-180 GPa of monocrystalline silicon). It is essentially a "flexible" material. Silicon oxide can absorb some stress through its own slight deformation (such as slight stretching or compression) to prevent the stress of the subsequently formed dielectric layer 107 (the dielectric layer 107 material can be, for example, silicon nitride) from being directly transmitted to the edge region 22 of the back side 12 of the semiconductor substrate 101 (the semiconductor substrate 101 material can be, for example, monocrystalline silicon). This buffers and reduces the stress of the dielectric layer 107 (refer to) subsequently formed on the back side of the semiconductor substrate 101. Figure 8 The stress between the semiconductor substrate 101 and the edge region 22 of the back side 12 is reduced to avoid stress concentration in the edge region 22 of the back side 12.

[0061] In some embodiments, filling the buffer layer 105 in the annular groove 103 includes: reference Figure 4 A buffer material layer 104 is formed in the annular groove 103 and on the back side of the semiconductor substrate 101. The buffer material layer 104 can be formed by a material chemical vapor deposition process. (Refer to...) Figure 5 The buffer material layer 104 and part of the semiconductor substrate 101 outside the annular groove 103 are removed by chemical mechanical polishing until the end surface of the via interconnect structure 102 away from the front surface 11 is exposed. The remaining buffer material layer 104 in the annular groove 103 serves as the buffer layer 105.

[0062] refer to Figure 6 In step S104, using the buffer layer 105 as a mask, the back side of the semiconductor substrate 101 is etched to expose a portion of the via interconnect structure 102.

[0063] The purpose of exposing a portion of the via interconnect structure 102 is to allow the subsequently formed dielectric layer to cover the exposed via interconnect structure 102, thereby protecting and supporting the via interconnect structure 102.

[0064] The back side of the semiconductor substrate 101 can be etched using a dry etching process or a wet etching process, or a combination of both.

[0065] When the back side of the semiconductor substrate 101 is etched using the buffer layer 105 as a mask to expose a portion of the via interconnect structure 102, part of the buffer layer 105 will also be consumed. Therefore, when the etching is finished, the remaining surface of the buffer layer 105 away from the front side 11 is lower than the surface of the via interconnect structure 102 away from the front side.

[0066] Next, refer to Figure 1 In conjunction with references Figures 7-8 In step S105, a dielectric layer 107 is formed on the back side of the semiconductor substrate 101, covering the buffer layer 105 and the sidewalls of the via interconnect structure 102, and the dielectric layer 107 exposes the end surface of the via interconnect structure 102 away from the front side.

[0067] The material of the dielectric layer 107 is different from the material of the buffer layer 105, or the material of the dielectric layer 107 in contact with the buffer layer 105 is different from the material of the buffer layer 105. The dielectric layer 107 can be a single layer or multiple layers. In some embodiments, when the dielectric layer 107 is a single layer, the material of the dielectric layer 107 is a nitrogen-containing silicide, which includes one of silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride. In other embodiments, when the dielectric layer 107 is multi-layered, in one specific example, when the dielectric layer 107 is a double layer, the dielectric layer 107 includes a nitrogen-containing silicide layer and a silicon oxide layer located on the nitrogen-containing silicide layer, and the material of the nitrogen-containing silicide layer includes one of silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride. The dielectric layer 107 is made of nitrogen-containing silicide. Nitrogen-containing silicide has high rigidity and is not easily deformed. Therefore, the dielectric layer 107 made of nitrogen-containing silicide can provide good protection and support for the through-hole interconnect structure.

[0068] In some embodiments, the formation process of the dielectric layer 107 includes: referencing Figure 7 A dielectric material layer 106 is formed on the back side of the semiconductor substrate 101, covering the buffer layer 105 and the via interconnect structure 102. The dielectric material layer 106 is formed using a chemical vapor deposition process (e.g., PECVD). (Reference) Figure 8 The dielectric material layer 106 is planarized using a chemical mechanical polishing process until the end surface of the through-hole interconnect structure 102 away from the front surface 11 is exposed, and the remaining dielectric material layer 106 serves as the dielectric layer 107.

[0069] In some embodiments, after forming the dielectric layer 107, the method further includes forming a second redistribution layer (not shown) on the surface of the dielectric layer 107 away from the back surface 12, the second redistribution layer being electrically connected to one end of the via interconnect structure 102 away from the front surface 11. The second redistribution layer includes a second dielectric layer located on the front surface 11 of the semiconductor substrate 101 and a second metal wiring located in the second dielectric layer. In one example, the material of the second dielectric layer is one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride, or the material of the second dielectric layer is a resin (such as ABF resin, PI resin, or BT resin), and the material of the second metal wiring is one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

[0070] Some embodiments of this application also provide a semiconductor packaging structure, see reference. Figure 8 ,include: A semiconductor substrate 101 includes a device region 21 and an edge region 22 surrounding the device region 21. The semiconductor substrate 101 includes a front side 11 and a back side 12, and a side surface located between the front side 11 and the back side 12. The device region 21 has a plurality of discrete via interconnect structures 102, and the back side 12 exposes a portion of the via interconnect structures 102. The buffer layer 105 is located on the surface of the edge region 22 of the back surface 12; A dielectric layer 107 is located on the back side 12, covering the sidewalls of the buffer layer 105 and the through-hole interconnect structure 102, and the dielectric layer 107 exposes the end surface of the through-hole interconnect structure 102 away from the front side.

[0071] In some embodiments, the material of the buffer layer 105 is different from the material of the medium layer 107.

[0072] In some embodiments, the material of the buffer layer 105 includes silicon oxide, and the material of the dielectric layer 107 includes one of silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride, or the material of the dielectric layer 107 includes a combination of one of silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride with silicon oxide.

[0073] In some embodiments, the surface of the buffer layer 105 away from the front face 11 is lower than the end surface of the through-hole interconnect structure 102 away from the front face 11.

[0074] In some embodiments, the system further includes a first redistribution layer (not shown) located on the front side of the semiconductor substrate 101, the first redistribution layer being electrically connected to one end of the via interconnect structure 102 away from the back side 12.

[0075] In some embodiments, the invention further includes a second redistribution layer (not shown) located on the surface of the dielectric layer 107 away from the back side, the second redistribution layer being electrically connected to one end of the via interconnect structure 102 away from the front side 11.

[0076] This application also provides a method for forming a semiconductor package structure. Figures 9-13This is a cross-sectional structural diagram of different stages in the semiconductor packaging structure formation method in some other embodiments of this application. The difference between this embodiment and the previous embodiment is that: during the formation of the semiconductor packaging structure, an annular transparent glass is attached to the edge region surface of the back side. Then, a first dielectric layer and a second dielectric layer covering the via interconnect and the annular transparent glass are sequentially formed on the back side of the semiconductor substrate. Then, the annular transparent glass and the first and second dielectric layers located on the annular transparent glass are removed together. Finally, the second dielectric layer and part of the first dielectric layer are planarized and removed to expose the via interconnect structure. The presence of the annular transparent glass ensures that when the first and second dielectric layers are formed, the first and second dielectric layers at the edge are not directly formed on the edge region surface of the semiconductor substrate, but are formed on the surface of the annular transparent glass. Before the planarization and removal of the second dielectric layer and part of the first dielectric layer, the removal of the annular transparent glass allows the first and second dielectric layers at the edge to be removed together with the annular transparent glass, thereby avoiding the peeling of the dielectric layer at the edge of the semiconductor substrate.

[0077] refer to Figure 9 A semiconductor substrate 101 is provided, the semiconductor substrate 101 including a device region 21 and an edge region 22 surrounding the device region 21, and the semiconductor substrate 101 including opposing front side 11 and back side 12, and a side surface located between the front side 11 and the back side 12, the device region 21 having a plurality of discrete through-hole interconnect structures 102; Continuing to refer to Figure 9 The back surface 12 of the semiconductor substrate 101 is etched to expose a portion of the via interconnect structure 102.

[0078] refer to Figure 10 An annular transparent glass 115 is attached to the surface of the edge region 22 of the back side 12.

[0079] The step of attaching the annular transparent glass 115 to the edge region 22 surface of the back surface 12 is performed after the step of etching the back surface 12 of the semiconductor substrate 101 to expose a portion of the height of the through-hole interconnect structure 102.

[0080] The shape of the annular transparent glass 115 is the same as that of the edge region 22. The annular transparent glass 115 is annular with a hollow center, exposing the device area.

[0081] The width of the annular transparent glass 115 is between 3mm and 6mm, specifically 3mm, 4mm, 5mm, and 6mm.

[0082] In some embodiments, the annular transparent glass 115 is adhered to the edge region 22 of the back surface 12 using UV adhesive, with the edge of the annular transparent glass 115 flush with the edge of the semiconductor substrate 101. When the annular transparent glass 115 is subsequently removed, the UV adhesive can be irradiated with UV light to eliminate its stickiness.

[0083] refer to Figure 11 A first dielectric layer 107a and a second dielectric layer 107b are sequentially formed on the back side 12 of the semiconductor substrate 101, covering the through-hole interconnect and the annular transparent glass 115.

[0084] The first dielectric layer 107a and the second dielectric layer 107b are formed by a chemical vapor deposition process (e.g., PECVD). The material of the first dielectric layer 107a is different from that of the second dielectric layer 107b. The material of the first dielectric layer 107a includes a nitrogen-containing silicide, which includes one of silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride. The material of the second dielectric layer 107b includes silicon oxide.

[0085] Since the edge region of the semiconductor substrate 101 is attached with an annular transparent glass 115, when the first dielectric layer 107a and the second dielectric layer 107b are formed, the first dielectric layer 107a and the second dielectric layer 107b at the edge are not directly formed on the surface of the edge region 22 of the semiconductor substrate 101, but are formed on the surface of the annular transparent glass 115. Subsequently, before the second dielectric layer 107b and part of the first dielectric layer 107b are removed by planarization, the first dielectric layer 107a and the second dielectric layer 107b at the edge are removed together with the annular transparent glass 115, thereby avoiding the peeling of the dielectric layer at the edge of the semiconductor substrate 101.

[0086] refer to Figure 12 The annular transparent glass 115 and the first dielectric layer 107a and the second dielectric layer 107b located on the annular transparent glass 115 are removed together, while the first dielectric layer 107a and the second dielectric layer 107b of the device region 21 are retained.

[0087] refer to Figure 13 The second dielectric layer 107b and part of the first dielectric layer 107a are planarized to expose the via interconnect structure 102.

[0088] The second dielectric layer 107b and part of the first dielectric layer 107a are removed by chemical mechanical polishing (CMP) to remove them.

[0089] This application also provides a method for forming a semiconductor package structure. Figures 14-19This is a cross-sectional structural diagram of different stages in the semiconductor packaging structure formation method in some other embodiments of this application. The difference between this embodiment and the previous embodiment is that an annular isolation trench is formed between the edge region and the device region on the back side of the semiconductor substrate. In addition to the aforementioned effects, the annular isolation trench isolates the annular transparent glass attached to the edge region from the device region in the middle, thereby avoiding affecting the morphology of the edges (near the annular transparent glass) of the first and second dielectric layers remaining on the device region when the annular transparent glass and the first and second dielectric layers located on the annular transparent glass are removed together.

[0090] refer to Figure 14 A semiconductor substrate 101 is provided, the semiconductor substrate 101 including a device region 21 and an edge region 22 surrounding the device region 21, and the semiconductor substrate 101 including a front side 11 and a back side 12 opposite to each other, and a side surface located between the front side 11 and the back side 12, the device region 21 having a plurality of discrete via interconnect structures 102; the back side 12 of the semiconductor substrate 101 is etched to expose a portion of the height of the via interconnect structures 102.

[0091] Continue to refer to Figure 14 A photoresist layer 108 is formed on the back side of the semiconductor substrate 101; the photoresist layer 108 is exposed using a mask 109.

[0092] refer to Figure 15 After developing the photoresist layer 108, an opening is formed in the photoresist layer 108; using the photoresist layer 108 as a mask, the back side of the semiconductor substrate 101 is etched along the opening, and an annular isolation trench 110 is formed between the edge region 22 and the device region 21 of the back side 12; after forming the annular isolation trench 110, the photoresist layer 108 is removed.

[0093] The annular isolation trench 110 isolates the annular transparent glass 115 attached to the subsequent edge region 22 from the central device region 21 (see reference). Figure 16 and Figure 17 ), thereby enabling the subsequent removal of the annular transparent glass 115 and the first dielectric layer 107a and the second dielectric layer 107b located on the annular transparent glass 115 together (see reference). Figure 17 and Figure 18 To avoid affecting the morphology of the edges (near the annular transparent glass portion) of the first and second dielectric layers 107a and 107b remaining on the device region 21.

[0094] refer to Figure 16 An annular transparent glass 115 is attached to the surface of the edge region 22 of the back side 12.

[0095] refer to Figure 17 A first dielectric layer 107a and a second dielectric layer 107b are sequentially formed on the back side 12 of the semiconductor substrate 101, covering the through-hole interconnect and the annular transparent glass 115.

[0096] The first dielectric layer 107a and the second dielectric layer 107b are formed by a chemical vapor deposition process (e.g., PECVD). The material of the first dielectric layer 107a is different from that of the second dielectric layer 107b. The material of the first dielectric layer 107a includes a nitrogen-containing silicide, which includes one of silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride. The material of the second dielectric layer 107b includes silicon oxide.

[0097] Since the edge region of the semiconductor substrate 101 is attached with an annular transparent glass 115, when the first dielectric layer 107a and the second dielectric layer 107b are formed, the first dielectric layer 107a and the second dielectric layer 107b at the edge are not directly formed on the surface of the edge region 22 of the semiconductor substrate 101, but are formed on the surface of the annular transparent glass 115. Subsequently, before the second dielectric layer 107b and part of the first dielectric layer 107b are removed by planarization, the first dielectric layer 107a and the second dielectric layer 107b at the edge are removed together with the annular transparent glass 115, thereby avoiding the peeling of the dielectric layer at the edge of the semiconductor substrate 101.

[0098] refer to Figure 18 The annular transparent glass 115 and the first dielectric layer 107a and the second dielectric layer 107b located on the annular transparent glass 115 are removed together, while the first dielectric layer 107a and the second dielectric layer 107b of the device region 21 are retained.

[0099] refer to Figure 19 The second dielectric layer 107b and part of the first dielectric layer 107a are planarized to expose the via interconnect structure 102.

[0100] The second dielectric layer 107b and part of the first dielectric layer 107a are removed by chemical mechanical polishing (CMP) to remove them.

[0101] This application also provides a method for forming a semiconductor package structure. Figures 20-24This is a cross-sectional structural diagram of different stages in the semiconductor package structure formation method in some other embodiments of this application. The difference between this embodiment and the previous embodiment is that: the step of attaching the annular transparent glass to the edge region surface of the back side is performed before the step of etching the back side of the semiconductor substrate to expose a portion of the height of the via interconnect structure; when performing the step of etching the back side of the semiconductor substrate to expose a portion of the height of the via interconnect structure, the annular transparent glass is used as an etching barrier layer, thereby isolating the annular transparent glass attached to the edge region from the device region in the middle. Therefore, when the annular transparent glass and the first dielectric layer and the second dielectric layer located on the annular transparent glass are removed together, the morphology of the edges of the first dielectric layer and the second dielectric layer remaining on the device region (near the annular transparent glass portion) is avoided.

[0102] refer to Figure 20 A semiconductor substrate 101 is provided, the semiconductor substrate 101 includes a device region 21 and an edge region 22 surrounding the device region 21, and the semiconductor substrate 101 includes a front side 11 and a back side 12 opposite to each other, and a side surface located between the front side 11 and the back side 12. The device region 21 has a plurality of discrete through-hole interconnect structures 102; an annular transparent glass 115 is attached to the surface of the edge region 22 of the back side 12.

[0103] refer to Figure 21 The back surface 12 of the semiconductor substrate 101 is etched to expose a portion of the via interconnect structure 102.

[0104] When etching the back surface 12 of the semiconductor substrate 101, the annular transparent glass 115 is used as an etching barrier layer.

[0105] refer to Figure 22 A first dielectric layer 107a and a second dielectric layer 107b are sequentially formed on the back side 12 of the semiconductor substrate 101, covering the through-hole interconnect and the annular transparent glass 115.

[0106] The first dielectric layer 107a and the second dielectric layer 107b are formed by a chemical vapor deposition process (e.g., PECVD). The material of the first dielectric layer 107a is different from that of the second dielectric layer 107b. The material of the first dielectric layer 107a includes a nitrogen-containing silicide, which includes one of silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride. The material of the second dielectric layer 107b includes silicon oxide.

[0107] Since the edge region of the semiconductor substrate 101 is attached with an annular transparent glass 115, when the first dielectric layer 107a and the second dielectric layer 107b are formed, the first dielectric layer 107a and the second dielectric layer 107b at the edge are not directly formed on the surface of the edge region 22 of the semiconductor substrate 101, but are formed on the surface of the annular transparent glass 115. Subsequently, before the second dielectric layer 107b and part of the first dielectric layer 107b are removed by planarization, the first dielectric layer 107a and the second dielectric layer 107b at the edge are removed together with the annular transparent glass 115, thereby avoiding the peeling of the dielectric layer at the edge of the semiconductor substrate 101.

[0108] refer to Figure 23 The annular transparent glass 115 and the first dielectric layer 107a and the second dielectric layer 107b located on the annular transparent glass 115 are removed together, while the first dielectric layer 107a and the second dielectric layer 107b of the device region 21 are retained.

[0109] refer to Figure 24 The second dielectric layer 107b and part of the first dielectric layer 107a are planarized to expose the via interconnect structure 102.

[0110] The second dielectric layer 107b and part of the first dielectric layer 107a are removed by chemical mechanical polishing (CMP) to remove them.

[0111] During planarization, a portion of the semiconductor substrate 101 in the edge region 22 is also removed.

[0112] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0113] It should be noted that, where there is no conflict, the features in the different embodiments of this application described above can be combined with each other. Furthermore, in each of the above embodiments, the focus is on describing the differences from other embodiments; other specific descriptions of the same / similar parts between the embodiments can be referred to (or referenced) interchangeably. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this application.

[0114] Although this application has been disclosed above with reference to preferred embodiments, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications to the technical solutions of this application by utilizing the methods and techniques disclosed above without departing from the spirit and scope of this application. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall fall within the protection scope of the technical solutions of this application.

Claims

1. A method for forming a semiconductor package structure, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate including a device region and an edge region surrounding the device region, and the semiconductor substrate including opposing front and back sides, and a side surface located between the front and back sides, the device region having a plurality of discrete through-hole interconnect structures; The edge region is etched along the back side to form an annular groove in the edge region, and the annular groove extends through a portion of the side side; A buffer layer is filled into the annular groove; Using the buffer layer as a mask, the back side of the semiconductor substrate is etched to expose a portion of the via interconnect structure; A dielectric layer is formed on the back side of the semiconductor substrate, covering the buffer layer and the sidewalls of the via interconnect structure, the dielectric layer exposing the end surface of the via interconnect structure away from the front side.

2. The method for forming a semiconductor package structure according to claim 1, characterized in that, The material of the buffer layer is different from the material of the medium layer.

3. The method for forming a semiconductor package structure according to claim 2, characterized in that, The material of the buffer layer includes silicon oxide, and the material of the dielectric layer includes one of silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride, or the material of the dielectric layer includes a combination of one of silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride with silicon oxide.

4. The method for forming a semiconductor package structure according to claim 1 or 2, characterized in that, Filling the annular groove with a buffer layer includes: forming a buffer material layer in the annular groove and on the back side of the semiconductor substrate; removing the buffer material layer outside the annular groove and a portion of the semiconductor substrate using a chemical mechanical polishing process until the surface of the via interconnect structure away from the front side is exposed, with the remaining buffer material layer in the annular groove serving as the buffer layer.

5. The method for forming a semiconductor package structure according to claim 1, characterized in that, The process of forming the dielectric layer includes: forming a dielectric material layer covering the buffer layer and the via interconnect structure on the back side of the semiconductor substrate; planarizing the dielectric material layer using a chemical mechanical polishing process until the surface of the via interconnect structure away from the front side is exposed, and the remaining dielectric material layer serves as the dielectric layer.

6. The method for forming a semiconductor package structure according to claim 1, characterized in that, Before forming the annular groove, the process further includes: planarizing the back side of the semiconductor substrate using a chemical mechanical polishing process, and removing a portion of the thickness of the semiconductor substrate along the back side of the semiconductor substrate.

7. The method for forming a semiconductor package structure according to claim 1, characterized in that, The width of the annular groove is equal to the width of the edge region; The bottom surface of the annular groove is lower than the end surface of the through-hole interconnect structure that is away from the front side; Using the buffer layer as a mask, the back side of the semiconductor substrate is etched to expose a portion of the via interconnect structure. The surface of the buffer layer away from the front side is lower than the surface of the via interconnect structure away from the front side.

8. The method for forming a semiconductor package structure according to claim 1, characterized in that, The process of forming the via interconnect structure includes: etching the semiconductor substrate along the front side of the semiconductor substrate to form a plurality of vias in the semiconductor substrate in the device region; filling the vias with metal to form the via interconnect structure.

9. The method for forming a semiconductor package structure according to claim 8, characterized in that, The via interconnect structure further includes forming a first redistribution layer on the front side of the semiconductor substrate, wherein the first redistribution layer is electrically connected to one end of the via interconnect structure away from the back side.

10. The method for forming a semiconductor package structure according to claim 1, characterized in that, After forming the dielectric layer, the method further includes: forming a second redistribution layer on the surface of the dielectric layer away from the back side, the second redistribution layer being electrically connected to one end of the via interconnect structure away from the front side.

11. A semiconductor packaging structure, characterized in that, include: A semiconductor substrate includes a device region and an edge region surrounding the device region, and the semiconductor substrate includes opposing front and back sides, and a side surface located between the front and back sides, the device region having a plurality of discrete via interconnect structures, and the back side exposing a portion of the via interconnect structures. A buffer layer located on the surface of the edge region of the back side; A dielectric layer located on the back side covers the buffer layer and the sidewall of the via interconnect structure, the dielectric layer exposing the end surface of the via interconnect structure away from the front side.

12. The semiconductor packaging structure according to claim 11, characterized in that, The material of the buffer layer is different from the material of the medium layer.

13. The semiconductor packaging structure according to claim 12, characterized in that, The material of the buffer layer includes silicon oxide, and the material of the dielectric layer includes one of silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride, or the material of the dielectric layer includes a combination of one of silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride with silicon oxide.

14. The semiconductor packaging structure according to claim 11, characterized in that, The surface of the buffer layer away from the front is lower than the surface of the through-hole interconnect structure away from the front.

15. The semiconductor packaging structure according to claim 11, characterized in that, Also includes: A first redistribution layer is located on the front side of the semiconductor substrate, and the first redistribution layer is electrically connected to the end of the via interconnect structure away from the back side.

16. The semiconductor packaging structure according to claim 11, characterized in that, Also includes: A second redistribution layer is located on the surface of the dielectric layer away from the back side, and the second redistribution layer is electrically connected to one end of the via interconnect structure away from the front side.

17. A method for forming a semiconductor package structure, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate including a device region and an edge region surrounding the device region, and the semiconductor substrate including opposing front and back sides, and a side surface located between the front and back sides, the device region having a plurality of discrete through-hole interconnect structures; The back side of the semiconductor substrate is etched to expose a portion of the via interconnect structure; A ring-shaped transparent glass is attached to the edge region surface of the back side; A first dielectric layer and a second dielectric layer are sequentially formed on the back side of the semiconductor substrate, covering the through-hole interconnect junction and the annular transparent glass. Remove the annular transparent glass and the first and second dielectric layers located on the annular transparent glass together; Planarization removes the second dielectric layer and a portion of the first dielectric layer, exposing the via interconnect structure.

18. The method for forming a semiconductor package structure according to claim 17, characterized in that, The shape of the annular transparent glass is the same as the shape of the edge region.

19. The method for forming a semiconductor package structure according to claim 17 or 18, characterized in that, The annular transparent glass is attached to the edge area of ​​the back surface using UV adhesive.

20. The method for forming a semiconductor package structure according to claim 17, characterized in that, Also includes: An annular isolation trench is formed between the edge region and the device region on the back side; The method of attaching an annular transparent glass to the surface of the edge region on the back side includes attaching an annular transparent glass to the surface of the edge region outside the annular isolation groove.

21. The method for forming a semiconductor package structure according to claim 17, characterized in that, The material of the first dielectric layer includes a nitrogen-containing silicide, and the material of the second dielectric layer includes silicon oxide.

22. The method for forming a semiconductor package structure according to claim 17, characterized in that, The second dielectric layer and part of the first dielectric layer are removed by a chemical mechanical polishing process to planarize them.

23. The method for forming a semiconductor package structure according to claim 17, characterized in that, The width of the annular transparent glass attached to the annular transparent glass ranges from 3mm to 6mm.

24. The method for forming a semiconductor package structure according to claim 17, characterized in that, The step of attaching an annular transparent glass to the edge region surface of the back side is performed after the step of etching the back side of the semiconductor substrate to expose a portion of the via interconnect structure.

25. The method for forming a semiconductor package structure according to claim 17, characterized in that, The step of attaching the annular transparent glass to the edge region surface of the back side is performed before the step of etching the back side of the semiconductor substrate to expose a portion of the height of the via interconnect structure; When etching the back side of the semiconductor substrate to expose a portion of the via interconnect structure, the annular transparent glass is used as an etching barrier layer.

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