Semiconductor package

Abstract

A semiconductor package includes: a base chip; a plurality of first semiconductor chips each having a first horizontal width; and a plurality of second semiconductor chips each having a second horizontal width different from the first horizontal width. The plurality of first semiconductor chips and the plurality of second semiconductor chips are alternately stacked on the base chip. An adhesive layer is between adjacent semiconductor chips of the plurality of first semiconductor chips and the plurality of second semiconductor chips that are alternately stacked.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0120316, filed on September 4, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The present invention relates to semiconductor packages, and more specifically, to semiconductor packages comprising a plurality of semiconductor chips stacked in a vertical direction. Background Technology

[0003] In the electronics market, the demand for portable devices has increased rapidly. Consequently, electronic components installed in electronic products have become increasingly lightweight and miniaturized. For example, there is a growing demand for miniaturized and lightweight semiconductor packages installed in electronic components to process high volumes of data while maintaining a small size and reduced defects.

[0004] Furthermore, semiconductor packages with multiple semiconductor chips stacked vertically have been developed to reduce the size of semiconductor packages. Research is underway on maintaining structural reliability in such semiconductor packages even with an increasing number of stacked semiconductor chips. Summary of the Invention

[0005] The present invention provides a semiconductor package that has increased reliability by reducing the temperature difference between the edge and center of a semiconductor chip in a thermal compression bonding (TCB) process.

[0006] Furthermore, the problems solved by the technical ideas of the embodiments of the present invention are not limited to those mentioned above, and other problems can be clearly understood by those skilled in the art through the following description.

[0007] According to an embodiment of the present invention, a semiconductor package includes: a substrate chip; a plurality of first semiconductor chips, each having a first horizontal width; and a plurality of second semiconductor chips, each having a second horizontal width different from the first horizontal width. The plurality of first semiconductor chips and the plurality of second semiconductor chips are alternately stacked on the substrate chip. An adhesive layer is disposed between adjacent semiconductor chips in the alternately stacked plurality of first semiconductor chips and the plurality of second semiconductor chips.

[0008] According to an embodiment of the present invention, a semiconductor package includes: a lower substrate having external connection terminals on a lower surface of the lower substrate; a substrate chip on the lower substrate; a plurality of first semiconductor chips, each having a first horizontal width; a plurality of second semiconductor chips, each having a second horizontal width greater than the first horizontal width; a top semiconductor chip having a height greater than the height of each of the plurality of second semiconductor chips and having a horizontal width equal to the second horizontal width; an adhesive layer between adjacent semiconductor chips among the plurality of first semiconductor chips and the plurality of second semiconductor chips, and between the uppermost first semiconductor chip and the top semiconductor chip among the plurality of first semiconductor chips, the adhesive layer including rounded corner portions extending in a horizontal direction; and a molding member filling the gaps between the substrate chip, the plurality of first semiconductor chips, the plurality of second semiconductor chips, the top semiconductor chip and the adhesive layer on the lower substrate. Each of the plurality of first semiconductor chips and the plurality of second semiconductor chips is alternately stacked on a substrate chip. The top semiconductor chip is on the uppermost of the plurality of first semiconductor chips. The first horizontal width is smaller than the horizontal width of the adhesive layer, the second horizontal width is substantially the same as the horizontal width of the adhesive layer, and the difference between the second horizontal width and the first horizontal width is substantially the same as the horizontal width of the rounded corner portion. The plurality of first semiconductor chips, the plurality of second semiconductor chips and the top semiconductor chip are stacked vertically such that the centers of the plurality of first semiconductor chips, the plurality of second semiconductor chips and the top semiconductor chip in the horizontal direction overlap each other in the vertical direction.

[0009] According to an embodiment of the present invention, a semiconductor package is provided, the semiconductor package comprising: a substrate chip; a plurality of first semiconductor chips, each having a first horizontal width; and a plurality of second semiconductor chips, each having a second horizontal width different from the first horizontal width, wherein a first semiconductor chip structure comprising the plurality of vertically stacked first semiconductor chips and the plurality of second semiconductor chips are alternately stacked on the substrate chip, and an adhesive layer is provided between adjacent first semiconductor chips and between each of the first semiconductor chip structures and each of the plurality of second semiconductor chips.

[0010] According to an embodiment of the present invention, a semiconductor package includes: a substrate chip; a plurality of first semiconductor chips, each having a first core region and a first dummy region; and a plurality of second semiconductor chips, each having a second core region and a second dummy region. The first core region and the second core region have the same horizontal width, and the second dummy region has a horizontal width greater than that of the first dummy region. The plurality of first semiconductor chips and the plurality of second semiconductor chips are alternately stacked on the substrate chip. An adhesive layer is disposed between adjacent semiconductor chips in the alternately stacked plurality of first semiconductor chips and the plurality of second semiconductor chips. The adhesive layer includes rounded corner portions having a horizontal length equal to the difference between the horizontal length of the second dummy region and the horizontal length of the first dummy region.

[0011] In one embodiment, the rounded corner portion is formed by a heat compression process.

[0012] In one embodiment, the side surface of each second semiconductor chip is aligned with the side surface of the adhesive layer.

[0013] In one embodiment, the plurality of first semiconductor chips and the plurality of second semiconductor chips are stacked vertically such that the horizontal centers of the plurality of first semiconductor chips and the plurality of second semiconductor chips overlap each other in the vertical direction.

[0014] According to an embodiment of the present invention, a semiconductor package includes: a substrate chip; a plurality of first semiconductor chip structures, each including a plurality of vertically stacked first semiconductor chips, each of the plurality of first semiconductor chips having a first horizontal width; and one or more second semiconductor chips, each having a second horizontal width different from the first horizontal width, wherein the plurality of first semiconductor chip structures and the one or more second semiconductor chips are alternately stacked on the substrate chip, and an adhesive layer is provided between adjacent first semiconductor chips in the plurality of first semiconductor chips and between each of the plurality of first semiconductor chip structures and each of the one or more second semiconductor chips. Attached Figure Description

[0015] Embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0016] Figure 1 This is a schematic cross-sectional view illustrating an embodiment of a semiconductor package according to the present invention.

[0017] Figure 2 This is an illustrative representation of an embodiment based on the concept of the present invention. Figure 1 A partial sectional view of EX1.

[0018] Figure 3This is an illustrative representation of an embodiment based on the concept of the present invention. Figure 1 A partial cross-sectional view of EX2.

[0019] Figures 4 to 11 This is a cross-sectional view schematically illustrating a method for manufacturing a chip stack structure according to an embodiment of the present invention, in the order of process steps.

[0020] Figure 12 This is a schematic cross-sectional view illustrating an embodiment of a semiconductor package according to the present invention.

[0021] Figures 13 to 16 This is a cross-sectional view schematically illustrating a method for manufacturing a chip stack structure according to an embodiment of the present invention, in the order of process steps.

[0022] Figure 17 This is a schematic cross-sectional view illustrating an embodiment of a semiconductor package according to the present invention. Detailed Implementation

[0023] In the following, embodiments of the inventive concept are described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals denote the same elements, and therefore, repeated descriptions of them will be omitted.

[0024] This invention relates to a semiconductor package having a first semiconductor chip and a second semiconductor chip alternately stacked on a substrate chip. An adhesive layer is located between each of the adjacent semiconductor chips in the alternately stacked first and second semiconductor chips. The first semiconductor chip has a horizontal width smaller than that of the second semiconductor chip. Because the horizontal width of the second semiconductor chip is greater than that of the first semiconductor chip, the pre-adhesive layer forming the adhesive layer can receive relatively uniform (consistent) heat at its edge and center portions during the manufacturing process to prevent non-wetting caused by temperature differences in different portions of the adhesive layer.

[0025] Figure 1 This is a schematic cross-sectional view of a semiconductor package 10 according to an embodiment. Figure 2 It is shown schematically. Figure 1 A partial sectional view of EX1. Figure 3 It is shown schematically. Figure 1 A partial cross-sectional view of EX2.

[0026] Reference Figures 1 to 3 The semiconductor package 10 may include a lower substrate 100, external connection terminals 160, a chip stack structure 200, and a molding component 290.

[0027] The lower substrate 100 of the semiconductor package 10 is a substrate on which the chip stack structure 200 is mounted, and may be located below the chip stack structure 200 (e.g., below the chip stack structure 200 in the Z-axis direction). For example, the lower substrate 100 may be located between the chip stack structure 200 and external connection terminals 160 (e.g., between the chip stack structure 200 and external connection terminals 160 in the Z-axis direction). The lower substrate 100 may be electrically connected to each of the chip stack structure 200 and the external connection terminals 160.

[0028] According to an embodiment, the lower substrate 100 may have a shape in which at least one of its upper and lower surfaces is substantially flat. In the figures, the X-axis and Y-axis directions may indicate directions parallel to the upper or lower surface of the lower substrate 100, which is a substantially flat surface, and the X-axis direction may be perpendicular to the Y-axis direction. The Z-axis direction may indicate a direction perpendicular to the upper or lower surface of the lower substrate 100. For example, the Z-axis direction may be a direction perpendicular to the XY plane. However, embodiments of the inventive concept are not necessarily limited to this, and the X-axis, Y-axis, and Z-axis directions may intersect each other at various different angles.

[0029] Furthermore, in the following description with reference to the accompanying drawings, the first horizontal direction, the second horizontal direction, and the vertical direction can be understood as follows: the first horizontal direction can be understood as the X-axis direction, the second horizontal direction can be understood as the Y-axis direction, and the vertical direction can be understood as the Z-axis direction.

[0030] The lower substrate 100 may include an insulating layer and wiring formed within the insulating layer. According to an embodiment, the lower substrate 100 may include a redistributed structure formed by a redistribution process. Here, the wiring of the lower substrate 100 can be understood as a redistributed pattern, and the insulating layer of the lower substrate 100 can be understood as a redistributed insulating layer. In one embodiment, the wiring of the lower substrate 100 may include a metal (such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), or ruthenium (Ru)) or an alloy of metals. However, embodiments of the inventive concept are not necessarily limited thereto, and in some embodiments, the wiring may be formed by stacking metals or alloys of metals on a seed layer comprising Cu, Ti, titanium nitride, or titanium-tungsten. Furthermore, the insulating layer of the lower substrate 100 may be formed of a photoimageable dielectric (PID) or a photosensitive polyimide (PSPI).

[0031] However, the lower substrate 100 is not limited to this, and in some embodiments, the lower substrate 100 may be formed of a ceramic substrate, a printed circuit board (PCB), an organic substrate, etc. In this embodiment, the wiring of the lower substrate 100 may include Cu, Ni, stainless steel, or beryllium copper, and the insulating layer of the lower substrate 100 may include at least one material selected from Class 4 flame retardant (FR-4), tetrafunctional epoxy resin, polyphenylene ether, epoxy resin / polyphenylene ether, bismaleimide triazine (BT), polyamide short fiber mat (Thermount), cyanate ester, polyimide, and liquid crystal polymer.

[0032] External connection terminal 160 may be located on the lower surface of the lower substrate 100 and electrically connected to the lower substrate 100 via a pad formed on the lower surface of the lower substrate 100. In one embodiment, external connection terminal 160 may be electrically connected to wiring formed in the lower substrate 100 via a base pad attached to the lower surface of the lower substrate 100. Since external connection terminal 160 is below the lower substrate 100, the upper surface of external connection terminal 160 may be in physical contact with the base pad attached to the lower surface of the lower substrate 100. External connection terminal 160 may be electrically connected to an external device (e.g., motherboard, PCB, package substrate, etc.). Since external connection terminal 160 is between the external device and the lower substrate 100, the lower surface of external connection terminal 160 may be physically connected to the external device.

[0033] In one embodiment, the external connection terminal 160 may be formed as a solder ball. However, according to an embodiment, the external connection terminal 160 may have a structure including a post and solder. In one embodiment, the external connection terminal 160 may include at least one of Cu, silver (Ag), gold (Au), and Sn.

[0034] The chip stack structure 200 may be located on the upper surface of the lower substrate 100. According to an embodiment, the chip stack structure 200 may be mounted on the upper surface of the lower substrate 100 in a flip-chip manner via a first bump 170. The first bump 170 may be located between the chip stack structure 200 and the lower substrate 100 (e.g., between the chip stack structure 200 and the lower substrate 100 in the Z-axis direction). The first bump 170 may electrically connect the connection pads 102 of the lower substrate 100 to the lower connection pads 214 of the substrate chip 210. In one embodiment, the first bump 170 may include a pillar structure, a ball structure, or a solder layer.

[0035] According to an embodiment, an underfill material layer 180 surrounding the first bump 170 may be located between the chip stack structure 200 and the lower substrate 100 (e.g., between the chip stack structure 200 and the lower substrate 100 in the Z-axis direction). In one embodiment, the underfill material layer 180 may comprise epoxy resin formed by, for example, a capillary underfill process. However, in some embodiments, the molding member 290 may directly fill the gap between the chip stack structure 200 and the lower substrate 100 using a molding underfill process. In this embodiment, the underfill material layer 180 may be omitted.

[0036] In one embodiment, the chip stacking structure 200 of the semiconductor package 10 may include a base chip 210, a plurality of first semiconductor chips 220, a plurality of second semiconductor chips 230, and a top semiconductor chip 240.

[0037] In one embodiment, the substrate chip 210 is the chip located at the bottom of the chip stack structure 200 and can be directly connected to the lower substrate 100 via a first bump 170. According to an embodiment, the substrate chip 210 can integrate signals from a plurality of first semiconductor chips 220, a plurality of second semiconductor chips 230, and a top semiconductor chip 240 stacked on the substrate chip 210, and transmit the integrated signals to the outside (e.g., the external environment), or transmit signals and power from the outside (e.g., the external environment) to the plurality of first semiconductor chips 220, a plurality of second semiconductor chips 230, and a top semiconductor chip 240. Therefore, in the specification, the substrate chip 210 may be referred to as a buffer chip or a control chip.

[0038] The substrate chip 210 may include various types of individual devices. In one embodiment, an individual device may include various microelectronic devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs) (e.g., complementary metal-oxide-semiconductor (CMOS) transistors), system-on-large-scale integrated circuit (LSI) chips, image sensors (e.g., CMOS imaging sensors (CIS)), microelectromechanical systems (MEMS), active devices, passive devices, etc. In some embodiments, the substrate chip 210 may not include memory cells. For example, in one embodiment, semiconductor devices included in the substrate chip 210 may include serial-to-parallel conversion circuitry, test logic circuitry (e.g., design fortest (DFT) circuitry, joint test action group (JTAG) circuitry, or memory-embedded self-test (MBIST) circuitry), and signal interface circuitry (e.g., physical layer devices (PHY)).

[0039] Multiple first semiconductor chips 220 and multiple second semiconductor chips 230 may be stacked alternately on the substrate chip 210 (e.g., stacked alternately on the substrate chip 210 in the Z-axis direction).

[0040] The plurality of first semiconductor chips 220 can be defined as chips included in the chip stacking structure 200 that are stacked on the substrate chip 210 in a vertical direction (e.g., the Z-axis direction) and below (e.g., directly below) or on (e.g., directly above) the second semiconductor chip 230. Since the first semiconductor chips 220 and the second semiconductor chips 230 are stacked alternately on the substrate chip 210, the plurality of first semiconductor chips 220 can be understood as chips between the substrate chip 210 and the second semiconductor chip 230 (e.g., between the substrate chip 210 and the second semiconductor chip 230 in the Z-axis direction) and between every two adjacent second semiconductor chips 230 (e.g., between every two adjacent second semiconductor chips 230 in the Z-axis direction). Furthermore, as described below, a plurality of first semiconductor chips 220 may be included between the second semiconductor chip 230 and the top semiconductor chip 240 (e.g., between the second semiconductor chip 230 and the top semiconductor chip 240 in the Z-axis direction).

[0041] For example, such as Figure 1 As shown in the embodiments, the plurality of first semiconductor chips 220 may be configured as a total of four first semiconductor chips 220 that are alternately stacked with a plurality of second semiconductor chips 230 on the substrate chip 210. However, the number of first semiconductor chips 220 is not limited to this, and the number of first semiconductor chips 220 can vary. For example, depending on the number of stacks in the chip stacking structure 200, the number of first semiconductor chips 220 may be 6, 8, etc. The first semiconductor chip 220 may be referred to as a memory chip or a core chip.

[0042] Each of the plurality of first semiconductor chips 220 may have a first horizontal width w1. In the specification, the term "horizontal width" refers to the length in a first horizontal direction (e.g., the X-axis direction) and / or the length in a second horizontal direction (e.g., the Y-axis direction). The first horizontal width w1 of each of the plurality of first semiconductor chips 220 may differ from the second horizontal width w2 of each of the plurality of second semiconductor chips 230. According to an embodiment, the first horizontal width w1 of each of the plurality of first semiconductor chips 220 may be smaller than the second horizontal width w2 of each of the plurality of second semiconductor chips 230. Furthermore, according to an embodiment, the first horizontal width w1 of the first semiconductor chip 220 and the second horizontal width w2 of the second semiconductor chip 230 may be smaller than the horizontal width of the substrate chip 210. The stacked structure of the plurality of first semiconductor chips 220 and the plurality of second semiconductor chips 230 is described below.

[0043] According to an embodiment, the first semiconductor chip 220 may include a first semiconductor substrate 221, a first semiconductor device layer 223, a first through electrode 225, a first upper connection pad 227, and a first lower connection pad 229. The first semiconductor substrate 221 may have a lower surface and an upper surface opposite to each other. The lower surface may be a surface facing the lower substrate 100. The lower surface may be referred to as an active surface, and the upper surface opposite to the lower surface may be referred to as a passive surface.

[0044] In one embodiment, the first semiconductor substrate 221 may include silicon (Si) (such as single-crystal Si, polycrystalline Si, or amorphous Si). Optionally, the first semiconductor substrate 221 may include an elemental semiconductor (such as germanium (Ge)) or a compound semiconductor (such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP)). Furthermore, the first semiconductor substrate 221 may have a silicon-on-insulator (SOI) structure. For example, the first semiconductor substrate 221 may include a buried oxide (BOX) layer. The first semiconductor substrate 221 may include conductive regions (such as impurity-doped wells or impurity-doped structures). Additionally, the first semiconductor substrate 221 may have various device isolation structures (such as shallow trench isolation (STI) structures).

[0045] According to an embodiment, a first semiconductor device layer 223 may be formed on the lower surface of a first semiconductor substrate 221, which serves as an active surface. In one embodiment, the first semiconductor device layer 223 may include a first core region 223C and a first dummy region 223D. In one embodiment, the first dummy region 223D may be disposed on a lateral end of the first semiconductor device layer 223, and the first core region 223C may be disposed on the central portion of the first semiconductor device layer 223. In one embodiment, an individual device may be formed in the first core region 223C of the first semiconductor device layer 223. The individual device may include various microelectronic devices, such as MOSFETs (e.g., CMOS transistors), LSI chips, image sensors (e.g., CIS), MEMS, active devices, passive devices, etc. The first dummy region 223D of the first semiconductor device layer 223 may be formed of Si. The individual device may not be formed in the first dummy region 223D of the first semiconductor device layer 223.

[0046] The first through electrode 225 may be formed to pass through the first semiconductor substrate 221 in a vertical direction (e.g., the Z-axis direction). In some embodiments, the first through electrode 225 may be formed to pass through a portion of the first semiconductor device layer 223 and the first semiconductor substrate 221. The first through electrode 225 may extend vertically (e.g., in the Z-axis direction) from the first semiconductor device layer 223 toward the upper surface of the first semiconductor substrate 221 and may be electrically connected to wiring disposed in the first semiconductor device layer 223. The first through electrode 225 may have a tapered shape having a horizontal width that gradually decreases or increases with its vertical level. At least a portion of the first through electrode 225 may have a columnar shape. In one embodiment, the first through electrode 225 may be a through silicon via (TSV).

[0047] The first upper connection pad 227 may be disposed on the upper surface of the first semiconductor substrate 221 (e.g., directly disposed on the upper surface of the first semiconductor substrate 221 in the Z-axis direction), the upper surface of the first semiconductor substrate 221 being a passive surface of the first semiconductor chip 220, and the first lower connection pad 229 may be disposed on the lower surface of the first semiconductor device layer 223 (e.g., directly disposed on the lower surface of the first semiconductor device layer 223 in the -Z-axis direction), the lower surface of the first semiconductor device layer 223 being an active surface of the first semiconductor chip 220. The first upper connection pad 227 may be electrically connected to the first through electrode 225. The first lower connection pad 229 may be electrically connected to the wiring of the first semiconductor device layer 223. In one embodiment, some of the first lower connection pads 229 may be electrically connected to the corresponding first through electrode 225.

[0048] According to an embodiment, the first semiconductor chip 220 may include a memory chip. The memory chip may be, for example, a volatile memory chip (such as dynamic random access memory (DRAM) or static random access memory (SRAM)) or a non-volatile memory chip (such as phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), or resistive random access memory (RRAM)). However, the first semiconductor chip 220 is not necessarily limited to these and may include logic chips (such as microprocessors (such as central processing unit (CPU), graphics processing unit (GPU), or application processor (AP)), analog devices, or digital signal processors).

[0049] The plurality of second semiconductor chips 230 may be defined as chips on the upper or lower surface of a plurality of first semiconductor chips 220 stacked in a vertical direction (e.g., the Z-axis direction). In one embodiment, the first semiconductor chip 220 may be a first semiconductor chip disposed on a substrate chip 210 (e.g., disposed on the substrate chip 210 in the Z-axis direction), and the second semiconductor chips 230 and the first semiconductor chips 220 may be alternately disposed on the aforementioned first semiconductor chips. Therefore, the plurality of second semiconductor chips 230 can be understood as chips between every two adjacent first semiconductor chips 220.

[0050] Each of the plurality of second semiconductor chips 230 may have a second horizontal width w2 (e.g., length in the X-axis and / or Y-axis direction) that is different from the first horizontal width w1 of each of the plurality of first semiconductor chips 220. The second horizontal width w2 may be greater than the first horizontal width w1.

[0051] According to an embodiment, the second semiconductor chip 230 may include a second semiconductor substrate 231, a second semiconductor device layer 233, a second through electrode 235, a second upper connection pad 237, and a second lower connection pad 239. The second semiconductor substrate 231 may have a lower surface and an upper surface that are opposite to each other (e.g., opposite to each other in the Z-axis direction). The lower surface may be the surface facing the first semiconductor chip 220. The lower surface may be referred to as an active surface, and the upper surface opposite to the lower surface may be referred to as a passive surface.

[0052] In one embodiment, the second semiconductor substrate 231 may comprise Si (such as monocrystalline Si, polycrystalline Si, or amorphous Si). The second semiconductor substrate 231 may have a larger length in the horizontal direction (e.g., the X-axis direction and / or the Y-axis direction) compared to the first semiconductor substrate 221.

[0053] The second semiconductor device layer 233 may be formed on the lower surface of the second semiconductor substrate 231, which serves as the active surface. In one embodiment, the second semiconductor device layer 233 may include a second core region 233C and a second dummy region 233D. In one embodiment, the second dummy region 233D may be disposed on a lateral end of the second semiconductor device layer 233, and the second core region 233C may be disposed on the central portion of the second semiconductor device layer 233. According to an embodiment, an individual device may be formed in the second core region 233C. According to an embodiment, the second dummy region 233D may be formed of Si. An individual device may not be formed in the second dummy region 233D.

[0054] According to an embodiment, the length of the second core region 233C in the horizontal direction (e.g., the X-axis and / or Y-axis direction) may be substantially the same as the length of the first core region 223C in the horizontal direction (e.g., the X-axis and / or Y-axis direction). In one embodiment, the length of the second dummy region 233D in the horizontal direction (e.g., the X-axis and / or Y-axis direction) may be greater than the length of the first dummy region 223D in the horizontal direction (X-axis and / or Y-axis direction). However, the relative lengths of the second core region 233C and the second dummy region 233D in the horizontal direction (e.g., the X-axis and / or Y-axis direction), as well as the relative lengths of the first core region 223C and the first dummy region 223D in the horizontal direction (e.g., the X-axis and / or Y-axis direction), are not necessarily limited to these, and the second core region 233C may be substantially the same as the first core region 223C.

[0055] The second through electrode 235 may be formed to pass through the second semiconductor substrate 231 in a vertical direction (e.g., the Z-axis direction). In some embodiments, the second through electrode 235 may be formed to pass through a portion of the second semiconductor device layer 233 and the second semiconductor substrate 231. The second through electrode 235 may extend vertically (e.g., in the Z-axis direction) from the second semiconductor device layer 233 toward the upper surface of the second semiconductor substrate 231 and may be electrically connected to wiring disposed in the second semiconductor device layer 233. The second through electrode 235 may have a tapered shape having a horizontal width that gradually decreases or increases with its vertical horizontal direction. At least a portion of the second through electrode 235 may have a columnar shape. In one embodiment, the second through electrode 235 may be a TSV.

[0056] The second upper connection pad 237 may be disposed on the upper surface of the second semiconductor substrate 231 (e.g., directly disposed on the upper surface of the second semiconductor substrate 231 in the Z-axis direction), the upper surface of the second semiconductor substrate 231 being the passive surface of the second semiconductor chip 230, and the second lower connection pad 239 may be disposed on the lower surface of the second semiconductor device layer 233 (e.g., directly disposed on the lower surface of the second semiconductor device layer 233 in the -Z-axis direction), the lower surface of the second semiconductor device layer 233 being the active surface of the second semiconductor chip 230. The second upper connection pad 237 may be electrically connected to the second through electrode 235. The second lower connection pad 239 may be electrically connected to the wiring of the second semiconductor device layer 233. Some of the second lower connection pads 239 may be electrically connected to the corresponding second through electrode 235, although such connections are not... Figure 1 It is clearly shown in the middle.

[0057] In one embodiment, the top semiconductor chip 240 may be stacked vertically (e.g., in the Z-axis direction) on top of the uppermost first semiconductor chip 220 among a plurality of first semiconductor chips 220 that are alternately stacked with a plurality of second semiconductor chips 230. For example, the top semiconductor chip 240 may replace the uppermost second semiconductor chip 230 among a plurality of second semiconductor chips 230 that are alternately stacked with a plurality of first semiconductor chips 220. For example, the top semiconductor chip 240 may be positioned in a location that would normally correspond to the uppermost second semiconductor chip 230 among a plurality of alternately stacked first semiconductor chips and second semiconductor chips 220, 230 of the chip stack structure 200, and may replace the uppermost second semiconductor chip 230 in such a position.

[0058] In one embodiment, the top semiconductor chip 240 may include a top semiconductor substrate 241, a top semiconductor device layer 243, and a third lower connection pad 249. According to another embodiment, the top semiconductor chip 240 may not include a through electrode.

[0059] According to an embodiment, the thickness of the top semiconductor chip 240 in the vertical direction (e.g., the Z-axis direction) may be greater than the thickness of each of the plurality of second semiconductor chips 230 in the vertical direction (e.g., the Z-axis direction). For example, as Figure 3 As shown in the embodiments, the height h2 of the top semiconductor chip 240 may be greater than the height h1 of the second semiconductor chip 230. Furthermore, according to the embodiments, the horizontal width w4 of the top semiconductor chip 240 (e.g., its length in the X-axis direction and / or Y-axis direction) may be the same as the second horizontal width w2 of the second semiconductor chip 230. However, the embodiments of the present invention are not necessarily limited to this.

[0060] For example, such as Figure 1As shown in the embodiments, a plurality of second semiconductor chips 230 may be stacked alternately with a plurality of first semiconductor chips 220 (e.g., in the Z-axis direction), and a top semiconductor chip 240 may be stacked on top of the topmost first semiconductor chip 220, such that a total of three second semiconductor chips 230 and one top semiconductor chip 240 are provided. However, the embodiments of the present invention are not limited thereto, and the number of second semiconductor chips 230 may vary. For example, depending on the number of stacks in the chip stack structure 200, the number of second semiconductor chips 230 may be 5, 7, etc.

[0061] In one embodiment, a plurality of first semiconductor chips 220, a plurality of second semiconductor chips 230 and a top semiconductor chip 240 stacked in a vertical direction (e.g., the Z-axis direction) can be stacked by a second bump 252 and an adhesive layer 254.

[0062] In one embodiment, the bottommost first semiconductor chip 220 of a plurality of first semiconductor chips 220 may be stacked on the substrate chip 210 in a flip-chip manner via a second bump 252. The second bump 252 may be located between the first lower connection pad 229 of the bottommost first semiconductor chip 220 and the upper connection pad 212 of the substrate chip 210 (e.g., directly between the first lower connection pad 229 of the bottommost first semiconductor chip 220 and the upper connection pad 212 of the substrate chip 210 in the Z-axis direction), and electrically connects the first lower connection pad 229 to the upper connection pad 212. In another embodiment, the second bump 252 may be located between the first lower connection pad 229 and the upper connection pad 212 (e.g., directly between the first lower connection pad 229 and the upper connection pad 212 in the Z-axis direction), and is connected between the first lower connection pad 229 and the upper connection pad 212 via a thermocompression bonding (TCB).

[0063] In one embodiment, the second semiconductor chip 230 may be stacked on the first semiconductor chip 220 in a flip-chip manner via a second bump 252. The second bump 252 may be located between a first upper connection pad 227 of the first semiconductor chip 220 and a second lower connection pad 239 of the second semiconductor chip 230 (e.g., directly between the first upper connection pad 227 of the first semiconductor chip 220 and the second lower connection pad 239 of the second semiconductor chip 230 in the Z-axis direction), and electrically connects the first upper connection pad 227 to the second lower connection pad 239.

[0064] In the chip stacking structure 200, since the first semiconductor chip 220 and the second semiconductor chip 230 are stacked alternately and repeatedly (e.g., in the Z-axis direction), the first semiconductor chip 220 can again be stacked on the upper surface of the second semiconductor chip 230 in a flip-chip manner via the second bump 252. The second bump 252 is located between the second upper connection pad 237 of the second semiconductor chip 230 and the first lower connection pad 229 of the first semiconductor chip 220 (e.g., directly between the second upper connection pad 237 of the second semiconductor chip 230 and the first lower connection pad 229 of the first semiconductor chip 220 in the Z-axis direction), and electrically connects the second upper connection pad 237 to the first lower connection pad 229.

[0065] In one embodiment, the top semiconductor chip 240 can be flip-chip stacked on the topmost first semiconductor chip 220 in the chip stack structure 200 via a second bump 252. The second bump 252 is located between the first upper connection pad 227 of the first semiconductor chip 220 and the third lower connection pad 249 of the top semiconductor chip 240 (e.g., directly between the first upper connection pad 227 of the first semiconductor chip 220 and the third lower connection pad 249 of the top semiconductor chip 240 in the Z-axis direction), and electrically connects the first upper connection pad 227 to the third lower connection pad 249.

[0066] The second bump 252 may include, for example, microbumps. According to an embodiment, the second bump 252 may include a pillar structure, a ball structure, or a solder layer.

[0067] The adhesive layer 254 may be present between the substrate chip 210 and the bottommost first semiconductor chip 220 (e.g., directly between the substrate chip 210 and the bottommost first semiconductor chip 220 in the Z-axis direction), between each first semiconductor chip 220 and each second semiconductor chip 230 (e.g., directly between each first semiconductor chip 220 and each second semiconductor chip 230 in the Z-axis direction), and between the topmost first semiconductor chip 220 and the top layer semiconductor chip 240 (e.g., directly between the topmost first semiconductor chip 220 and the top layer semiconductor chip 240 in the Z-axis direction). For example, the adhesive layer 254 may be directly disposed between each of adjacent semiconductor chips in a plurality of alternately stacked first semiconductor chips 220 and a plurality of second semiconductor chips 230. In some embodiments, the adhesive layer 254 may include a film having self-adhesive properties. For example, the adhesive layer 254 may include a non-conductive film (NCF).

[0068] As described above, the chip stack structure 200 can be formed by alternately stacking a first semiconductor chip 220 and a second semiconductor chip 230 with different horizontal widths in a vertical direction (e.g., the Z-axis direction). The second horizontal width w2 of the second semiconductor chip 230 can be greater than the first horizontal width w1 of the first semiconductor chip 220. The first semiconductor chip 220 and the second semiconductor chip 230 can be stacked vertically such that the centers (or horizontal centers) of the first semiconductor chip 220 and the second semiconductor chip 230 in the horizontal direction (X-axis direction and / or Y-axis direction) overlap each other (e.g., overlap each other in the vertical direction (such as the Z-axis direction)). For example, as... Figure 2 As shown in the embodiment, when the first side surface 220a and the second side surface 220b of the first semiconductor chip 220 correspond to the third side surface 230a and the fourth side surface 230b of the second semiconductor chip 230 stacked on the first semiconductor chip 220, the horizontal distance d between the first side surface 220a and the third side surface 230a can be the same as the horizontal distance d between the second side surface 220b and the fourth side surface 230b.

[0069] In one embodiment, even if the first horizontal width w1 is different from the second horizontal width w2, the horizontal width of the first core region 223C of the first semiconductor chip 220 can be substantially the same as the horizontal width of the second core region 233C of the second semiconductor chip 230. The first semiconductor chip 220 and the second semiconductor chip 230 can be configured such that the first core region 223C and the second core region 233C are stacked (e.g., stacked in the Z-axis direction).

[0070] As described above, the adhesive layer 254 may be located between the first semiconductor chip 220 and the second semiconductor chip 230 (e.g., directly between the first semiconductor chip 220 and the second semiconductor chip 230 in the Z-axis direction) to bond the second semiconductor chip 230 to the first semiconductor chip 220. When the second semiconductor chip 230 is bonded to the first semiconductor chip 220 by a thermal compression process, the adhesive layer 254 may protrude from the first semiconductor chip 220 in a horizontal direction (e.g., the X-axis direction and / or the Y-axis direction).

[0071] The horizontal width w3 of the adhesive layer 254 (e.g., its length in the X-axis and / or Y-axis directions) may correspond to the horizontal width of the fillet portion 254F included in a thermal compression process (e.g., formed by thermal compression). In one embodiment, the horizontal width w3 of the adhesive layer 254 may be greater than the first horizontal width w1 of the first semiconductor chip 220 and substantially the same as the second horizontal width w2 of the second semiconductor chip 230. The difference between the second horizontal width w2 and the first horizontal width w1 may be substantially the same as the horizontal width of the fillet portion 254F extending in the horizontal direction (e.g., the X-axis and / or Y-axis directions) by a thermal compression process. For example, in one embodiment, the difference between the second horizontal width w2 and the first horizontal width w1 may be approximately 400 μm. In this embodiment, the first semiconductor chip 220 and the second semiconductor chip 230 may be configured such that each of the horizontal distance d between the first side surface 220a and the third side surface 230a and the horizontal distance d between the second side surface 220b and the fourth side surface 230b is approximately 200 μm. According to an embodiment, the second semiconductor chip 230 may be configured such that the side surface of the second semiconductor chip 230 is aligned with the side surface of the adhesive layer 254 (e.g., aligned along the Z-axis direction). For example, when the second horizontal width w2 of the second semiconductor chip 230 is substantially the same as the horizontal width w3 of the adhesive layer 254, the side surface of the second semiconductor chip 230 may be aligned with the side surface of the adhesive layer 254.

[0072] The bonding relationship between the topmost first semiconductor chip 220 and the top layer semiconductor chip 240 is basically the same as the bonding relationship between the first semiconductor chip 220 and the second semiconductor chip 230, therefore, its description is omitted here.

[0073] The molding member 290 of the semiconductor package 10 may be formed around the chip stack structure 200 on the upper surface of the lower substrate 100. In one embodiment, the molding member 290 may be formed of a molding material (such as epoxy molding compound (EMC)) or a photosensitive material (such as photoimageable encapsulant (PIE)). In some embodiments, a portion of the molding member 290 may be formed of an insulating material (such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film). However, the molding member 290 is not limited to these and may be formed of a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide), or a resin including reinforcing materials (such as inorganic fillers) (in addition, particularly Ajinomoto build-up film (ABF), FR-4, BT, etc.).

[0074] Figures 4 to 11 This is a cross-sectional view schematically illustrating the method of manufacturing a chip stack structure 200 according to an embodiment, in the order of process steps.

[0075] Reference Figure 1 and Figure 4 A substrate chip 210, a first semiconductor chip 220, and a second semiconductor chip 230 are sequentially stacked (e.g., sequentially stacked in the Z-axis direction) on a bonding chuck 301. An adhesive layer 254P may be prepared between the substrate chip 210 and the first semiconductor chip 220 (e.g., directly between the substrate chip 210 and the first semiconductor chip 220 in the Z-axis direction) and between the first semiconductor chip 220 and the second semiconductor chip 230 (e.g., directly between the first semiconductor chip 220 and the second semiconductor chip 230 in the Z-axis direction). The adhesive layer 254P may include NCF.

[0076] Reference Figure 5 Heat and pressure can be applied to the substrate chip 210, the first semiconductor chip 220, and the second semiconductor chip 230 to bond them together. In one embodiment, an adhesive layer 254P (see [link to adhesive layer]) is prepared due to thermal compression. Figure 4 An adhesive layer 254 with a horizontal width w3 can be formed, which has a rounded corner portion 254F.

[0077] In the thermal compression process, a pre-adhesive layer 254P (see...) is used between the first semiconductor chip 220 and the second semiconductor chip 230. Figure 4 The bonding head 303 sequentially receives heat through the head adhesive layer 305 and the second semiconductor chip 230. In one embodiment, the head adhesive layer 305 may be, for example, Teflon tape. Because the second horizontal width w2 of the second semiconductor chip 230 is greater than the first horizontal width w1 of the first semiconductor chip 220, an adhesive layer 254P (see [link to product]) is prepared. Figure 4 It can receive relatively uniform heat at its edge and center portions. Therefore, the prepared adhesive layer 254P (see...) Figure 4 The temperature difference between the central and edge portions of the product can be reduced, thereby preventing the occurrence of unwetting, which can lead to adhesive failure at the edge portions due to temperature differences.

[0078] After the thermal compression process, the adhesive layer 254 may include rounded corner portions 254F extending from both sides of the adhesive layer 254 in a horizontal direction (e.g., the X-axis direction and / or the Y-axis direction). The second horizontal width w2 of the second semiconductor chip 230 may be substantially the same as the horizontal width w3 of the adhesive layer 254 including the rounded corner portions 254F.

[0079] Reference Figures 6 to 9 ,exist Figure 5The pre-adhesive layer 254P, the first semiconductor chip 220, the pre-adhesive layer 254P, and the second semiconductor chip 230 are sequentially stacked and prepared on the upper surface of the topmost second semiconductor chip 230, and a thermal compression process is performed on them. Figures 6 to 9 The process is based on a reference. Figure 4 and Figure 5 The described process is repetitive, therefore, for the sake of brevity, its detailed explanation has been omitted.

[0080] Reference Figure 10 and Figure 11 ,exist Figure 9 On the upper surface of the topmost second semiconductor chip 230 of the resulting material, a pre-adhesive layer 254P, a first semiconductor chip 220, a pre-adhesive layer 254P, and a top semiconductor chip 240 are sequentially stacked and prepared, and a thermal compression process is performed on them. Except that the top semiconductor chip 240 is stacked on the first semiconductor chip 220 instead of the second semiconductor chip 230, Figure 10 and Figure 11 The process corresponds to the reference. Figure 4 and Figure 5 The described process is repetitive, therefore its detailed description is omitted.

[0081] Figure 1 The semiconductor package 10 can be packaged by using a first bump 170 and an underfill material layer 180. Figure 11 The resulting product is attached to the lower substrate 100 and then formed into a molded component 290 to provide it.

[0082] In the semiconductor package 10 according to an embodiment of the present invention, the horizontal width of the semiconductor chip disposed on the even-numbered layers (e.g., the second semiconductor chip) may be greater than the horizontal width of the semiconductor chip disposed on the odd-numbered layers (e.g., the first semiconductor chip) to provide uniform heat to the edge and center portions of the adhesive layer during the thermal compression process, thereby preventing unwetting and providing a semiconductor chip or semiconductor package with increased reliability. However, the semiconductor package 10 is not limited to this, and in some embodiments, the horizontal width of the semiconductor chip disposed on the odd-numbered layers may be greater than the horizontal width of the semiconductor chip disposed on the even-numbered layers.

[0083] Figure 12 This is a schematic cross-sectional view of a semiconductor package 10A according to an embodiment. Most of the components constituting the semiconductor package 10A, which will be described below, and the materials forming said components are the same as those referenced above. Figures 1 to 3 The components and materials described are the same or similar. Therefore, for ease of description, the main focus is on... Figure 12 Semiconductor package 10A and Figure 1 The differences between the semiconductor packages 10.

[0084] In one embodiment, the semiconductor package 10A according to the embodiment may include a lower substrate 100, an external connection terminal 160, a chip stack structure 200a, and a molding member 290.

[0085] The chip stack structure 200a may be located on the upper surface of the lower substrate 100. In one embodiment, the chip stack structure 200a may include a substrate chip 210, a plurality of first semiconductor chip structures 220C, a plurality of second semiconductor chips 230, and a top semiconductor chip 240.

[0086] The first semiconductor chip structure 220C and the second semiconductor chip 230 may be alternately stacked on the substrate chip 210 (e.g., alternately stacked on the substrate chip 210 in the Z-axis direction). The first semiconductor chip structure 220C may be defined as a structure formed by vertically stacking a plurality of first semiconductor chips 220. Each of the plurality of first semiconductor chips 220 constituting the first semiconductor chip structure 220C may have a first horizontal width w1. For example, as Figure 12 As shown, the first semiconductor chip structure 220C may include three first semiconductor chips 220. However, embodiments of the present invention are not limited to this, and the number of first semiconductor chips 220 in the first semiconductor chip structure 220C may vary.

[0087] The second semiconductor chip 230 stacked on the upper surface of the first semiconductor chip structure 220C may have a second horizontal width w2 that is greater than the first horizontal width w1.

[0088] The first semiconductor chip structure 220C can be stacked on the second semiconductor chip 230, and the top semiconductor chip 240 can be stacked on the upper surface of the topmost first semiconductor chip structure 220C. For example, as Figure 12 As shown in the embodiments, the first semiconductor chip structure 220C may include three first semiconductor chips 220, and the chip stack structure 200a may include a total of six first semiconductor chips 220, one second semiconductor chip 230, and one top semiconductor chip 240. However, the construction of the chip stack structure 200a is not limited to this. For example, the chip stack structure 200a may include three first semiconductor chip structures 220C (e.g., a total of nine first semiconductor chips 220), two second semiconductor chips 230, and one top semiconductor chip 240.

[0089] The second bump 252 and the adhesive layer 254 may be disposed between every two adjacent first semiconductor chips 220 (e.g., directly between every two adjacent first semiconductor chips 220 in the Z-axis direction), between the first semiconductor chip 220 and the second semiconductor chip 230 (e.g., directly between the first semiconductor chip 220 and the second semiconductor chip 230 in the Z-axis direction), and between the first semiconductor chip 220 and the top semiconductor chip 240 (e.g., directly between the first semiconductor chip 220 and the top semiconductor chip 240 in the Z-axis direction).

[0090] The horizontal width w3 of the adhesive layer 254 may correspond to the horizontal width of the rounded portion 254F included in the thermal compression process. In one embodiment, the horizontal width w3 of the adhesive layer 254 may be greater than the first horizontal width w1 of the first semiconductor chip 220 and substantially the same as the second horizontal width w2 of the second semiconductor chip 230. The difference between the second horizontal width w2 and the first horizontal width w1 may be substantially the same as the horizontal width of the rounded portion 254F extending in the horizontal direction (e.g., the X-axis direction and / or the Y-axis direction) by the thermal compression process. According to an embodiment, the second semiconductor chip 230 may be configured such that the side surface of the second semiconductor chip 230 is aligned with the side surface of the adhesive layer 254 (e.g., aligned along the Z-axis direction).

[0091] Figures 13 to 16 This is a cross-sectional view schematically illustrating a method for manufacturing a chip stack structure 200a according to an embodiment of the present invention, in the order of processes.

[0092] Reference Figure 12 and Figure 13 A substrate chip 210, a first semiconductor chip structure 220C, and a second semiconductor chip 230 are sequentially stacked and fabricated on a bonding chuck 301. A pre-adhesive layer 254P may be present between the substrate chip 210 and the first semiconductor chip 220 (e.g., directly between the substrate chip 210 and the first semiconductor chip 220 in the Z-axis direction), between every two adjacent first semiconductor chips 220 (e.g., directly between every two adjacent first semiconductor chips 220 in the Z-axis direction), and between the first semiconductor chip 220 and the second semiconductor chip 230 (e.g., directly between the first semiconductor chip 220 and the second semiconductor chip 230 in the Z-axis direction). For example, in one embodiment, the pre-adhesive layer 254P may include an NCF (non-linear condenser).

[0093] Reference Figure 14 Heat and pressure can be applied to bond the substrate chip 210, the first semiconductor chip structure 220C, and the second semiconductor chip 230 to each other. In one embodiment, an adhesive layer 254P (see [link to adhesive layer]) is prepared due to thermal compression. Figure 13An adhesive layer 254 with a horizontal width w3 can be formed, which has a rounded corner portion 254F.

[0094] Reference Figure 15 and Figure 16 ,exist Figure 14 On the upper surface of the topmost second semiconductor chip 230 of the resulting product, a pre-adhesive layer 254P, a first semiconductor chip structure 220C, a pre-adhesive layer 254P, and a top semiconductor chip 240 are sequentially stacked and prepared, and a thermal compression process is performed on them. Except that the top semiconductor chip 240 replaces the second semiconductor chip 230 and is disposed on the first semiconductor chip structure 220C, Figure 15 and Figure 16 The process corresponds to the reference. Figure 13 and Figure 14 The described process is repetitive, therefore, in order to save space, its detailed description has been omitted.

[0095] In a semiconductor package 10A according to an embodiment of the present invention, the horizontal width of the semiconductor chip (e.g., a second semiconductor chip) disposed at every four stacks may be greater than the horizontal width of each of the other semiconductor chips (e.g., a first semiconductor chip) to provide uniform heat to the edge and center portions of the adhesive layer during the thermal compression process, thereby preventing unwetting and providing semiconductor chips or semiconductor packages with increased reliability. However, embodiments of the present invention are not necessarily limited to stacks comprising four first semiconductor chips and one second semiconductor chip, and the number of first semiconductor chips may be modified differently.

[0096] Figure 17 This is a schematic cross-sectional view of a semiconductor package 10B according to an embodiment. In the following text, reference will be made to... Figure 1 The semiconductor package 10 described mainly describes Figure 17 Semiconductor package 10B and Figure 1 The differences between the semiconductor packages 10.

[0097] Reference Figure 17 In one embodiment, the semiconductor package 10B may include a lower substrate 100, an intermediate substrate 150, a chip stack structure 200, and a semiconductor chip 400.

[0098] According to an embodiment, the interposer substrate 150 may be on the lower substrate 100. In one embodiment, the interposer substrate 150 may be formed based on Si and electrically connect the chip stack structure 200 to the semiconductor chip 400. According to an embodiment, the interposer substrate 150 may be electrically connected to the lower substrate 100 via bumps. An underfill material layer 180 surrounding the bumps may be between the lower substrate 100 and the interposer substrate 150. In one embodiment, the underfill material layer 180 may be formed of epoxy resin formed by, for example, a capillary underfill process. However, in some embodiments, the molding member 290 may directly fill the gap between the lower substrate 100 and the interposer substrate 150 via a molding underfill process. In this embodiment, the underfill material layer 180 may be omitted.

[0099] The interposer substrate 150 may include a body layer 152 and a wiring layer 154. The wiring layer 154 may be located on the upper surface of the body layer 152. In one embodiment, the wiring layer 154 may include a wiring pattern. The wiring pattern may electrically connect the chip stack structure 200 to the semiconductor chip 400, or make electrical connections between the chip stack structure 200 and the through electrode 153 and between the semiconductor chip 400 and the through electrode 153.

[0100] A through electrode 153 may be formed in the body layer 152. The through electrode 153 may extend through the body layer 152 in a vertical direction (e.g., the Z-axis direction). According to an embodiment, the through electrode 153 may include a TSV. The through electrode 153 may be electrically connected to a bump via a pad formed on the lower surface of the body layer 152.

[0101] Each of the chip stack structure 200 and the semiconductor chip 400 may be located on the upper surface of the intermediate substrate 150. The chip stack structure 200 is related to a reference... Figure 1 The described chip stacking structures are basically the same or similar, therefore, their descriptions are omitted for brevity.

[0102] Semiconductor chip 400 may be located on the upper surface of the intermediate substrate 150 and spaced apart from chip stack structure 200 in a first horizontal direction (e.g., the X-axis direction). According to embodiments, semiconductor chip 400 may include logic chips. Logic chips may include microprocessors (such as CPUs, GPUs, or APs), analog devices, or digital signal processors. However, semiconductor chip 400 is not necessarily limited to logic chips and may include memory chips. In one embodiment, the memory chip may be, for example, a volatile memory chip (such as DRAM or SRAM) or a non-volatile memory chip (such as PRAM, MRAM, FeRAM, or RRAM).

[0103] While the inventive concept has been specifically shown and described with reference to non-limiting embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept.

Claims

1. A semiconductor package, comprising: Substrate chip; Multiple first semiconductor chips, each having a first horizontal width; as well as Multiple second semiconductor chips, each having a second horizontal width different from the first horizontal width, The plurality of first semiconductor chips and the plurality of second semiconductor chips are alternately stacked on a substrate chip, and an adhesive layer is placed between adjacent semiconductor chips in the alternately stacked plurality of first semiconductor chips and the plurality of second semiconductor chips.

2. The semiconductor package according to claim 1, wherein, The second horizontal width is greater than the first horizontal width.

3. The semiconductor package according to claim 1, wherein: The adhesive layer includes rounded corner portions extending in the horizontal direction, wherein the rounded corner portions are formed by a heat compression process, and The difference between the second horizontal width and the first horizontal width is the same as the horizontal width of the rounded corner.

4. The semiconductor package according to claim 1, wherein: The first horizontal width is smaller than the horizontal width of the adhesive layer, and The second horizontal width is the same as the horizontal width of the adhesive layer.

5. The semiconductor package according to claim 1, wherein, The side surface of each second semiconductor chip is aligned with the side surface of the adhesive layer.

6. The semiconductor package according to claim 1, wherein, The plurality of first semiconductor chips and the plurality of second semiconductor chips are stacked vertically such that the horizontal centers of the plurality of first semiconductor chips and the plurality of second semiconductor chips overlap each other in the vertical direction.

7. The semiconductor package according to claim 1, wherein: Each of the plurality of first semiconductor chips includes a first side surface and a second side surface that are opposite to each other. Each of the plurality of second semiconductor chips includes a third side surface corresponding to the first side surface and a fourth side surface corresponding to the second side surface, and Each of the plurality of second semiconductor chips is on each of the plurality of first semiconductor chips, wherein the horizontal distance between the first side surface and the third side surface is the same as the horizontal distance between the second side surface and the fourth side surface.

8. The semiconductor package according to claim 1, wherein: Each of the plurality of first semiconductor chips includes a first core region having an individual device thereon. Each of the plurality of second semiconductor chips includes a second core region thereon having individual devices, and The first core area has the same horizontal width as the second core area.

9. The semiconductor package according to claim 1, wherein: The bump is between each of the plurality of first semiconductor chips and each of the plurality of second semiconductor chips. Each bump electrically connects the first semiconductor chip to the second semiconductor chip, and An adhesive layer is placed between the first semiconductor chip and the second semiconductor chip to surround the bump.

10. The semiconductor package according to claim 1, wherein, The adhesive layer includes a non-conductive film.

11. The semiconductor package according to any one of claims 1 to 10, further comprising: The top semiconductor chip, located on the uppermost of the plurality of first semiconductor chips. The top-layer semiconductor chip has the same horizontal width as the second horizontal width, and The height of the top semiconductor chip is greater than the height of each of the plurality of second semiconductor chips.

12. The semiconductor package according to any one of claims 1 to 10, wherein, The horizontal width of the substrate chip is greater than each of the first and second horizontal widths.

13. A semiconductor package, comprising: The lower substrate has external connection terminals on its lower surface. The substrate chip is located on the lower substrate. Multiple first semiconductor chips, each having a first horizontal width; Multiple second semiconductor chips, each having a second horizontal width greater than the first horizontal width; The top semiconductor chip has a height greater than the height of each of the plurality of second semiconductor chips, and has a horizontal width the same as the second horizontal width; An adhesive layer is provided between adjacent semiconductor chips in the plurality of first semiconductor chips and the plurality of second semiconductor chips, and between the uppermost first semiconductor chip and the top semiconductor chip in the plurality of first semiconductor chips, the adhesive layer including rounded corner portions extending in the horizontal direction; as well as A molded component, wherein a substrate is filled with a base chip, a plurality of first semiconductor chips, a plurality of second semiconductor chips, a top semiconductor chip, and an adhesive layer, filling the gap between them. In this configuration, the plurality of first semiconductor chips and the plurality of second semiconductor chips are alternately stacked on a substrate chip. The top semiconductor chip is located on the uppermost of the plurality of first semiconductor chips. The first horizontal width is smaller than the horizontal width of the adhesive layer, the second horizontal width is the same as the horizontal width of the adhesive layer, and the difference between the second horizontal width and the first horizontal width is the same as the horizontal width of the rounded corner portion. Furthermore, the plurality of first semiconductor chips, the plurality of second semiconductor chips, and the top semiconductor chip are stacked vertically such that the centers of the plurality of first semiconductor chips, the plurality of second semiconductor chips, and the top semiconductor chip in the horizontal direction overlap each other in the vertical direction.

14. The semiconductor package of claim 13, wherein, An intermediate substrate is on a lower substrate, and a substrate chip and a semiconductor chip spaced horizontally from the substrate chip are on the intermediate substrate. The intermediate substrate includes a host layer, a wiring layer, and a through electrode that passes through the host layer in a vertical direction. The wiring layer includes a wiring pattern that electrically connects the substrate chip to the semiconductor chip.

15. A semiconductor package, comprising: Substrate chip; A plurality of first semiconductor chip structures, each comprising a plurality of first semiconductor chips stacked vertically, each of the plurality of first semiconductor chips having a first horizontal width; as well as One or more second semiconductor chips, each having a second horizontal width different from the first horizontal width. The plurality of first semiconductor chip structures and the one or more second semiconductor chips are alternately stacked on a substrate chip, and an adhesive layer is applied between adjacent first semiconductor chips and between each of the plurality of first semiconductor chip structures and each of the one or more second semiconductor chips.

16. The semiconductor package of claim 15, wherein, Each of the plurality of first semiconductor chip structures includes three first semiconductor chips.

17. The semiconductor package of claim 15, wherein, The second horizontal width is greater than the first horizontal width.

18. The semiconductor package of claim 15, wherein: The adhesive layer includes rounded corner portions extending in the horizontal direction, wherein the rounded corner portions are formed by a heat compression process, and The difference between the second horizontal width and the first horizontal width is the same as the horizontal width of the rounded corner.

19. The semiconductor package of claim 15, wherein: The first horizontal width is less than the horizontal width of the adhesive layer, and the second horizontal width is the same as the horizontal width of the adhesive layer.

20. The semiconductor package according to any one of claims 15 to 19, wherein, The side surface of each of the one or more second semiconductor chips is aligned with the side surface of the adhesive layer.

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