Double-side cooled electronic device
By employing a multilayer substrate structure and dual-sided cooling technology in the lateral FET package, the problem of heat dissipation in the package is solved, achieving efficient thermal management and power density improvement, making it suitable for high-frequency and high-voltage switching applications.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2020-05-08
- Publication Date
- 2026-03-13
AI Technical Summary
Lateral field-effect transistor (FET) packages are difficult to cool effectively, especially due to the difficulty in heat dissipation caused by grounding the bottom side of the die, which affects power density and energy efficiency. Existing electrically isolated thermal interface materials also have poor thermal conductivity issues.
The system employs a multilayer substrate structure, including a ceramic layer and metal layers on both sides thereof. It is electrically isolated by an isolation layer and provides heat dissipation paths on both sides of the package structure, avoiding the use of electrically isolated thermal interface materials. The metal layers of the package structure are directly connected using a conductive heat sink.
It achieves dual-sided cooling, improves thermal management efficiency, reduces transistor junction temperature, increases power density and device reliability, reduces thermal resistance, and is suitable for high-frequency, high-voltage switching applications.
Smart Images
Figure CN121666153A_ABST
Abstract
Description
[0001] Information related to divisional application
[0002] This case is a divisional application. The parent application of this divisional application is the invention patent application filed on May 8, 2020, with application number 202080033821.9 and invention title "Double-sided cooling electronic device". Technical Field
[0003] This application relates to electronic devices with dual-sided cooling. Background Technology
[0004] Transistors and other circuit elements in packaged electronics exhibit performance characteristics that vary with operating temperature. Various package types, such as Quad Flat No-Leader (QFN) packages, may include exposed die attachment pads or other exposed thermal pads for cooling via the bottom of the packaged device. Lateral field-effect transistors (FETs) in packaged electronics, however, are difficult to cool. The top surface of a lateral FET die has pads with transistor electrical nodes. The bottom side of the die sometimes operates at ground potential. Heat generated by the die is dissipated to the outside of the package through the bottom-side substrate. Increased power density necessitates improved heat dissipation to facilitate transistor operation in switching applications such as DC-DC converters. Heat dissipation via the bottom side of the die and / or package makes it difficult to increase power density and / or energy efficiency of wide bandgap (WBG) transistors, such as GaN power stage FETs used for switching high voltages at high frequencies. The pad arrangement of lateral FET dies limits the interconnect options for wire or solder connection bumps with limited thermal capacity on top. One cooling solution for QFN packages dissipates heat from the die attach pads (DAPs) to the heatsink via a printed circuit board (PCB) with thermal holes, wherein an electrically insulating thermal interface material (TIM) is provided between the heatsink and the PCB. However, the electrically insulating thermal interface material is typically a poor thermal conductor. Summary of the Invention
[0005] A packaged electronic device is described, comprising: a die attachment pad; first and second semiconductor dies, first sides of which are connected to first sides of the die attachment pad; a substrate; and a package structure surrounding the semiconductor dies, the die attachment pad, and a portion of the substrate. The substrate includes a ceramic layer, a first metal layer formed on a first side of the ceramic layer, and a second metal layer formed on a second side of the ceramic layer. The second metal layer is connected to a second side of the semiconductor die. A first side of the package structure exposes a portion of the first metal layer of the substrate, and a second side of the package structure exposes a portion of a second side of the die attachment pad.
[0006] In another aspect, a packaged electronic device includes: a package structure that surrounds a first semiconductor die and a second semiconductor die; die attachment pads that are soldered to one of the semiconductor dies and exposed along one side of the package structure; and a substrate having a first metal layer exposed along the other side of the package structure, a second metal layer soldered to the semiconductor die, and an isolation layer extending between and separating the first metal layer and the second metal layer.
[0007] One described method includes attaching a first side of first and second semiconductor dies to a first side of die attachment pads, attaching a metal layer on one side of a substrate to a second side of the semiconductor dies, and forming a package structure surrounding the semiconductor dies, wherein the package structure includes a first side exposing a first metal layer on one side of the substrate and a second side exposing one side of the die attachment pads. Attached Figure Description
[0008] Figure 1 It is along Figure 2 and 3 The cross-sectional side view of the packaged electronic device is taken from line 1-1.
[0009] Figure 2 yes Figure 1 Top perspective view of the packaged electronic device.
[0010] Figure 3 yes Figure 1 and 2 Bottom perspective view of the packaged electronic device.
[0011] Figure 4 This is a flowchart of a method for manufacturing packaged electronic devices.
[0012] Figure 5 It is along Figure 6 and 7 The line 5-5 is cut off. Figures 1 to 3 A cross-sectional side view of the substrate of a packaged electronic device.
[0013] Figure 6 yes Figure 5 and 7 Top perspective view of the substrate.
[0014] Figure 7 yes Figure 5 and 6 Bottom perspective view of the substrate.
[0015] Figure 8 It is a cross-sectional side view of a lead frame with die attachment pads and leads.
[0016] Figure 9It is a cross-sectional side view of the first and second semiconductor dies disposed on the first side of the die attachment pad.
[0017] Figure 10 It is a cross-sectional side view of the conductive post located on the secondary lead side of the lead frame.
[0018] Figure 11 It is along Figure 12 The cross-sectional side view of the semiconductor die and lead frame taken from line 11-11 shows the reflow process of soldering the semiconductor die to the die attachment pad and soldering the conductive pillars to the secondary leads.
[0019] Figure 12 This is the scripture Figure 11 Top perspective view of the semiconductor die and lead frame after reflow process.
[0020] Figure 13 It is set in Figure 11 and 12 On semiconductor bare dies and conductive pillars Figures 5 to 7 A cross-sectional side view of the substrate.
[0021] Figure 14 It is along Figure 15 The cross-sectional side view taken by line 14-14 shows the second reflow process of soldering the contacts on the top side of the semiconductor die to a patterned metal layer on the substrate.
[0022] Figure 15 This is the scripture Figure 14 Top perspective view of the semiconductor die and substrate after reflow process.
[0023] Figure 16 It is a cross-sectional side view of the substrate that has been wire bonded to the top side of the semiconductor die and conductive pillar after being processed by wire bonding.
[0024] Figure 17 It is a cross-sectional side view of the substrate that has been molded to form a package structure and then soldered to the top side of the semiconductor die and conductive pillars.
[0025] Figure 18 This is a cross-sectional side view of another exemplary packaged electronic device. Detailed Implementation
[0026] In the accompanying drawings, the same reference numerals always refer to the same elements, and various features are not necessarily drawn to scale. Furthermore, the term "couple" (or "couples") includes indirect or direct electrical or mechanical connections, or combinations thereof. For example, if a first device is coupled to or with a second device, the connection can be a direct electrical connection or an indirect electrical connection via one or more intermediate devices and connectors.
[0027] Figures 1 to 3 An exemplary packaged electronics 100 is shown that provides top-side and bottom-side heat dissipation paths and can be used in conjunction with lateral FETs and other circuit elements. Figure 1 It shows along Figure 2 and 3 The cross-sectional view of the packaged electronic device 100 taken from line 1-1 in the figure. Figure 2 A top perspective view of the packaged electronic device 100 is shown. Figure 3 A bottom perspective view of a packaged electronic device 100 is shown. An exemplary packaged electronic device 100 includes a first semiconductor die 101 and a second semiconductor die 102. In another example, the packaged electronic device 100 includes more than two semiconductor dies.
[0028] In one example, packaged electronic device 100 comprises a starting leadframe structure and has die attachment pads 104 and one or more eventually separated lead structures called leads. In another example, packaged electronic device 100 uses a main leadframe structure having die attachment pads 104 and one or more leads, as described in the following references. Figure 11 and 12 The secondary lead frame structure shown is constructed as described. Figure 1 The packaged electronic device 100 includes leads 106 that are initially included in a die attachment pad 104 within a primary lead frame structure, and secondary leads 108 that are initially part of a secondary lead frame structure. The packaged electronic device 100 includes conductive posts 109 connected (e.g., soldered) to the leads 108.
[0029] In one example, the die attachment pads 104, leads 106 and 108, and conductive post 109 are made of a conductive metal, such as copper. In another example, structures 104, 106, 108, and / or 109 can be different conductive metals, such as aluminum. In one example, the initial master lead frame includes the die attachment pads 104 and leads 106, which are subsequently separated prior to molding, and the second lead frame structure includes lead 108. In another example, conductive structures 104, 106, and 108 are separate structures disposed on a carrier such as tape, followed by die attachment processing and other manufacturing processes to create packaged electronic device 100.
[0030] The packaged electronic device 100 includes a multilayer substrate 110 having an isolation layer 112 (such as a ceramic layer) extending between and separating a lower metal layer and an upper metal layer. The isolation layer 112 is an electrical insulator. The isolation layer 112 includes an upper first side 113. The lower metal layer includes a first conductive portion 114 connected to a lower second side 115 of the isolation layer 112, and a second conductive portion 116 connected to the second side 115. Figures 1 to 3In this example, the first part 114 is electrically isolated from the second part 116.
[0031] The exemplary substrate 110 also includes an upper metal layer 118 (sometimes referred to herein as a first metal layer) extending along a portion of the upper first side 113 of the isolation layer 112. The isolation layer 112 does not include conductive vias and electrically isolates the first and second metal layers from each other, such that the upper first metal layer 118 is electrically isolated from the lower metal layers 114, 116 (sometimes referred to herein as second metal layers). In one example, the first and second metal layers comprise copper. In other embodiments, different conductive metals, such as aluminum, or combinations of conductive metal materials may be used.
[0032] In one example, the first metal layer 118 and the patterned second metal layers 114, 116 are formed on the initial isolation layer substrate 112 (e.g., a ceramic material) using one or more suitable metallization materials and processes, such as direct copper bonding (DBC), active metal brazing (AMB), insulating metal substrate (IMS) processing, direct aluminum bonding (DBA), etc. The metal substrate features of the lower metal layers 114 and 116 can be patterned according to the die arrangement using etching, electroplating, or printing techniques. The conductive metal layers 114, 116, and 118 can be or include any suitable conductive material, such as Cu, Ni, Pd, Ag, Au. In one example, the thickness of the isolation layer 112 (e.g., along...) Figure 1 The thickness of the first metal layer 118 is 50 µm or more and about 300 µm or less in the Z direction, and the thickness of the second metal layers 114 and 116 is 50 µm or more and about 100 µm or less.
[0033] The packaged electronic device 100 also includes a package structure 120 that surrounds the sides of the first semiconductor die 101 and the second semiconductor die 102. Furthermore, the package structure 120 surrounds a portion of the die attachment pad 104, a portion of leads 106 and 108, and a portion of the substrate 110. In one example, the package structure 120 is a molding material, such as plastic. In another example, a ceramic package material may be used. The package structure 120 exposes the bottoms of leads 106 and 108 and the bottom of the die attachment pad 104, for example, to solder these features to a main printed circuit board (PCB, not shown). Furthermore, in the illustrated example, the sides of leads 106, 108 are exposed, which is not strictly required in all possible implementations. Figure 2 and 3 Additionally, the exemplary packaged electronic device 100 is shown to be a QFN type package with device leads on all four sides.
[0034] Refer again Figure 1 The first semiconductor die 101 includes a first contact 121 and a second contact 122 on its upper side 124 or along said upper side. Contacts 121 and 122 are conductive features, such as copper or aluminum die pads exposed along the outer surface of one side 124 of the semiconductor die 101. In one example, contacts 121 and 122 are solder 125 or include said solder, such as solder bumps, to facilitate soldering operations during fabrication. The second contact 122 of the first semiconductor die 101 is soldered along the lower side 126 of the substrate 110 to a first portion 114 of the second metal layer. Figure 1 In the cross-section shown, the first contact 121 is soldered to the first lead 106 via bonding wire 127. In one example, other leads (not shown) of the packaged electronic device 100 are soldered to contacts of corresponding first and / or second semiconductor dies 101, 102. The first semiconductor die 101 in this example includes conductive contacts 128 on its lower side 129. The lower side 129 of the first semiconductor die 101 is sometimes referred to herein as the first side, and the upper side 124 of the first semiconductor die 101 is sometimes referred to herein as the second side of the first semiconductor die 101. For example, the first side 129 is connected to the first side 130 of the die attachment pad 104 by soldering the conductive contacts 128 to the upper first side 130 of the die attachment pad 104.
[0035] The second semiconductor die 102 includes a first contact 131 and a second contact 132 extending on or along an upper side 134. The second semiconductor die 102 also includes a contact 138 connected (e.g., by soldering) to a first side 130 of a die attachment pad 104. The contact 138 extends on or along a lower side 139 of the second semiconductor die 102. The lower side 139 of the second semiconductor die 102 is sometimes referred to herein as the first side, and the upper side 134 of the second semiconductor die 102 is sometimes referred to herein as the second side of the second semiconductor die 102. Figures 1 to 3 In one example, a first portion 114 of the second metal layer is soldered to a contact 122 of the first semiconductor die 101, and the first portion 114 is also soldered to a contact 131 of the second semiconductor die 102. Furthermore, a second portion 116 of the second metal layer is soldered to a contact 132 of the second semiconductor die 102.
[0036] The multilayer substrate 110 has an upper first side 140 formed by an exposed portion of a first metal layer 118. The fully packaged electronic device 100 has an upper first side 141 and a lower second side 142. (As...) Figure 1 and 2As shown, the exposed portion of the first side 140 of the substrate 110 provides an upper heat dissipation path for heat generated from or on one or both of the semiconductor dies 101 and / or 102. Figure 1 and 3 As shown, the lower second side 144 of the die attachment pad 104 is exposed along the second side 142 of the packaged electronics 100, thereby providing a second (lower) heat dissipation path for heat generated in or by one or both of the semiconductor dies 101 and / or 102. The lower side 126 of the substrate 110 is sometimes referred to herein as the second side of the substrate 110. Figures 1 to 3 In one example, the first side 130 of the die attachment pad 104 is soldered to the contact 128 of the first semiconductor die 101 and the contact 138 of the second semiconductor die 102.
[0037] like Figure 1 As shown, a first metal layer 118 is formed on a first side 113 of an exemplary isolation layer 112, and second metal layers 114 and 116 are formed on a second side 115 of the isolation layer 112. In one example, the second metal layers 114 and 116 are patterned metal (e.g., copper) layers, and the first and second portions 114 and 116 are characterized by being designed to interconnect with specific contacts of the first and second semiconductor dies 101 and 102. In the illustrated example, the second portion 116 is also connected (e.g., soldered) to a conductive post 109 to electrically connect the contacts 132 of the second semiconductor die 102 to the lead 108.
[0038] The following text combines Figures 4 to 15 Further described, dies 101 and 102 and substrate 110 can be fabricated separately and incorporated into the packaging process along with the lead frame to form a packaged electronic device 100 with top-side interconnects and top-side exposed pads formed by a first metal layer 118. Substrate 110 provides a good heat dissipation path as a top-side cooling path via the upper second sides 124 and 134 of the respective first and second semiconductor dies 101 and 102. Furthermore, the exposed first metal layer 118 is electrically isolated from the second metal layers 114, 116. This electrical isolation provides isolated thermal pads that facilitate the connection (e.g., gluing) of an external heat sink (not shown) to a first side 140 of the first metal layer 118, thereby eliminating the need for an electrically insulating thermal interface material (TIM) between the heat sink and the first metal layer 118. In one example, substrate 110 is soldered or otherwise attached to the respective second sides 124, 134 of the first and second semiconductor dies 101 and 102 to create both electrical and thermal contacts. The lower first sides 29 and 139 of the corresponding first and second semiconductor dies 101, 102 are connected (e.g., soldered) to the conductive die attachment pads 104 below, thereby making both electrical and thermal contacts therewith.
[0039] As described below, one or more contacts (e.g., contact 121) are wire-connected for the remaining I / O pins or other required electrical connections to the host PCB and / or die. Exemplary device 100 includes leads usable on four external sides, but this is not strictly required in all possible implementations. In one example, packaged electronics 100 is molded into a QFN package shape, such as... Figures 1 to 3 As shown. In other instances, other completed package shapes can be provided, having bottom and top heat dissipation paths to facilitate heat dissipation to the underlying host PCB and the top environment or attached heat sink. In one embodiment, the second semiconductor die 102 of the packaged electronics 100 includes a high-voltage transistor (e.g., a gallium nitride (GaN) FET) whose drain terminal is connected to contact 132 (e.g., in...). Figure 1 The source terminal (marked as "D") is connected to contact 131 (e.g., in...). Figure 1 (marked as "S" in the middle).
[0040] A first portion 114 of the second metal layer electrically connects the transistor source terminal to a contact 122 of the first semiconductor die 101. In this example, the first semiconductor die 101 includes gate driver circuitry to control the transistor operation of the second semiconductor die 102. The first semiconductor die 101 provides an electrical connection between the contact 122 on the second side 124 and the contact 128 on the lower first side 129. Furthermore, the second semiconductor die 102 provides an electrical connection between the contact 131 on the upper second side 134 and the contact 138 on the lower first side 139. In this example, die attachment pads 104 are electrically connected to the transistor source terminal, and the lower second side 144 of the die attachment pads 104 can be soldered to ground or other reference voltage connections on a host PCB (not shown). In addition to power connection, the die attachment pad 104 also serves as a heat-dissipating pad, allowing heat to be removed from the respective lower first sides 129 and 139 of the semiconductor dies 101 and 102 and into the underlying host PCB structure. Furthermore, in this example, a second portion 116 of the second metal layer of the substrate 110 provides an electrical connection from the transistor drain terminal (e.g., contact 132 of the second semiconductor die 102) through conductive posts 109 to lead 108. This electrical connection allows the transistor drain terminal to be connected to the host PCB by soldering the lead 108 to the corresponding PCB pad (not shown).
[0041] In one application, the transistor drain terminal can be connected to a high-voltage signal relative to ground or another reference voltage of the source terminal. A first metal layer 118 is exposed along a first side 141 of the package structure 120. An isolation layer 112 extends between and separates the first metal layer 118 and second metal layers 114, 116 to provide electrical isolation. The electrical isolation of the first and second metal layers of the substrate 110 helps prevent the application of high voltage to the first metal layer 118, and the conductive heat sink structure can be soldered or otherwise attached to the upper first side 140 of the substrate 110 without the need for an electrically insulating thermal interface material. In this example, the second metal layers 114, 116 are soldered to contacts 122 of the first semiconductor die 101 and contacts 131 and 132 of the second semiconductor die 102. In this way, the exemplary substrate 110 facilitates heat transfer, allowing heat to pass through the substrate 110, and ( Figure 1 The material is moved upwards to the environment of the packaged electronic device 100 or any attached heat sink (not shown), thereby being removed from the upper second side 124 and 134 of the respective first and second semiconductor dies 101 and 102. Figures 1 to 3 In the example, the package structure 120 surrounds a first semiconductor die 101 and a second semiconductor die 102, as well as a die attachment pad 104, a portion of a substrate 110, and a portion of device leads 106 and 108.
[0042] Now for reference Figures 4 to 17 , Figure 4 A method 400 for fabricating packaged electronic devices is shown. Figures 5 to 15 An exemplary packaged electronic device 100 prepared according to method 400 is shown. Figure 4 In one example, a ceramic substrate with patterned metal on the lower side and isolation metal on the upper side is provided at 401. Figures 5 to 7 As shown above Figure 1 The example of substrate 110 shown, the substrate in Figure 4 Provided at 401. In one example, substrate 110 is fabricated separately, for example, made of ceramic or other insulating substrate 112. In one embodiment, a first metal layer 118 and patterned second metal layers 114, 116 are formed on the insulating layer 112 using one or more of DBC, AMB, IMS, and DBA processes at 401. In one example, in such... Figure 4 In the illustrated process 400, substrate 110 is provided as an input component. In another possible embodiment, method 400 includes the fabrication of substrate 110. Figure 6 An exemplary top perspective view of substrate 110 is shown, wherein a generally uniform first metal layer 118 is formed on the upper first side 113 of the isolation layer 112 along the upper side 140 of substrate 110. Figure 5 It shows along Figure 6and 7 A cross-sectional side view of substrate 110 taken by line 5-5. In this example, Figure 7 An exemplary patterned copper structure is shown, comprising a first portion 114 and a second portion 116 of a second metal layer formed on a lower second side 115 of an isolation layer 112 along a lower second side 126 of a substrate 110.
[0043] Method 400 in Figure 4 Continue at 402, where solder is applied to select the die attachment pads and a portion of the upper side of any included subleads. Figure 8 An example is shown in which a solder deposition process 800 is performed to apply solder 802 to a specific portion of the upper first side 130 of the die attachment pad 104 and the top side of the secondary lead 108. In one example, solder is applied at 402 using a solder mask (not shown) via a screen printing process 800. In another example, solder is applied at 402 via a printing process 800.
[0044] At 404, method 400 continues, wherein the first and second semiconductor dies are placed on die attachment pads. Figure 9 An example is shown in which a die attachment process 900 is performed to attach the lower first sides 129 and 139 of corresponding first and second semiconductor dies 101 and 102 to the upper first side 130 of a die attachment pad 104. In one example, the die attachment process 900 includes operating an automated pick-and-place machine (not shown) to position the semiconductor dies 101 and 102 at predetermined locations on the first side 130 of the die attachment pad, such as... Figure 10 Further as shown. In Figure 4 At position 405, method 400 further includes placing one or more conductive posts (e.g., copper) on the secondary lead. Figure 10 An example is shown in which a conductive post placement process 1000 is performed to place a conductive post 109 at a predetermined position on the upper side of the secondary lead 108. Any suitable placement process 1000 can be used, such as an automated pick-and-place process using a suitable machine (not shown). See below for further details. Figure 16 In another embodiment, the placement of the copper pillar at 405 can be omitted from method 400.
[0045] Method 400 in Figure 4 Continue at position 406, where semiconductor die contacts are soldered to die attachment pads via reflow soldering and any included conductive pillars are soldered to the top of the secondary lead. Figure 11 and 12 An example is shown, in which... Figure 11A thermal reflow process 1100 is performed, in which pre-placed solder is reflowed to solder the contacts on the lower sides 129 and 139 of the corresponding first and second dies 101 and 102 to the first side 130 of the die attachment pad 104, and one or more copper pillars 109 are soldered to the upper part of the secondary lead 108, such as... Figure 12 As shown. In one example, multiple copper pillars 109 are welded to a secondary lead frame portion having multiple associated secondary leads 108, as... Figure 8 As shown.
[0046] Method 400 in Figure 4 The process continues at 408 and 410, wherein the substrate 110 is attached to the semiconductor die and any included conductive pillars. At 408, method 400 includes placing the lower side of the ceramic substrate on top of the first and second semiconductor dies and any included conductive pillars. Figure 13 An example is shown in which a placement process 1300 is performed to place second metal layers 114, 116 of a second side 126 of a substrate 110 onto a second side 124 of a first semiconductor die 101 and a second side 134 of a second semiconductor die 102. In one example, solder 125 is provided on the top side of a conductive pillar 109, and the first and second semiconductor dies 101 and 102 include solder bumps 125 formed on corresponding contacts 121, 122, 131, and 132 on the respective upper second sides 124 and 134, as shown. Figure 13 As shown. In another example, screen printing, printing, or other solder application processes are performed before substrate placement to apply solder 125, as... Figure 13 As shown. In this example, placement process 1300 also places a portion of the lower side 126 of the second portion 116 onto the top surface of the conductive post 109, as shown. Figure 14 As shown.
[0047] Refer again Figure 14 and 15 Method 400 Figure 4 The process continues at point 410, where reflow solder is used to bond the second metal layer of the substrate with the semiconductor die and conductive pillars. Figure 14 An example is shown in which a thermal reflow process 1400 is performed, reflowing solder 125 to bond the lower second side 126 of the second metal layer to contacts 122, 131, and 132 of the respective semiconductor dies 101 and 102. Process 1400 also bonds a second portion 116 of the second metal layer to the top side of the conductive pillar 109, thereby forming... Figure 5 The partially completed device 100 is shown.
[0048] Method 400 in Figure 4 Continue at point 412, where lead wire bonding is performed. Figure 16An example is shown in which a wire bonding process 1600 is performed to attach one or more bonding wires 127 to pre-specified contacts and / or between leads. Figure 16 An exemplary cross-sectional view illustrates an exemplary bonding wire 127, with a first end soldered to a contact 121 of a first semiconductor die 101 and a second end soldered to a lead 106. In one example, the wire bonding process 1600 creates multiple bonding wire connections between the contacts of dies 101 and 102, between one of the dies and a lead, or a combination thereof. In one example described above, the first semiconductor die 101 includes drive circuitry having multiple contacts soldered to corresponding leads of packaged electronics 100 to interface the drive circuitry with external host circuitry (not shown), and some embodiments may include more than two semiconductor dies having corresponding bonding wire connections (not shown) to connect to associated contacts of any included additional semiconductor dies, or to connect between said associated contacts.
[0049] Method 400 in Figure 4 Continue at point 414 to perform molding to form the encapsulation structure. Figure 17 An example is shown in which a molding process 1700 is performed to form an exemplary molded package structure 120 surrounding a first semiconductor die 101 and a second semiconductor die 102. In one example, the package structure 120 includes: a first side 141 that exposes a first metal layer 118 of a substrate 110; and a lower second side 142 that exposes a second side 144 of die attachment pads 104. As described above, Figure 1 and 17 The resulting packaged electronic device 100 provides top-side and bottom-side cooling paths to improve the power density and energy efficiency of various semiconductor circuit types, including power conversion and associated power transistors of one or both of semiconductor dies 101 and 102.
[0050] Figure 18 Another exemplary packaged electronic device 1800 is shown in a cross-sectional side view, which includes the components described above. Figure 1 The features described in device 100. Unlike packaged electronic device 100, Figure 18 The packaged electronic device 1800 does not include the aforementioned lead 108 or conductive post 109. Instead, the drain connection of the device 1800 is formed by a shaped clip lead 1708 extending to the bottom side 142 of the packaged electronic device 1800 and including an angled portion that is directly soldered to a second portion 116 of the second metal layer of the substrate 110. The exemplary packaged electronic device 1800 can use the above-described Figure 4 The exemplary method 400 is used to prepare it, wherein the placement of the copper pillar at point 405 is omitted.
[0051] Exemplary packaged electronic devices 100 and 1800, and exemplary method 400, provide solutions for facilitating unidirectional package cooling (e.g., top-side and bottom-side cooling) of packaged devices comprising lateral FETs or other semiconductor dies having a multi-node contact or pad arrangement on the top side of the die. The concept employs an isolation substrate structure 110 for compact dual-side cooling, and the illustrated techniques can be used in conjunction with a standard lead frame for die attachment and an insulating substrate for top-side interconnection. The illustrated examples show implementations of packaged electronic devices 100 and 1800 with the final standard QFN package form. Improved thermal management through dual-side cooling helps reduce transistor junction temperature, which can improve device reliability and contribute to increased power density. Dual-side cooling technology splits the transistor's thermal resistance network into two parallel paths, and the junction-to-ambient thermal resistance (i.e., The reduction of ) makes it easier to have higher power capacity and / or lower junction temperature in the package.
[0052] The examples above are merely illustrative of several possible implementations of various aspects of the specification, and others skilled in the art will derive equivalent changes and / or modifications upon reading and understanding this specification and the accompanying drawings. Modifications to the examples are possible within the scope of the claims, and other implementations are also possible.
Claims
1. A packaged electronic device, comprising: The bare die attachment pad includes a first side and a second side opposite to the first side; A first semiconductor die includes a first side attached to a first side of the die attachment pad and a second side opposite to the first side of the first semiconductor die, the second side of the first semiconductor die including a first contact and a second contact. Substrate, comprising: An isolation layer comprising a first side and a second side opposite to the first side of the isolation layer. A first metal layer is formed on the first side of the insulating layer, and A second metal layer is formed on the second side of the isolation layer. The second metal layer includes a first portion and a second portion. The first portion is attached to the second side of the first semiconductor die and electrically coupled to the first contact of the first semiconductor die. The first portion is electrically isolated from the second portion. as well as A package structure surrounding the first semiconductor die, a portion of the die attachment pads, and a portion of the substrate, the package structure comprising: The first side exposes a portion of the first metal layer of the substrate.
2. The packaged electronic device of claim 1, wherein the package structure includes a second side that exposes a portion of the second side of the die attachment pad.
3. The packaged electronic device of claim 1, wherein the second portion of the second metal layer is attached to the second side of the first semiconductor die and electrically coupled to the second contact of the first semiconductor die.
4. The packaged electronic device of claim 1, comprising a second semiconductor die, the second semiconductor die including a first side attached to a first side of the die attachment pad and a second side opposite to the first side of the second semiconductor die, the second side of the second semiconductor die including a third contact.
5. The packaged electronic device according to claim 4, The first portion of the second metal layer is attached to the second side of the second semiconductor die and electrically coupled to the third contact.
6. The packaged electronic device of claim 1, comprising a lead connected to the second portion of the second metal layer.
7. The packaged electronic device of claim 1, wherein the first side of the first semiconductor die includes a fourth contact electrically coupled to the die attachment pad.
8. The packaged electronic device of claim 4, wherein the first side of the second semiconductor die includes a fifth contact electrically coupled to the die attachment pad.
9. A packaged electronic device, comprising: The bare die attachment pad includes a first side and a second side opposite to the first side; A first semiconductor die includes a first side attached to a first side of the die attachment pad and a second side opposite to the first side of the first semiconductor die, the second side of the first semiconductor die including a first contact and a second contact. Substrate, comprising: An isolation layer comprising a first side and a second side opposite to the first side of the isolation layer. A first metal layer is formed on the first side of the insulating layer, and A second metal layer is formed on the second side of the isolation layer. The second metal layer includes a first portion that is attached to the second side of the first semiconductor die and electrically coupled to the first contact of the first semiconductor die. A lead wire that connects to the first portion of the second metal layer; as well as A package structure surrounding the first semiconductor die, a portion of the die attachment pads, a portion of the leads, and a portion of the substrate, the package structure comprising: The first side exposes a portion of the first metal layer of the substrate, and The second side exposes a portion of the second side of the die attachment pad.
10. The packaged electronic device of claim 9, wherein the second metal layer includes a second portion attached to a second side of the first semiconductor die and electrically coupled to a second contact of the first semiconductor die, wherein the second portion is electrically isolated from the first portion.
11. The packaged electronic device of claim 9, wherein the isolation layer comprises a ceramic material.
12. The packaged electronic device of claim 10, comprising a second semiconductor die, the second semiconductor die including a first side attached to a first side of the die attachment pad and a second side opposite to the first side of the second semiconductor die, the second side of the second semiconductor die including a third contact.
13. The packaged electronic device of claim 12, wherein the second portion of the second metal layer is attached to the second side of the second semiconductor die and electrically coupled to the third contact of the second semiconductor die.
14. The packaged electronic device of claim 9, wherein the first side of the first semiconductor die includes a fourth contact electrically coupled to the die attachment pad.
15. The packaged electronic device of claim 12, wherein the first side of the second semiconductor die includes a fifth contact electrically coupled to the die attachment pad.
16. The packaged electronic device of claim 9, comprising a metal pillar connected between the lead and the first portion of the second metal layer.
17. The packaged electronic device of claim 9, wherein the package structure includes a second side that exposes a portion of the second side of the die attachment pad.
18. A packaged electronic device comprising: The bare die attachment pad includes a first side and a second side opposite to the first side; A first semiconductor die includes a first side attached to a first side of the die attachment pad and a second side opposite to the first side of the first semiconductor die, the second side of the first semiconductor die including a first contact and a second contact. The second semiconductor die includes a first side attached to a first side of the die attachment pad and a second side opposite to the first side of the second semiconductor die, the second side of the second semiconductor die including a third contact. Substrate, comprising: An isolation layer comprising a first side and a second side opposite to the first side of the isolation layer. A first metal layer is formed on the first side of the insulating layer, and A second metal layer is formed on the second side of the isolation layer. The second metal layer includes a first portion that is attached to the second side of the first semiconductor die and electrically coupled to the first contact of the first semiconductor die, and a third contact that is attached to the second side of the second semiconductor die and electrically coupled to the first semiconductor die. as well as A package structure surrounding the first semiconductor die, a portion of the die attachment pads, a portion of the leads, and a portion of the substrate, the package structure comprising: The first side exposes a portion of the first metal layer of the substrate, and The second side exposes a portion of the second side of the die attachment pad.
19. The packaged electronic device of claim 18, wherein the package structure includes a second side that exposes a portion of the second side of the die attachment pad.
20. The packaged electronic device of claim 18, wherein the second metal layer includes a second portion attached to a second side of the first semiconductor die and electrically coupled to a second contact of the first semiconductor die, wherein the second portion is electrically isolated from the first portion.
21. The packaged electronic device of claim 20, comprising a lead connected to the second portion of the second metal layer.
22. The packaged electronic device of claim 18, wherein the first side of the first semiconductor die includes a fourth contact electrically coupled to the die attachment pad.
23. The packaged electronic device of claim 18, wherein the first side of the second semiconductor die includes a fifth contact electrically coupled to the die attachment pad.