Computing performance improving method and electronic equipment

Abstract

The embodiment of the invention provides a calculation performance improving method and electronic equipment. The method comprises the following steps: acquiring a working load parameter of a current time period; based on the workload parameter of the current time period, determining a workload parameter of a next time period; based on the workload parameters of the next time period, determining the proportion of basic workloads of the next time period; and determining a combination (target CPU frequency, target DDR frequency) that satisfies the required CPU capacity of the next time period, the required CPU capacity of the next time period being determined based on the task utilization rate of the current time period. According to the technical scheme, the calculation performance improving method can improve the performance of the electronic equipment.

Description

Technical Field

[0001] Embodiments of this application relate to the field of communication technology, and more specifically, to a method for improving computing performance and an electronic device. Background Technology

[0002] CPU capacity is a number that provides scheduler information about the CPU's performance characteristics.

[0003] CPU capacity can be obtained by running the Dhrystone benchmark at its highest frequency on each CPU. The obtained Dhrystone million instructions per second (DMIPS) is further divided by the CPU frequency to obtain DMIPS / MHz, making it easier to compare CPUs running at different clock rates.

[0004] However, since CPU capacity is evaluated against a benchmark at maximum frequency, some applications may not have their execution speed linearly dependent on CPU frequency. CPU capacity obtained by running the Dhrystone benchmark may result in performance degradation. Summary of the Invention

[0005] Embodiments of this application provide a method and electronic device for improving computing performance, which can flexibly adjust the CPU frequency and DDR frequency to improve device performance.

[0006] According to a first aspect, embodiments of this application provide a method for improving computing performance, comprising: obtaining workload parameters for a current time period; determining workload parameters for a next time period based on the workload parameters for the current time period; determining the proportion of the basic workload for the next time period based on the workload parameters for the next time period; and determining a combination of a target CPU frequency and a target DDR frequency to satisfy the required CPU capacity for the next time period, wherein the required CPU capacity for the next time period is determined based on the task utilization rate of the current time period.

[0007] To meet the required CPU capacity for the next time period, the CPU capacity corresponding to the target CPU frequency and target DDR frequency is equal to or greater than the required CPU capacity. The task utilization rate of the current cycle is collected to determine the required capacity for the next cycle. Optionally, the task utilization rates of previous cycles are also used to determine the required capacity for the next cycle.

[0008] According to the above technical solution, workload parameters are collected to decompose one or more running workloads or tasks into basic workloads. The combination of target CPU frequency and target DDR frequency is selected based on the decomposition of the basic workload for the next time period. Since the scheduling of CPU frequency and DDR frequency takes workload parameters into account, it is expected to offer other advantages such as lower power consumption while maintaining the same performance.

[0009] In one alternative implementation, the electronic device includes one or more CPU cores, and determining the combination of target CPU frequency and target DDR frequency to meet the required CPU capacity for the next time period includes: determining the combination of target CPU cores, target CPU frequency, and target DDR frequency to meet the required CPU capacity for the next time period.

[0010] The electronic device may include one or more CPU cores. When the electronic device includes more than one CPU core, the CPU cores for the next time period are also determined. That is, for the next cycle, a combination of target CPU cores, target CPU frequency, and target DDR frequency that meets the required CPU capacity is determined.

[0011] In one optional implementation, determining the combination of target CPU frequency and target DDR frequency to satisfy the required CPU capacity for the next time period includes: determining different CPU capacities and corresponding different combinations of CPU frequency and DDR frequency; determining at least one combination of CPU frequency and DDR frequency to satisfy the required CPU capacity, wherein the combination of target CPU frequency and target DDR frequency corresponds to the minimum power consumption of at least one combination of CPU frequency and DDR frequency.

[0012] For each combination of CPU frequency and DDR frequency, determine the corresponding CPU capacity. The relationship between CPU capacity and the combination of CPU frequency and DDR frequency can be represented or shown in a graph, table, or simple array of numbers (list of arrays).

[0013] Based on the above technical solution, a power model corresponding to each basic workload can be prepared in advance. When one or more running tasks or workloads are broken down into basic workloads, the power consumption of the running tasks or workloads on each configuration (CPU frequency and DDR frequency), and possibly the power consumption on each CPU core, can be determined. Then, a combination of target CPU frequency and target DDR frequency is selected according to the power model to save power while meeting the required CPU capacity for the next time period.

[0014] Alternatively, the combination with the fastest processing speed can be selected from all combinations of CPU frequency and DDR frequency to reduce processing time.

[0015] Alternatively, you can choose a combination of target CPU frequency and target DDR frequency based on other rules.

[0016] In one alternative implementation, the workload parameters include: instructions, cycles, and L3 cache backfilling.

[0017] Instructions, cycles, and L3 cache refill can be collected from the PMU. Additionally, workload parameters may include at least one of the following: backend stall, frontend stall, and L2 cache refill.

[0018] In one alternative implementation, the basic workload for the next time period includes CPU-limited workload and memory-limited workload.

[0019] In one alternative implementation, the memory-limited workload includes at least one of the following workloads: memory latency-limited workload, memory bandwidth-limited workload, and front-end-limited workload.

[0020] In addition, the basic workload for the next time period may not include one or more of the basic workloads listed above, or may include other types of basic workloads. For different types of workloads, different workload parameters need to be collected.

[0021] In one alternative implementation, the length of the current time period and / or the length of the next time period is between 4 ms and 100 ms.

[0022] Optionally, the length of the next time period can be less than 4 ms, such as 1 ms, 2 ms, 3 ms, etc.

[0023] The current time period and the next time period can have different lengths. Furthermore, they may have the same length.

[0024] In one optional implementation, determining the workload parameters for the next time period based on the workload parameters for the current time period includes: determining the workload parameters for the next time period based on the workload parameters for the current time period using trivial forecasting or EMA forecasting.

[0025] According to a second aspect, embodiments of this application provide a computer-readable storage medium including instructions. When the instructions are executed on a computer, they cause the computer to perform the methods of the first aspect or any optional implementation thereof.

[0026] According to a third aspect, an electronic device is provided, including a processor and a memory. The processor is connected to the memory. The memory is used to store instructions, and the processor is used to execute the instructions. When the processor executes the instructions stored in the memory, the processor performs the methods of the first aspect or any optional implementation thereof.

[0027] According to a fourth aspect, a chip system is provided, wherein the chip system includes a memory and a processor, wherein the memory is used to store a computer program, and the processor is used to call the computer program from the memory and run the computer program to cause a device in which the chip system resides to perform the methods of the first aspect or any optional implementation thereof.

[0028] According to a fifth aspect, a computer program product is provided that, when the computer program product is run on a device, causes the device to perform the methods of the first aspect or any optional implementation thereof. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this application.

[0030] Figure 2 This is a flowchart of a method for improving computing performance provided in an embodiment of this application.

[0031] Figure 3 This is a schematic diagram illustrating the variation of CPU capacity when running different basic workloads, according to an embodiment of this application.

[0032] Figure 4 This is a schematic flowchart illustrating the relationship between CPU capacity and the combination of CPU frequency and DDR frequency under different basic workload ratios, according to an embodiment of this application.

[0033] Figure 5 This is a schematic flowchart of a method for improving computing performance provided in an embodiment of this application.

[0034] Figure 6 This is a schematic block diagram of an electronic device 600 provided in an embodiment of this application.

[0035] Figure 7 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0036] The technical solutions in this application are described below with reference to the accompanying drawings.

[0037] The terminology used in the following embodiments of this application is for describing specific embodiments only and is not intended to limit this application. Unless the context clearly indicates otherwise, the singular terms "a," "the," "the," "this," and "the one" used in this specification and the appended claims are also intended to include plural forms such as "one or more." It should also be understood that in the following embodiments of this application, "at least one" or "one or more" refers to one, two, or more. The term "and / or" describes the association between related objects, indicating that three relationships may exist. For example, A and / or B can represent the following three cases: only A exists, both A and B exist, and only B exists. A and B can be in singular or plural form. The character " / " generally indicates an "or" relationship between related objects.

[0038] In this specification, references to "one embodiment," "some embodiments," etc., indicate that one or more embodiments of this application include the specific features, structures, or characteristics described in the reference embodiments. Therefore, in this specification, unless otherwise stated, expressions such as "in one embodiment," "in some embodiments," "in some other embodiments," "in other embodiments," etc., appearing in different places do not necessarily refer to the same embodiment, but rather to "one or more embodiments, but not all embodiments." Unless otherwise stated, the terms "include / comprise," "have," and variations thereof all mean "including but not limited to."

[0039] refer to Figure 1 The diagram shows a hardware structure schematic of an electronic device provided in an embodiment of this application.

[0040] In some embodiments, the electronic device may be a portable electronic device that also includes other functions such as personal digital assistant functionality and / or music player functionality, such as a mobile phone, tablet computer, or wearable electronic device with wireless communication capabilities (e.g., a smartwatch). Exemplary embodiments of the portable electronic device include, but are not limited to, portable electronic devices using HarmonyOS®, OpenHarmony®, iOS®, Android®, Microsoft®, or other operating systems. The portable electronic device may also be other portable electronic devices, such as a laptop computer. It should also be understood that in some other embodiments, the electronic device may also be a desktop computer instead of a portable electronic device.

[0041] Electronic device 100 may include processor 110, external memory interface 120, internal memory 121, universal serial bus (USB) port 130, charging management module 140, power management module 141, battery 142, antenna 1, antenna 2, mobile communication module 150, wireless communication module 160, audio module 170, speaker 170A, receiver 170B, microphone 170C, headphone jack 170D, sensor module 180, button 190, motor 191, indicator light 192, camera 193, display 194, subscriber identification module (SIM) card interface 195, etc.

[0042] It is understood that the structures shown in the embodiments of this application do not constitute a specific limitation on the electronic device 100. In some other embodiments of this application, the electronic device 100 may include more or fewer components than shown, or some components may be combined, some components may be separated, or different component arrangements may be used. The components shown in the figures can be implemented by hardware, software, or a combination of software and hardware.

[0043] Processor 110 may include one or more processing units. For example, processor 110 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural network processing unit (NPU). Different processing units may be independent devices or integrated into one or more processors. In some embodiments, electronic device 101 may also include one or more processors 110. The controller may generate operation control signals based on instruction opcodes and time-series signals to control the reading and execution of instructions. In some other embodiments, processor 110 may also include memory for storing instructions and data. For example, the memory in processor 110 may be a cache memory. The memory may store instructions and data that have just been used by processor 110 or that have been repeatedly used by processor 110. If processor 110 needs to reuse an instruction or data, it can directly retrieve the instruction or data from memory to avoid repeated access. This reduces the waiting time of processor 110 and improves the efficiency of electronic device 101 in processing data or executing instructions.

[0044] The processor 110 can implement the technical solutions proposed in this application.

[0045] Internal memory 121 can be used to store one or more computer programs, wherein the one or more computer programs include instructions. Processor 110 can execute the instructions stored in internal memory 121, causing electronic device 101 to perform the always-on display method, various applications, data processing, etc., provided in some embodiments of this application. Internal memory 121 may include a program storage area and a data storage area. The program storage area may store an operating system. The program storage area may also store one or more applications (e.g., Gallery and Contacts, etc.). The data storage area may store data (e.g., photos and contacts) created during the use of electronic device 101. In addition, internal memory 121 may include high-speed random-access memory (RAM), and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or universal flash storage (UFS). In some embodiments, processor 110 can execute instructions stored in internal memory 121 and / or instructions stored in memory set in processor 110 to cause electronic device 101 to perform the always-on display method, other applications, data processing, etc., provided in embodiments of this application.

[0046] CPU capacity is a number that provides scheduler information about the CPU's performance characteristics.

[0047] CPU capacity can be obtained by running the Dhrystone benchmark at its highest frequency on each CPU. The obtained Dhrystone million instructions per second (DMIPS) is further divided by the CPU frequency to obtain DMIPS / MHz, making it easier to compare CPUs running at different clock rates.

[0048] However, since CPU capacity is evaluated against a benchmark at maximum frequency, some applications may not have their execution speed linearly dependent on CPU frequency. CPU capacity obtained by running the Dhrystone benchmark may result in performance degradation.

[0049] Embodiments of this application provide a computational improvement method for electronic devices, thereby enhancing the performance of the electronic devices. (Reference) Figure 2 Methods to improve computing performance include the following steps: S210: Get the workload parameters for the current time period.

[0050] Workload parameters include: instructions, cycles, and L3 cache backfill.

[0051] For example, instructions can be instructions per second (IPS). In addition, the term is often used in conjunction with metric prefixes, such as kilo instructions per second (KIPS), millions of instructions per second (MIPS), and billion instructions per second (BIPS).

[0052] The cycle can be an instruction cycle, a CPU cycle, or a clock cycle. An instruction cycle, also known as a fetch-decode-execute cycle or simply a fetch-execute cycle, is the cycle from startup to shutdown for the CPU to process instructions.

[0053] An instruction cycle consists of several CPU cycles, and a CPU cycle consists of several clock cycles.

[0054] Instructions and cycles can be represented by the number of instructions per cycle (IPC).

[0055] L3 cache fill, also known as "L3D cache fill," is an event that tracks all cacheable read transactions returned from dynamIQ shared units (DSUs) and from outside the cluster. L3 cache fill can be presented as per-instruction L3 cache fill.

[0056] By using instructions, cycles, and L3 cache backfill collected for the current time period, one or more workloads or tasks running on an electronic device can be broken down into CPU-limited workloads and memory-limited workloads, and a combination of CPU frequency and DDR frequency can be determined for the next time period, which will be described later in this application.

[0057] In this application, the workload parameters may also include at least one of the following parameters: backend stall, frontend stall, and L2 cache backfill.

[0058] L2 cache backfilling counts the reads and prefetches of newly allocated fill buffer entries, which can be used to further determine the L3 cache frequency for the next time period. In other words, in addition to the CPU and DDR frequencies for the next time period, the L3 cache frequency for the next time period can also be selected to improve computational performance.

[0059] Back-end stagnation and front-end stagnation can be used to identify the proportion of back-end-bound-workload (BE-bound-workload) and front-end-bound-workload (FE-bound-workload).

[0060] When one or more workloads or tasks are running and completed online during the current time period, workload parameters can be collected from the performance monitor unit (PMU) counters.

[0061] In this application, for example, CPU frequency and DDR frequency scheduling can be accomplished through CFS. For CFS, the length of the next time period is not predefined (but known). Therefore, the current time period and the next time period can be determined by CFS, and can be aperiodic.

[0062] Optionally, in this application, the CPU frequency and DDR frequency can be scheduled periodically. Then the length of the current time period and the next time period are both equal to the scheduling cycle.

[0063] The length of the current time interval and the next time interval can range from 4 ms to 100 ms. For example, the length of the current time interval and the next time interval could be 4 ms, 11 ms, 16 ms, 20 ms, 100 ms, etc. It is also possible that the length of the current time interval and the next time interval is less than 4 ms.

[0064] S220: Determine the workload parameters for the next time period based on the workload parameters for the current time period.

[0065] In S220, different schemes can be used to determine the workload parameters for the next time period.

[0066] Option 1: For example, collect the workload parameters for the current time period, and propose that the workload parameters for the next time period remain unchanged, that is, the workload parameters for the next time period are the same as the workload parameters for the current time period (trivial forecasting).

[0067] Option 2: For example, in addition to the current time period, workload parameters from several previous time periods can also be collected. For instance, workload parameters from the previous four time periods can be collected, and an exponential moving average (EMA) can be used to predict the workload parameters for the next time period. Furthermore, the exponential moving average can be replaced by a linear moving average or other forecasting schemes; this application does not limit this choice.

[0068] In addition to the above-mentioned methods, other methods can be used to determine the workload parameters for the next time period, such as simple moving average (SMA) and weighted moving average (WMA). This application does not limit the method used to determine the workload parameters for the next time period. Furthermore, different methods can be used to predict the workload parameters for the next time period for different workload parameters.

[0069] After collecting the necessary parameters (workload parameters for the current time period), S220 can be completed online.

[0070] S230: Determine the proportion of the basic workload for the next time period based on the workload parameters for the next time period.

[0071] Prior to S230, several types of workloads can be evaluated in advance as the basic workloads for one or more applications, tasks, or tasks running on electronic devices. The basic workloads for the next time period include: CPU-limited workloads and memory-limited workloads.

[0072] Optionally, memory-bound workloads include at least one of the following: memory latency-bound workloads, memory bandwidth-bound workloads, and front-end-bound workloads (FE-bound-workload). Memory latency-bound workloads and memory bandwidth-bound workloads are also referred to as back-end-bound workloads (BE-bound-workload).

[0073] In other words, the workload can be broken down into at least CPU-limited workloads and memory-limited workloads. Furthermore, memory-limited workloads can be further broken down into memory latency-limited workloads, memory bandwidth-limited workloads, and front-end-limited workloads. Additionally, CPU-limited workloads can be further decomposed using the corresponding parameters collected within the current time period.

[0074] In this application, memory latency-limited workloads and memory bandwidth-limited workloads can be indistinguishable, which means that the basic workload at the next time step includes: CPU-limited workloads, and at least one of BE-limited workloads and FE-limited workloads.

[0075] Based on the workload parameters obtained from S220, the proportion of different types of basic workloads is determined. For example, a higher number of instructions per cycle (IPC) or instructions per second (IPS) means the CPU can process more instructions per cycle or second, and the proportion of CPU-limited workloads may be higher; a higher number of L3-cache-refills per instruction (L3pi) means the proportion of memory-limited workloads may be higher. In addition, other workload parameters can determine the proportion of other types of basic workloads.

[0076] For example, the workload for the next time period can be broken down into CPU-limited workload and memory-limited workload. The workload can then be represented as CPU-limited workload C + memory-limited workload M, where C + M = 1.

[0077] For example, the workload for the next time period can be decomposed into CPU-limited workload, BE-limited workload, and FE-limited workload. The workload can then be expressed as CPU-limited workload C + BE-limited workload B + FE-limited workload F, where C + B + F = 1.

[0078] Because the proportion of some types of basic workloads is not only linearly related to the workload parameters collected from the PMU counter, but also non-linearly dependent on the workload parameters, optionally, when the electronic device includes more than one CPU core, the relationship between the proportion of some types of basic workloads and the workload parameters varies depending on the hardware (system on chip, SoC). In this application, it is preferable to evaluate offline workloads that can serve as basic workloads as far in advance as possible, for example, before implementing the technical solution of this application, to schedule the CPU frequency and DDR frequency. For example, a model / algorithm (e.g., a neural network) can be trained to decompose one or more workloads or one or more tasks into basic workloads. One or more workloads that can be decomposed into basic workloads of a predefined proportion can be run offline to collect the corresponding parameters as data for training the model / algorithm. Therefore, when one or more actual workloads or one or more tasks are running on the electronic device, one or more workloads or one or more tasks can be decomposed into basic workloads using a trained model / algorithm based on the workload parameters.

[0079] In addition, the type of workload to be used as the base workload can be evaluated online.

[0080] Different basic workloads have different characteristics. The time to complete a CPU-limited workload (or compute-limited workload) is primarily determined by the CPU's speed. When executing a CPU-limited workload, the processor's task utilization is very high, potentially reaching 100% utilization during benchmark runs.

[0081] Memory-limited workloads are any type of workload that requires more data or instruction access (in memory) than CPU operations or CPU caches. Examples include memory latency-limited workloads (processing instructions in the CPU while accessing data unavailable to the CPU, potentially of undesirable size), memory bandwidth-limited workloads (requiring access to large amounts of data unavailable to the CPU), and FE-limited workloads (where the next instruction cannot be fetched in advance due to program structure, as its location is defined by the result of the current instruction's computation)—where the CPU waits for memory accesses to fetch the next instruction for execution.

[0082] When different types of basic workloads are running, CPU capacity varies in response to changes in CPU frequency and DDR frequency. For example, if a memory-limited workload is not further broken down into memory latency-limited, memory bandwidth-limited, and front-side-limited workloads, the workload for the next time period can be broken down into CPU-limited and memory-limited workloads. Analysis of collected data on basic workloads has shown that for CPU-limited workloads, CPU capacity depends on the CPU frequency; while for memory-limited workloads (including at least one of memory latency-limited, memory bandwidth-limited, and front-side-limited workloads), CPU capacity depends on the DDR frequency, which differs from the CPU capacity measured for CPU-limited workloads. It is beneficial to analyze the changes in CPU capacity caused by variations in CPU frequency and DDR frequency in response to different types of basic workloads in advance (e.g., before one or more applications or tasks run).

[0083] Figure 3 This illustrates CPU capacity variations when running different base workloads. Black squares represent the relationship between CPU capacity and CPU frequency when running CPU-limited workloads. CPU capacity is linearly related to CPU frequency and independent of DDR frequency. Gray circles represent the relationship between CPU capacity and CPU frequency at different DDR frequencies when running memory-limited workloads. CPU capacity depends on both the DDR frequency and the CPU frequency of the memory-limited workload. At a CPU frequency of approximately 2400MHz, the CPU capacity for memory-limited workloads varies significantly with different DDR frequencies compared to CPU capacity when running CPU-limited workloads, potentially increasing by 30% with increasing DDR frequency and decreasing by 20% with decreasing DDR frequency (as shown in box 310). Memory-limited workloads exhibit a non-linear dependence on CPU frequency. Furthermore, in... Figure 3 In this context, as the CPU frequency changes from its lowest to its highest value, the CPU capacity can remain almost the same even with different DDR frequencies.

[0084] In order to obtain Figure 3 Prior to S210, different types of basic workloads were run in advance on all configurations (different combinations of CPU frequencies and different combinations of DDR frequencies), and the relationship between CPU capacity and the combination of CPU frequency and DDR frequency was calculated for different types of basic workloads.

[0085] For example, the basic workload capacity value (CPU capacity on the Y-axis) can be collected by running each basic workload on each core at each CPU frequency and each DDR frequency and collecting workload parameters.

[0086] For example, CPU capacity can be calculated as 1 / execution_time. These values ​​are then normalized by referring to the highest score obtained in the system.

[0087] In another example, CPU capacity can be calculated as instructions / CPU cycles * CPU frequency. These values ​​are then normalized by referencing the highest score achieved in the system.

[0088] The results of CPU capacity calculations based on the execution results of basic workloads at each CPU frequency and each DDR frequency can be presented in tabular form, such as... Figure 3 As shown.

[0089] based on Figure 3 The chart shows that for a given workload / task where the proportion of memory-limited workloads is greater than 0, there are several combinations of CPU and DDR frequencies that provide acceptable CPU capacity (above the required CPU capacity). A combination can be selected from several options to meet specific conditions. For example, a combination corresponding to the lowest power consumption can be chosen to improve energy efficiency.

[0090] Despite Figure 3 Although not shown in the text, it is clear that while all workloads are memory-limited workloads, the relationship between CPU capacity and the combination of CPU frequency and DDR frequency differs for FE-limited, memory latency-limited, and memory bandwidth-limited workloads. The relationship between CPU capacity and the combination of CPU frequency and DDR frequency was also analyzed offline for FE-limited, memory latency-limited, and memory bandwidth-limited workloads (and other basic workloads not limited to those provided in this application). Therefore, for different basic workloads, by running these basic workloads on electronic devices, different CPU capacities and corresponding different combinations of CPU frequency and DDR frequency can be recorded, such as... Figure 3 As shown.

[0091] Furthermore, the relationship between CPU capacity and the combination of CPU frequency and / or DDR frequency may differ for different CPU cores and for different types of basic workloads, although... Figure 3 The relationship of only one CPU core is shown.

[0092] By analyzing the relationship between CPU capacity and the combination of CPU frequency and DDR frequency for basic workloads, it is possible to determine the decomposition of basic workloads for the next time period to facilitate scheduling CPU frequency and DDR frequency.

[0093] S240: Determine the combination of (target CPU frequency, target DDR frequency) to meet the required CPU capacity for the next time period.

[0094] The required capacity for the next time period can be determined based on the task utilization rate collected for the current time period (or task utilization rates collected for several past time periods), where task utilization is a percentage representing the throughput demand of a task. For example, 100% utilization indicates that the task is a busy cycle, while 10% utilization indicates that it is a short-cycle task with a longer sleep time than execution time. In other words, the required capacity for the next time period is determined based on the task utilization rate of the current time period or the task utilization rate of several recent time periods.

[0095] It should be noted that the task here refers to the workload running within the current time period. It can be a single task or application, or several tasks or applications, which are regarded as a whole as a task. For example, when the current time period is a time segment in which three tasks are running, these three tasks can be regarded as a whole.

[0096] To schedule combinations of CPU frequency and DDR frequency (and possibly CPU cores), it is necessary to determine the relationship between CPU capacity and combinations of CPU frequency and DDR frequency (and possibly CPU cores) for one or more workloads or tasks being run. This relationship can be determined based on the relationships of the basic workloads, which will be discussed in detail later.

[0097] For example, Figure 4 (a) and Figure 4 (b) shows the relationship between CPU capacity and the combination of CPU frequency and DDR frequency under 70% CPU-limited workload + 30% memory-limited workload and 30% CPU-limited workload + 70% memory-limited workload, respectively.

[0098] Figure 4The CPU capacity on the Y-axis can be determined based on the CPU capacity of the corresponding base workload and the proportion of each base workload. For example, the CPU capacity at a specified combination of CPU frequency and DDR frequency is linearly related to the CPU capacity of each base workload at the specified combination of CPU frequency and DDR frequency. If one or more workloads or tasks are broken down into 70% CPU-limited workload and 30% memory-limited workload, then the CPU capacity at a specified combination of CPU frequency and DDR frequency can be calculated using the following formula: Capacity = Capacity1 * P1 + Capacity2 * P2, where Capacity is the CPU capacity of the one or more running tasks, Capacity1 is the CPU capacity of the CPU-limited workload, P1 is the proportion of the CPU-limited workload, Capacity2 is the CPU capacity of the memory-limited workload, and P2 is the proportion of the memory-limited workload.

[0099] The function above is just an example to demonstrate how to calculate the CPU capacity of one or more running tasks or workloads, and is not intended to limit the method of calculating the CPU capacity of one or more running tasks or workloads.

[0100] If there is more than one CPU core, select the combination of the target CPU core, target CPU frequency, and target DDR frequency.

[0101] According to such Figure 4 The analysis shown allows you to select at least one combination that meets the required CPU capacity, and based on specific needs, select a combination of target CPU cores, target CPU frequency, and target DDR frequency from at least one combination. For example, a combination of target CPU cores, target CPU frequency, and target DDR frequency can be selected based on a power model (power consumption for each configuration of each basic workload), and this combination corresponds to the most energy-efficient configuration for running the task.

[0102] Then, for the next time period, the electronic device can switch to the target CPU core and schedule the target CPU core to the target CPU frequency, and schedule the DDR to the target DDR frequency for application use.

[0103] For the next time period, similar steps can be performed to determine the combination of target CPU cores, target CPU frequency, and target DDR frequency for that time period.

[0104] Based on the technical solution provided in this application, the performance of the CPU was observed.

[0105] Table 1

[0106] As shown in Table 1, the "baseline" represents the OS controlling CPU and DDR frequencies and task placement (unmodified CFS collects utilization information via WALT and selects the target CPU for tasks, the schedutil governor controls CPU frequency, and the memlatgovernor controls DDR frequency). Compared to the baseline results, CPU time was reduced by 19.2% and power consumption by 2.4%.

[0107] Figure 5 A schematic flowchart of a computational performance improvement method provided by an embodiment of this application is shown, the method comprising the following steps: S502: Collect workload parameters for the current time period.

[0108] S504: Predict workload parameters for the next time period.

[0109] S506: Decompose the workload for the next time period into basic workloads.

[0110] S508: Select all combinations of CPU cores, CPU frequencies, and DDR frequencies corresponding to the acceptable CPU capacity (the acceptable CPU capacity is equal to or greater than the required CPU capacity).

[0111] S510: Select an energy-efficient combination from all acceptable combinations (target CPU core, target CPU frequency, target DDR frequency).

[0112] S512: Schedule the running task to (target CPU core, target CPU frequency, target DDR frequency).

[0113] Figure 5 For details of the methods provided, please refer to [link / reference]. Figure 2 The corresponding content is shown in the original text. To avoid repetition, it will not be repeated here.

[0114] Figure 6 This is a schematic block diagram of an electronic device 600 provided in an embodiment of this application.

[0115] like Figure 6 As shown, the electronic device 600 includes: an acquisition module 610, used to acquire workload parameters for the current time period; and a determination module 620, used to: determine workload parameters for the next time period based on the workload parameters for the current time period; determine the proportion of basic workload for the next time period based on the workload parameters for the next time period; and determine a combination of target CPU frequency and target DDR frequency to meet the required CPU capacity for the next time period, wherein the required CPU capacity for the next time period is determined based on the task utilization rate of the current time period.

[0116] In one alternative implementation, the electronic device 600 includes more than one CPU core, and the determining module 620 is further configured to determine a combination of target CPU cores, target CPU frequency, and target DDR frequency to meet the required CPU capacity for the next time period.

[0117] In one alternative implementation, the determining module 620 is further configured to: determine different CPU capacities and corresponding different combinations of CPU frequency and DDR frequency; and, based on a first correlation, determine at least one combination of CPU frequency and DDR frequency that satisfies the required CPU capacity, wherein (the target CPU frequency and the target DDR frequency correspond to the minimum power consumption of at least one combination of CPU frequency and DDR frequency).

[0118] In one alternative implementation, workload parameters include: instructions, cycles, and L3 cache backfilling.

[0119] In one alternative implementation, the base workload for the next time period includes CPU-limited workload and memory-limited workload.

[0120] In one alternative implementation, the memory-limited workload includes at least one of the following workloads: memory latency-limited workload, memory bandwidth-limited workload, and front-end-limited workload.

[0121] In one alternative implementation, the length of the current time period and / or the length of the next time period is between 4 ms and 100 ms.

[0122] In an alternative implementation, the determination module 620 is further configured to: determine the workload parameters for the next time period based on the workload parameters for the current time period, using trivial forecasting or EMA forecasting.

[0123] Figure 7 This is a schematic diagram of the hardware structure of the electronic device 700 provided in an embodiment of this application. Figure 7 The illustrated electronic device 700 includes a memory 710, a processor 720, a communication interface 730, and a bus 740. The memory 710, processor 720, and communication interface 730 are interconnected via the bus 740.

[0124] The memory 710 can store programs. When the program stored in the memory 710 is executed by the processor 720, the processor 720 is used to execute the embodiments of this application. Figure 2 or Figure 5 The steps of methods to improve computational performance.

[0125] The processor 720 may use a general-purpose CPU, microprocessor, ASIC, GPU, or one or more integrated circuits to execute relevant programs to perform the computing performance improvement methods in the embodiments of this application.

[0126] The processor 720 can also be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the computational performance improvement method in the embodiments of this application can be accomplished through integrated logic circuits in the hardware of the processor 720 or through software instructions.

[0127] It should be noted that although only the memory, processor, and communication interface are shown in device 700, those skilled in the art should understand that in specific implementations, device 700 may also include other components necessary for normal operation. Furthermore, based on specific needs, those skilled in the art should understand that device 700 may also include hardware components for implementing other additional functions. Additionally, those skilled in the art should understand that device 700 may only include the components required to implement the embodiments of this application, and may include... Figure 7 All the devices shown.

[0128] Those skilled in the art will recognize that, based on the units and algorithm steps described in the examples of the embodiments disclosed in this specification, the embodiments of this application can be implemented by electronic hardware or a combination of computer software and electronic hardware. Whether the function is executed by hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0129] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the above-described systems, devices, and units can be referred to the corresponding process in the above-described method embodiments, and will not be repeated here.

[0130] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the described apparatus embodiments are merely exemplary. For example, dividing into units is merely a logical functional division and may be other divisions in actual implementation. For example, multiple units or components may be merged or integrated into another system, or some features may be ignored or not performed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be implemented through some interface. Indirect coupling or communication connection between apparatuses or units may be implemented electronically, mechanically, or otherwise.

[0131] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0132] In addition, the functional units in the embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0133] When these functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for instructing a computer device (which may be a personal computer, server, network device, etc.) to execute all or part of the steps of the methods described in the embodiments of this application. The aforementioned storage medium includes any medium capable of storing program code, such as a USB flash drive, portable hard drive, ROM, RAM, magnetic disk, or optical disk.

[0134] The above description is merely a specific implementation of this application and is not intended to limit the scope of protection of this application. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A method for improving the computing performance of electronic devices, characterized in that, include: Get the workload parameters for the current time period; Based on the workload parameters of the current time period, determine the workload parameters for the next time period; Based on the workload parameters of the next time period, determine the proportion of the basic workload for the next time period; Determine a combination of target CPU frequency and target DDR frequency to meet the required CPU capacity for the next time period, wherein the required CPU capacity for the next time period is determined based on the task utilization of the current time period.

2. The method according to claim 1, characterized in that, The electronic device includes one or more CPU cores, and determining the combination of the target CPU frequency and the target DDR frequency to meet the required CPU capacity for the next time period includes: Determine the combination of target CPU cores, target CPU frequency, and target DDR frequency to meet the required CPU capacity for the next time period.

3. The method according to claim 1 or 2, characterized in that, The determination of the combination of target CPU frequency and target DDR frequency to meet the required CPU capacity for the next time period includes: Determine the different CPU capacities, and the corresponding combinations of CPU frequency and DDR frequency; Determine at least one combination of CPU frequency and DDR frequency that satisfies the required CPU capacity, wherein the combination of the target CPU frequency and the target DDR frequency corresponds to the minimum power consumption of at least one combination of the CPU frequency and DDR frequency.

4. The method according to any one of claims 1 to 3, characterized in that, The workload parameters include: Instructions, cycles, and L3 cache backfilling.

5. The method according to any one of claims 1 to 4, characterized in that, The basic workload for the next time period includes CPU-bound workload and memory-bound workload.

6. The method according to claim 5, characterized in that, The memory-limited workloads include at least one of the following workloads: Memory latency limits workload, memory bandwidth limits workload, and front-end limits workload.

7. The method according to any one of claims 1 to 6, characterized in that, The length of the current time period and / or the length of the next time period is between 4 ms and 100 ms.

8. The method according to any one of claims 1 to 7, characterized in that, Determining the workload parameters for the next time period based on the workload parameters for the current time period includes: Based on the workload parameters of the current time period, the workload parameters for the next time period are determined using trivial forecasting or EMA forecasting.

9. An electronic device, characterized in that, include: The acquisition module is used to obtain workload parameters for the current time period; The determination module is used for: Based on the workload parameters of the current time period, determine the workload parameters for the next time period; Based on the workload parameters of the next time period, determine the proportion of the basic workload for the next time period; Determine a combination of target CPU frequency and target DDR frequency to meet the required CPU capacity for the next time period, wherein the required CPU capacity for the next time period is determined based on the task utilization of the current time period.

10. The electronic device according to claim 10, characterized in that, The electronic device includes one or more CPU cores, and the determining module is further configured to determine a combination of target CPU cores, target CPU frequency, and target DDR frequency that meet the required CPU capacity for the next time period.

11. The electronic device according to claim 9 or 10, characterized in that, The determining module is also used for: Determine the different CPU capacities, and the corresponding combinations of CPU frequency and DDR frequency; Based on the first correlation, at least one combination of CPU frequency and DDR frequency that satisfies the required CPU capacity is determined, wherein the target CPU frequency and target DDR frequency correspond to the minimum power consumption of at least one combination of the CPU frequency and DDR frequency.

12. The electronic device according to any one of claims 9 to 11, characterized in that, The workload parameters include: Instructions, cycles, and L3 cache backfilling.

13. The electronic device according to any one of claims 9 to 12, characterized in that, The basic workload for the next time period includes CPU-limited workload and memory-limited workload.

14. The electronic device according to claim 14, characterized in that, The memory-limited workloads include at least one of the following workloads: Memory latency limits workload, memory bandwidth limits workload, and front-end limits workload.

15. The electronic device according to any one of claims 9 to 14, characterized in that, The length of the current time period and / or the length of the next time period is between 4 ms and 100 ms.

16. The electronic device according to any one of claims 9 to 15, characterized in that, The determining module is further configured to: determine the workload parameters for the next time period based on the workload parameters for the current time period using trivial prediction or EMA prediction.

17. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores instructions that, when executed on the device, cause the device to perform the method according to any one of claims 1 to 8.

18. A computer program product, characterized in that, When the computer program product is run on the device, it causes the device to perform the method according to any one of claims 1 to 8.

19. A chip system, characterized in that, The device includes a memory and a processor, wherein the memory is used to store a computer program, and the processor is used to retrieve the computer program from the memory and run the computer program to cause the device in which the chip system resides to perform the method according to any one of claims 1 to 8.

Images