Battery cell impedance sampling method and system based on machine learning and MCU control

Abstract

The application discloses a battery cell impedance sampling method and system based on machine learning and MCU control, and relates to the technical field of battery cell impedance sampling. The method comprises the following steps: S1, collecting impedance measurement data of each path in real time and performing pretreatment; S2, establishing a sensitivity relationship of temperature and current to impedance, obtaining a normalized equivalent impedance representation result, and extracting impedance residual feature of each path; S3, identifying the stability state of the sampling link, implementing offset determination on the path continuously deviating from the stability state, and generating an MCU control strategy; S4, identifying a parasitic resistance offset event, extracting an offset direction strength representation, and distinguishing a stable window from a disturbance window; and S5, evaluating a cell internal resistance aging trend, determining a health grade, and constructing an internal resistance aging trajectory. The method solves the problems of unstable measurement and undeterminable aging trend of the cell internal resistance measurement caused by the superposition of parasitic resistance and environmental drift under the two-wire method and the single-pole double-throw switch structure.

Description

Technical Field

[0001] This invention relates to the field of battery cell impedance sampling technology, specifically to a battery cell impedance sampling method and system based on machine learning and MCU control. Background Technology

[0002] With the widespread application of power batteries, energy storage systems, and electric equipment in transportation, renewable energy grid connection, and emergency power supply scenarios, the refined monitoring and long-term performance evaluation of individual battery cells are becoming increasingly important. Under the influence of factors such as charge-discharge cycles, environmental temperature changes, and mechanical vibrations, the internal electrochemical characteristics of batteries evolve over time, manifesting externally as dynamic changes in impedance and temperature characteristics. To ensure the safety, stability, and lifespan management of battery systems, the industry generally requires continuous monitoring of the operating status of individual cells and extraction of key features reflecting battery health trends from multi-source monitoring data. Therefore, battery state monitoring and evaluation technologies for complex operating conditions and long-term operation scenarios are gradually becoming an important research direction in the field of battery management.

[0003] For example, invention patent CN106093583B discloses a device and method for measuring the impedance of individual battery cells in a vehicle-mounted battery pack. This device measures the AC impedance of individual battery cells connected in series within multiple battery modules of a battery pack. The device includes: an AC excitation module to provide a sinusoidal excitation current of a certain frequency and amplitude to the multiple series-connected battery modules; a battery pack controller to control the AC excitation module to generate the excitation current; a current measurement module to measure the excitation current injected into the battery pack by the AC excitation module and send the detected current value to the battery pack controller; and a battery cell voltage measuring module to measure the response voltage of all series-connected battery cells in the battery module and obtain the excitation current value from the battery pack controller via a communication module to calculate the AC impedance of the individual battery cells. Compared with existing technologies, this invention has advantages such as centralized excitation, individual measurement, and accurate measurement.

[0004] For example, invention patent CN116529618A discloses a charging and discharging fixture for impedance measurement of a battery cell, comprising: a fixture body on which the battery cell is mounted in the longitudinal direction; a first busbar and a second busbar, which are disposed on both sides of the fixture body, and leads at both ends of the battery cell are connected to the first busbar and the second busbar; an impedance measuring plate disposed on the fixture body; and a wire for impedance measurement, wherein the wire for impedance measurement forms an impedance measuring circuit by connecting the first busbar, the impedance measuring plate, and the second busbar, wherein a portion of the wire for impedance measurement has a wide surface facing the battery cell and extends in the longitudinal direction of the battery cell.

[0005] However, in practical applications of battery modules, under the two-wire method and single-pole double-throw switch structure, the measurement results of the internal resistance of a single cell will be superimposed with the resistance of the connecting strip, the resistance of the wire harness, the resistance of the switch contacts, and the dynamic offset caused by temperature drift. These parasitic quantities change with temperature, aging, and vibration, and vary significantly between different cells. This makes it difficult for the simple differential method to achieve stable separation of internal resistance and connecting strip resistance, resulting in problems such as "large measurement fluctuations, large batch differences, and unpredictable aging trends," thereby reducing the reliability of fault identification and health assessment.

[0006] Therefore, in order to address the above problems, there is an urgent need for a battery cell impedance sampling method and system based on machine learning and MCU control. Summary of the Invention

[0007] Technical problems to be solved

[0008] To address the shortcomings of existing technologies, this invention provides a battery cell impedance sampling method and system based on machine learning and MCU control. This solves the problems of unstable measurement, large differences, and unpredictable aging trend caused by the superposition of parasitic resistance and environmental drift in the two-wire method and single-pole double-throw switch structure.

[0009] To achieve the above objectives, this invention provides the following technical solution: a battery cell impedance sampling method based on machine learning and MCU control, comprising the following steps: S1, real-time acquisition of impedance measurement data for each path, and performing robust preprocessing, sampling window alignment, and normalization on the impedance measurement data; S2, based on historical preprocessed impedance measurement data, establishing the sensitivity relationship between temperature and current to impedance, and obtaining the normalized equivalent impedance characterization result; extracting the impedance residual characteristics of each path based on the equivalent impedance characterization result; S3, identifying the stability of the sampling link based on the impedance residual characteristics of each path. In the qualitative state, offset determination is performed on the continuously deviating path, and an MCU control strategy is generated to perform real-time steady-state enhancement of the sampled link; S4, the parasitic resistance offset event is identified by using the impedance residual characteristics of each path, and the offset direction intensity characterization is extracted; the stable window and the disturbance window are distinguished according to the offset direction intensity characterization, and the equivalent impedance characterization results of different windows are marked; S5, based on the equivalent impedance characterization results within the stable window, the window mean and robust deviation are extracted to evaluate the aging trend of the single-cell internal resistance; the health level is determined according to the aging trend, the internal resistance aging trajectory is constructed, and health warning and evolution reference are generated.

[0010] Furthermore, the specific process of real-time acquisition of impedance measurement data for each path, and the robust preprocessing, sampling window alignment, and normalization of the impedance measurement data is as follows: The MCU controls a single-pole double-throw switch to enter different paths, including: the individual unit internal resistance measurement path, the left connecting strip measurement path, and the right connecting strip measurement path. Impedance measurement data is acquired in real time for each path, including: sampling voltage, sampling current, individual unit temperature, measurement path identifier, and timestamp; the rated internal resistance value is recorded synchronously; multi-point robust denoising is performed on the sampling voltage and sampling current based on median filtering to filter isolated spike interference caused by contact bounce, transient pulses, and relay jitter; abnormal sampling points are eliminated using amplitude threshold discrimination and physical consistency verification; consistency checks are performed on the timestamp and measurement path identifier using time series integrity verification, and sampling period alignment is performed based on the sampling timestamp to align the effective sampling points of different paths to a unified sampling window; minimum-maximum normalization is performed on the impedance measurement data; an individual unit impedance sampling database is established, and the original and preprocessed impedance measurement data are written into the individual unit impedance sampling database.

[0011] Furthermore, based on the preprocessed historical impedance measurement data, the specific process for establishing the sensitivity relationship between temperature and current to impedance and obtaining the normalized equivalent impedance characterization results is as follows: Obtain the preprocessed impedance measurement data for each path; calculate the difference between the sampling voltage and the sampling current at the current moment and the previous moment, respectively, to obtain the changes in sampling voltage and sampling current; divide the changes in sampling voltage by the changes in sampling current to obtain the equivalent impedance value; based on the distribution of individual unit temperature and sampling current amplitude within the historical window, select the median as the reference value for individual unit temperature and the reference value for sampling current, respectively, and simultaneously select the median of the historical equivalent impedance value distribution to obtain the impedance reference value; under the condition that the sampling current is within the current range centered on the sampling current reference value, extract the corresponding historical individual unit temperature and equivalent impedance value set. The temperature impedance slope is obtained by performing least squares fitting, and then normalized according to the impedance reference value to obtain the temperature sensitivity coefficient. Under the condition that the individual unit temperature is within the temperature range centered on the individual unit temperature reference value, the corresponding historical sampling current amplitude and equivalent impedance value set are extracted, and the current impedance slope is obtained by performing least squares fitting, and then normalized according to the impedance reference value to obtain the current sensitivity coefficient. The difference between the individual unit temperature and the individual unit temperature reference value is calculated and multiplied by the temperature sensitivity coefficient. The product is added to a constant to obtain the temperature correction term. The difference between the sampling current amplitude and the sampling current reference value is calculated and multiplied by the current sensitivity coefficient. The product is added to a constant to obtain the current correction term. The equivalent impedance value is divided by the product of the temperature correction term and the current correction term to obtain the normalized equivalent impedance value under the operating condition.

[0012] Furthermore, the specific process of extracting the impedance residual characteristics of each path based on the equivalent impedance characterization results is as follows: calculate the normalized equivalent impedance value of each path and write it into the buffer window, and calculate the average value and standard deviation of the normalized equivalent impedance value of the corresponding path; for each path, calculate the difference between the normalized equivalent impedance value and the corresponding average value, and divide it by the corresponding standard deviation to obtain the standardized impedance residual; write the normalized equivalent impedance value and standardized impedance residual of each path into the individual impedance sampling database.

[0013] Furthermore, based on the impedance residual characteristics of each path, the stability state of the sampling link is identified, offset determination is performed on paths that continuously deviate, and an MCU control strategy is generated. The specific process of real-time steady-state enhancement of the sampling link is as follows: the normalized equivalent impedance value, the corresponding average normalized equivalent impedance value, and the standardized impedance residual of each path are read; when the duration of the normalized equivalent impedance value being higher than the corresponding average value exceeds the allowable time threshold, an instruction to increase the conduction signal stabilization time and sampling delay of the path is generated, where the conduction signal stabilization time is the on / off buffer time of the single-pole double-throw switch; when the standardized impedance residual is higher than the residual threshold, an instruction to increase the sampling frequency of the corresponding path is generated; the instruction is sent to the MCU in real time; if the change in sampling voltage or sampling current is detected to exceed the corresponding change threshold, resampling is triggered; at the same time, if the duration of the normalized equivalent impedance value of a path being higher than that of other paths exceeds the allowable time threshold, the MCU is controlled to correct the sampling voltage and sampling current of the path according to the deviation of the normalized equivalent impedance value.

[0014] Furthermore, the specific process of identifying parasitic resistance shift events using the impedance residual characteristics of each path and extracting the intensity characterization of the shift direction is as follows: The standardized impedance residuals of each path are arranged into residual vectors according to the path order. The average residual vector is calculated based on the residual vector sequence within the historical window, and the covariance matrix of the residual vectors is calculated. The median of the standardized impedance residuals of each path is selected as the path residual directional median. The path residual directional median is substituted into the sign function to calculate the shift direction term. The current residual vector is right-multiplied by the inverse of the covariance matrix of the residual vector to obtain the intermediate vector. The transpose of the residual vector is then multiplied by the intermediate vector to obtain a scalar value. The scalar value is divided by the number of paths and the square root is taken to obtain the Mahalanobis distance value. The Mahalanobis distance value is added to a constant and the natural logarithm is taken to obtain the Mahalanobis shift logarithm term. The shift direction term is multiplied by the Mahalanobis shift logarithm term to obtain the parasitic resistance shift value.

[0015] Furthermore, the specific process of distinguishing between stable windows and disturbance windows based on the intensity characterization of the offset direction, and marking the equivalent impedance characterization results of different windows, is as follows: The parasitic resistance offset value is compared with the offset alarm threshold. When the absolute value of the parasitic resistance offset value is higher than the offset alarm threshold, and the duration exceeds the allowable time threshold, the sampling window is marked as a parasitic resistance anomaly window, and the corresponding measurement path identifier and timestamp are recorded. For parasitic resistance anomaly windows, the corresponding normalized equivalent impedance value is marked as parasitic disturbance data. For sampling windows not marked as parasitic resistance anomaly windows, the normalized equivalent impedance value is marked as parasitic stable data. The parasitic resistance offset value and the corresponding mark are written into the individual impedance sampling database.

[0016] Further, based on the equivalent impedance characterization results within the stable window, the specific process of extracting the window mean and robust deviation to evaluate the internal resistance aging trend of the monomer is as follows: Extract the normalized equivalent impedance values of the working conditions that are marked as parasitic stable data and belong to the internal resistance measurement path of the monomer from the monomer impedance sampling database in timestamp order to construct an impedance time series; Based on a fixed sliding time window, calculate the average value of the impedance time series to obtain the average equivalent internal resistance; At the same time, calculate the median absolute deviation of the normalized equivalent impedance values within the window based on the average equivalent internal resistance as the window robust deviation scale value; Obtain the rated internal resistance value, subtract the rated internal resistance value from the average equivalent internal resistance to get the internal resistance offset, divide the internal resistance offset by the rated internal resistance value to get the relative internal resistance offset ratio, take the opposite of the relative internal resistance offset ratio as the exponential power for natural exponential operation, and subtract the result of the natural exponential operation from the constant one to get the exponential decay term; Divide the internal resistance offset by the sum of the window robust deviation scale value and the minimum constant value to get the fluctuation normalization term; Multiply the exponential decay term by the fluctuation normalization term to get the internal resistance aging trend value of the monomer.

[0017] Further, the specific process of determining the health level according to the aging trend, constructing the internal resistance aging trajectory, and generating a health warning and evolution reference is as follows: Compare the internal resistance aging trend value of the monomer with the multi-level aging thresholds L1 and L2: When < L1, generate an internal resistance health mark and keep the sampling frequency and sampling delay strategy of the MCU unchanged; When L1 ≤ < L2, generate a mild internal resistance aging mark, increase the sampling frequency of the internal resistance measurement path of the monomer, and shorten the sampling delay of the internal resistance measurement path of the monomer; When, ≥ L2, generate a significant internal resistance aging mark, push a monomer aging warning, enable the dynamic sampling delay compensation mechanism, adjust the conduction signal stabilization time, and at the same time control the battery monomer to operate at a derated level; Write the internal resistance aging trend value of the monomer, the corresponding timestamp, the measurement path identifier, and the aging level mark into the monomer impedance sampling database, and form a trajectory of the internal resistance aging trend value of the monomer evolving with time; Statistically analyze the change slope of the internal resistance aging trend value trajectory, evaluate the deterioration speed of the internal resistance of the monomer, and generate an internal resistance health assessment report based on the aging level and the result of the deterioration speed of the internal resistance of the monomer.

[0018] The second aspect of this invention provides a battery cell impedance sampling system based on machine learning and MCU control, comprising: a data acquisition and preprocessing module for real-time acquisition of impedance measurement data for each path, and performing robust preprocessing, sampling window alignment, and normalization on the impedance measurement data; a working condition normalization and residual modeling module for establishing the sensitivity relationship between temperature and current to impedance based on historical preprocessed impedance measurement data, and obtaining the normalized equivalent impedance characterization result; extracting the impedance residual features of each path based on the equivalent impedance characterization result; and an MCU control and stability enhancement module for identifying the stability of the sampling link based on the impedance residual features of each path. The system performs offset determination on continuously deviating paths and generates MCU control strategies to enhance the real-time steady-state performance of the sampled links. A parasitic resistance offset identification module identifies parasitic resistance offset events using the impedance residual characteristics of each path and extracts the offset direction intensity characterization. Based on the offset direction intensity characterization, it distinguishes between stable and disturbance windows and marks the equivalent impedance characterization results for different windows. A single-unit internal resistance aging assessment module extracts the window mean and robust deviation to assess the aging trend of single-unit internal resistance based on the equivalent impedance characterization results within the stable window. It determines the health level based on the aging trend, constructs the internal resistance aging trajectory, and generates health warnings and evolution references.

[0019] The present invention has the following beneficial effects:

[0020] (1) This invention performs robust denoising, sampling window alignment and temperature and current dual-sensitivity normalization on impedance data of different measurement paths, so that the equivalent impedance has consistent characterization ability under different working conditions, thereby reducing impedance offset caused by temperature drift, current fluctuation and path difference from the source, and improving the stability and comparability of impedance measurement.

[0021] (2) In this invention, a link stability determination mechanism is established by utilizing the standardized impedance residuals of each path, and MCU control strategies such as adjusting the conduction signal stabilization time, increasing the sampling frequency, controlling the sampling delay, and compensating for voltage and current are triggered, so that the measurement link can be automatically corrected when there are signs of deviation, thereby improving the stability and continuity of impedance sampling under the two-wire method structure.

[0022] (3) This invention, through the combination of residual vector modeling, covariance matrix analysis and Mahalanobis distance calculation, can identify the directionality and intensity of parasitic resistance shift, and divide the sampling window into a stable window and a disturbance window, thereby effectively removing the dynamic interference caused by parasitic quantities such as connecting strips, cables and contacts, and improving the sensitivity of impedance characterization to changes in real internal resistance.

[0023] (4) In this invention, the mean internal resistance and robust deviation are extracted from the data of the parasitic stability window. The aging trend value of the single-cell internal resistance is obtained by the exponential decay term and the fluctuation normalization term. Combined with the multi-level aging threshold, the health level judgment, link parameter adjustment and derated operation strategy are implemented, thereby constructing a real aging trajectory that can evolve over time, which improves the accuracy and engineering applicability of aging detection and health early warning.

[0024] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0025] Figure 1 The flowchart shows a battery cell impedance sampling method based on machine learning and MCU control.

[0026] Figure 2 This is a structural diagram of a battery cell impedance sampling system based on machine learning and MCU control.

[0027] Figure 3 This is a schematic diagram of a multipath measurement and MCU switching control structure for single-unit impedance.

[0028] Figure 4 This is a time-series evolution diagram of the aging trend value of the monomer internal resistance. Detailed Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. As those skilled in the art will understand, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] Please see Figures 1-4 This invention provides a technical solution: a battery cell impedance sampling method and system based on machine learning and MCU control, such as... Figure 1As shown, the process includes the following steps: S1, real-time acquisition of impedance measurement data for each path, and robust preprocessing, sampling window alignment, and normalization of the impedance measurement data; S2, based on historical preprocessed impedance measurement data, establishing the sensitivity relationship between temperature and current to impedance, and obtaining the normalized equivalent impedance characterization results; extracting the impedance residual characteristics of each path based on the equivalent impedance characterization results; S3, identifying the stability state of the sampling link based on the impedance residual characteristics of each path, implementing offset judgment for paths with continuous deviations, and generating MCU control strategies to perform real-time steady-state enhancement of the sampling link; S4, identifying parasitic resistance offset events using the impedance residual characteristics of each path, and extracting the offset direction intensity characterization; distinguishing between stable windows and disturbance windows based on the offset direction intensity characterization, and marking the equivalent impedance characterization results of different windows; S5, based on the equivalent impedance characterization results within the stable window, extracting the window mean and robust deviation to assess the aging trend of the single-cell internal resistance; determining the health level based on the aging trend, constructing the internal resistance aging trajectory, and generating health warnings and evolution references.

[0031] Specifically, the process of real-time acquisition of impedance measurement data for each path, and the robust preprocessing, sampling window alignment, and normalization of the impedance measurement data are as follows: The MCU controls a single-pole double-throw switch to enter different paths, including: the single-cell internal resistance measurement path, the left connecting strip measurement path, and the right connecting strip measurement path. Impedance measurement data is acquired in real time for each path, including: sampling voltage, sampling current, single-cell temperature, measurement path identifier, and timestamp; the rated internal resistance value is recorded synchronously. The sampling voltage is obtained by a voltage sampling module located at the input end of the measurement path, which can be implemented using a voltage divider resistor network and an ADC conversion circuit; the sampling current is obtained by a Hall current sensor connected in series in the measurement path; the single-cell temperature is read by a digital temperature sensor attached to the surface of the battery cell; the measurement path identifier is automatically written by the MCU when controlling the single-pole double-throw switch to switch paths, and each sampling is accompanied by a corresponding path number; the timestamp is generated in real time by an internal timer of the MCU to ensure that all path data has a globally consistent synchronized time stamp; the rated internal resistance value is a fixed device parameter, written into the database during initialization. The MCU responds to control scheduling with a fixed sampling period, switching the on / off ports of the single-pole double-throw switch to ensure that the three physical paths sequentially enter the measurement state on the same hardware platform. This guarantees that impedance measurements of different paths are based on consistent power supply conditions and synchronous timing, enabling continuous acquisition of multi-path impedance data. Median filtering is used to perform robust multi-point denoising on the sampled voltage and current, filtering isolated spike interference caused by contact bounce, transient pulses, and relay jitter. The median filter window length can be set to 3 to 7 sampling points depending on the sampling frequency, suppressing high-amplitude isolated noise without disrupting the true trend of change, ensuring the stability and accuracy of the voltage and current data used in subsequent impedance calculations. Amplitude threshold discrimination and physical consistency verification are used to eliminate abnormal sampling points. The amplitude threshold can be set according to the sensor specifications and the actual operating voltage and current range. For example, voltage changes exceeding the threshold or current direction not conforming to load state changes are considered abnormal points. Physical consistency verification includes judging the sign relationship between voltage and current and the reasonableness of temperature change rate, further eliminating spurious data caused by poor contact and signal disturbance. Time series integrity verification is used to check the consistency between timestamps and measurement path identifiers, and sampling period alignment is performed based on sampling timestamps to align valid sampling points from different paths to a unified sampling window. Time series integrity verification ensures that data is written in the order of path number and sampling period, and that there are no issues of packet loss, out-of-order, or duplicate sampling. Alignment processing establishes a unified time benchmark and inserts sampling points from each path into the same time window, providing a strict basis for comparison when performing residual analysis and offset identification on the three-path data.Minimum-maximum normalization is performed on the impedance measurement data to eliminate the differences in the original measurement amplitude between different paths, so that the impedance characteristics of multiple paths can be included in residual modeling and parasitic analysis on the same scale, thereby improving the model convergence and numerical stability. A single-unit impedance sampling database is established, and the original and preprocessed impedance measurement data are written into the single-unit impedance sampling database using a structured storage method.

[0032] like Figure 3 The diagram illustrates a multi-path impedance measurement and MCU switching control structure for a single unit. Using two adjacent units, Unit 1 and Unit 2, as examples, the diagram explains the multi-path switching and impedance acquisition method. Each unit is connected to a sampling circuit module via positive and negative leads. The sampling circuit is integrated with the MCU and used to perform basic measurements such as voltage, current, and temperature. A connecting strip forms a conductive path across the two units. The MCU controls a single-pole double-throw switch to switch between the unit's internal resistance measurement path, the left connecting strip measurement path, and the right connecting strip measurement path, enabling the sequential acquisition of three types of impedance data under the same sampling circuit. The sampling circuit maintains real-time communication with the upper-level management system via a bus including RS-485 communication, power, and ground lines, ensuring that the measured impedance data is categorized and stored in the impedance sampling database according to path identification. This structure allows for the stable sequential acquisition of impedance data from different paths without altering the hardware topology, providing a hardware foundation for subsequent normalized modeling of operating conditions, residual detection, parasitic resistance offset identification, and assessment of the aging trend of unit internal resistance.

[0033] In this implementation scheme, robust preprocessing, time alignment, and normalization of multi-path impedance measurements ensure comparability of data from different paths under consistent conditions. Median filtering and consistency checks effectively eliminate noise and spurious data, improving the stability of impedance measurements. A unified sampling window ensures the reliability of multi-path residual analysis, and normalization enhances model convergence and numerical stability. The overall scheme significantly improves the accuracy and usability of multi-path impedance acquisition, providing a reliable data foundation for parasitic offset identification and single-unit internal resistance aging assessment.

[0034] Specifically, based on historical preprocessed impedance measurement data, the sensitivity relationships between temperature and current to impedance are established, and the normalized equivalent impedance characterization results are obtained as follows: Preprocessed impedance measurement data for each path are obtained; the difference between the sampled voltage and the sampled current at the current moment and the previous moment is calculated to obtain the sampled voltage change and sampled current change, respectively; the equivalent impedance value is obtained by dividing the sampled voltage change by the sampled current change; The sampled voltage change and sampled current change are both derived from a stable and denoised dataset after preprocessing, ensuring that the impedance calculation results are not affected by isolated noise points and jumps. The equivalent impedance value serves as the basic feature quantity for subsequent modeling and is updated in real-time in each sampling period based on the latest voltage and current changes. Based on the distribution of cell temperature and sampling current amplitude within the historical window, the median is selected as the reference value for both cell temperature and sampling current. Simultaneously, the median of the historical equivalent impedance distribution is selected to obtain the impedance reference value. The historical window can be adaptively set according to the sampling frequency, preferably a sliding interval of 1 to 3 minutes, used to statistically analyze the typical temperature, current, and impedance behavior of the battery within the stable operating range. The introduction of the median helps to avoid deviations in the reference value caused by extreme temperature points and abnormal current points, ensuring the robustness and representativeness of the reference value. Under the condition that the sampling current is within the current range centered on the sampling current reference value, the corresponding historical cell temperature and equivalent impedance value set is extracted, and least squares fitting is performed to obtain the temperature impedance slope. The temperature impedance slope is then normalized according to the impedance reference value to obtain the temperature sensitivity coefficient. The width of the current interval can be set according to the rated current ratio, preferably within ±10% to 20% of the sampling current reference value, to ensure that the slope fitting is based on a data subset with high operating condition consistency, guaranteeing the reliability of the temperature sensitivity fitting results. The least squares fitting process is used to output stable linear sensitivity parameters. Under the condition that the unit temperature is within the temperature range centered on the unit temperature reference value, the corresponding historical sampling current amplitude and equivalent impedance value set are extracted, and the current impedance slope is obtained by least squares fitting. The current impedance slope is then normalized according to the impedance reference value to obtain the current sensitivity coefficient. The temperature range is set in the same way as the current range, preferably within ±10% to 20% of the unit temperature reference value, so as to avoid the interference of abnormal temperature drift on the current sensitivity modeling, thereby obtaining a more physically meaningful current sensitivity coefficient.Before performing least squares fitting, the candidate sample set is screened for linear fitting availability. The number of samples should be no less than 20 to 50 points to ensure statistical significance. The median absolute deviation method is used to remove isolated outliers that deviate from the median by more than 3 times the MAD to avoid noise interference with the fitting results. The coefficient of determination R² is calculated for the initial fitting results. When R² is lower than the interpretability threshold of 0.3 to 0.5, the sample set is determined to not satisfy the linear relationship and the fitting is abandoned. At the same time, the variation range of temperature or current samples should not be less than 1°C or 5% of the rated current, respectively, and the samples should be sourced from a window of continuous time without abrupt changes in operating conditions to ensure that the fitting slope has physical meaning and robustness. The difference between the unit temperature and the unit temperature reference value is calculated and multiplied by the temperature sensitivity coefficient. The product is then added to a constant to obtain the temperature correction term. Similarly, the difference between the sampled current amplitude and the sampled current reference value is calculated and multiplied by the current sensitivity coefficient. The product is then added to a constant to obtain the current correction term. These two correction terms characterize the impact of current deviations from the reference point on the equivalent impedance. The correction terms are constructed in the form of "one plus deviation effect" to ensure that the impedance normalization calculation always remains positive, possessing interpretability and physical rationality. Dividing the equivalent impedance value by the product of the temperature and current correction terms yields the operating condition-normalized equivalent impedance value. This eliminates the influence of external disturbances in temperature and current, allowing impedance values ​​at different sampling times and along different paths to be compared under unified operating conditions. This provides a consistent and reliable data foundation for subsequent residual modeling, parasitic offset identification, and unit aging trend analysis.

[0035] The specific formula for the normalized equivalent impedance value under operating conditions is as follows:

[0036] ;

[0037] In the formula, It represents the normalized equivalent impedance value under operating conditions, which is used to characterize the true impedance level after eliminating the influence of temperature and current. It is the core quantity for subsequent residual calculation, parasitic resistance offset identification and internal resistance aging trend assessment. This indicates the amount of change in the sampled voltage. This represents the change in the sampled current, calculated from the changes at two sampling points. It constitutes the original equivalent impedance, which is the most basic impedance measurement. However, it fluctuates with changes in temperature and current, so it requires subsequent normalization correction. The temperature sensitivity coefficient represents the degree to which the impedance changes with temperature, and is obtained by fitting historical data. It indicates the temperature of a single cell, used to reflect the real-time temperature status of the battery under the current environment and operating conditions; This represents the reference temperature of the monomer, which serves as the standard temperature for impedance normalization. The current sensitivity coefficient represents the degree to which impedance changes with the magnitude of current, and is obtained by fitting historical data. The sampling current amplitude represents the magnitude of the instantaneous current experienced by the individual cell during measurement, and is one of the main factors causing impedance deviation. Indicates the sampling current; This represents the reference value of the sampled current, used to establish a unified current reference so that the impedance value does not shift due to different sampled current magnitudes.

[0038] In this implementation scheme, by constructing the sensitivity relationship between temperature, current and impedance within a historical window and using robust reference values ​​and interval screening for linear fitting, this method can accurately separate the influence of ambient temperature and current fluctuations on equivalent impedance. At the same time, based on temperature and current correction terms, the impedance is normalized according to operating conditions, so that the impedance characteristics of different sampling times and different paths are mapped to a unified benchmark, thereby significantly improving the consistency and comparability of impedance characterization, and providing a stable, reliable and physically interpretable data foundation for subsequent residual analysis, parasitic offset identification and internal resistance aging trend assessment.

[0039] Specifically, the process of extracting the impedance residual characteristics of each path based on the equivalent impedance characterization results is as follows: The normalized equivalent impedance value for each path is calculated and written into a cache window. The cache window is a sliding data structure constructed according to timestamp order, used to temporarily store the normalized equivalent impedance values ​​within the most recent sampling period. The window size can be preferably set to 10 to 50 sampling points based on the sampling frequency to ensure the statistics are representative and can be updated in real time. The update step size is determined by the sampling frequency; each time a new sampling point is acquired, the window slides forward by one sampling period, thus ensuring that the window statistics are refreshed in real time with the sampling process. The mean and standard deviation of the normalized equivalent impedance values ​​for the corresponding path are calculated. Each path has a corresponding normalized equivalent impedance value and its mean and standard deviation. The mean is used to characterize the impedance stability level of the path within the current window, and the standard deviation is used to measure the impedance fluctuation amplitude. Both are calculated based on all valid data within the cache window to avoid statistical result deviations due to transient disturbances. For each path, the difference between the normalized equivalent impedance value and the corresponding average value is calculated to quantify the deviation of the current sampling point from the path's stable state. A larger difference indicates that the current path is more likely to be affected by parasitic disturbances, poor contact, or temperature drift. The difference is then divided by the corresponding standard deviation to obtain the standardized impedance residual. Standardization unifies the dimensions and amplitude differences between different paths, making the residuals comparable and amplifying weak but stable offset trends, facilitating statistical discrimination by the subsequent parasitic offset identification module. The normalized equivalent impedance value and standardized impedance residual of each path are written into the individual impedance sampling database. A time-stamped structured storage method is used, with each record containing the measurement path identifier, the normalized equivalent impedance value, the standardized impedance residual, and the corresponding calculation context. This enables long-term tracking of multi-path impedance characteristics, providing a continuous and complete historical data source for parasitic resistance offset identification and internal resistance aging trend analysis.

[0040] This implementation scheme can construct sliding statistical features on the normalized impedance sequence under conditions of temperature, current fluctuations, and parasitic interference in multi-path impedance data, and express the degree of deviation of each path from its own stable baseline in a standardized residual manner, thereby robustly revealing the subtle trends of path impedance changes on a unified scale. This processing not only improves the comparability of residual features between different paths and enhances the sensitivity and reliability of parasitic offset identification, but also provides a continuous, stable, and noise-suppressing foundation for subsequent Mahalanobis distance discrimination and aging trend assessment, making the overall impedance analysis link more accurate, robust, and engineering feasible.

[0041] Specifically, the process of identifying the stability state of the sampling link based on the impedance residual characteristics of each path, determining the offset of continuously deviating paths, and generating MCU control strategies to enhance the real-time steady-state of the sampling link is as follows: read the normalized equivalent impedance value of each path, the average value of the corresponding normalized equivalent impedance value, and the standardized impedance residual; the MCU reads the normalized equivalent impedance value of the latest data buffer window at fixed intervals through a timed task, so that the link determination is real-time. When the duration of the normalized equivalent impedance value exceeding the corresponding average value exceeds the allowable time threshold, instructions for increasing the stabilization time of the conduction signal and the sampling delay are generated. The stabilization time of the conduction signal is the on / off buffer time controlling the single-pole double-throw switch, set according to the contact mechanical bounce characteristics of the single-pole double-throw switch, with an initial value preferably between 3ms and 10ms, and adaptively adjusted by the MCU based on the stability of the sampled voltage and current changes after path switching. The sampling delay is set based on the electrical steady-state establishment time of the equivalent circuit of each path, with an initial value preferably between 50ms and 200ms, and adaptively adjusted by the MCU based on the convergence characteristics of the sampled voltage and current changes. The allowable time threshold can be adaptively set according to the sampling period; for example, when the sampling period is 50ms, the allowable time threshold is preferably between 200 and 500ms to avoid misjudgments caused by instantaneous temperature drift or current bounce. The stabilization time of the conduction signal is preferably set to the millisecond level to ensure that the switch contacts are fully closed before sampling, reducing voltage and current jumps caused by contact bounce. When the standardized impedance residual exceeds the residual threshold, an instruction to increase the sampling frequency of the corresponding path is generated and sent to the MCU in real time. The residual threshold can be set based on the 95th quantile of the historical residual distribution to distinguish between normal fluctuations and significant deviations. The instruction to increase the sampling frequency is implemented by the MCU adjusting the internal timer division coefficient, so that the path obtains denser impedance data in a short time to verify whether the anomaly persists. After generating the adjustment instructions for the conduction signal stabilization time, sampling delay, or sampling frequency, the MCU reads the adjusted normalized equivalent impedance value and the standardized impedance residual in real time in the next sampling cycle and compares the change in residual before and after adjustment. If the residual amplitude decreases compared to before adjustment, it indicates that the link offset has been suppressed, and the control parameters are maintained or gradually restored to the default values ​​to avoid over-adjustment causing link oscillation. If the residual does not decrease or increases further, the MCU continues to slightly increase the conduction signal stabilization time or extend the sampling delay according to the set safety slope until the residual falls back below the residual threshold, thus forming a closed-loop process of "offset detection, parameter adjustment, residual verification, and parameter convergence".If the detected change in sampled voltage or sampled current exceeds the corresponding change threshold, resampling is triggered. The change threshold is determined by the noise bandwidth of the voltage and current sensors and the load jump frequency. For example, a voltage fluctuation exceeding 1% to 2% of the rated voltage or a current fluctuation exceeding 2% of the rated current can be considered an abnormal fluctuation. After triggering, the MCU discards the current point and immediately resamples to ensure the validity and reliability of the physical quantities input for impedance calculation. Simultaneously, if the normalized equivalent impedance value of a path is higher than that of other paths for a duration exceeding the allowable time threshold, the MCU corrects the sampled voltage and sampled current of the path based on the deviation of the normalized equivalent impedance value. Correction methods may include adjusting the excitation current amplitude, extending the resting time before sampling, or increasing the average number of samplings to reduce the interference of parasitic quantities on instantaneous measurements, ensuring that impedance measurement results from different paths are comparable under consistent conditions.

[0042] In this implementation scheme, the stability of the sampling link is identified in real time by combining residual characteristics with dynamic thresholds. Targeted steady-state enhancement strategies, such as sampling delay adjustment, conduction signal stabilization time compensation, and sampling frequency enhancement, can be implemented for continuously deviating paths. Simultaneously, a resampling mechanism is triggered by real-time monitoring of voltage and current abrupt changes, and sampling conditions are automatically corrected when cross-path deviations occur. This ensures consistency and reliability of multi-path measurements under unified operating conditions, significantly improving the stability and anti-interference capability of the impedance acquisition process and providing more accurate basic data for subsequent parasitic offset identification and internal resistance aging analysis.

[0043] Specifically, the process of identifying parasitic resistance offset events using the impedance residual characteristics of each path and extracting the intensity characterization of the offset direction is as follows: The standardized impedance residuals of each path are arranged into residual vectors according to the path order, preferably in the order of "left connecting strip measurement path, single-unit internal resistance measurement path, right connecting strip measurement path." This sequence is fixed by the MCU during initialization and remains unchanged throughout its lifecycle, ensuring the stability of the residual vector's dimensional meaning, comparability across different sampling periods, and avoiding vector structure drift or statistical model failure due to changes in the path call order. The average residual vector is calculated based on the residual vector sequence within the historical window, and the covariance matrix of the residual vectors is also calculated. The residual vectors are arranged in a fixed path order so that the residuals of the three paths can jointly describe the parasitic offset state in vector form. The covariance matrix reflects the joint change relationship of the residuals across multiple paths, providing a statistical distribution basis for subsequent Mahalanobis distance calculations. The length of the historical window can be set according to the sampling frequency and the module's dynamic stability, preferably between 30 and 120 seconds, ensuring sufficient sample size for covariance estimation without excessively smoothing instantaneous offsets. Furthermore, to avoid the covariance matrix becoming non-invertible due to excessive correlation of the three-path residuals in engineering scenarios, an additive is used to adjust the covariance matrix before calculating its inverse. Regular terms, where It is a very small constant value, taking the value of , The identity matrix is ​​used to ensure matrix invertibility and improve the numerical stability of Mahalanobis distance calculation. The median of the standardized impedance residuals for each path is selected as the median of the path residual directionality. The median of the path residual directionality is substituted into the sign function to calculate the offset direction term. When the median of the path residual directionality is greater than zero, the sign function outputs a positive 1; when the median of the path residual directionality is equal to zero, the sign function outputs 0; when the median of the path residual directionality is less than zero, the sign function outputs a negative 1. The median is used to suppress isolated bias points in the residuals, so that the direction term only reflects the dominant directional trend of the multi-path residual offset, without being disturbed by extreme values. The ±1 output of the sign function can characterize the directional information of the parasitic offset tendency to increase or decrease. The intermediate vector is obtained by right-multiplying the current residual vector by the inverse of the covariance matrix of the residual vector. Then, the scalar value is obtained by multiplying the intermediate vector by the transpose of the residual vector. The scalar value is divided by the number of paths and the square root is taken to obtain the Mahalanobis distance. The inverse of the covariance matrix measures the deviation of the current residual vector from its historical statistical distribution. The order of right and left multiplication ensures that the calculation process conforms to the mathematical definition of Mahalanobis distance. A larger scalar value indicates a more significant deviation of the residual from its historical stable range. The number of paths is used to normalize for different path sizes, ensuring the Mahalanobis distance remains comparable under different configurations. The Mahalanobis distance value is added to a constant and the natural logarithm is taken to obtain the logarithm of the Mahalanobis offset. The natural logarithm transformation is used to compress the magnitude in high offset cases, making the incremental change in offset more linear and interpretable, and avoiding excessive sensitivity of the control strategy due to extreme anomalies. The constant ensures the defined nature of the logarithmic operation, preventing mathematical infeasibility issues when the Mahalanobis distance is zero. The parasitic resistance offset value is obtained by multiplying the offset direction term by the logarithm of the Mahalanobis offset term. The parasitic resistance offset value comprehensively reflects the magnitude and direction of the offset, and can be used to determine the dynamic trend of parasitic resistance changes. It serves as an important criterion for subsequent window classification, parasitic disturbance shielding, and health analysis, enabling quantitative tracking and robust identification of parasitic disturbances.

[0044] The specific formula for the parasitic resistance offset value is as follows:

[0045] ;

[0046] In the formula, This represents the parasitic resistance offset value, which is used to quantitatively assess whether the current measurement link has experienced a parasitic resistance offset based on the directionality and statistical deviation strength of the impedance residual, and to calculate the degree of offset, providing a basis for judgment for stability window screening and subsequent aging analysis; It represents the directional median of the path residual, reflecting the overall tendency of the residual to skew in a certain direction, and is used to determine the direction of the offset; The sign function is used to identify the direction of parasitic resistance offset. The directionality is used to distinguish different offset modes such as increased contact resistance, contact oxidation, and mechanical loosening. The number of paths represents the number of paths involved in impedance sampling, including the individual internal resistance measurement path, the left connecting strip measurement path, and the right connecting strip measurement path. It is used to normalize the covariance scale of the multipath residual. Indicates the length of the historical window, used to statistically analyze the historical distribution characteristics of the residuals; This represents the residual vector within the historical window, used to construct the covariance matrix and the average residual vector; This represents the average residual vector, used to measure the degree to which the current residual deviates from the historical normal pattern; This represents the transpose of the residual vector, used to construct a quadratic form, thereby calculating the degree of deviation of the current residual from the center of the historical distribution; This represents the current residual vector, which is the real-time input for offset recognition; The covariance matrix, representing the residual vector, is used to characterize the correlation between residuals across multiple paths, helping to identify anomalous link states with common offsets across multiple paths. It is a core statistic for Mahalanobis distance calculation.

[0047] In this implementation scheme, by constructing vectors from multi-path residuals and introducing statistical quantities such as the inverse of the covariance matrix and the logarithmic representation of Mahalanobis distance, parasitic resistance shifts can be robustly identified under the joint distribution of multiple paths. This not only accurately distinguishes the direction and magnitude of the shift but also effectively suppresses misjudgments caused by isolated noise points and temperature and current disturbances. It enables continuous tracking of the dynamic changes of parasitic quantities, providing reliable and interpretable shift criteria for subsequent stable window screening and internal resistance aging assessment, and significantly improving the sensitivity and stability of parasitic disturbance identification.

[0048] Specifically, the process of distinguishing stable windows from disturbance windows based on the intensity of the offset direction, and marking the equivalent impedance characterization results of different windows, is as follows: The parasitic resistance offset value is compared with the offset alarm threshold. The offset alarm threshold can be adaptively set by the upper quantile of the historical parasitic resistance offset value distribution, preferably P90 to P95, to ensure that anomaly marking is triggered only when a significant offset occurs, avoiding misjudgments due to normal fluctuations. The allowable time threshold is adaptively set according to the sampling frequency and automatically converted into the number of sampling points to identify persistent rather than transient disturbances: when the absolute value of the parasitic resistance offset value is higher than the offset alarm threshold, and the duration exceeds the allowable time threshold, the sampling window is marked as a parasitic resistance anomaly window, and the corresponding measurement path identifier and timestamp are recorded. The measurement path identifier is automatically written by the MCU during path switching, and the timestamp is generated by a high-precision timer within the MCU, making the anomaly window traceable. The recording method for the anomaly window includes the window start and end times, the parasitic resistance offset value, and the amplitude of the parasitic resistance offset value, used for subsequent analysis of the evolution trend of the parasitic resistance offset. For parasitic resistance anomaly windows, the corresponding normalized equivalent impedance values ​​under operating conditions are marked as parasitic disturbance data. This parasitic disturbance data is used to eliminate unsteady impedance points generated during drastic changes in parasitic resistance, preventing them from entering the aging trend modeling process. It can also be stored separately for fault diagnosis analysis. For sampling windows not marked as parasitic resistance anomaly windows, the normalized equivalent impedance values ​​under operating conditions are marked as parasitic stable data. The parasitic stable data set is used for subsequent extraction of mean, deviation, and health features. Its stability has been verified by the offset determination process and can serve as an effective source of features for individual unit impedances. The parasitic resistance offset values ​​and corresponding markers are written into the individual unit impedance sampling database.

[0049] In this implementation scheme, by jointly determining the directionality and intensity of parasitic resistance offset values, it is possible to accurately distinguish between stable windows and disturbance windows during real-time sampling, avoiding interference from sudden changes in parasitic quantities on impedance characteristics. At the same time, by structurally writing abnormal windows and stable data into the database, high-quality impedance data that can be used for aging assessment can be continuously obtained, thereby significantly improving the accuracy of parasitic offset identification and the reliability of impedance feature extraction, providing stable and reliable basic data for subsequent health assessment.

[0050] Specifically, based on the equivalent impedance characterization results within the stable window, the process of extracting the window mean and robust deviation to assess the aging trend of the single-unit internal resistance is as follows: Normalized equivalent impedance values ​​marked as parasitic stable data and belonging to the single-unit internal resistance measurement path are extracted from the single-unit impedance sampling database in time-stamp order to construct an impedance time series. The parasitic stable data is generated by the preceding offset identification module, ensuring that the input time series is unaffected by fluctuations in connecting strip resistance and poor contact at the contacts, thus truly reflecting the evolution of the single-unit impedance over time. The impedance time series is read according to the unified timestamp order recorded in the database, ensuring strict temporal continuity for trend analysis. Based on a fixed sliding time window, the average value of the impedance time series is calculated to obtain the equivalent internal resistance mean. The sliding window length can be adaptively set according to the sampling period, preferably 30 to 120 seconds, to cover sufficient sampling points to suppress instantaneous fluctuations while maintaining sensitivity to impedance change inflection points. The window average value is used to characterize the typical internal resistance level under stable conditions and serves as a benchmark statistic for subsequent offset judgment. Simultaneously, the median absolute deviation is calculated based on the mean of the equivalent internal resistance and the normalized equivalent impedance value within the window, serving as the robust deviation scale value for the window. Compared to the standard deviation, the median absolute deviation is insensitive to isolated outliers and can robustly reflect the natural fluctuation range of impedance, making it suitable for asymmetric disturbance characteristics that may occur in batteries under various operating conditions. The rated internal resistance value is obtained, and the internal resistance offset is obtained by subtracting the rated internal resistance value from the mean of the equivalent internal resistance. The internal resistance offset is then divided by the rated internal resistance value to obtain the relative internal resistance offset ratio. The negative of the relative internal resistance offset ratio is used as the exponent for natural exponential calculation. The result of the natural exponential calculation is subtracted from the constant to obtain the exponential decay term. The rated internal resistance value is a factory calibration parameter initialized and written into the database. The exponential decay term is used to construct a nonlinear mapping that is monotonically sensitive to increases in internal resistance, distinguishing between slight and significant offsets in the value range. Dividing the internal resistance offset by the sum of the window robust bias scale value and the minimum constant value yields the fluctuation normalization term. The minimum constant value is used to avoid computational instability caused by the denominator approaching zero. The fluctuation normalization term measures the relative drasticness of internal resistance changes, ensuring that the assessment results simultaneously reflect mean deviation and fluctuation anomalies. Multiplying the exponential decay term by the fluctuation normalization term yields the cell internal resistance aging trend value. While maintaining physical interpretability, the cell internal resistance aging trend value characterizes the aging rate and degree in a monotonically increasing manner, providing a unified quantitative indicator for health level determination, lifespan assessment, and early warning mechanisms.

[0051] The specific formula for the aging trend value of monomer internal resistance is as follows:

[0052] ;

[0053] In the formula, This represents the aging trend value of the internal resistance of a single cell. It is used to calculate the true aging trend of the internal resistance of a single cell based on the change in equivalent internal resistance and its fluctuation scale within a stable window after eliminating parasitic resistance disturbances. This is used for health level determination and aging trajectory construction. It represents the average equivalent internal resistance, reflecting the steady-state level of the current cycle's single-unit internal resistance, and serves as a reference for estimating the current true internal resistance state; This indicates the rated internal resistance value, representing the reference internal resistance in the early stages of health. This represents the window robustness deviation scale value, reflecting the natural fluctuation range of the equivalent internal resistance within the window; This represents a very small constant value used to maintain numerical stability and prevent divergence caused by an excessively small denominator when the window robustness bias scale value is very small. It is determined based on the noise baseline of the impedance sampling link, the accuracy of voltage and current measurements, and commonly used numerical stability strategies in robust statistics. The preferred value is [value to be filled in]. arrive .

[0054] In this embodiment, Table 1 is a data table of monomer internal resistance aging trend values. The rated internal resistance is 2.00, and the minimum constant is 0.0001. The table records in detail the average equivalent internal resistance, window robustness deviation scale value, and monomer internal resistance aging trend value corresponding to five sampling times. Among them, the average equivalent internal resistance at time 1 is 2.02, the window robustness deviation scale value is 0.015, and the monomer internal resistance aging trend value is 0.0132; the average equivalent internal resistance at time 2 is 2.05, the window robustness deviation scale value is 0.018, and the monomer internal resistance aging trend value is 0.0132. The potential value is 0.0682; the equivalent internal resistance mean value at time 3 is 2.13, the window robustness deviation scale value is 0.020, and the monomer internal resistance aging trend value is 0.4070; the equivalent internal resistance mean value at time 4 is 2.23, the window robustness deviation scale value is 0.025, and the monomer internal resistance aging trend value is 0.9955; the equivalent internal resistance mean value at time 5 is 2.30, the window robustness deviation scale value is 0.030, and the monomer internal resistance aging trend value is 1.3883.

[0055] Table 1. Data on Aging Trend Values ​​of Monomer Internal Resistance

[0056]

[0057] like Figure 4 The figure shows the time-series evolution of the aging trend value of the monomer internal resistance. It displays the time-series evolution curves of the aging trend value of the monomer internal resistance calculated at five sampling times, and also provides reference lines for the aging thresholds L1 and L2. The line graph intuitively reflects the changing trend of the equivalent internal resistance mean deviation from the rated value over time, as well as the influence of the robust deviation scale on the internal resistance fluctuation, clearly determining the aging level of the monomer at different time stages. Combined with Table 1 and... Figure 4It can be seen that from time 1 to time 5, the aging trend value of the internal resistance of the monomer shows a significant upward trend, indicating that the internal resistance of the monomer gradually increases with the running time, and the aging trend is obvious and accelerating; the aging trend values of the internal resistance of the monomer at time 1 and time 2 are significantly lower than L1 and are in a healthy state; time 3 falls between L1 and L2, entering the mild aging range; time 4 and time 5 exceed the threshold L2, indicating that the monomer has entered the significant aging stage, and the aging trend value at time 5 is close to 1.4 and shows an intensifying trend; the change rate of the overall aging trend continuously increases, the aging process is non-linear, and the internal resistance grows faster in the later stage, which may be related to the increase of parasitic resistance, the aggravation of interface deterioration or the enhancement of temperature effect.

[0058] In this implementation plan, by extracting the mean and robust deviation of the equivalent impedance sequence within the stable window, and combining with the rated internal resistance offset, exponential decay mapping and fluctuation normalization evaluation, the aging trend value can simultaneously reflect the degree of internal resistance increase and the characteristics of abnormal fluctuations; the overall process has the advantages of high robustness, insensitivity to noise and parasitic disturbances, continuous and consistent trend description and strong physical interpretability, providing a reliable data basis and a more accurate aging metric for subsequent health level determination and aging evolution tracking.

[0059] Specifically, the specific process of constructing the internal resistance aging trajectory, generating health warnings and evolution references based on the aging trend to determine the health level is as follows: the aging trend value of the internal resistance of the monomer is compared with the multi-level aging thresholds L1 and L2: when < L1, an internal resistance health mark is generated, and the sampling frequency and sampling delay strategy of the MCU are kept unchanged; when L1 ≤ < L2, an internal resistance mild aging mark is generated, the sampling frequency of the internal resistance measurement path of the monomer is increased, and the sampling delay of the internal resistance measurement path of the monomer is shortened; when When L2 is ≥, a significant aging marker for internal resistance is generated, and a single-cell aging warning is pushed out. A dynamic sampling delay compensation mechanism is activated, and the conduction signal stabilization time is adjusted. Simultaneously, the battery cell is controlled to operate at a reduced rate. The multi-level aging thresholds L1 and L2 can be derived from the distribution range of historical single-cell internal resistance aging trend values ​​and can be adaptively updated according to the battery model and application scenario to improve the consistency of health assessment across different battery platforms. L1 is preferably selected from the P60 to P75 quantile range of the single-cell internal resistance aging trend value distribution, and L2 is preferably selected from the P85 to P95 quantile range of the single-cell internal resistance aging trend value distribution. Sampling frequency adjustment and sampling delay reduction are implemented by the MCU through internal clock scheduling, which can directly affect the impedance sampling task scheduling table, allowing battery cells with higher aging levels to receive more frequent monitoring cycles, thereby improving the early identification capability of degradation. Derating can be achieved by limiting the allowable operating current of the battery cell or reducing the proportion of the battery cell participating in power distribution to prevent further deterioration of degraded cells under high load conditions. The aging trend value of the individual cell's internal resistance, the corresponding timestamp, the measurement path identifier, and the aging level mark are written into the individual cell impedance sampling database, forming a trajectory of the individual cell's internal resistance aging trend value over time. The slope of the trajectory is statistically analyzed to assess the rate of degradation of the individual cell's internal resistance, and a health assessment report is generated based on the aging level and the rate of degradation. The slope is calculated using linear regression to measure the speed of the aging trend. The health assessment report includes the trajectory of the individual cell's internal resistance aging trend value, aging level, degradation rate, future risk warnings, and recommended operating strategies, providing directly actionable maintenance and operation references.

[0060] In this implementation scheme, the aging status of individual cells is determined in a hierarchical manner through multi-level thresholds, and combined with control measures such as dynamic sampling scheduling, conduction signal adjustment, and derating operation, the monitoring strategy can be adaptively adjusted according to the degree of aging. At the same time, a health assessment report is generated based on the aging trend trajectory and degradation rate, realizing continuous quantification and visualization of the long-term degradation process of battery cells, thereby significantly improving the early aging identification capability and operational safety.

[0061] Reference Figure 2As shown, the second aspect of the present invention provides a battery cell impedance sampling system based on machine learning and MCU control, applied to the aforementioned battery cell impedance sampling method based on machine learning and MCU control, comprising: a data acquisition and preprocessing module, used to acquire impedance measurement data of each path in real time, and perform robust preprocessing, sampling window alignment and normalization processing on the impedance measurement data; a working condition normalization and residual modeling module, used to establish the sensitivity relationship between temperature and current to impedance based on historical preprocessed impedance measurement data, and obtain the normalized equivalent impedance characterization result; extract the impedance residual features of each path based on the equivalent impedance characterization result; and an MCU control and stability enhancement module, used to perform MCU control and stability enhancement based on each path. Impedance residual characteristics identify the stability state of the sampling link, perform offset determination on paths with continuous deviations, and generate MCU control strategies to enhance the real-time steady-state of the sampling link. The parasitic resistance offset identification module is used to identify parasitic resistance offset events using the impedance residual characteristics of each path and extract the offset direction intensity characterization. Based on the offset direction intensity characterization, it distinguishes between stable windows and disturbance windows and marks the equivalent impedance characterization results of different windows. The single-unit internal resistance aging assessment module is used to extract the window mean and robust deviation to assess the aging trend of single-unit internal resistance based on the equivalent impedance characterization results within the stable window. Based on the aging trend, it determines the health level, constructs the internal resistance aging trajectory, and generates health warnings and evolution references.

[0062] In this implementation scheme, a complete link self-calibration and health diagnosis system is constructed through multi-path impedance acquisition, normalized modeling of operating conditions, residual stability analysis, parasitic offset identification, and aging trend assessment. This system achieves measurement noise suppression, dynamic separation of parasitic quantities, enhancement of link steady state, and quantitative determination of single-cell aging. It ensures that impedance measurement results remain consistent and interpretable under complex operating conditions and can output reliable health levels and aging evolution references, significantly improving the accuracy and feasibility of single-cell state assessment.

[0063] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0064] The preferred embodiments of the present invention disclosed above are merely illustrative of the invention. These preferred embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. As those skilled in the art will understand, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A battery cell impedance sampling method based on machine learning and MCU control, characterized in that, Includes the following steps: S1 collects impedance measurement data for each path in real time and performs robust preprocessing, sampling window alignment and normalization on the impedance measurement data. S2. Based on the historical preprocessed impedance measurement data, establish the sensitivity relationship between temperature and current to impedance, and obtain the normalized equivalent impedance characterization results; extract the impedance residual characteristics of each path based on the equivalent impedance characterization results. S3 identifies the stability state of the sampling link based on the impedance residual characteristics of each path, performs offset determination on the continuously deviating path, and generates MCU control strategy to perform real-time steady-state enhancement of the sampling link. The specific process of identifying the stability state of the sampling link based on the impedance residual characteristics of each path, determining the offset of continuously deviating paths, and generating an MCU control strategy to enhance the real-time steady-state of the sampling link is as follows: Read the normalized equivalent impedance value, the corresponding average normalized equivalent impedance value, and the standardized impedance residual for each path. When the normalized equivalent impedance value under the operating condition is higher than the corresponding average value for a duration exceeding the allowable time threshold, an instruction to increase the conduction signal stabilization time and sampling delay of the path is generated, where the conduction signal stabilization time is the on / off buffer time of the single-pole double-throw switch; when the normalized impedance residual is higher than the residual threshold, an instruction to increase the sampling frequency of the corresponding path is generated; the instruction is sent to the MCU in real time. If the detected change in sampling voltage or sampling current exceeds the corresponding change threshold, resampling is triggered. At the same time, if the detected normalized equivalent impedance value of the path is higher than that of other paths for a duration exceeding the allowable time threshold, the control MCU will correct the sampling voltage and sampling current of the path according to the deviation of the normalized equivalent impedance value. S4. Parasitic resistance shift events are identified by utilizing the impedance residual characteristics of each path, and the intensity characterization of the shift direction is extracted. The stability window and the disturbance window are distinguished based on the intensity characterization of the shift direction, and the equivalent impedance characterization results of different windows are marked. The specific process of identifying parasitic resistance offset events using the impedance residual characteristics of each path and extracting the intensity characterization of the offset direction is as follows: The standardized impedance residuals of each path are arranged into residual vectors according to the path order. The average residual vector is calculated based on the residual vector sequence within the historical window, and the covariance matrix of the residual vector is calculated. The median of the standardized impedance residuals of each path is selected as the path residual directional median. The path residual directional median is substituted into the sign function to calculate the offset direction term. The intermediate vector is obtained by right-multiplying the current residual vector by the inverse of the covariance matrix of the residual vector. The scalar value is obtained by multiplying the intermediate vector by the transpose of the residual vector. The scalar value is divided by the number of paths and the square root is taken to obtain the Mahalanobis distance value. The Mahalanobis distance value is added to a constant and the natural logarithm is taken to obtain the Mahalanobis offset logarithm term. The offset direction term is multiplied by the Mahalanobis offset logarithm term to obtain the parasitic resistance offset value. S5. Based on the equivalent impedance characterization results within the stable window, the window mean and robust deviation are extracted to assess the aging trend of the monomer's internal resistance. Health levels are determined based on aging trends, an internal resistance aging trajectory is constructed, and health warnings and evolutionary references are generated.

2. The battery cell impedance sampling method based on machine learning and MCU control according to claim 1, characterized in that, The specific process of acquiring impedance measurement data for each path in real time and performing robust preprocessing, sampling window alignment, and normalization on the impedance measurement data is as follows: The MCU controls a single-pole double-throw switch to enter different paths, including: the individual cell internal resistance measurement path, the left connecting bar measurement path, and the right connecting bar measurement path. Impedance measurement data is collected in real time for each path. The impedance measurement data includes: sampling voltage, sampling current, individual cell temperature, measurement path identifier, and timestamp; the rated internal resistance value is recorded synchronously. Multi-point robust denoising is performed on the sampled voltage and current based on median filtering to filter isolated spike interference caused by contact bounce, transient pulses, and relay jitter. Abnormal sampling points are eliminated using amplitude threshold discrimination and physical consistency verification. Consistency checks are performed on timestamps and measurement path identifiers using time series integrity verification, and sampling period alignment is performed based on the sampling timestamps to align valid sampling points from different paths to a unified sampling window. Minimum-maximum normalization is performed on the impedance measurement data. A single-unit impedance sampling database is established, and the raw and preprocessed impedance measurement data are written into the single-unit impedance sampling database.

3. The battery cell impedance sampling method based on machine learning and MCU control according to claim 1, characterized in that, The specific process of establishing the sensitivity relationship between temperature and current to impedance based on historical preprocessed impedance measurement data, and obtaining the normalized equivalent impedance characterization result is as follows: Obtain the preprocessed impedance measurement data for each path, calculate the difference between the sampled voltage and the sampled current at the current time and the previous time, and obtain the change in sampled voltage and the change in sampled current, respectively. The equivalent impedance value is obtained by dividing the change in sampled voltage by the change in sampled current. Based on the distribution of individual unit temperature and sampling current amplitude within the historical window, the median is selected as the reference value for individual unit temperature and sampling current, respectively. At the same time, the median of the distribution of historical equivalent impedance values ​​is selected to obtain the impedance reference value. Under the condition that the sampling current is within the current range centered on the sampling current reference value, the corresponding historical unit temperature and equivalent impedance value set are extracted, and the least squares fitting is performed to obtain the temperature impedance slope. The temperature impedance slope is then normalized according to the impedance reference value to obtain the temperature sensitivity coefficient. Under the condition that the unit temperature is within the temperature range centered on the unit temperature reference value, the corresponding set of historical sampling current amplitude and equivalent impedance values ​​are extracted, and the current impedance slope is obtained by least square fitting. The current impedance slope is then normalized according to the impedance reference value to obtain the current sensitivity coefficient. Calculate the difference between the monomer temperature and the monomer temperature reference value, multiply it by the temperature sensitivity coefficient, and add the product to a constant to obtain the temperature correction term; Calculate the difference between the sampled current amplitude and the sampled current reference value, multiply it by the current sensitivity coefficient, add the product to a constant to obtain the current correction term, and divide the equivalent impedance value by the product of the temperature correction term and the current correction term to obtain the normalized equivalent impedance value under operating conditions.

4. The battery cell impedance sampling method based on machine learning and MCU control according to claim 1, characterized in that, The specific process for extracting the impedance residual characteristics of each path based on the equivalent impedance characterization results is as follows: The normalized equivalent impedance value of each path is calculated and written into the buffer window, and the average value and standard deviation of the normalized equivalent impedance value of the corresponding path are calculated. For each path, calculate the difference between the normalized equivalent impedance value under operating conditions and the corresponding average value, and divide it by the corresponding standard deviation to obtain the standardized impedance residual; write the normalized equivalent impedance value and standardized impedance residual of each path into the individual impedance sampling database.

5. The battery cell impedance sampling method based on machine learning and MCU control according to claim 1, characterized in that, The specific process of distinguishing between stable windows and disturbance windows based on the intensity characterization of the offset direction, and marking the equivalent impedance characterization results of different windows, is as follows: Compare the parasitic resistance offset value with the offset alarm threshold: When the absolute value of the parasitic resistance offset is higher than the offset alarm threshold and the duration exceeds the allowable time threshold, the sampling window is marked as a parasitic resistance abnormal window, and the corresponding measurement path identifier and timestamp are recorded; for the parasitic resistance abnormal window, the corresponding normalized equivalent impedance value is marked as parasitic disturbance data. For sampling windows that are not marked as parasitic resistance anomaly windows, the normalized equivalent impedance value under operating conditions is marked as parasitic stable data. Write the parasitic resistance offset value and the corresponding tag into the single-unit impedance sampling database.

6. The battery cell impedance sampling method based on machine learning and MCU control according to claim 1, characterized in that, The specific process for extracting the window mean and robust deviation to assess the aging trend of the monomer's internal resistance based on the equivalent impedance characterization results within the stable window is as follows: Extract the normalized equivalent impedance values ​​of the working conditions that are marked as parasitic stable data and belong to the internal resistance measurement path of the single-unit impedance sampling database in the order of timestamp, and construct the impedance time series; calculate the average value of the impedance time series based on a fixed sliding time window to obtain the mean value of the equivalent internal resistance; at the same time, calculate the median absolute deviation of the normalized equivalent impedance values ​​of the working conditions within the window based on the mean value of the equivalent internal resistance as the window robust deviation scale value. Obtain the rated internal resistance value, subtract the rated internal resistance value from the equivalent internal resistance mean to obtain the internal resistance offset, divide the internal resistance offset by the rated internal resistance value to obtain the internal resistance relative offset ratio, take the negative of the internal resistance relative offset ratio as the exponent for natural exponent calculation, subtract the natural exponent calculation result from the constant to obtain the exponential decay term; divide the internal resistance offset by the sum of the window robust deviation scale value and the minimum constant value to obtain the fluctuation normalization term; multiply the exponential decay term and the fluctuation normalization term to obtain the single-cell internal resistance aging trend value.

7. The battery cell impedance sampling method based on machine learning and MCU control according to claim 1, characterized in that, The specific process of determining health level based on aging trends, constructing internal resistance aging trajectory, and generating health early warning and evolution reference is as follows: The aging trend value of monomer internal resistance Compare with multi-level aging thresholds L1 and L2: When When <L1, generate an internal resistance health flag and keep the sampling frequency and sampling delay strategy of the MCU unchanged; When L1 ≤ < L2, generate a mild internal resistance aging mark, increase the sampling frequency of the internal resistance measurement path of the cell, and shorten the sampling delay of the internal resistance measurement path of the cell; when When the resistance is ≥L2, a significant aging marker is generated, and a single cell aging warning is pushed. The dynamic sampling delay compensation mechanism is enabled, and the conduction signal stabilization time is adjusted. At the same time, the battery cells are controlled to operate at reduced derating. The aging trend value of the internal resistance of a single cell, the corresponding timestamp, the measurement path identifier and the aging level mark are written into the single cell impedance sampling database, and a trajectory of the aging trend value of the internal resistance of a single cell that evolves over time is formed. The slope of the trajectory of the aging trend value of the monomer internal resistance is statistically analyzed to assess the rate of degradation of the monomer internal resistance, and a monomer internal resistance health assessment report is generated based on the aging level and the rate of degradation of the monomer internal resistance.

8. A battery cell impedance sampling system based on machine learning and MCU control, employing the battery cell impedance sampling method based on machine learning and MCU control as described in any one of claims 1-7, characterized in that, include: The data acquisition and preprocessing module is used to acquire impedance measurement data of each path in real time, and perform robust preprocessing, sampling window alignment and normalization on the impedance measurement data. The operating condition normalization and residual modeling module is used to establish the sensitivity relationship between temperature and current to impedance based on historical preprocessed impedance measurement data, and obtain the normalized equivalent impedance characterization results; and extract the impedance residual characteristics of each path based on the equivalent impedance characterization results. The MCU control and stability enhancement module is used to identify the stability state of the sampling link based on the impedance residual characteristics of each path, perform offset determination on the continuously deviating path, and generate MCU control strategies to perform real-time steady-state enhancement of the sampling link. The parasitic resistance offset identification module is used to identify parasitic resistance offset events by utilizing the impedance residual characteristics of each path and extract the intensity characterization of the offset direction; it distinguishes between stable windows and disturbance windows based on the intensity characterization of the offset direction and marks the equivalent impedance characterization results of different windows. The single-cell internal resistance aging assessment module is used to extract the window mean and robust deviation to assess the aging trend of single-cell internal resistance based on the equivalent impedance characterization results within the stable window. Health levels are determined based on aging trends, an internal resistance aging trajectory is constructed, and health warnings and evolutionary references are generated.

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