Memory management method and storage device

Abstract

The invention provides a memory management method and a storage device. The method comprises the following steps: confirming whether a first entity unit in a memory module relates to a continuous write event or not; and if the first entity unit relates to the continuous write event, prohibiting determining the first entity unit as the source unit. In a data sorting operation for a memory module, valid data stored in a source unit may be migrated to a target unit in the memory module. Therefore, the execution efficiency of the data arrangement operation aiming at the memory module can be effectively ensured and / or improved.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and more particularly to a memory management method and a storage device. Background Technology

[0002] Generally, during garbage collection within a storage device, the memory controller selects the physical block containing the least amount of valid data in the memory module as the source block, and migrates the valid data collected from the source block to the target block for centralized storage. After the valid data has been completely migrated from the source block, the source block can be erased to make room for new data.

[0003] In practice, it has been found that the selection of source blocks is crucial to the performance of garbage collection operations. If an inappropriate entity block is selected as the source block, it may lead to poor performance of garbage collection operations, and may even cause the storage device to repeatedly restart the garbage collection operation, which will seriously affect the user experience and / or reduce the lifespan of the storage device. Summary of the Invention

[0004] This invention provides a memory management method and a storage device that can optimize the selection of source units, thereby effectively ensuring and / or improving the performance of data processing operations for memory modules.

[0005] This invention provides a memory management method for a storage device, wherein the storage device includes a memory module, and the memory management method includes: confirming whether a first entity unit in the memory module is involved in a continuous write event; and if the first entity unit is involved in the continuous write event, prohibiting the first entity unit from being identified as a source unit, wherein in a data processing operation for the memory module, valid data stored in the source unit is migrated to a target unit in the memory module.

[0006] This invention also provides a storage device, which includes a connection interface, a memory module, and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory controller is used to execute the memory management method described above.

[0007] Based on the above, after confirming that the first entity cell in the memory module is involved in a continuous write event, the first entity cell can be prevented from being identified as a source cell. During data compaction operations on the memory module, valid data stored in the source cell will be migrated to the target cell in the memory module. Therefore, by optimizing the selection of the source cell, the performance of data compaction operations on the memory module can be effectively ensured and / or improved (e.g., effectively reducing the occurrence of invalid data compaction operations). Attached Figure Description

[0008] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0009] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0010] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention;

[0011] Figure 4 This is a schematic diagram illustrating the prohibition or permission to identify a specific entity unit as a source unit according to an embodiment of the present invention;

[0012] Figure 5 This is a schematic diagram illustrating the sorting of multiple entity units in a memory module based on valid count information, according to an embodiment of the present invention.

[0013] Figure 6 This is a schematic diagram of a multi-layer mapping table according to an embodiment of the present invention;

[0014] Figure 7 This is a flowchart illustrating a memory management method according to an embodiment of the present invention. Detailed Implementation

[0015] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0016] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention. Please refer to... Figure 1 The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, tablet computer, laptop computer, desktop computer, industrial computer, game console, server, or computer system installed in a specific carrier (such as a vehicle, aircraft, or ship), and the type of host system 11 is not limited to these. In addition, the storage device 12 may include a solid-state drive, USB flash drive, memory card, or other types of non-volatile storage device.

[0017] The host system 11 may include a processor 111 and a buffer memory 112. The processor 111 is used to handle all or part of the operation of the host system 11. For example, the processor 111 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or other similar devices or combinations thereof.

[0018] Buffer memory 112 is connected to processor 111 and used to cache data. For example, buffer memory 112 may include static random access memory (SRAM), dynamic random access memory (DRAM), or other types of volatile memory. Buffer memory 112 can be used as the main memory of host system 11. In addition, host system 11 may also include various hardware circuit modules such as power management circuitry, mouse, keyboard, screen, and / or wired / wireless communication circuitry, which will not be described in detail here.

[0019] Storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect storage device 12 to host system 11. For example, connection interface 121 may support embedded multi-media card (eMMC), universal flash storage (UFS), peripheral component interconnect express (PCI Express), non-volatile memory express (NVM express), Serial Advanced Technology Attachment (SATA), universal serial bus (USB), or other types of connection interface standards. Therefore, storage device 12 can communicate with host system 11 (e.g., exchange signals, instructions, and / or data) via connection interface 121.

[0020] Memory module 122 is used to store data. For example, memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also known as threshold voltage). For example, memory module 122 may include a Single Level Cell (SLC) NAND flash memory module, a Multi Level Cell (MLC) NAND flash memory module, a Triple Level Cell (TLC) NAND flash memory module, a Quad Level Cell (QLC) NAND flash memory module, and / or other memory modules with the same or similar characteristics.

[0021] Memory controller 123 is connected to connection interface 121 and memory module 122. Memory controller 123 can be considered the control core of storage device 12 and is used to control storage device 12. For example, memory controller 123 can be used to control or manage the overall or partial operation of storage device 12. For example, memory controller 123 may include a CPU, or other programmable general-purpose or special-purpose microprocessor, DSP, programmable controller, ASIC, PLD, or other similar device or a combination of these devices. In one embodiment, memory controller 123 may include a flash memory controller.

[0022] The memory controller 123 can send instruction sequences to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read instruction sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase instruction sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations; this invention is not limited thereto. The memory module 122 can receive instruction sequences from the memory controller 123 and access its internal memory cells according to these instruction sequences.

[0023] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 2The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 via the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0024] Memory control circuitry 23 is connected to host interface 21 and memory interface 22. Memory control circuitry 23 can be used to control or manage the overall or partial operation of memory controller 123. For example, memory control circuitry 23 can communicate with host system 11 via host interface 21 and access memory module 122 via memory interface 22. For example, memory control circuitry 23 may include control circuitry such as embedded controllers or microcontrollers. In the following embodiments, the description of memory control circuitry 23 is equivalent to the description of memory controller 123.

[0025] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuitry 23 and is used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122. The buffer memory 24 may include SRAM, DRAM, or other types of volatile memory.

[0026] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data integrity. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code. In one embodiment, the memory controller 123 may also include other types of circuit modules (e.g., power management circuitry), which is not limited by the present invention.

[0027] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention. Please refer to... Figures 1 to 3 The memory module 122 includes multiple physical units 301(1) to 301(B). Each physical unit includes multiple storage units for non-volatile storage of data.

[0028] In one embodiment, an entity unit may include at least one entity erasure unit. Furthermore, an entity erasure unit may include multiple entity programming units.

[0029] In one embodiment, an entity programming unit may include multiple entity sectors. For example, the data capacity of an entity sector may be 512 bytes (B), and an entity programming unit may include 32 entity sectors. However, the data capacity of an entity sector and / or the total number of entity sectors included in an entity programming unit can be adjusted according to practical needs, and the present invention is not limited thereto. For example, the storage capacity of an entity programming unit may be 16 kilobytes, and the present invention is not limited thereto. In one embodiment, an entity programming unit is also referred to as an entity page.

[0030] In one embodiment, a physical programming unit is the smallest unit of synchronously written data in memory module 122. For example, when performing a programming operation (also called a write operation) on a physical programming unit to write data to that physical programming unit, multiple memory cells in that physical programming unit can be synchronously programmed to store the corresponding data. For example, when programming a physical programming unit, a write voltage can be applied to that physical programming unit to change the threshold voltage of at least some of the memory cells in that physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in that memory cell.

[0031] In one embodiment, multiple programmed units within a single physical erase unit can be erased simultaneously. For example, when an erase operation is performed on a single physical erase unit, an erase voltage can be applied to the multiple programmed units within that unit to change the threshold voltage of at least a portion of the memory cells in those units. By performing an erase operation on a single physical erase unit, the data stored in that unit can be erased. In one embodiment, a physical erase unit is also referred to as a physical block.

[0032] In one embodiment, the memory control circuit 23 can logically associate entity units 301(1)-301(A) and 301(A+1)-301(B) with the data area 31 and the idle area 32, respectively. Entity units 301(1)-301(A) in the data area 31 all store data (also called user data) from the host system 11. For example, any entity unit in the data area 31 can store valid data and / or invalid data. In addition, entity units 301(A+1)-301(B) in the idle area 32 do not store any data (e.g., valid data).

[0033] In one embodiment, if a certain entity unit does not store valid data, this entity unit can be associated with the free area 32. Furthermore, entity units in the free area 32 can be erased to clear the data in that entity unit. In one embodiment, entity units in the free area 32 are also referred to as idle entity units. In one embodiment, the free area 32 is also referred to as the free pool.

[0034] In one embodiment, when data needs to be stored, the memory control circuit 23 can select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data into the selected physical units. After the data is stored into this physical unit, this physical unit can be associated with the data area 31. In other words, one or more physical units can be used alternately between the data area 31 and the idle area 32.

[0035] In one embodiment, the memory control circuit 23 may be configured with multiple logic units 302(1)-302(C) to map physical units (i.e., physical units 301(1)-301(A)) in the data area 31. For example, a logic unit may correspond to a logical block address (LBA) or other logical management unit. A logic unit may be mapped to one or more physical units.

[0036] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in this physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that this physical unit does not currently store any valid data.

[0037] In one embodiment, the memory control circuit 23 may record the mapping relationship between logic units and physical units in at least one management table (also known as a logic-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing, or erasing based on the information (also known as mapping information) in this management table (i.e., the logic-to-physical mapping table).

[0038] In one embodiment, the memory control circuit 23 can detect whether the total number of idle entity units in the memory module 122 is less than a threshold (also referred to as a first threshold). For example, each entity unit in the idle area 32 (e.g., entity unit 301(A+1)-301(B)) can be considered as an idle entity unit. For example, the first threshold can be 3, 5, 10, or other positive integers.

[0039] In one embodiment, in response to the total number of idle physical units in memory module 122 being less than a first threshold, memory control circuitry 23 may trigger a data compaction operation for memory module 122. This data compaction operation is used to increase the total number of idle physical units in memory module 122. For example, in the data compaction operation for memory module 122, valid data stored in at least one physical unit (also referred to as a source unit) in memory module 122 is migrated to at least one physical unit (also referred to as a target unit) in memory module 122.

[0040] In one embodiment, this data compaction operation may include a garbage collection (GC) operation. In another embodiment, this data compaction operation may also include a wear leveling operation or other operations that can free up non-idle physical units through data migration.

[0041] In one embodiment, after triggering a data defragmentation operation for memory module 122, memory control circuit 23 may identify at least one entity unit from the non-idle entity units in memory module 122 as a source unit. For example, each entity unit in data area 31 (e.g., entity units 301(1)-301(A)) may be considered a non-idle entity unit. On the other hand, memory control circuit 23 may identify at least one entity unit from the idle entity units in memory module 122 as a target unit. Subsequently, in this data defragmentation operation, memory control circuit 23 may instruct memory module 122 to migrate (i.e., move or copy) valid data stored in the source unit to the target unit for centralized storage. After the valid data stored in a certain source unit has been completely migrated to the target unit, this source unit may be associated with idle area 32 and may be erased. This frees up more idle entity units (i.e., increases the total number of idle entity units in memory module 122) to maintain the normal operation of storage device 12.

[0042] In one embodiment, after triggering a data defragmentation operation for the memory module 122, the memory control circuit 23 continuously detects whether the total number of idle physical units in the memory module 122 is not less than a threshold value (also referred to as a second threshold value). For example, the second threshold value can be 3, 5, 10, or other positive integers. Furthermore, the second threshold value can be the same as or different from the first threshold value, and the present invention is not limited thereto. For example, in one embodiment, the second threshold value can be greater than the first threshold value.

[0043] In one embodiment, after a data defragmentation operation is triggered for memory module 122, in response to the total number of idle entity units in memory module 122 being no less than a second threshold, memory control circuit 23 may stop (e.g. terminate) the data defragmentation operation for memory module 122.

[0044] In one embodiment, the memory control circuit 23 may receive operation instructions from the host system 11. For example, these operation instructions may include write instructions, read instructions, and delete instructions. A write instruction may be used to instruct the storage (i.e., updating) of data belonging to at least one logical unit. A read instruction may be used to instruct the reading of data belonging to at least one logical unit. A delete instruction may be used to instruct the deletion of data belonging to at least one logical unit. Furthermore, the operation instructions from the host system 11 may also include other types of operation instructions, which are not limited by the present invention.

[0045] In one embodiment, the memory control circuit 23 can instruct the memory module 122 to perform corresponding operations based on operation instructions from the host system 11. For example, based on a write instruction from the host system 11, the memory control circuit 23 can instruct the memory module 122 to perform a write operation to store new data belonging to at least one logical unit into the memory module 122. Based on a read instruction from the host system 11, the memory control circuit 23 can instruct the memory module 122 to perform a read operation to read data belonging to at least one logical unit from the memory module 122. Alternatively, based on a delete instruction from the host system 11, the memory control circuit 23 can instruct the memory module 122 to perform a delete operation to delete (i.e., erase) data belonging to at least one logical unit from the memory module 122.

[0046] In one embodiment, the memory control circuit 23 can detect consecutive write events. These consecutive write events correspond to multiple write instructions (also called consecutive write instructions). These write instructions (i.e., consecutive write instructions) are used to instruct the consecutive storage (i.e., updating) of data belonging to multiple consecutive logical ranges.

[0047] In one embodiment, the memory control circuit 23 may sequentially receive N write instructions CMD(1)-CMD(N) (i.e., consecutive write instructions) from the host system 11. Write instruction CMD(1) instructs the storage (i.e., updating) of data belonging to the logical range R(1). Similarly, write instruction CMD(N) instructs the storage (i.e., updating) of data belonging to the logical range R(N). The logical ranges R(1)-R(N) are consecutive.

[0048] In one embodiment, N can be 3, 5, or any integer greater than 1. In one embodiment, N must be greater than a preset value (e.g., 2 or 3). In one embodiment, the total logical range consisting of logical ranges R(i)-R(N) must be greater than a preset range (e.g., spanning a preset number of logical addresses or logical offsets). In one embodiment, based on write instructions CMD(1)-CMD(N), the memory control circuit 23 can determine that the continuous write event has been detected. However, if N is not greater than the preset value and / or the total logical range consisting of logical ranges R(1)-R(N) is not greater than the preset range, the memory control circuit 23 can determine that the continuous write event has not been detected.

[0049] In one embodiment, if a sequential write event is used to update data currently stored in a certain entity unit (also referred to as a specific entity unit) and belonging to a relatively large logical range, then the valid data in this specific entity unit may be gradually updated to invalid data as this sequential write event is executed. Consequently, during the execution of this sequential write event, the amount of valid data in this specific entity unit gradually decreases (equivalent to the amount of invalid data gradually increasing). In this case, if a data compaction operation (e.g., garbage collection) is triggered for memory module 122 during the execution of this sequential write event, this specific entity unit has a high probability of being selected as the source unit in the data compaction operation (because the amount of valid data in the specific entity unit may be relatively small) in an attempt to accelerate the execution of the data compaction operation.

[0050] However, the above operation may cause a problem: after selecting a specific entity unit as the source unit and performing data migration on the valid data stored in that specific entity unit, the valid data that has just been migrated to the target unit may be quickly updated to invalid data due to the continuous execution of the continuous write events. This situation is similar to directly migrating invalid data originally stored in some source units during a data cleanup operation (normal data cleanup operations only migrate valid data). As a result, the performance of the data cleanup operation may be lower than expected, system performance may be wasted, and / or the write amplification (WA) of the memory module 122 may be increased meaninglessly.

[0051] In one embodiment, the memory control circuit 23 can determine whether at least one physical cell (also referred to as the first physical cell) in the memory module 122 is involved in the sequential write event. In one embodiment, the first physical cell may include... Figure 3The first entity unit belongs to any entity unit among entity units 301(1)-301(A) in data area 31. In one embodiment, the first entity unit may also include any entity unit in data area 31 that has been or will be selected as a source unit in the data processing operation. In one embodiment, the first entity unit may also include any entity unit in data area 31 that meets the filtering criteria for source units.

[0052] In one embodiment, the memory control circuit 23 can determine whether the first entity unit stores data updated as indicated by at least one of the plurality of consecutive write instructions. If the first entity unit stores data updated as indicated by at least one of the plurality of consecutive write instructions, it means that with the execution of at least one of the plurality of consecutive write instructions, at least a portion of the data in the first entity unit will be updated to invalid data because it belongs to the same logical unit as the new data stored as indicated by at least one of the plurality of consecutive write instructions. In this case, in response to the first entity unit storing data updated as indicated by at least one of the plurality of consecutive write instructions, the memory control circuit 23 can determine that the first entity unit is involved in the consecutive write event. However, if the first entity unit does not store data updated as indicated by at least one of the plurality of consecutive write instructions, the memory control circuit 23 can determine that the first entity unit is not involved in the consecutive write event.

[0053] In one embodiment, the memory control circuit 23 can also determine whether the first entity unit stores the updated data indicated by the last write instruction (e.g., write instruction CMD(N)) among the plurality of consecutive write instructions. If the first entity unit stores the updated data indicated by the last write instruction among the plurality of consecutive write instructions, it means that with the execution of the last write instruction among the plurality of consecutive write instructions, at least a portion of the data in the first entity unit will be updated to invalid data because it belongs to the same logical unit as the new data indicated by the last write instruction among the plurality of consecutive write instructions. In this case, in response to the first entity unit storing the updated data indicated by the last write instruction among the plurality of consecutive write instructions, the memory control circuit 23 can determine that the first entity unit is involved in the consecutive write event. However, if the first entity unit does not store the updated data indicated by the last write instruction among the plurality of consecutive write instructions, the memory control circuit 23 can determine that the first entity unit is not involved in the consecutive write event.

[0054] In other words, in one embodiment, the memory control circuit 23 can determine that the first entity unit is involved in the consecutive write event as long as the first entity unit stores the updated data indicated by any one of the plurality of consecutive write instructions (e.g., write instruction CMD(i), where i is between 1 and N). However, in one embodiment, the memory control circuit 23 will only determine that the first entity unit is involved in the consecutive write event when the first entity unit stores the updated data indicated by the last of the plurality of consecutive write instructions.

[0055] In one embodiment, if the memory control circuit 23 determines that the first entity cell is involved in the continuous write event, the memory control circuit 23 may prevent the first entity cell from being identified as the source cell. For example, after detecting a continuous write event and triggering a data defragmentation operation for the memory module 122, if the memory control circuit 23 determines that the first entity cell is involved in the continuous write event, the memory control circuit 23 may prevent the first entity cell from being identified as the source cell for this data defragmentation operation. This ensures that during the execution of this data defragmentation operation, valid data collected from the source cell will not become invalid data after being migrated to the target cell due to involvement in the continuous write event. This ensures and / or improves the performance of the data defragmentation operation for the memory module 122.

[0056] In one embodiment, if the memory control circuit 23 determines that the first entity cell is not involved in the continuous write event, the memory control circuit 23 may allow the first entity cell to be identified as the source cell. For example, after the first entity cell is identified as the source cell, valid data stored in the first entity cell (i.e., the source cell) can be migrated to the target cell during the data cleanup operation. After all valid data stored in the first entity cell has been completely migrated to the target cell, the first entity cell can be associated with the idle area 32 and can be erased to become a new idle entity cell.

[0057] In one embodiment, after determining that the first entity unit is involved in the consecutive write event, the memory control circuit 23 may further confirm whether the data updated by the last write instruction among the plurality of consecutive write instructions is located in the last storage space in the first entity unit. For example, the last storage space in the first entity unit refers to the last entity programmed unit in the first entity unit. During the programming of the first entity unit, this last storage space is the last storage space in the first entity unit to be programmed (i.e., the last entity programmed unit to be programmed).

[0058] In one embodiment, if the first entity unit is involved in the consecutive write event, and the last write instruction among the plurality of consecutive write instructions indicates that the updated data is located in the last storage space (e.g., the last entity programmable unit) of the first entity unit, it means that even though the first entity unit is involved in the consecutive write event, there is no longer any valid data in the first entity unit that will be affected by the consecutive write event and become invalid. In this case (in response to the first entity unit being involved in the consecutive write event, and the last write instruction among the plurality of consecutive write instructions indicating that the updated data is located in the last storage space of the first entity unit), the memory control circuit 23 may still allow the first entity unit to be identified as the source unit.

[0059] In one embodiment, if a first entity unit is involved in the continuous write event, and the data updated by the last write instruction among the plurality of continuous write instructions is not located in the last storage space (e.g., the last programmed entity unit) of the first entity unit, it indicates that even if the first entity unit is involved in the continuous write event, there is still valid data in the first entity unit that may be subsequently affected by the continuous write event and become invalid. In this case (responding to the first entity unit being involved in the continuous write event, and the data updated by the last write instruction among the plurality of continuous write instructions not being located in the last storage space of the first entity unit), the memory control circuit 23 can prevent the first entity unit from being identified as the source unit. Thus, compared to directly prohibiting all entity units involved in the continuous write event from being identified as source units, the operational accuracy can be further improved, and the performance of data processing operations can be further reduced due to the use of an overly strict screening mechanism.

[0060] Figure 4 This is a schematic diagram illustrating the prohibition or permission to identify a specific entity as a source element according to an embodiment of the present invention. Please refer to... Figure 4 Assume that the plurality of consecutive write instructions include write instructions 41-43 received sequentially from host system 11. Write instruction 41 is the first write instruction among write instructions 41-43 (e.g., the first write instruction received among write instructions 41-43). Write instruction 43 is the last write instruction among write instructions 41-43 (e.g., the last write instruction received among write instructions 41-43).

[0061] In one embodiment, write instruction 41 instructs the storage (i.e., update) of data belonging to logical range R(1). Write instruction 42 instructs the storage (i.e., update) of data belonging to logical range R(2). Write instruction 43 instructs the storage (i.e., update) of data belonging to logical range R(3). Logical ranges R(1)-R(3) are consecutive. For example, logical range R(1) is between logical addresses LBA(1)-LBA(x), logical range R(2) is between logical addresses LBA(x)-LBA(y), and logical range R(3) is between logical addresses LBA(y)-LBA(z). Each logical address may correspond to one logical unit. Based on write instructions 41-43, memory control circuit 23 can determine that the consecutive write events have been detected.

[0062] In one embodiment, the first entity unit includes entity unit 401(i). For example, entity unit 401(i) may be... Figure 3 One of the entity units 301(1)-301(A) in the data area 31. In response to the continuous write event, the memory control circuit 23 can determine whether entity unit 401(i) is involved in the continuous write event.

[0063] In one embodiment, it is assumed that all data originally stored in entity unit 401(i) is valid data. Write instruction 43 instructs to update the data stored in the slashed region 402 of entity unit 401(i), and the slashed region 402 does not include the last storage space in entity unit 401(i) (e.g., the last procedural unit in entity unit 401(i)). After execution of write instruction 43 (i.e., in response to the execution of write instruction 43), the data stored in the slashed region 402 of entity unit 401(i) will be updated to invalid data (data outside the slashed region 402 of entity unit 401(i) can remain valid data).

[0064] In one embodiment, in response to a write instruction 43 instructing the updating of data in entity unit 401(i) (and the data to be updated by the write instruction 43 is not located in the last storage space in entity unit 401(i)), the memory control circuit 23 may prevent entity unit 401(i) from being identified as source unit 410. Alternatively, in one embodiment, in response to a write instruction 43 instructing the updating of data in entity unit 401(i) (and the data to be updated by the write instruction 43 is not located in the last storage space in entity unit 401(i)), the memory control circuit 23 may exclude (e.g., remove) entity unit 401(i) from source unit 410.

[0065] In one embodiment, source unit 410 may include entity units 411(1)-411(D). For example, during a data defragmentation operation performed on memory module 122, valid data stored in source unit 410 (i.e. entity units 411(1)-411(D)) may be migrated to target unit to free up new idle entity units from source unit 410.

[0066] In one embodiment, by disallowing entity unit 401(i) from being identified as source unit 410 and / or excluding (e.g., removing) entity unit 401(i) from source unit 410, data migration of valid data currently stored in entity unit 401(i) but likely to become invalid due to the continuous write event can be avoided during the execution of a continuous write event. This ensures and / or improves the performance of data defragmentation operations for the memory module (e.g., effectively reducing the occurrence of invalid data defragmentation operations).

[0067] In one embodiment, the first entity unit further includes entity unit 401(j). In response to the sequential write event, memory control circuitry 23 can determine whether entity unit 401(j) is involved in the sequential write event. In response that entity unit 401(j) is not involved in the sequential write event (e.g., entity unit 401(j) does not store the updated data indicated by any of write instructions 41-43), memory control circuitry 23 can allow entity unit 401(j) to be identified as source unit 410. For example, memory control circuitry 23 can allow entity unit 401(j) to be added to source unit 410 to become one of entity units 411(1)-411(D).

[0068] In one embodiment, in response to the continuous write event, the memory control circuit 23 may update a flag value from one value (also referred to as a first value) to another value (also referred to as a second value). For example, the first value may be "0" and the second value may be "1". Alternatively, the first value may be "1" and the second value may be "0", without limitation by the present invention.

[0069] In one embodiment, if this flag value is a first value, it indicates that no continuous write event has been detected. Conversely, if this flag value is a second value, it indicates that the continuous write event has been detected. For example, this flag value may be recorded in a management table.

[0070] In one embodiment, in response to a data defragmentation operation being triggered, the memory control circuit 23 can access the memory module 122 (i.e., Figure 3The first entity cell is selected in the data area 31), and the flag value is checked. For example, the memory control circuit 23 can check whether the flag value is a second value to quickly confirm whether a continuous write event has been detected.

[0071] In one embodiment, in response to the data defragmentation operation being triggered and the flag value being a second value (indicating that a continuous write event has been detected), the memory control circuit 23 may perform the aforementioned operation of confirming whether the first entity unit is involved in the continuous write event. The relevant operational details have been described above and will not be repeated here. However, if the flag value is not the second value (for example, if the flag value is the first value, indicating that no continuous write event has been detected), then after triggering the data defragmentation operation, the memory control circuit 23 may not perform the aforementioned operation of confirming whether the first entity unit is involved in the continuous write event. For example, the memory control circuit 23 may skip the aforementioned operation of confirming whether the first entity unit is involved in the continuous write event and directly (or allow) determine the first entity unit as the source unit.

[0072] In one embodiment, the memory control circuit 23 can obtain valid count information corresponding to a plurality of physical units in the memory module 122. For example, this valid count information can reflect the amount of valid data stored in each of the plurality of physical units.

[0073] In one embodiment, the valid count information may include multiple count values ​​(also referred to as valid counts). These count values ​​may respectively reflect the amount of valid data stored in the plurality of entity units. For example, suppose the valid count corresponding to a certain entity unit is "10". The memory control circuit 23 may determine, based on this valid count, that the 10 entity programmable units in this entity unit currently store valid data (i.e., the amount of valid data stored in this entity unit is equal to the capacity of the 10 entity programmable units).

[0074] In one embodiment, the memory control circuit 23 can use this valid count information to control the memory module 122 (i.e., Figure 3 The multiple entity units in the data area 31) are sorted to obtain a sorting result. For example, based on this valid count information, the memory control circuit 23 can sort the multiple entity units from most to least or from least to most based on the amount of valid data stored in each entity unit. Therefore, the sorting result can reflect which entity units in the memory module 122 store relatively more valid data, and / or which entity units store relatively less valid data, etc.

[0075] In one embodiment, the memory control circuit 23 may determine a first entity unit from the memory module 122 based on the sorting result. For example, the memory control circuit 23 may, based on the sorting result, assign a first entity unit to the memory module 122 (i.e., ... Figure 3 The entity unit that stores the least or relatively few valid data in the data area 31) is determined as the first entity unit.

[0076] In one embodiment, the memory control circuit 23 can determine at least one physical cell from the memory module 122 that meets the filtering criteria of the source cell based on the valid count information. For example, the memory control circuit 23 can determine the memory module 122 (i.e., Figure 3 At least one entity cell storing the least or relatively few valid data in the data area 31) is identified as an entity cell in the memory module 122 that meets the filtering criteria for source cells. Then, the memory control circuit 23 can determine the first entity cell from the at least one entity cell in the memory module 122 that meets the filtering criteria for source cells. In one embodiment, the filtering criteria for source cells can also be adjusted according to practical needs, and this invention is not limited thereto.

[0077] Figure 5 This is a schematic diagram illustrating the sorting of multiple physical units in a memory module based on valid count information, according to an embodiment of the present invention. Please refer to... Figure 5 Assuming that the memory module 122 (i.e., based on the valid count information) is... Figure 3 After sorting multiple entity units in data area 31), the sorting result shows that entity unit 401(i) has the smallest effective count, entity unit 401(j) has the second smallest effective count, and entity unit 401(k) has the largest effective count. The specific sorting result is as follows: Figure 5 As shown, the effective counts corresponding to each entity unit gradually increase from left to right.

[0078] In one embodiment, the memory control circuit 23 may select entity unit 401(i) as the first entity unit based on this sorting result. The number of entity units 401(i) may be one or more, and the present invention is not limited thereto.

[0079] In one embodiment, after entity unit 401(i) is determined as the first entity unit, if entity unit 401(i) is prohibited from being a source unit (e.g.) Figure 4 If the source unit 410 is selected, the memory control circuit 23 can select another physical unit (also called the second physical unit) from the memory module 122 to replace the first physical unit as the source unit. It should be noted that the first physical unit and the second physical unit are different physical units in the memory module 122.

[0080] by Figure 5 For example, after determining entity unit 401(i) as the first entity unit, if entity unit 401(i) is prohibited from being used as a source unit (e.g.) Figure 4 If the source unit 410 is selected, the memory control circuit 23 can select entity unit 401(j) as the second entity unit. For example, entity unit 401(j) can be used to replace the first entity unit as the source unit.

[0081] In one embodiment, the total amount of valid data stored in entity unit 401(i) may be less than the total amount of valid data stored in entity unit 401(j), such as... Figure 5 As shown. Therefore, even if the entity unit storing the least amount of effective data is not selected as the source unit at present, the performance of data processing operations can still be effectively improved. The relevant details have been described above and will not be repeated here. In one embodiment, the determination (i.e., selection) of the first entity unit and / or the second entity unit may also refer to other types of parameters, such as the degree of damage of the entity unit, bit error rate and / or data storage duration, etc., and the present invention does not impose any limitations.

[0082] In one embodiment, after selecting a physical unit from the memory module 122 as the second physical unit, the memory control circuit 23 may further confirm whether this physical unit is involved in the aforementioned continuous write event. If this physical unit is also involved in the aforementioned continuous write event, the memory control circuit 23 may discard this physical unit and select another physical unit in the memory module 122 as the second physical unit again, until a physical unit that is not involved in the aforementioned continuous write event is selected.

[0083] In one embodiment, the memory control circuit 23 may also be configured with a multi-level mapping table. The memory control circuit 23 may record multiple flag bits (also referred to as first-type flag bits) in the first level of this multi-level mapping table. These first-type flag bits can be used to reflect the usage status of multiple logic units respectively. For example, the first-type flag bit corresponding to a certain logic unit can reflect whether this logic unit has been used to store data from the host system 11.

[0084] In one embodiment, the memory control circuit 23 may record multiple flag bits (also referred to as second-type flag bits) in the second-level mapping table of this multi-level mapping table. These second-type flag bits can be used to reflect the usage status of multiple entity units respectively. For example, the second-type flag bit corresponding to a certain entity unit can reflect whether this entity unit has been used to store data from the host system 11. Subsequently, the memory control circuit 23 can refer to this multi-level mapping table to confirm whether the first entity unit is involved in the continuous write event. For example, by comparing the first-type flag bits in the first-level mapping table with the second-type flag bits in the second-level mapping table, the memory control circuit 23 can quickly confirm whether the first entity unit is involved in the continuous write event.

[0085] Figure 6 This is a schematic diagram of a multi-layer mapping table according to an embodiment of the present invention. Please refer to... Figure 6 Assume the multi-level mapping table includes a first-level mapping table 61 and a second-level mapping table 62. The first-level mapping table 61 can be used to record usage status information related to multiple logical units. For example, the first-level mapping table 61 can be used to record the logical range between logical addresses LBA(y) and LBA(z) (e.g., ...). Figure 4 The usage status information of R(3)).

[0086] In one embodiment, the first-level mapping table 61 may record flag bits 601 and 611. Flag bits 601 and 611 correspond to logical addresses LBA(y) and LBA(z), respectively. When both flag bits 601 and 611 are "1", it reflects that the usage status of logical addresses LBA(y) and LBA(z) is "used" (i.e., they have been used to store data from the host system 11). However, if a certain flag bit in the first-level mapping table 61 is "0", it reflects that the logical address corresponding to this flag bit has not yet been used (i.e., it has not yet been used to store data from the host system 11).

[0087] In one embodiment, it is assumed that the logical range belongs to the logical address range between LBA(y) and LBA(z) (e.g. Figure 4 The data within the logical range R(3) is currently stored at entity address PBA(i). For example, entity address PBA(i) corresponds to Figure 4 The entity unit 401(i). Therefore, based on the inter-layer mapping relationship in this multi-layer mapping table, the memory control circuit 23 can find the second-layer mapping table 62.

[0088] In one embodiment, the second-level mapping table 62 can be used to record usage status information related to at least one entity unit. For example, the second-level mapping table 62 can be used to record usage status information related to entity unit 401(i).

[0089] In one embodiment, the second-level mapping table 62 may record a flag bit 602. The flag bit 602 corresponds to the entity address PBA(i). When the flag bit 602 is "1", it indicates that the entity address PBA(i) is in a "used" state (i.e., it has been used to store data from the host system 11 and can be considered as a source unit for data processing operations, for example, belonging to...). Figure 3 Data area 31). In one embodiment, the second-level mapping table 62 may further record the usage status of each entity programmable unit in entity unit 401(i), such as whether it is used to store data belonging to logical range R(3).

[0090] In one embodiment, based on the first-level mapping table 61 and the second-level mapping table 62, the memory control circuit 23 can quickly determine whether the first entity cell (e.g., entity cell 401(i)) is involved in the continuous write event. The relevant details have been described above and will not be repeated here.

[0091] In one embodiment, the memory control circuit 23 may also record a plurality of flag bits (also referred to as third-type flag bits) in the second-level mapping table. These third-type flag bits can be used to reflect whether the plurality of entity units are involved in the continuous write event.

[0092] by Figure 6 For example, in one embodiment, the second-level mapping table 62 can also be used to record a flag bit 603. Similar to flag bit 602, flag bit 603 also corresponds to the entity address PBA(i). Flag bit 603 being "1" indicates that entity unit 401(i) is involved in a continuous write event. For example, after determining that entity unit 401(i) is involved in a continuous write event, the memory control circuit 23 can update flag bit 603 to "1". Conversely, if entity unit 401(i) is not involved in a continuous write event, the memory control circuit 23 can set flag bit 603 to "0".

[0093] In one embodiment, the memory control circuit 23 can quickly determine whether a first entity cell (e.g., entity cell 401(i)) is involved in the continuous write event, and whether to prevent the first entity cell (e.g., entity cell 401(i)) from being identified as the source cell, based on the first-level mapping table 61 and the second-level mapping table 62. The relevant details have been described above and will not be repeated here.

[0094] In one embodiment, after determining that the first entity unit is involved in the continuous write event, the memory control circuit 23 may also refer to the multi-layer mapping table to search for a second entity unit (e.g., entity unit 401(j)) from the plurality of entity units to replace the first entity unit (e.g., entity unit 401(i)).

[0095] by Figure 6 For example, in one embodiment, the multi-level mapping table further includes a second-level mapping table 63. The second-level mapping table 63 can be used to record and... Figure 4 The usage status information related to entity unit 401(j). For example, entity address PBA(j) corresponds to entity unit 401(j). Note that the logical range between logical addresses LBA(y) and LBA(z) (e.g.) Figure 4 The data in the logical range R(3) is not currently stored in the physical address PBA(j).

[0096] In one embodiment, the second-level mapping table 62 may record a flag bit 612. The flag bit 612 corresponds to the entity address PBA(j). When the flag bit 612 is "1", it indicates that the entity address PBA(j) is in a "used" state (i.e., it has been used to store data from the host system 11 and can be considered as a source unit for data processing operations, for example, belonging to...). Figure 3 Data area 31).

[0097] In one embodiment, based on the first-level mapping table 61 and the second-level mapping table 63, the memory control circuit 23 can quickly determine whether the second entity unit (e.g., entity unit 401(j)) is involved in the continuous write event. The relevant details have been described above and will not be repeated here. In response to the second entity unit (e.g., entity unit 401(j)) not being involved in the continuous write event, the memory control circuit 23 can use the second entity unit (e.g., entity unit 401(j)) to replace the first entity unit (e.g., entity unit 401(i)) as the source unit for valid data.

[0098] In one embodiment, the second-level mapping table 63 can also be used to record a flag bit 613. Similar to flag bit 612, flag bit 613 also corresponds to the entity address PBA(j). Flag bit 613 being "0" indicates that entity unit 401(j) is not involved in a continuous write event. For example, after determining that entity unit 401(j) is not involved in a continuous write event, the memory control circuit 23 can set flag bit 613 to "0" to indicate that entity unit 401(j) is not involved in a continuous write event. Conversely, if entity unit 401(j) is involved in a continuous write event, the memory control circuit 23 can set flag bit 603 to "1" to indicate that entity unit 401(j) is involved in a continuous write event.

[0099] In one embodiment, the memory control circuit 23 can quickly determine a second entity unit (e.g., entity unit 401(j)) to replace the first entity unit (e.g., entity unit 401(i)) based on the first-level mapping table 61 and the second-level mapping table 63. Furthermore, the memory control circuit 23 can also quickly determine whether it is permissible to identify the second entity unit (e.g., entity unit 401(j)) as the source unit based on the first-level mapping table 61 and the second-level mapping table 63. The relevant details have been described above and will not be repeated here.

[0100] It should be noted that the above-described management, information recording format, and usage of multi-level mapping tables are merely examples and are not intended to limit the present invention. In one embodiment, the above-described management, information recording format, and usage of multi-level mapping tables can be adjusted or optimized according to practical needs to achieve optimal operational performance.

[0101] Figure 7 This is a flowchart illustrating a memory management method according to an embodiment of the present invention. Please refer to... Figure 7 In step S701, it is determined whether the first entity cell in the memory module is involved in a continuous write event. If the first entity cell is involved in the continuous write event, in step S702, identifying the first entity cell as a source cell is prohibited. In particular, during data processing operations on the memory module, valid data stored in the source cell is migrated to the target cell in the memory module. Furthermore, if the first entity cell is not involved in the continuous write event, in step S703, identifying the first entity cell as a source cell is permitted.

[0102] However, Figure 7 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 7 Each step can be implemented as multiple program codes or circuits, and this invention is not limited thereto. Furthermore, Figure 7 The method can be used in conjunction with the above examples and embodiments, or it can be used alone. This invention does not impose any limitations.

[0103] In summary, the memory management method and memory device proposed in this invention can optimize the selection strategy for source cells (including considering whether the first entity cell that may be a source cell is involved in consecutive write events). This effectively ensures and / or improves the performance of data compaction operations on the memory module (e.g., effectively reducing the occurrence of invalid data compaction operations).

[0104] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method characterized by comprising: A memory management method for a storage device, wherein the storage device comprises a memory module, and the memory management method comprises: determining whether a first physical unit in the memory module is involved in a continuous write event; and if the first physical unit is involved in the continuous write event, prohibiting the first physical unit from being determined as a source unit, wherein the source unit is used as a physical unit that needs to be subjected to a data grooming operation.

2. The memory management method of claim 1, wherein the first physical unit comprises a physical unit in the memory module that meets a screening condition of the source unit.

3. The memory management method of claim 1, wherein the continuous write event corresponds to a plurality of write instructions, and the step of determining whether the first physical unit in the memory module is involved in the continuous write event comprises: determining whether the first physical unit stores data that is updated by at least one of the plurality of write instructions.

4. The memory management method of claim 3, wherein the step of determining whether the first physical unit stores the data that is updated by at least one of the plurality of write instructions comprises: determining whether the first physical unit stores data that is updated by a last write instruction of the plurality of write instructions.

5. The memory management method of claim 4, wherein the step of prohibiting the first physical unit from being determined as the source unit if the first physical unit is involved in the continuous write event comprises: in response to the first physical unit being involved in the continuous write event and the data that is updated by the last write instruction of the plurality of continuous write instructions not being located in a last storage space in the first physical unit, prohibiting the first physical unit from being determined as the source unit.

6. The memory management method of claim 1, wherein the step of determining whether the first physical unit in the memory module is involved in the continuous write event comprises: updating a flag value from a first value to a second value in response to the continuous write event; in response to the data grooming operation being triggered, selecting the first physical unit from the memory module and checking the flag value; and if the flag value is the second value, determining whether the first physical unit is involved in the continuous write event.

7. The memory management method of claim 6, wherein the step of selecting the first physical unit from the memory module comprises: sorting a plurality of physical units in the memory module according to valid count information to obtain a sorting result; and selecting the first physical unit from the memory module according to the sorting result.

8. The memory management method of claim 1, wherein the step of prohibiting the first physical unit from being determined as the source unit further comprises: selecting a second physical unit from the memory module to replace the first physical unit as the source unit, wherein the first physical unit and the second physical unit are different physical units in the memory module. ​ ​ 9. The memory management method of claim 8, wherein a total amount of valid data stored in the first physical unit is less than a total amount of valid data stored in the second physical unit.

10. The memory management method of claim 1, further comprising: determining the first physical unit as the source unit if the first physical unit is not involved in the continuous write event.

11. The memory management method of claim 1, further comprising: configuring a multi-level mapping table; recording a plurality of first type flag bits in a first level mapping table of the multi-level mapping table to respectively reflect usage status of a plurality of logical units; recording a plurality of second type flag bits in a second level mapping table of the multi-level mapping table to respectively reflect usage status of a plurality of physical units; and referencing the multi-level mapping table to determine whether the first physical unit is involved in the continuous write event.

12. The memory management method of claim 11, further comprising: recording a plurality of third type flag bits in the second level mapping table to respectively reflect whether the plurality of physical units are involved in the continuous write event.

13. The memory management method of claim 11, further comprising: after determining that the first physical unit is involved in the continuous write event, searching for a second physical unit to replace the first physical unit from the plurality of physical units by referencing the multi-level mapping table. comprising:

14. A memory device, comprising: a connection interface to connect to a host system; a memory module; and a memory controller connected to the connection interface and the memory module, wherein the memory controller is configured to perform the memory management method of any one of claims 1 to 13.

14. A memory system, comprising: a connection interface to connect to a host system; a memory module; and a memory controller connected to the connection interface and the memory module, wherein the memory controller is configured to perform the memory management method of any one of claims 1 to 13.

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