Vehicle application scenario-based control chip core requirement adaptation evaluation method and device

Abstract

The application discloses a kind of based on whole vehicle application scene to the adaptation evaluation method and device of core demand of control chip.It is determined that the target whole vehicle application scene of the control chip to be evaluated is included in the method;Based on target whole vehicle application scene generates a test case set containing multidimensional function test;In the test platform of simulating whole vehicle operating environment, test case set is executed, to carry out test to the control chip to be evaluated deployed therein;Response data generated in the process of testing is collected to the control chip to be evaluated;Based on response data, carry out abnormality determination and performance quantification, to obtain the adaptability evaluation result of control chip in target whole vehicle application scene;By comparing the adaptability evaluation result of multiple control chips to be evaluated, output chip selection suggestion.The application can realize multidimensional, quantifiable, comparable adaptability evaluation of control chip based on real whole vehicle working condition, to provide reliable basis for accurate, efficient chip selection.

Description

Technical Field

[0001] This invention belongs to the field of automotive electronics technology, and more specifically, relates to a method and apparatus for adapting and evaluating the core requirements of control chips based on vehicle application scenarios. Background Technology

[0002] As the automotive industry evolves towards electrification, intelligence, and connectivity, its electronic and electrical architecture is rapidly evolving from distributed control to a centralized architecture of domain controllers and even central computing platforms. In this process, the control chip, as the core of each electronic control unit (ECU) in the vehicle, directly determines the functionality, safety, efficiency, and cost of the entire vehicle system due to its performance, reliability, and adaptability to specific application scenarios.

[0003] In various vehicle applications, such as Battery Management Systems (BMS), Motor Controllers, Advanced Driver Assistance Systems (ADAS), and Smart Cockpits, control chips face vastly different computational loads, real-time requirements, communication data throughput, signal sampling accuracy, and power drive demands. Therefore, quickly and accurately selecting the optimal performance and cost-effective chip from a wide range of control chip models for a specific application scenario has become a key technical challenge for OEMs and component suppliers in the early stages of R&D.

[0004] Currently, the mainstream methods for selecting and evaluating control chips in the industry mainly fall into the following two categories:

[0005] The first category is the static parameter comparison method based on chip datasheets. This method relies on specifications provided by chip manufacturers, such as clock speed, number of cores, memory capacity, and the type and number of peripheral interfaces, for horizontal comparison and selection. However, this method has significant limitations: First, the specifications are usually theoretical limits of the chip under ideal, single operating conditions, and cannot reflect its actual performance in real-world automotive environments (such as wide temperature ranges, electromagnetic interference, multi-tasking concurrency, and complex loads); second, this method only focuses on isolated functional parameters and lacks a comprehensive evaluation of the chip's core capabilities, such as computing, communication, sampling, and driving, working collaboratively in specific vehicle control logic and functional scenarios. Therefore, relying solely on static selection often leads to the problem of "sufficient parameters but insufficient performance" after the chip is actually installed in the vehicle. For example, computing bottlenecks cause control delays, communication congestion leads to packet loss, and insufficient driving capabilities seriously affect the stability and security of the system.

[0006] The second category is testing and verification methods based on Automated Test Equipment (ATE) or Hardware-in-the-Loop (HIL). General ATE testing focuses on the electrical characteristics and basic functional testing during chip manufacturing, and cannot simulate complex vehicle application scenarios. While HIL testing can build a high-fidelity vehicle simulation environment, its current application mainly focuses on verifying control strategies, functional testing, and fault injection for pre-designed ECUs. In this case, the test cases are designed based on the vehicle's control logic and functional requirements, aiming to verify the correctness of the controller software, rather than specifically for evaluating and exploring the physical performance boundaries of the control chip itself under extreme scenarios. This method cannot, during the chip selection phase, conduct multi-dimensional quantitative performance assessments and horizontal comparisons of bare dies or different chip models under uniform and comparable vehicle scenario pressures.

[0007] In summary, existing technologies suffer from inherent drawbacks in the early selection and evaluation of control chips, including scenario-specificity, limited evaluation dimensions, lack of extreme stress testing, and poor horizontal comparability. This leads to a reliance on engineer experience in the chip selection process, resulting in significant uncertainty, prolonged development cycles, and increased risks and costs associated with later rectification due to inappropriate selection. Therefore, there is an urgent need for a new method and apparatus that can be closely integrated with specific vehicle application scenarios to systematically, quantitatively, and with high fidelity evaluate the core capabilities of control chips, supporting scientific, efficient, and accurate chip selection decisions. Summary of the Invention

[0008] The purpose of this invention is to propose a method and apparatus for adapting and evaluating the core requirements of control chips based on vehicle application scenarios. This solves the problems of inaccurate and incomplete evaluation caused by existing control chip selection methods relying on static parameters and being detached from actual vehicle application scenarios. The invention enables multi-dimensional, quantifiable, and comparable adaptability evaluation of control chips based on real vehicle operating conditions, thereby providing a reliable basis for accurate and efficient chip selection.

[0009] To achieve the above objectives, in a first aspect, the present invention proposes an adaptation evaluation method for the core requirements of control chips based on vehicle application scenarios, comprising:

[0010] Determine the target vehicle application scenario for the control chip to be evaluated;

[0011] A test case set containing multi-dimensional functional tests is generated based on the target vehicle application scenario;

[0012] The test case set is executed in a test platform that simulates the operating environment of a complete vehicle to test the control chip to be evaluated deployed therein;

[0013] The response data generated by the control chip to be evaluated during the test is collected.

[0014] Based on the response data, anomaly detection and performance quantification are performed to obtain the adaptability evaluation results of the control chip in the target vehicle application scenario.

[0015] By comparing the compatibility evaluation results of multiple control chips to be evaluated, chip selection recommendations are provided.

[0016] Optionally, generating a test case set containing multi-dimensional functional tests based on the target vehicle application scenario includes:

[0017] Functional and load analysis was performed on the target vehicle application scenario to analyze its core requirements for control chips in multiple different dimensions.

[0018] For each core requirement identified in the analysis, corresponding test cases are designed to form the test case set.

[0019] Optionally, the plurality of different dimensions include:

[0020] The dimensions are: computing power, communication power, data sampling power, and driving power.

[0021] Optionally, the test platform simulating the vehicle operating environment is a hardware-in-the-loop test platform, which includes:

[0022] Hardware-in-the-loop simulation unit, and a control chip carrier board that is signal-connected to the hardware-in-the-loop simulation unit.

[0023] Optionally, the control chip carrier board adopts a modular design, including replaceable chip adapter units and fixed interface and peripheral circuit units.

[0024] Optionally, the anomaly determination includes at least one of the following types of detection:

[0025] Detection of abnormal operating status of control chip;

[0026] Detection of the correctness of the functional logic of the control chip;

[0027] Control chip communication robustness testing;

[0028] Detection of abnormal electrical parameters of control chip.

[0029] Optionally, the adaptability evaluation results include:

[0030] The anomaly determination result indicates whether the control chip under evaluation has an anomaly during the test and the type of anomaly.

[0031] The performance quantification results include one or more performance indicators of the control chip to be evaluated in the target vehicle application scenario.

[0032] And the compatibility conclusions generated based on the anomaly determination results and performance quantification results.

[0033] Optionally, the performance metrics include:

[0034] The actual highest computational throughput that characterizes computing power;

[0035] The error-free maximum communication bandwidth that characterizes communication capability;

[0036] The highest sampling rate that guarantees accuracy while characterizing data sampling capability;

[0037] The stable output maximum driving capability characterizes the driving capability.

[0038] Secondly, this invention proposes an adaptation and evaluation device for the core requirements of control chips based on vehicle application scenarios, comprising:

[0039] The determination module is used to determine the target vehicle application scenario for the control chip to be evaluated;

[0040] The generation module is used to generate a test case set containing multi-dimensional functional tests based on the target vehicle application scenario.

[0041] The test platform is used to execute the test case set in a test platform that simulates the operating environment of a whole vehicle in order to test the control chip to be evaluated deployed therein;

[0042] The test platform includes a hardware-in-the-loop simulation unit and a control chip test board connected to the hardware-in-the-loop simulation unit.

[0043] The hardware-in-the-loop simulation unit includes:

[0044] The signal sending unit is used to send test stimulus signals corresponding to the test case set to the control chip test board to simulate real and comprehensive vehicle signals and loads;

[0045] The data acquisition unit is used to acquire response data generated by the control chip to be evaluated during the test; and based on the response data, to perform anomaly judgment and performance quantification to obtain the adaptability evaluation result of the control chip in the target vehicle application scenario;

[0046] The results output module is used to output chip selection recommendations by comparing the compatibility evaluation results of multiple control chips to be evaluated.

[0047] Optionally, the control chip test board adopts a structure of replaceable control chip daughter board and fixed interface mother board.

[0048] The beneficial effects of this invention are as follows: By deeply binding the evaluation of the control chip with specific vehicle application scenarios and constructing a dedicated test case set containing multi-dimensional functional tests, the test content can accurately reflect the core requirements and pressures faced by the chip in the actual vehicle environment. By executing these test cases in a high-fidelity test platform simulating the vehicle's operating environment, the extreme performance and stability of the chip in terms of computing, communication, data sampling, and driving can be realistically and comprehensively stimulated and evaluated. Furthermore, by systematically collecting response data and completing anomaly judgment and performance quantification, quantifiable and comparable compatibility evaluation results are generated, ultimately providing engineers with objective, data-driven chip selection recommendations. This method effectively overcomes the limitations of traditional static selection based on specifications or general functional testing, significantly improving the accuracy, comprehensiveness, and efficiency of chip selection, and reducing the development risks and costs of the entire vehicle electronic system caused by improper chip compatibility from the source.

[0049] The system of the present invention has other features and advantages that will be apparent from or will be set forth in detail in the accompanying drawings and following detailed description, which together serve to explain the particular principles of the invention. Attached Figure Description

[0050] The above and other objects, features and advantages of the present invention will become more apparent from the accompanying drawings, in which like reference numerals generally denote like parts.

[0051] Figure 1 A flowchart illustrating the steps of an adaptation evaluation method for the core requirements of control chips based on a whole vehicle application scenario, according to Embodiment 1 of the present invention, is shown.

[0052] Figure 2 A schematic diagram of a test platform according to Embodiment 1 of the present invention is shown. Detailed Implementation

[0053] The invention will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0054] Example 1

[0055] like Figure 1 As shown, this embodiment provides a method for adapting and evaluating the core requirements of control chips based on vehicle application scenarios, including:

[0056] S1. Determine the target vehicle application scenario for the control chip to be evaluated;

[0057] Specifically, identifying the target vehicle application scenario for the control chip to be evaluated is the first and crucial step in the evaluation process. This aims to precisely link the chip's evaluation process with its specific functional role and demanding operating environment in a real vehicle. This process begins with understanding the vehicle's electronic and electrical architecture and functional definitions to determine the specific functional domain in which the control chip will be applied. For example, it could be a battery management system responsible for energy management (including intelligent charging and low-charge protection for low-voltage batteries, and static, driving, and charging states for high-voltage batteries); motor control responsible for vehicle motion (covering drive, energy recovery, and torque control); body domain control (such as smart key positioning, anti-pinch windows, and headlight control); power domain control (involving vehicle power management, acceleration, coasting, and braking modes); and chassis control systems such as ESP (responsible for anti-lock braking, vehicle dynamic control, and single lane change on snow); and cockpit domain control (covering instrument display, large screen control, navigation, and audio / video control). After defining the functional domain, it is necessary to further decompose its included control function sub-items. For example, in gear control, automatic, manual, and creep modes need to be considered, while in engine control, tasks such as starting, idling, and thermal management need to be analyzed. Only through task decomposition and load analysis of these specific sub-items can the core requirements of the application scenario for the control chip in terms of real-time performance, computing power, communication bandwidth, sampling accuracy, drive capability, functional safety level, and information security be clearly mapped. This ensures that the subsequently generated test case set has a high degree of scenario relevance and engineering practical significance, so that the evaluation results can directly and realistically reflect the chip's adaptability performance in a specific automotive environment.

[0058] S2. Generate a test case set containing multi-dimensional functional tests based on the target vehicle application scenario;

[0059] In this step, a test case set containing multi-dimensional functional tests is generated based on the target vehicle application scenario, including:

[0060] Functional and load analysis was performed on the target vehicle application scenario to analyze its core requirements for control chips in multiple different dimensions.

[0061] For each core requirement identified in the analysis, corresponding test cases are designed to form a test case set.

[0062] Specifically, based on the clearly defined target vehicle application scenario, the core task of this step is to generate a test case set that accurately and comprehensively covers the core stresses of that scenario. Its implementation process includes two key steps:

[0063] First, an in-depth functional and load analysis is conducted on the target vehicle application scenario. This is not a simple listing of functions, but rather a task decomposition and behavioral modeling of specific control function sub-items in the scenario (such as "high-voltage charging" monitoring in battery management, or "high-frequency torque regulation" in motor control). The analysis examines their execution logic, data flow, real-time window, and resource consumption, thereby systematically revealing the specific and quantifiable core requirements that the scenario places on the control chip in different dimensions such as computing power, communication capabilities, data sampling capabilities, and driving capabilities.

[0064] For example, the analysis might conclude that, in the "communication capability dimension," the chip needs to process a specific CAN FD message with a load rate of no less than 80% within 5 milliseconds, or in the "computing capability dimension," it needs to complete a million specific floating-point matrix operations per second.

[0065] Secondly, based on a clear understanding of the quantitative requirements for each dimension, corresponding and executable test cases are designed accordingly. Each test case aims to simulate an extreme stress condition or typical operating mode under that dimension. For example, to test the maximum communication capability, a dense message stream close to the theoretical bandwidth of the bus is designed to be generated and the correctness and real-time performance of the chip processing are verified; to test the driving capability, a PWM signal with an extreme duty cycle or frequency is designed to drive the dynamic load; the data required to test the computing capability is typically abstracted according to the needs of the whole vehicle scenario, such as obtaining it from the cache, communication or data sampling channels, and sending the results to memory or sending them out through the communication interface.

[0066] Finally, the test cases designed for all key dimensions will be systematically integrated and orchestrated to form a complete and logically rigorous set of test cases. This set ensures that the core capabilities of the chip can be fully mobilized and evaluated in the subsequent simulation test platform, and that the internal bus resources of the control chip can be fully utilized, thereby providing a unified and standardized stress test benchmark for objectively evaluating its scenario adaptability.

[0067] In this step, several different dimensions are included:

[0068] The dimensions are: computing power, communication power, data sampling power, and driving power.

[0069] Specifically, multiple dimensions point to computing power, communication capability, data sampling capability, and driving capability. These four dimensions together constitute a complete evaluation system for the core performance and adaptability of automotive-grade control chips in complex vehicle application scenarios.

[0070] For the specific vehicle application scenario (such as motor control, battery management system, or smart cockpit), a deep analysis of these four core functional requirements is necessary:

[0071] The evaluation of computing power focuses on computing power requirements, namely the chip's ability to process integer and single / double floating-point data. It assesses the single-core or multi-core computing throughput and accuracy under various operation models such as matrix transformation, Gaussian elimination, and Fourier transform, and also covers the effective computing power of functional safety cores and information security-related encryption and decryption performance. A typical scenario is the high-frequency operation of FOC (field-oriented control) algorithms in motor control, which puts extreme requirements on the chip's MIPS (millions of instructions per second).

[0072] The communication capability dimension corresponds to communication requirements and aims to evaluate the real-time response, protocol processing capabilities, and sustainable data rates of various communication interfaces integrated into the chip (such as SPI, I2C, CAN, CANFD, LIN, Ethernet, etc.) under actual high loads. For example, in intelligent cockpit domain control, processing massive audio and video streams and navigation data poses a severe challenge to Ethernet bandwidth and CANFD communication rates.

[0073] The data sampling capability dimension revolves around data sampling requirements, focusing on testing the chip's analog / digital conversion channels (such as ADC and DAC) and the sampling rate, conversion accuracy, linearity, and synchronization of digital I / O. Taking the BMS scenario as an example, it is necessary to acquire battery pack voltage and temperature signals with high precision and high frequency, so extremely strict standards are set for the accuracy and rate of AD sampling.

[0074] The driving capability dimension corresponds to driving requirements, assessing the chip's ability to directly control and drive external power loads through interfaces such as GPIO and PWM, including output current intensity, voltage level, response speed, and load stability. For example, in ignition or motor drive scenarios, there are specific indicators for the chip's driving current capability and PWM response speed when driving motors or high-power actuators. By performing scenario-based analysis and quantification of the requirements in these four dimensions, this evaluation method provides a precise test design basis and performance evaluation benchmark.

[0075] Based on the above analysis, the system automatically generates a corresponding set of test cases. For example, for "Scenario 1", it generates test case 1 for computation (such as high-load matrix operation), test case 1 for communication (such as CANFD bus load rate 98% test), test case 1 for data sampling (such as full-channel AD synchronous sampling), and test case 1 for drive (such as high-frequency PWM wave output). The data required for the computation test cases should be obtained from cache, communication, or data sampling channels according to the needs of the whole vehicle scenario, and the results should be sent to memory or sent out through the communication interface.

[0076] S3. Execute the test case set in the test platform that simulates the operating environment of the whole vehicle to test the control chip to be evaluated deployed therein;

[0077] Specifically, the test case set generated in the early stages, targeting specific vehicle application scenarios, is loaded and run on a high-fidelity test platform simulating the operating environment of a complete vehicle. This applies realistic and comprehensive stress testing to the control chip under evaluation deployed on the platform. The core of this test platform typically consists of a hardware-in-the-loop (HIL) simulation unit and a control chip carrier board, forming a complete closed loop from vehicle signal simulation to chip physical implementation. The execution process begins with powering on and initializing the test platform. The HIL simulation unit simulates the vehicle power-on sequence, sequentially sending wake-up and ignition signals to the control chip carrier board, causing the chip under test to enter normal operating mode from sleep mode. Subsequently, based on the preset test case set, the test platform, through the signal excitation module of the simulation unit, injects simulated sensor signals, network packets, load changes, and other scenario-based stimuli into the corresponding pins of the control chip under test in real time via real vehicle communication interfaces or I / O lines. Simultaneously, the platform's data acquisition system monitors all critical responses of the chip, including the output packets of its communication interface, the processor's calculation results, the level and timing of external drive signals, and internal status parameters. The entire test execution process is highly automated, strictly following the process, load and evaluation criteria defined in the test case set, simulating various working conditions from normal operation to extreme boundary conditions, thereby accurately reproducing and evaluating the actual behavior, performance boundaries and stability of the control chip in the target vehicle application scenario in a laboratory environment.

[0078] In this step, the test platform simulating the vehicle's operating environment is a hardware-in-the-loop test platform, which includes:

[0079] Hardware-in-the-loop simulation unit, and a control chip carrier board that is connected to the hardware-in-the-loop simulation unit for signal transmission.

[0080] Specifically, the test platform simulating the vehicle's operating environment is a hardware-in-the-loop (HIL) test platform, consisting of two core components: a HIL simulation unit and a control chip carrier board tightly connected to the HIL simulation unit via electrical signals. The HIL simulation unit, acting as the platform's "brain" and "environment simulator," integrates high-precision vehicle dynamics models, in-vehicle network models, sensor models, and load models. It can calculate and generate various electrical signals and data streams in real time that are completely consistent with the actual vehicle's operating state, such as simulating engine speed, battery voltage, vehicle sensor status, and CAN bus messages. Simultaneously, this unit includes sophisticated signal conditioning and power amplification circuits to ensure that the generated excitation signals meet automotive standards in terms of electrical characteristics. The control chip carrier board, acting as the platform's "body" and the chip's "cabin," has the core function of physically housing the control chip to be evaluated and providing all the necessary peripheral support circuits for its operation, including precise power management, clock circuits, reset circuits, and a rich set of interface adapters (such as CAN transceivers, Ethernet PHYs, and ADC input conditioning circuits). This allows the platform to construct a realistic and independent in-vehicle ECU-level hardware environment for the chip in the laboratory. The two are connected by a wiring harness or connector. The simulation unit applies simulated sensor signals, network communication, power conditions, etc. to the corresponding pins of the chip on the carrier board and collects the chip's response output in real time. This forms a closed-loop test system from the virtual vehicle environment to the real chip hardware, enabling the chip to undergo comprehensive testing in a highly simulated vehicle electrical and functional scenario.

[0081] In one specific embodiment, the hardware-in-the-loop test platform is such as Figure 2 As shown, the hardware-in-the-loop simulation unit is used to simulate the vehicle's operating environment and sensor / actuator signals, and to collect data and output reports. The signal transmission unit is responsible for sending control signals such as wake-up, ignition, and test commands to the test board. The signal transmission and wake-up circuits are connected to the wake-up pin (WAKE) and ignition pin (IGN) of the control chip test board via a level conversion circuit.

[0082] At the start of the test, the system sends signals according to the preset timing diagram: first, at time T0, the wake-up signal is pulled high to switch the chip from low power mode to running mode; at time T1, an ignition signal is sent to turn on the internal power management module; at time T2, an "activate communication" command is sent through the diagnostic interface (such as CAN or UART) to establish a handshake protocol.

[0083] The data sampling unit acquires test data during the control chip's operation in real time through various interfaces (GPIO, CANFD, SPI, I2C, AD, ETH, etc.), and ultimately collects the data via EHT. The data sampling unit uses an FPGA as its core, and its main functions for real-time bus data acquisition include:

[0084] Timing monitoring: Records the start and end times of tests, accurate to the microsecond level, to assess the chip's real-time performance when processing computational test cases;

[0085] Anomaly detection: The monitoring circuit is equipped with a voltage comparator. Once a drop in the chip's power supply voltage or a reset pin trigger is detected, an "anomaly" will be marked immediately.

[0086] Data stream matching: The acquisition unit compares the "stimulus data" sent by HIL with the "response data" fed back by the chip (read via SPI / ETH) in real time to verify the correctness of the control chip's logic processing.

[0087] The output unit is responsible for processing the collected data. After testing multiple models of control chips, the system compares the performance indicators (maximum computing power, maximum communication capability, maximum data sampling rate, and maximum driving capability) of different chips in the same application scenario, and generates the final test report and selection recommendations.

[0088] The control chip test board adopts a motherboard-daughter board format, serving as a carrier for the control chip under test and providing the peripheral circuits required for its operation. It is also designed with abundant interface resources to adapt to different control chips, such as:

[0089] CANFD Interface: The test board integrates a CANFD transceiver, which connects to the HIL's CAN bus. During "communication capability" testing, the HIL simulates a full load of vehicle network messages. The chip must process all messages within a specified time. The data sampling unit monitors the waveforms of CANH / CANL and calculates the bit error rate and load rate.

[0090] AD Sampling Interface: For "data sampling capability" testing, HIL outputs a high-precision analog voltage signal (such as simulating battery voltage fluctuations), which is connected to the chip's AD pin through a low-pass filter. The data sampling unit simultaneously acquires the digital values ​​from the HIL output source and the chip's AD conversion, comparing and calculating the sampling accuracy and linearity.

[0091] SPI / I2C interface: used to connect external sensors or memory, and to test the clock frequency limits and signal integrity of the chip during peripheral communication.

[0092] Drive and GPIO: Connect a load (such as a light bulb or motor coil) to HIL through a power amplifier circuit to test the voltage pull-up capability and drive current of the chip's IO port.

[0093] In this step, the control chip carrier board adopts a modular design, including replaceable chip adapter units and fixed interface and peripheral circuit units.

[0094] Specifically, the control chip carrier board adopts a highly flexible modular design, with its structure mainly divided into two functional units: a replaceable chip adapter unit and a fixed interface and peripheral circuit unit. The replaceable chip adapter unit is the core of the design; it is essentially a dedicated daughterboard that can be independently plugged in. It integrates the dedicated package socket (such as BGA, LQFP, etc.) for the target evaluation control chip, matching pin routing, necessary decoupling capacitors, chip-level configuration circuitry, and a voltage regulator module to power the specific chip core. This unit design allows for the evaluation of control chips with different packages, pin definitions, and even from different manufacturers without redesigning or replacing the entire test baseboard; only the corresponding chip adapter daughterboard needs to be replaced, greatly improving the versatility and switching efficiency of the test platform. The fixed interfaces and peripheral circuit units constitute the universal baseboard of the carrier board, which integrates stable and universal infrastructure, including power management circuitry to power the entire board, clock source, physical layer transceivers for various automotive communication interfaces (such as CAN / CAN FD, LIN, Ethernet PHY), analog front-ends for signal conditioning (such as operational amplifiers and filter circuits), power drive interfaces, and standard connectors for connecting hardware-in-the-loop emulation units. This modular architecture of "replaceable core + fixed universal base" ensures the consistency of the test environment (such as power quality and interface electrical characteristics), provides a fair benchmark for horizontal comparison of different chips, and achieves the flexibility of rapid adaptation to different chips under test. It significantly reduces the hardware cost and preparation time of the evaluation and is a key hardware innovation for achieving efficient and standardized testing in this evaluation device.

[0095] S4. Collect the response data generated by the control chip to be evaluated during the test;

[0096] Specifically, during the execution of the test case set, the system uses a sophisticated data acquisition unit to capture and record in real time the full-dimensional response data generated by the control chip under evaluation deployed on the test platform. This process is not a simple signal reading, but a high-precision, multi-channel synchronous monitoring activity. The acquired data comprehensively covers all core functional outputs of the chip: including but not limited to network messages and data frames actively sent or received by the chip through various communication interfaces (such as CAN FD, Ethernet, SPI) and their precise timestamps; the level status, timing, and frequency characteristics of the drive control signals output from its general-purpose input / output ports or dedicated PWM pins; the calculation results and status information output by the chip's internal processing unit through memory or specific registers after running the test algorithm; and the digital code value output by its analog-to-digital conversion channel after sampling the externally injected analog excitation signal. The data acquisition unit typically consists of a high-performance FPGA, a dedicated protocol analyzer, and a high-precision data acquisition card, ensuring the synchronous capture of multiple electrical and logic signals with microsecond or even nanosecond time accuracy, and real-time uploading to the processing unit. This stage is the core bridge connecting "test stimulus input" and "result analysis and evaluation". The captured raw response data completely and objectively reflects the real behavior of the control chip under simulated scenario pressure, providing indisputable raw data basis for subsequent anomaly judgment and performance quantification.

[0097] S5. Based on the response data, perform anomaly detection and performance quantification to obtain the adaptability evaluation results of the control chip in the target vehicle application scenario.

[0098] Specifically, based on the high-fidelity response data acquired in real time, the system enters the core analysis and evaluation phase, namely, anomaly detection and performance quantification, ultimately generating a comprehensive adaptability evaluation result for the target vehicle application scenario. Anomaly detection is the primary safety and stability screening step. The system performs multi-dimensional comparisons between the acquired raw data and the expected behavior and electrical specifications preset in the test cases to identify any abnormal signs deviating from the normal range. This includes, but is not limited to: detecting whether the chip has experienced functional crashes, unexpected resets, or program crashes; verifying the correctness of its functional logic, i.e., comparing whether the injected stimulus data is consistent with the calculation results or control instructions fed back by the chip, and checking for data overflow, calculation errors, or logical fallacies; monitoring the robustness of communication, checking for erroneous frames, message loss, response timeouts, or load rates that continuously exceed thresholds on the bus; and simultaneously monitoring whether the chip's key electrical parameters (such as core voltage, clock stability, junction temperature, etc.) are always maintained within a safe operating window. Any triggered anomalies are accurately classified, recorded, and marked as critical events. After confirming that there are no major anomalies or marking acceptable anomalies, the system immediately initiates performance quantification. This process extracts key performance indicators from the response data. For example, it calibrates the actual maximum computational throughput by analyzing the shortest completion cycle of the computation task, determines the maximum error-free communication bandwidth by gradually increasing the bus load until frame drops occur, determines the maximum sampling rate while ensuring accuracy by evaluating the deviation between the analog-to-digital conversion result and the standard signal, and determines the maximum driving capability for stable operation by incrementally increasing the load until output distortion occurs. Finally, it performs a comprehensive correlation analysis between a detailed anomaly determination report (including anomaly type, occurrence conditions, and frequency) and a quantified performance indicator report (including performance boundary data for each dimension), generating a structured adaptability evaluation result. This result not only objectively states whether the chip "can work normally," but also accurately answers "how well it performs" and "where the safety boundaries are" in the target scenario, providing a scientifically sound basis with sufficient data support for the final chip selection decision.

[0099] In this step, anomaly detection includes at least one of the following types of detection:

[0100] Detection of abnormal operating status of control chip;

[0101] Detection of the correctness of the functional logic of the control chip;

[0102] Control chip communication robustness testing;

[0103] Detection of abnormal electrical parameters of control chip.

[0104] Specifically, anomaly detection is a systematic diagnostic process designed to identify defects and instabilities in the control chip during testing from different levels, encompassing at least one of the following core types of detection:

[0105] Abnormal detection of the control chip's operating status is achieved by monitoring the chip's "vital signs," including continuously monitoring its watchdog status, reset pin level, whether the program counter runs out of control or gets stuck in an infinite loop, and whether critical tasks are completed within the specified real-time window. Any unexpected reset, suspension, or execution timeout is judged as a serious abnormal status.

[0106] The correctness test of the functional logic of the control chip focuses on verifying the accuracy of the chip's processing logic. By comparing the input stimulus data injected into the test platform with the actual output response data of the chip (such as calculation results, control instructions, and status codes) bit by bit or in terms of conformity, deep functional defects such as data calculation errors, logical judgment fallacies, numerical overflows, or violations of application layer protocol specifications can be discovered.

[0107] Control chip communication robustness testing focuses on the reliability of the chip's interaction with external networks and devices. By deeply analyzing the transmit and receive data streams of its communication interfaces (such as CAN and Ethernet), it detects in real time whether there are error frames, message loss, verification failure, or response timeout, and assesses whether the bus load rate continuously exceeds the design tolerance, thereby judging the chip's communication stability and fault tolerance in complex network environments.

[0108] Control chip electrical parameter anomaly detection ensures chip operation safety from a physical perspective. High-precision sensors monitor the chip's power supply voltage, core current, clock signal stability, junction temperature, and key I / O pin level characteristics in real time. Once these parameters deviate from the safe operating range specified in the chip datasheet or exhibit unstable fluctuations, they are judged as electrical parameter anomalies. Such anomalies are usually direct manifestations of chip overheating, overcurrent, or signal integrity problems.

[0109] The above-mentioned multi-type detection work together to form a comprehensive monitoring network from the physical layer to the application layer, ensuring that various potential faults that may occur in the chip during extreme scenario testing can be captured, providing a solid technical basis for assessing its reliability.

[0110] In this step, the fit assessment results include:

[0111] The anomaly determination result indicates whether the control chip under evaluation has an anomaly during the test and the type of anomaly.

[0112] The performance quantification results include one or more performance indicators of the control chip to be evaluated in the target vehicle application scenario.

[0113] And the adaptability conclusions generated based on the anomaly detection results and performance quantification results.

[0114] Specifically, the compatibility assessment result is the final output of the entire testing and analysis process. It is a structured, data-driven comprehensive technical report that mainly includes the following three levels of core content:

[0115] As a foundational layer, the anomaly determination result clearly indicates whether the control chip under evaluation has ever deviated from its expected normal behavior during the entire testing process. It also accurately records the specific type of anomaly that occurred (such as system crashes and resets in abnormal operating states, calculation deviations in functional logic errors, frame loss timeouts in communication robustness, or voltage overshoots in electrical parameter anomalies), the specific test case conditions that triggered the anomaly, the time of occurrence, and the duration. This result is essentially a "health check report" of the chip's reliability and stability, used to determine whether it has fundamental or scenario-related defects.

[0116] As the core data layer, the performance quantification results extract and analyze key features from the response data, transforming them into one or more measurable and comparable performance indicators. These indicators directly map to the core capability boundaries of the chip in the target vehicle application scenario, such as the actual sustainable maximum computing throughput (MIPS or MFLOPS), the maximum bus load rate and bandwidth (Mbps) for error-free communication, the maximum signal sampling rate (KSPS) under the specified accuracy, and the maximum output current (A) for stable driving load. These results provide an objective and quantitative benchmark for comparing the performance of different chips.

[0117] Ultimately, the compatibility conclusion generated based on the anomaly detection results and performance quantification results serves as the comprehensive decision-making layer. The system correlates and weighs these two pieces of information: First, based on the severity and frequency of the anomaly detection, it assesses whether the control chip meets the basic functional safety and reliability standards in this vehicle application scenario; second, after confirming its stability and reliability, it judges whether its various capability indicators meet or exceed the preset requirements of this scenario based on the performance quantification results, and assesses its performance margin; finally, it generates a clear conclusive judgment, such as "fully compatible and performance redundant," "compatible but requires attention to a certain dimension of performance boundary," "basically compatible but has minor anomalies that need to be monitored," or "incompatible." This compatibility conclusion is not only a qualitative judgment, but also a direct and scientific basis for subsequent multi-chip horizontal comparisons and outputting selection recommendations.

[0118] In this step, the performance metrics include:

[0119] The actual highest computational throughput that characterizes computing power;

[0120] The error-free maximum communication bandwidth that characterizes communication capability;

[0121] The highest sampling rate that guarantees accuracy while characterizing data sampling capability;

[0122] The stable output maximum driving capability characterizes the driving capability.

[0123] Specifically, the key performance indicators defined and quantified in this evaluation system constitute the core data benchmark for objectively comparing the adaptability of control chips in target scenarios.

[0124] The actual maximum computing throughput, which characterizes computing power, refers to the maximum number of instructions or floating-point operations per second that a control chip can achieve when continuously and stably processing a specific computing model (such as control algorithms, filtering, or encryption) under simulated real vehicle load, temperature, and concurrent task conditions. This indicator reflects the actual performance of the chip in processing core computing tasks in the application scenario, rather than the theoretical peak computing power.

[0125] The error-free maximum communication bandwidth, which characterizes communication capability, refers to the limit rate at which a chip can transmit data for a long time without errors or frame loss through a specific communication interface (such as CAN FD or Ethernet) in a test that gradually increases the bus load or data rate. It directly reflects the bottleneck of the chip in reliably exchanging information in a complex network environment.

[0126] The highest sampling rate under guaranteed accuracy characterizes data sampling capability. It emphasizes the maximum sampling frequency that the chip's analog-to-digital conversion channel can achieve while meeting the conversion accuracy (such as linearity and error band) specified by the application scenario. This indicator balances speed and accuracy and is the key to evaluating the chip's sensing capability.

[0127] The stable output maximum driving capability, which characterizes the driving ability, refers to the maximum current or power that the chip's driving interface can provide without distortion or attenuation of the output signal, and the duration for which it can maintain a stable output under this limit. It directly determines the strength and reliability of the load on the chip's driven actuator. These four indicators systematically quantify the chip's capability boundaries in four core dimensions, providing accurate and comparable data support for the final compatibility conclusion.

[0128] S6. By comparing the compatibility evaluation results of multiple control chips to be evaluated, output chip selection recommendations.

[0129] Specifically, after independently testing and evaluating multiple control chips under the same target vehicle application scenario, the system enters the final decision analysis stage. This involves a horizontal and systematic comparison of the compatibility evaluation results of multiple chips, and based on this, outputting scientific and objective chip selection recommendations. This comparative analysis is not simply a listing of performance parameters, but a multi-criteria decision-making process that integrates stability, performance boundaries, cost-effectiveness, and scenario requirement compliance. The system first screens the anomaly judgment results of all chips, directly marking chips that exhibit serious or frequent functional anomalies, communication failures, or electrical parameter exceedances as "unsuitable" or "high-risk," thereby eliminating options with insufficient basic reliability from the selection pool. Subsequently, for chips that pass the stability screening, the system conducts an in-depth comparison of their performance quantification results: under the same coordinate system, the specific performance indicators of each chip in the four dimensions of computing, communication, sampling, and driving (such as actual maximum computing throughput, maximum error-free communication bandwidth, etc.) are compared with the preset performance requirement thresholds of the target application scenario, identifying which chips "fully meet" the requirements, which "have performance shortcomings," and which "have significant performance redundancy." Furthermore, the system may incorporate weighted analysis, assigning appropriate weights to performance indicators across different dimensions based on the characteristics of the target scenario (e.g., motor control prioritizes computing power and drive capabilities, while the cockpit domain prioritizes communication bandwidth), and calculating the overall performance score for each chip. Finally, considering external factors such as cost, supply, and ecosystem support (which can be preset configuration parameters), the system generates structured selection recommendations. These recommendations are typically not a single answer but rather a priority list or categorization suggestions. For example, explicitly recommending the "best performance fit" chip with the best overall performance; listing the "most cost-effective" option that meets all core requirements; and highlighting the unique advantages of certain chips in specific dimensions for reference when special needs arise. This process liberates engineers from tedious data comparisons and subjective experience-based decision-making, enabling rapid and accurate selection based on unified and comprehensive test data.

[0130] In this embodiment, the method further includes:

[0131] After completing the evaluation of the first target vehicle application scenario, the test configuration will be switched to the second target vehicle application scenario;

[0132] The test configuration includes at least the simulation model and test case set of the hardware-in-the-loop simulation unit;

[0133] Based on the second target vehicle application scenario, a new round of compatibility assessment is automatically performed.

[0134] Specifically, this method also includes a key extended process: after the system completes a full evaluation cycle for the first target vehicle application scenario (e.g., Battery Management System, BMS), it can perform a scenario switching operation to continuously and automatically evaluate the same or another control chip in a second target vehicle application scenario (e.g., the smart cockpit domain). The core of this step lies in the overall switching of the "test configuration". The "test configuration" defined here is a comprehensive set of parameters and resources, which includes at least two core components: first, a simulation model running in the hardware-in-the-loop simulation unit, which defines the dynamic behavior, sensor characteristics, actuator load, and network communication characteristics of the simulated vehicle; second, a set of test cases specifically generated for this scenario, which includes various test cases designed for the core requirements of this scenario, such as computation, communication, sampling, and driving, and their evaluation criteria.

[0135] During the switchover, the system automatically unloads or stops the simulation models and test case sets related to the first scenario from the preset resource library and loads the corresponding resources pre-configured for the second target scenario. For example, the simulation model switches from simulating a battery pack, cell voltage, and temperature sensors to simulating an in-vehicle display, touch input, audio bus, and navigation data stream; the test case set switches from cases focusing on high-precision ADC sampling and equalization logic verification to cases focusing on high-bandwidth Ethernet communication, graphics processing throughput, and multi-application concurrent scheduling. After the switchover, the system immediately initializes the test platform based on the new simulation environment and test logic without manual intervention, applies stimulus signals consistent with the new scenario to the control chip, and then starts and executes a new round of complete adaptability evaluation. This design not only greatly improves the utilization efficiency and comprehensiveness of the test system, but more importantly, it ensures that the benchmark conditions for cross-scenario testing are automatically and consistently established by the system, thus providing an objective and comparable evaluation basis for the performance of the same chip in different scenarios, or the adaptability of different chips in the same series of scenarios.

[0136] Example 2

[0137] This embodiment provides an adaptation and evaluation device for the core requirements of control chips based on vehicle application scenarios, including:

[0138] The determination module is used to determine the target vehicle application scenario for the control chip to be evaluated;

[0139] The generation module is used to generate a test case set containing multi-dimensional functional tests based on the target vehicle application scenario;

[0140] The test platform is used to execute test case sets in a test platform that simulates the operating environment of a complete vehicle in order to test the control chip to be evaluated deployed therein;

[0141] The test platform includes a hardware-in-the-loop simulation unit and a control chip test board connected to the hardware-in-the-loop simulation unit.

[0142] The hardware-in-the-loop simulation unit includes:

[0143] The signal transmission unit is used to send test stimulus signals corresponding to the test case set to the control chip test board to simulate real and comprehensive vehicle signals and loads;

[0144] The data acquisition unit is used to collect response data generated by the control chip to be evaluated during the test; and based on the response data, it performs anomaly detection and performance quantification to obtain the adaptability evaluation results of the control chip in the target vehicle application scenario.

[0145] The results output module is used to output chip selection recommendations by comparing the compatibility evaluation results of multiple control chips to be evaluated.

[0146] In this embodiment, the control chip test board adopts a structure of replaceable control chip daughter board and fixed interface mother board.

[0147] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A method for adapting and evaluating the core requirements of control chips based on whole-vehicle application scenarios, characterized in that, include: Determine the target vehicle application scenario for the control chip to be evaluated; A test case set containing multi-dimensional functional tests is generated based on the target vehicle application scenario; The test case set is executed in a test platform that simulates the operating environment of a complete vehicle to test the control chip to be evaluated deployed therein; The response data generated by the control chip to be evaluated during the test is collected. Based on the response data, anomaly detection and performance quantification are performed to obtain the adaptability evaluation results of the control chip in the target vehicle application scenario. By comparing the compatibility evaluation results of multiple control chips to be evaluated, chip selection recommendations are output. The step of generating a test case set containing multi-dimensional functional tests based on the target vehicle application scenario includes: Functional and load analysis was performed on the target vehicle application scenario to analyze its core requirements for control chips in multiple different dimensions. For each of the core requirements identified in the analysis, corresponding test cases are designed to form the test case set; the multiple different dimensions include: Computing capability dimension, communication capability dimension, data sampling capability dimension, and driving capability dimension; Functional and load analysis is performed on the target vehicle application scenario, including: Based on the identified target vehicle application scenario, the specific control function sub-items of the target vehicle application scenario are decomposed into tasks and modeled in behavior. The execution logic, data flow, real-time window and resource consumption are analyzed to systematically parse the core requirements of the target vehicle application scenario for the control chip in multiple different dimensions. Based on the aforementioned core requirements, corresponding and executable test cases are designed in a targeted manner. Each test case aims to simulate an extreme stress condition or typical working mode under the corresponding dimension. The test cases corresponding to each dimension are systematically integrated and arranged to form the test case set; Among them, the core requirements of the computing power dimension correspond to computing power requirements. The corresponding test cases include: designing test cases to assess the single-core or multi-core computing throughput of the chip under various standard computing models, and covering the effective computing power of functional safety cores and information security-related encryption and decryption performance. The core requirements of the communication capability dimension correspond to communication requirements. The corresponding test cases are designed to include: designing test cases to evaluate the real-time response, protocol processing capability and sustainable data rate of various communication interfaces integrated in the chip under actual high load. The core requirements of the data sampling capability dimension correspond to data sampling requirements. The corresponding test cases are designed as follows: test cases are designed to test the sampling rate, conversion accuracy, linearity and synchronization of the analog / digital conversion channel and digital I / O of the test chip. The core requirements of the driving capability dimension correspond to driving requirements, and the corresponding test cases are designed, including: designing test cases for output current intensity, voltage level, response speed and load stability.

2. The method for adapting and evaluating the core requirements of control chips based on vehicle application scenarios as described in claim 1, characterized in that, The test platform simulating the vehicle's operating environment is a hardware-in-the-loop test platform, which includes: Hardware-in-the-loop simulation unit, and a control chip carrier board that is signal-connected to the hardware-in-the-loop simulation unit.

3. The method for adapting and evaluating the core requirements of control chips based on vehicle application scenarios as described in claim 2, characterized in that, The control chip carrier board adopts a modular design, including replaceable chip adapter units and fixed interface and peripheral circuit units.

4. The method for adapting and evaluating the core requirements of control chips based on vehicle application scenarios as described in claim 1, characterized in that, The anomaly determination includes at least one of the following types of detection: Detection of abnormal operating status of control chip; Detection of the correctness of the functional logic of the control chip; Control chip communication robustness testing; Detection of abnormal electrical parameters of control chip.

5. The method for adapting and evaluating the core requirements of control chips based on vehicle application scenarios according to claim 1, characterized in that, The compatibility assessment results include: The anomaly determination result indicates whether the control chip under evaluation has an anomaly during the test and the type of anomaly. The performance quantification results include one or more performance indicators of the control chip to be evaluated in the target vehicle application scenario. And the compatibility conclusions generated based on the anomaly determination results and performance quantification results.

6. The method for adapting and evaluating the core requirements of control chips based on vehicle application scenarios as described in claim 5, characterized in that, The performance indicators include: The actual highest computational throughput that characterizes computing power; The error-free maximum communication bandwidth that characterizes communication capability; The highest sampling rate that guarantees accuracy while characterizing data sampling capability; The stable output maximum driving capability characterizes the driving capability.

7. A device for adapting and evaluating the core requirements of control chips based on whole-vehicle application scenarios, characterized in that, include: The determination module is used to determine the target vehicle application scenario for the control chip to be evaluated; The generation module is used to generate a test case set containing multi-dimensional functional tests based on the target vehicle application scenario. The test platform is used to execute the test case set in a test platform that simulates the operating environment of a whole vehicle in order to test the control chip to be evaluated deployed therein; The test platform includes a hardware-in-the-loop simulation unit and a control chip test board connected to the hardware-in-the-loop simulation unit. The hardware-in-the-loop simulation unit includes: The signal sending unit is used to send test stimulus signals corresponding to the test case set to the control chip test board to simulate real and comprehensive vehicle signals and loads; The data acquisition unit is used to acquire response data generated by the control chip to be evaluated during the test; and based on the response data, to perform anomaly judgment and performance quantification to obtain the adaptability evaluation result of the control chip in the target vehicle application scenario; The result output module is used to output chip selection recommendations by comparing the compatibility evaluation results of multiple control chips to be evaluated. The step of generating a test case set containing multi-dimensional functional tests based on the target vehicle application scenario includes: Functional and load analysis was performed on the target vehicle application scenario to analyze its core requirements for control chips in multiple different dimensions. For each core requirement identified in the analysis, corresponding test cases are designed to form the test case set. The multiple different dimensions include: Computing capability dimension, communication capability dimension, data sampling capability dimension, and driving capability dimension; Functional and load analysis is performed on the target vehicle application scenario, including: Based on the identified target vehicle application scenario, the specific control function sub-items of the target vehicle application scenario are decomposed into tasks and modeled in behavior. The execution logic, data flow, real-time window and resource consumption are analyzed to systematically parse the core requirements of the target vehicle application scenario for the control chip in multiple different dimensions. Based on the aforementioned core requirements, corresponding and executable test cases are designed in a targeted manner. Each test case aims to simulate an extreme stress condition or typical working mode under the corresponding dimension. The test cases corresponding to each dimension are systematically integrated and arranged to form the test case set; Among them, the core requirements of the computing power dimension correspond to computing power requirements. The corresponding test cases include: designing test cases to assess the single-core or multi-core computing throughput of the chip under various standard computing models, and covering the effective computing power of functional safety cores and information security-related encryption and decryption performance. The core requirements of the communication capability dimension correspond to communication requirements. The corresponding test cases are designed to include: designing test cases to evaluate the real-time response, protocol processing capability and sustainable data rate of various communication interfaces integrated in the chip under actual high load. The core requirements of the data sampling capability dimension correspond to data sampling requirements. The corresponding test cases are designed as follows: test cases are designed to test the sampling rate, conversion accuracy, linearity and synchronization of the analog / digital conversion channel and digital I / O of the test chip. The core requirements of the driving capability dimension correspond to driving requirements, and the corresponding test cases are designed, including: designing test cases for output current intensity, voltage level, response speed and load stability.

8. The adaptation and evaluation device for the core requirements of control chips based on vehicle application scenarios as described in claim 7, characterized in that, The control chip test board adopts a structure of replaceable control chip daughterboard and fixed interface motherboard.

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