Driver circuit and chip

Abstract

The invention provides a driver circuit and a chip, and relates to the technical field of integrated circuits, and the driver circuit comprises a power tube, a booster circuit, a ripple suppression circuit and a gate drive circuit. A first electrode of the power tube is used for coupling a power supply, and a second electrode of the power tube is used for coupling a load; the booster circuit is coupled with the power supply and is configured to boost a power supply voltage provided by the power supply to a boosted voltage; the ripple suppression circuit is coupled to the boost circuit, and the ripple suppression circuit is configured to perform ripple suppression processing on the boost voltage to obtain a gate turn-on voltage; the gate drive circuit is coupled to the ripple suppression circuit and the control electrode of the power tube, and the gate drive circuit is configured to provide a drive current to the control electrode of the power tube based on the gate turn-on voltage to reach the gate turn-on voltage when the conduction control signal is in the effective level signal period. The problem that the electromagnetic compatibility of the driver circuit is poor is solved.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, specifically to a driver circuit and chip. Background Technology

[0002] Driver circuits can be applied to scenarios such as, but not limited to, high-side drivers and motor drivers. They are primarily used to control power transistors located on the power supply side, and their operating principle is mainly based on power electronic switching technology to control the load. For example, when the driver circuit receives a turn-on control signal, it controls the switching on and off of the power transistor and limits the output current according to the high or low level of the turn-on control signal, thereby achieving the driving and control of the load. However, driver circuits in related technologies often exhibit poor electromagnetic compatibility. Summary of the Invention

[0003] The main purpose of this disclosure is to provide a driver circuit and chip to solve the problem of poor electromagnetic compatibility of driver circuits.

[0004] To achieve the above objectives, a first aspect of this disclosure provides a driver circuit comprising: a power transistor, a boost circuit, a ripple suppression circuit, and a gate drive circuit; wherein a first terminal of the power transistor is coupled to a power supply, and a second terminal of the power transistor is coupled to a load; the boost circuit is coupled to the power supply and configured to boost the power supply voltage provided by the power supply to a boost voltage; the ripple suppression circuit is coupled to the boost circuit and configured to perform ripple suppression processing on the boost voltage to obtain a gate turn-on voltage; the gate drive circuit is coupled to the ripple suppression circuit and the control terminal of the power transistor and configured to: during the period when the turn-on control signal is at an active level, provide a drive current to the control terminal of the power transistor based on the gate turn-on voltage to achieve the gate turn-on voltage.

[0005] In some embodiments of this disclosure, the ripple suppression circuit includes at least one of an LDO circuit and a source follower.

[0006] In some embodiments of this disclosure, the ripple suppression circuit includes a source follower and an LDO circuit, wherein the drain of the source follower is coupled to the output of the boost circuit, the source of the source follower is coupled to the input of the LDO circuit, the gate of the source follower is coupled to a reference voltage node, and the output of the LDO circuit is coupled to a gate drive circuit.

[0007] In some embodiments of this disclosure, the driver circuit further includes an RC parallel circuit, the first end of which is coupled to the output of the boost circuit, and the second end of which is coupled to a power supply, a ground terminal, or the second terminal of a power transistor, to form a reference voltage node at the first end of the RC parallel circuit.

[0008] In some embodiments of this disclosure, the power supply is also configured to supply power to other chips, wherein a first end of the load is coupled to the second terminal of the power transistor, and a second end of the load is coupled to ground; a first end of the other chip is coupled to the power supply, and a second end of the other chip is coupled to ground.

[0009] In some embodiments of this disclosure, the power transistor includes an NMOS transistor, with the first terminal and the second terminal being the source and drain of the NMOS transistor, respectively, and the control terminal being the gate of the NMOS transistor.

[0010] In some embodiments of this disclosure, the boost circuit includes a charge pump, the input of which is coupled to a power supply, and the output of which is coupled to a ripple suppression circuit; wherein the charge pump is a charge pump with a fixed operating frequency, or a charge pump with a dithering operating frequency.

[0011] In some embodiments of this disclosure, the gate drive circuit includes a control signal terminal, a drive voltage terminal, and a drive output terminal, wherein the control signal terminal is used to receive a turn-on control signal, the drive voltage terminal is coupled to a ripple suppression circuit, and the drive output terminal is coupled to the control electrode of the power transistor.

[0012] A second aspect of this disclosure provides a driver circuit comprising: a power transistor, a charge pump, a source follower, an LDO circuit, and a gate drive circuit. The power transistor has a first terminal coupled to a power supply and a second terminal coupled to a load. The power supply is also configured to power other chips. The input of the charge pump is coupled to the power supply and configured to boost the power supply voltage to a boost voltage. The drain of the source follower is coupled to the output of the charge pump, the gate of the source follower is coupled to a reference voltage node, and the source of the source follower is coupled to the input of the LDO circuit to output a gate turn-on voltage at the output of the LDO circuit. The gate drive circuit includes a control signal terminal, a drive voltage terminal, and a drive output terminal. The control signal terminal receives a turn-on control signal, the drive voltage terminal is coupled to the output of the LDO circuit, and the drive output terminal is coupled to the control electrode of the power transistor. The gate drive circuit is configured to provide a drive current to the control electrode of the power transistor based on the gate turn-on voltage to achieve the gate turn-on voltage while the turn-on control signal is at a valid level.

[0013] A third aspect of this disclosure provides a chip that includes driver circuitry according to a first or second aspect of this disclosure.

[0014] A fourth aspect of this disclosure provides an electronic device that includes a chip according to a third aspect of this disclosure.

[0015] In the driver circuit and chip provided in the embodiments of this disclosure, a ripple suppression circuit is added between the boost circuit and the gate drive circuit. The ripple suppression circuit performs ripple suppression processing on the boost voltage to obtain the gate turn-on voltage, thereby reducing the ripple noise on the boost voltage output from the boost circuit from being conducted to the power supply. This improves the technical problem of poor electromagnetic compatibility of the driver circuit caused by the ripple noise on the boost voltage being conducted to the power supply. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is an exemplary circuit diagram of a driver circuit in the related art; Figure 2 In response to Figure 1 A schematic diagram of ripple conduction during charge pump operation in a driver circuit; Figure 3 An exemplary circuit diagram of a driver circuit provided for embodiments of this disclosure; Figure 4 An exemplary circuit diagram of another driver circuit provided for embodiments of this disclosure; Figure 5 An exemplary circuit diagram of another driver circuit provided for embodiments of this disclosure; Figure 6 A schematic diagram of ripple conduction during charge pump operation in another driver circuit provided in this embodiment of the present disclosure; Figure 7 A schematic diagram of the circuit topology of a ripple suppression circuit provided in an embodiment of this disclosure; Figure 8 An exemplary circuit diagram of another driver circuit provided for embodiments of this disclosure.

[0018] It should be noted that the elements in the attached diagram are schematic and not drawn to scale. Detailed Implementation

[0019] To enable those skilled in the art to better understand the present disclosure, the technical solutions of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present disclosure, and not all embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present disclosure.

[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0021] In this disclosure, the terms "upper," "middle," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily used to better describe this disclosure and its embodiments, and are not intended to limit the indicated devices, elements, or components to having a particular orientation, or to be constructed and operated in a particular orientation.

[0022] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0023] In all embodiments of this disclosure, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the other two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. Furthermore, for the sake of consistency, in this context, the base of a bipolar junction transistor (BJT) is referred to as the control terminal, the emitter of the BJT is referred to as the first terminal, and the collector of the BJT is referred to as the second terminal.

[0024] It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0025] Figure 1 An exemplary circuit diagram of a driver circuit 100 in the related art is shown. VS represents the power supply and / or the power supply voltage provided by the power supply, typically serving as the highest input voltage of the entire chip where the driver circuit 100 resides. Power transistor ( Figure 1 In the PWR MOS, the first terminal of power transistor 102 is coupled to power supply VS, the second terminal of power transistor 102 is coupled to the first terminal of load 103, and the second terminal of load 103 is coupled to ground terminal GND. Thus, by turning power transistor 102 on and off, power supply VS is controlled to supply power to load 103 or to stop supplying power. Figure 1 The power transistor 102 is an NMOS (N-type Metal Oxide Semiconductor) transistor. The first and second terminals of the power transistor 102 are the drain and source of the NMOS transistor, respectively, and the gate of the power transistor 102 is the gate of the NMOS transistor.

[0026] Figure 1 In this context, CP (Charge Pump) represents charge pump 104, which is responsible for generating a boost voltage Vcp higher than the power supply voltage VS. In other words, charge pump 104 is used to boost the power supply voltage VS to the boost voltage Vcp. DRV (Driver) represents the gate drive circuit 106 of power transistor 102. The gate drive circuit 106 is coupled between charge pump 104 and the control electrode of power transistor 102. The gate drive circuit 106 controls the turn-on and turn-off of power transistor 102 according to the turn-on control signal Ctrl. When the turn-on control signal Ctrl is active, power transistor 102 is turned on, and the gate drive circuit 106 drives the gate voltage of power transistor 102 to reach the gate turn-on voltage Vg. At this time, power transistor 102 is fully turned on, and power supply VS supplies power to load 103 through power transistor 102.

[0027] Figure 2 Showing targets Figure 1 A schematic diagram of ripple conduction during the operation of charge pump 104 in driver circuit 100 is shown below. Figure 2The red wavy lines in the diagram represent voltage ripple at various locations. The inventors of this disclosure have discovered a new technical problem: when the charge pump 104 is operating, there is ripple on its output boost voltage Vcp. When the power transistor 102 is turned on, the gate voltage of the power transistor 102 equals the boost voltage Vcp output by the charge pump 104. At this time, the ripple on the charge pump 104 is transmitted to the gate of the power transistor 102, and then through the power transistor 102 to the output terminal of the load 103. Finally, it is transmitted through the channel of the power transistor 102 to the power supply VS of the chip, ultimately causing electromagnetic compatibility (EMC) interference to other chips (Device A in the figure) powered by the same power supply VS, resulting in poor EMC of the driver circuit 100. Related technologies mainly improve the poor EMC problem of the driver circuit 100 by employing clock jitter technology in the charge pump 104. This disclosure provides another way to improve poor EMC, achieving essentially the same technical effect.

[0028] Example 1 To address the aforementioned issues, this disclosure provides a driver circuit designed to improve the electromagnetic compatibility of the driver circuit. Figure 3 A schematic block diagram of a driver circuit 300 according to an embodiment of the present disclosure is shown. Figure 3 As shown, the driver circuit 300 includes: a power transistor 302, a boost circuit 304, a ripple suppression circuit 305, and a gate drive circuit 306. The first terminal of the power transistor 302 is connected to node B, which is a lead from the power supply 301, thus coupling the power supply 301. The second terminal of the power transistor 302 is used to couple the load 303. By turning the power transistor 302 on and off, the power supply 301 can be controlled to supply power to or stop supplying power to the load 303.

[0029] Continue to refer to Figure 3The maximum output voltage of power supply 301 is VS, which is less than the gate turn-on voltage Vg of power transistor 302. Boost circuit 304 is coupled to node B, thereby boosting the power supply voltage VS provided by power supply 301 to a boost voltage Vcp. As described in the foregoing related technical description, the boost voltage Vcp obtained after boosting by boost circuit 304 has a relatively large ripple. This disclosure couples a ripple suppression circuit 305 between boost circuit 304 and gate drive circuit 306. Utilizing the power supply noise suppression characteristics of ripple suppression circuit 305, ripple suppression circuit 305 is configured to suppress the ripple of boost voltage Vcp to obtain gate turn-on voltage Vg, thereby reducing the ripple amplitude on the gate turn-on voltage Vg input to gate drive circuit 306, achieving the purpose of reducing the ripple noise on the boost voltage Vcp output from boost circuit 304. Specifically, the boost voltage Vcp output by the boost circuit 304 is higher than the gate turn-on voltage Vg. The ripple suppression circuit 305 has at least two functions: one is to stabilize the boost voltage Vcp to the gate turn-on voltage Vg, and the other is that the ripple on the gate turn-on voltage Vg is greatly suppressed compared to the boost voltage Vcp.

[0030] like Figure 3 In this circuit, the gate drive circuit 306 is coupled to the ripple suppression circuit 305 and the control electrode G1 of the power transistor 302. The gate drive circuit 306 is configured to provide a drive current to the control electrode G1 of the power transistor 302 based on the ripple-suppressed gate turn-on voltage Vg during the period when the turn-on control signal Ctrl is at an active level, thereby achieving the gate turn-on voltage Vg and turning on the power transistor 302. Since the gate drive circuit 306 provides a drive current to the control electrode G1 of the power transistor 302 based on the ripple-suppressed gate turn-on voltage Vg, it can suppress the high-frequency ripple noise transmitted from the boost voltage Vcp signal output from the boost circuit 304 to the control electrode G1 of the power transistor 302, thereby improving the purpose of ripple noise on the boost voltage Vcp being conducted to the control electrode G1 of the power transistor 302, and thus greatly improving the ripple noise transmitted from the boost voltage Vcp to the power supply 301 through the power transistor 302. When power supply 301 is also configured to supply power to other chips, since the ripple noise on the boost voltage Vcp of driver circuit 300 is not transmitted to power supply 301, it does not affect the normal power supply of power supply 301 to other chips. This achieves the technical effect of improving the overall electromagnetic compatibility of driver circuit 300, and further improves the technical problem of poor electromagnetic compatibility of driver circuit 300 caused by the ripple noise on the boost voltage Vcp output by boost circuit 304 being conducted to power supply 301.

[0031] The following combination Figures 3 to 7 The driver circuit 300 is described in detail, wherein, Figure 4 Compared to Figure 3 The main difference lies in the detailed description of the ripple suppression circuit 305. Figure 5 Compared to Figure 3 The main difference lies in the addition of relevant descriptions for other chips, such as the 307. Figure 6 Compared to Figure 3 The main difference lies in providing specific application examples for components such as the boost circuit 304, ripple suppression circuit 305, gate drive circuit 306, and power transistor 302. Figure 7 A schematic diagram of the circuit topology for a ripple suppression circuit 305 is shown. It should be understood that the attached diagram... Figures 3 to 7 This description is for informational purposes only and is not intended to limit the scope of protection for driver circuit 300.

[0032] The ripple suppression circuit 305 can be implemented in various ways, some of which are illustrated below. For example, refer to... Figure 4 The ripple suppression circuit 305 may include at least one of an LDO (Low Dropout regulator) circuit and a source follower 3051. Specifically, the ripple suppression circuit 305 may include only an LDO circuit 3052 or a source follower 3051, or it may include both an LDO circuit 3052 and a source follower 3051. Since the LDO circuit 3052 and the source follower 3051 have power supply suppression characteristics, the ripple suppression effect of the ripple suppression circuit 305 can be improved by utilizing the advantages of the LDO circuit 3052 and the source follower 3051, which have good ripple suppression effect and simple structure and are easy to obtain, thereby improving electromagnetic compatibility.

[0033] When the ripple suppression circuit 305 includes a source follower 3051 and an LDO circuit 3052, the specific coupling method of the ripple suppression circuit 305 can be varied, as exemplarily shown below. (Exemplary examples are provided below.) Figure 4 The drain D2 of the source follower 3051 is coupled to the output of the boost circuit 304, the source S2 of the source follower 3051 is coupled to the input of the LDO circuit 3052, the gate G2 of the source follower 3051 is coupled to the reference voltage node Vref, and the output of the LDO circuit 3052 is coupled to the gate drive circuit 306. That is, the source follower 3051 acts as a primary ripple suppression structure, and the LDO circuit 3052 acts as a secondary ripple suppression structure, thus forming a two-stage ripple suppression structure (e.g., ...). Figure 6In this context, "High PSR LDO" refers to a ripple suppression circuit 305 with high bandwidth and high PSR characteristics. This structure features high bandwidth and high PSR characteristics, enabling faster response to sudden changes in load 303 when power transistor 302 is turned on. This reduces output voltage fluctuations caused by sudden changes in load 303 at the moment power transistor 302 turns on. Furthermore, the high PSR characteristics significantly suppress voltage ripple on the boost circuit 304 after power transistor 302 is turned on. It should be noted that the ripple of the boost voltage Vcp in this disclosure includes at least the voltage ripple output from the boost circuit 304 itself after boosting, as well as the voltage jumps caused by pull-down sudden changes and pull-up recovery of the boost voltage Vcp at the moment power transistor 302 turns on due to sudden changes in load 303.

[0034] and Figure 2 Compared to the driver circuit 100 in the related art shown, such as Figure 6 The driver circuit 300 shown in this embodiment of the present disclosure is as follows: Figure 6 The red wavy lines in the diagram represent the voltage ripple at various locations. Because a high PSR LDO circuit (ripple suppression circuit 305) is set between the charge pump 3041 and the gate drive circuit 306, the ripple on the gate turn-on voltage Vg output by the ripple suppression circuit 305 is significantly smaller than the ripple on the boost voltage Vcp. This greatly improves the ripple on the boost voltage Vcp that is transmitted to the system power supply VS through the power transistor 302, thereby improving the EMC interference problem caused to other chips 307 powered by this power supply VS and enhancing the overall EMC characteristics of the driver circuit 300.

[0035] Regarding the configuration of the source follower 3051, there are several methods, some of which are illustrated below. For example, refer to... Figure 7 The source follower 3051 may include an NMOS transistor, and may also include other components besides an NMOS transistor. The source S2, gate G2, and drain D2 of the NMOS transistor serve as the source S2, gate G2, and drain D2 of the source follower 3051, respectively.

[0036] There are several ways to set the reference voltage node Vref. Some methods are illustrated below. In the following embodiments, the voltage value of the reference voltage node Vref is greater than the power supply voltage VS, thereby increasing the conduction degree of the NMOS transistor in the source follower 3051, reducing the on-resistance of the NMOS transistor in the source follower 3051, and thus reducing its voltage drop.

[0037] For example, refer to Figure 7The driver circuit may also include an RC parallel circuit 308, the first terminal of which is coupled to the output terminal of the boost circuit 304, and the second terminal of which is coupled to the power supply VS, the ground terminal GND, or the second terminal of the power transistor 302 (e.g., Figures 3 to 7 The output voltage of the second terminal of the medium-power transistor 302 is Vout), so as to form a reference voltage node Vref at the first terminal of the RC parallel circuit 308. That is, the first terminal of the RC parallel circuit 308 is also coupled to the gate G2 of the source follower 3051. There are various ways to configure the RC parallel circuit 308. For example, refer to... Figure 7 The RC parallel circuit 308 may include a resistor R and a capacitor C connected in parallel. The first end of resistor R and the first end of capacitor C are coupled together to form the first terminal of the RC parallel circuit 308, and the second end of resistor R and the second end of capacitor C are coupled together to form the second terminal of the RC parallel circuit 308. In this manner, by utilizing the boost voltage Vcp and leveraging the filtering and voltage regulation characteristics of the RC parallel circuit 308, a stable reference voltage node Vref is provided to the gate G2 of the source follower 3051, eliminating the need for an additional reference voltage power supply. Of course, in other embodiments, the reference voltage node Vref can also be configured in other ways.

[0038] It should be understood that the coupling method of the source follower 3051 and the LDO circuit 3052 is not limited to the method shown above. Other methods may also be used.

[0039] For example, the chip to which the driver circuit 300 is located or coupled can be applied to any scenario that requires driving a high-side power transistor. For instance, it can be applied to scenarios such as, but not limited to, high-side drivers and motor drives.

[0040] For example, when the driver circuit 300 is applied to a high-side driver, the high-side driver can be set in the driver chip of the bridge arm switch, and the driver circuit 300 of this disclosure can be used as a high-side driver circuit. The application scenarios of the bridge arm switch can be applied to various scenarios such as, but not limited to, DC-DC converters, PFC (Power Factor Correction) circuits, AC-DC converters, etc.

[0041] For example, the load 303 of this disclosure can be any type of electrical device. For instance, the load 303 can include various electronic devices such as, but not limited to, drive motors, air conditioning compressors, and vehicle fans, and can be applied to scenarios such as motor drives that require driving high-side power transistors.

[0042] For example, refer to Figure 5The power supply 301 is also configured to power other chips 307; that is, the power supply 301 is not limited to powering the chip containing the driver circuit 300 of this disclosure, but is also used to power other chips 307. For example... Figure 6 In this context, Device A represents another chip 307. This other chip 307 can be any type of chip, for example, another driver chip, or a processor chip, memory chip, etc., in electronic devices such as, but not limited to, vehicle terminals. Powering multiple different chips through the same power supply 301 reduces the number of power supplies 301, thereby reducing costs; and because the driver circuit 300 of this disclosure has good electromagnetic compatibility, it will not transmit a large amount of ripple noise to the power supply 301, thus not affecting the normal operation of other chips 307 coupled to the same power supply 301.

[0043] When power supply 301 also supplies power to other chips 307, the coupling method between power supply 301, load 303 and other chips 307 can be adopted in various ways. Some methods are illustrated below.

[0044] For example, refer to Figure 5 The first terminal of load 303 is coupled to the second terminal of power transistor 302, and the second terminal of load 303 is coupled to ground GND. The first terminal of other chip 307 is coupled to power supply 301, and the second terminal of other chip 307 is coupled to ground GND. By connecting load 303 and other chips 307 in parallel between power supply 301 and ground GND, both can operate normally without interference. It should be noted that the ground GND to which load 303 is coupled and the ground GND to which other chips 307 are coupled can be the same ground GND or different ground GNDs.

[0045] Regarding the power transistor 302 of this disclosure, it can be any type of transistor such as, but not limited to, NMOS transistors, IGBTs, bipolar transistors, etc., as the power transistor 302. For example, refer to... Figure 6 The power transistor 302 may include an NMOS transistor. In this case, the first and second terminals of the power transistor 302 can be the source and drain of the NMOS transistor, respectively, and the control terminal G1 can be the gate of the NMOS transistor. Figure 6 For example, the first electrode of power transistor 302 is the drain of the NMOS transistor, and the second electrode of power transistor 302 is the source of the NMOS transistor.

[0046] When configuring the boost circuit 304, any circuit capable of performing DC-DC boost functionality can be used. Some examples are described below. For example, refer to... Figure 6The boost circuit 304 may include a charge pump 3041, the input of which is coupled to a power supply 301, and the output of which is coupled to a ripple suppression circuit 305. Regarding the circuit topology of the charge pump 3041, a charge pump circuit composed of components such as, but not limited to, transistors and capacitors can be used. By employing the charge pump 3041 as the boost circuit 304 of this disclosure, the advantages of the charge pump 3041's high efficiency and low cost can be utilized to reduce the number of components and cost.

[0047] Depending on the control strategy adopted for the operating frequency, the charge pump 3041 can be divided into a charge pump 3041 with a fixed operating frequency and a charge pump 3041 with a frequency dithering technique. The charge pump 3041 in this embodiment can be either of the above two types, thereby improving the compatibility of the components in the driver circuit 300 of this disclosure.

[0048] The gate drive circuit 306 can be configured in various ways. For example, refer to... Figure 3 The gate drive circuit 306 may include a control signal terminal P1, a drive voltage terminal P2, and a drive output terminal P3. The control signal terminal P1 receives the turn-on control signal Ctrl, which can be received by coupling it to a control unit. For the power transistor 302, the turn-on control signal Ctrl may include a valid level signal controlling the power transistor 302 to turn on and an invalid level signal controlling the power transistor 302 to turn off. The valid and invalid level signals can form a PWM control signal, where the valid and invalid level signals can be high and low level signals, respectively. For example, the valid level signal can be high and the invalid level signal can be low, or vice versa.

[0049] The drive voltage terminal P2 is coupled to the ripple suppression circuit 305, meaning that the drive voltage terminal P2 is coupled to the output terminal of the ripple suppression circuit 305, thereby receiving the gate turn-on voltage Vg signal after ripple suppression processing by the ripple suppression circuit 305. The drive output terminal P3 is coupled to the control electrode G1 of the power transistor 302; for example, the drive output terminal P3 is coupled to the gate of the NMOS transistor 302. Thus, when the turn-on control signal Ctrl is at an active level, the gate drive circuit 306 can provide a drive current to the control electrode G1 of the power transistor 302 based on the gate turn-on voltage Vg output by the LDO circuit 3052, so that the gate voltage of the power transistor 302 reaches the gate turn-on voltage Vg, thereby turning on the power transistor 302.

[0050] By setting up a gate drive circuit 306 that includes at least a control signal terminal P1, a drive voltage terminal P2, and a drive output terminal P3, and by adopting the above-described manner, the gate drive circuit 306 can easily receive the turn-on control signal Ctrl and the gate turn-on voltage Vg, and control the drive circuit for turning on and off the power transistor 302 based on the two signals it receives.

[0051] Regarding the internal circuit topology of the gate drive circuit 306, it can be composed of any components such as, but not limited to, amplifiers and transistors, and can control the power transistor 302 to turn on and off based on the turn-on control signal Ctrl and the gate turn-on voltage Vg.

[0052] It should be understood that the driver circuit 300 of this disclosure may include other components in addition to the components shown above, and these components are all within the protection scope of the driver circuit 300 of this disclosure.

[0053] Example 2 Another driver circuit 300 is provided in this disclosure embodiment, referenced to Figure 8 The driver circuit 300 may include: a power transistor 302, a charge pump 3041, a source follower 3051, an LDO circuit 3052, and a gate drive circuit 306. The first terminal of the power transistor 302 is coupled to a power supply 301, and the second terminal of the power transistor 302 is coupled to a load 303. The power supply 301 is also configured to power other chips 307. The input terminal of the charge pump 3041 is coupled to the power supply 301, and the charge pump 3041 is configured to boost the power supply voltage VS provided by the power supply 301 to a boost voltage Vcp. The drain D2 of the source follower 3051 is coupled to the output terminal of the charge pump 3041, and the gate G2 of the source follower 3051 is coupled to a reference voltage node Vref. The source S2 of transistor 51 is coupled to the input terminal of LDO circuit 3052 to output a gate turn-on voltage Vg at the output terminal of LDO circuit 3052. Gate drive circuit 306 includes a control signal terminal P1, a drive voltage terminal P2, and a drive output terminal P3. Control signal terminal P1 receives the turn-on control signal Ctrl, drive voltage terminal P2 is coupled to the output terminal of LDO circuit 3052, and drive output terminal P3 is coupled to the control electrode G1 of power transistor 302. Gate drive circuit 306 is configured to provide a drive current to the control electrode G1 of power transistor 302 based on the gate turn-on voltage Vg output by LDO circuit 3052 during the period when the turn-on control signal Ctrl is at a valid level, thereby achieving the gate turn-on voltage Vg. The arrangement of each component in driver circuit 300 in this embodiment can be referred to the corresponding description in Embodiment 1, and will not be repeated here.

[0054] Example 3 This disclosure provides a chip that includes a driver circuit as shown in Embodiment 1 or Embodiment 2. This chip is, for example, a driver chip that requires precise control or protection of a load.

[0055] Example 4 This disclosure provides an electronic device that includes the chip shown in Embodiment 3. This electronic device may be, for example, an industrial control device, a motor drive device, or an automotive electronic device.

[0056] As can be seen from the above description, this disclosure achieves the following technical effects: by adding a high-bandwidth, high-PSR ripple suppression circuit between the boost circuit and the gate drive circuit, and based on the charge pump using fixed frequency or frequency dithering technology in the boost circuit, the ripple noise conducted from the charge pump output to the power supply supplying this chip is further reduced, thereby improving the electromagnetic compatibility performance of the chip.

[0057] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0058] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this disclosure may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0059] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims. Although embodiments of this disclosure have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this disclosure, and all such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A driver circuit, characterized by, The power tube has a first pole for coupling a power supply and a second pole for coupling a load. A boost circuit coupled to the power supply and configured to boost a supply voltage provided by the power supply to a boosted voltage. A ripple suppression circuit coupled to the boost circuit and configured to perform a ripple suppression process on the boosted voltage to obtain a gate-on voltage. A gate drive circuit coupled to the ripple suppression circuit and coupled to a control pole of the power tube, the gate drive circuit configured to provide a drive current to the control pole of the power tube based on the gate-on voltage during a period when an on control signal is at an active level signal. The ripple suppression circuit includes at least one of a source follower and an LDO circuit. The ripple suppression circuit includes a source follower and an LDO circuit, wherein 2. The driver circuit of claim 1, wherein, a drain of the source follower is coupled to an output of the boost circuit, a source of the source follower is coupled to an input of the LDO circuit, a gate of the source follower is coupled to a reference voltage node, and an output of the LDO circuit is coupled to the gate drive circuit.

3. The driver circuit of claim 2, wherein, Further comprising: an RC parallel circuit having a first end coupled to an output of the boost circuit and a second end coupled to the power supply, a ground terminal, or a second pole of the power tube to form the reference voltage node at the first end of the RC parallel circuit.

4. The driver circuit of claim 3, wherein, The power supply is further configured to supply power to other chips, wherein a first end of the load is coupled to the second pole of the power tube, and a second end of the load is coupled to the ground terminal; a first end of the other chips is coupled to the power supply, and a second end of the other chips is coupled to the ground terminal.

5. The driver circuit of claim 1, wherein, The power tube includes an NMOS tube, the first pole and the second pole are respectively a source and a drain of the NMOS tube, and the control pole is a gate of the NMOS tube. The boost circuit includes a charge pump having an input coupled to the power supply and an output coupled to the ripple suppression circuit.

6. The driver circuit of claim 1, wherein, The charge pump is a charge pump with a fixed frequency of working frequency, or the charge pump is a charge pump with a frequency jittering technique of working frequency.

7. The driver circuit of claim 1, wherein, The gate drive circuit includes a control signal end for receiving the on control signal, a drive voltage end coupled to the ripple suppression circuit, and a drive output end coupled to the control pole of the power tube. The power tube has a first pole for coupling a power supply and a second pole for coupling a load, and the power supply is further configured to supply power to other chips.

8. The driver circuit of claim 1, wherein, A charge pump having an input coupled to the power supply and configured to boost a supply voltage provided by the power supply to a boosted voltage.

9. A driver circuit, characterized by ​ ​ ​ a source follower and an LDO circuit, a drain of the source follower is coupled to an output of the charge pump, a gate of the source follower is coupled to a reference voltage node, a source of the source follower is coupled to an input of the LDO circuit to output a gate-on voltage at an output of the LDO circuit; and, a gate drive circuit, the gate drive circuit comprises a control signal terminal, a drive voltage terminal and a drive output terminal, wherein the control signal terminal is configured to receive a turn-on control signal, the drive voltage terminal is coupled to the output of the LDO circuit, and the drive output terminal is coupled to a control electrode of the power transistor; the gate drive circuit is configured to provide a drive current to the control electrode of the power transistor based on the gate-on voltage to reach the gate-on voltage during the turn-on control signal is at an active level signal.

10. A chip, characterized by the chip comprises the driver circuit according to any one of claims 1 to 9.

Images