Time sequence control method of analog-to-digital converter, analog-to-digital converter and chip

Abstract

The invention provides a sequential control method of an analog-to-digital converter, the analog-to-digital converter and a chip, and relates to the technical field of integrated circuits. The method comprises the following steps: firstly, sampling an input signal to obtain a first sampling signal, then quantizing to generate a first residual signal, and finally amplifying and outputting the residual signal as a first amplification signal. And the second-stage circuit synchronously performs similar processing: while sampling the first amplified signal, amplifying a second residual signal generated by self quantization, and finally outputting a second amplified signal. The amplification stage of the first stage is partially overlapped with the sampling working stage and the amplification stage of the second stage, and the duty ratio corresponding to the amplification working stage of the first-stage amplification circuit is greater than a duty ratio threshold value. The objective of the invention is to improve the problem that the data processing speed of an existing assembly line ADC cannot be further improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a timing control method for an analog-to-digital converter, an analog-to-digital converter, and a chip. Background Technology

[0002] With the continuous development of technology, the application of digital signal processing technology is becoming increasingly widespread. As a key component connecting analog signals and digital processing systems, the performance requirements for analog-to-digital converters (ADCs) are also becoming increasingly stringent. Pipeline ADCs are widely used due to their simple structure and fast response.

[0003] However, pipelined ADCs are limited by amplifier settling time, which prevents further improvements in their data processing speed. Summary of the Invention

[0004] The embodiments disclosed in this application provide a timing control method for an analog-to-digital converter, an analog-to-digital converter, and a chip. The embodiments of this application adopt the following technical solutions: A first aspect provides a timing control method for an analog-to-digital converter (ADC). The method includes: sampling an input signal during a sampling phase of a first-stage amplifier circuit to obtain a first sampled signal; quantizing the first sampled signal during a quantization phase of the first-stage amplifier circuit to obtain a first residual signal; amplifying the first residual signal during an amplification phase of the first-stage amplifier circuit to obtain a first amplified signal; sampling the first amplified signal during a sampling phase of a second-stage amplifier circuit to obtain a second sampled signal; quantizing the second sampled signal during a quantization phase of the second-stage amplifier circuit to obtain a second residual signal; amplifying the second residual signal during an amplification phase of the second-stage amplifier circuit to obtain and output the second amplified signal. The amplification phase of the first-stage amplifier circuit partially overlaps with the sampling phase of the second-stage amplifier circuit, and the duty cycle corresponding to the amplification phase of the first-stage amplifier circuit is greater than a duty cycle threshold.

[0005] The timing control method for an analog-to-digital converter (ADC) provided in this application achieves parallel operation of the two amplifier stages by advancing the amplification phase of the first-stage amplifier circuit and partially overlapping it with the sampling and amplification phase of the second-stage amplifier circuit. This increases the overall conversion rate without adding extra duty cycles, thereby improving the system's conversion performance. Optimizing the timing arrangement effectively improves the ADC's conversion speed and data processing efficiency.

[0006] In one possible implementation of the first aspect, the amplification operation stage of the first-stage amplifier circuit includes a pre-amplifier sub-operation stage and a main amplifier sub-operation stage, with the pre-amplifier sub-operation stage preceding the main amplifier sub-operation stage.

[0007] The timing control method for an analog-to-digital converter provided in this application adds a pre-amplification sub-stage and advances it before the main amplification sub-stage, enabling the first-stage amplifier to operate in parallel with the second-stage amplifier during the pre-amplification stage. Furthermore, the first-stage amplifier gains a longer time margin during signal setup, improving signal amplification quality, reducing noise and distortion, and enhancing the overall accuracy and stability of the analog-to-digital converter.

[0008] In one possible implementation of the first aspect, the main amplifier operating phase completely overlaps with the sampling operating phase of the second-stage amplifier circuit.

[0009] In one possible implementation of the first aspect, the pre-amplification sub-operation phase of the first-stage amplifier circuit partially overlaps with the amplification operation phase of the second-stage amplifier circuit.

[0010] In one possible implementation of the first aspect, during the pre-amplifier operation phase, the amplifier input load of the first-stage amplifier circuit includes the quantizer capacitor of the second-stage amplifier circuit and the amplifier capacitor of the first-stage amplifier circuit; during the main amplifier operation phase, the amplifier input load of the first-stage amplifier circuit includes the quantizer capacitor of the second-stage amplifier circuit, the amplifier capacitor of the first-stage amplifier circuit, and the sampler capacitor of the second-stage amplifier circuit.

[0011] Secondly, an analog-to-digital converter (ADC) is provided. The ADC includes a cascaded first-stage amplifier circuit and a second-stage amplifier circuit. The timing signal input terminals of the first-stage amplifier circuit and the second-stage amplifier circuit are coupled to a timing control circuit. The ADC is configured to: sample the input signal during the sampling operation phase of the first-stage amplifier circuit to obtain a first sampled signal; quantize the first sampled signal during the quantization operation phase of the first-stage amplifier circuit to obtain a first residual signal; amplify the first residual signal during the amplification operation phase of the first-stage amplifier circuit to obtain a first amplified signal; sample the first amplified signal during the sampling operation phase of the second-stage amplifier circuit to obtain a second sampled signal; quantize the second sampled signal during the quantization operation phase of the second-stage amplifier circuit to obtain a second residual signal; amplify the second residual signal during the amplification operation phase of the second-stage amplifier circuit to obtain and output a second amplified signal. The amplification operation phase of the first-stage amplifier circuit and the sampling operation phase of the second-stage amplifier circuit partially overlap, and the duty cycle corresponding to the amplification operation phase of the first-stage amplifier circuit is greater than a duty cycle threshold.

[0012] In one possible implementation of the second aspect, the amplification operation stage of the first-stage amplifier circuit includes a pre-amplifier sub-operation stage and a main amplifier sub-operation stage, with the pre-amplifier sub-operation stage preceding the main amplifier sub-operation stage.

[0013] In one possible implementation of the second aspect, the main amplifier's operating phase completely overlaps with the sampling operating phase of the second-stage amplifier circuit.

[0014] In one possible implementation of the second aspect, the pre-amplification sub-operation phase of the first-stage amplifier circuit partially overlaps with the amplification operation phase of the second-stage amplifier circuit.

[0015] In one possible implementation of the second aspect, during the pre-amplifier operation phase, the amplifier input load of the first-stage amplifier circuit includes the quantizer capacitor of the second-stage amplifier circuit and the amplifier capacitor of the first-stage amplifier circuit. During the main amplifier operation phase, the amplifier input load of the first-stage amplifier circuit includes the quantizer capacitor of the second-stage amplifier circuit, the amplifier capacitor of the first-stage amplifier circuit, and the sampler capacitor of the second-stage amplifier circuit.

[0016] Thirdly, a chip is provided that includes any of the analog-to-digital converters of the first aspect.

[0017] Understandably, the technical effects of the third aspect refer to the technical effects of the first aspect and any of its embodiments, and will not be repeated here. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of a pipelined analog-to-digital converter provided in an embodiment of this application; Figure 2 A timing diagram of an analog-to-digital converter provided in an embodiment of this application; Figure 3 A flowchart illustrating the steps of a timing control method for an analog-to-digital converter provided in this application embodiment; Figure 4 This is a timing diagram of another analog-to-digital converter provided in an embodiment of this application. Detailed Implementation

[0019] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0020] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, a particular feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.

[0021] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0022] In describing some embodiments, the term "electrical connection" and its derivative expressions may be used. For example, the term "electrical connection" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact; in this case, "electrical connection" can also be described as "electrical connection". Furthermore, the term "electrical connection" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0023] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0024] "A and / or B" includes three combinations: A only, B only, and a combination of A and B. The use of "applies to" or "configured to" in this document implies open and inclusive language, which does not preclude applicability to or configuration to perform additional tasks or steps on devices. Additionally, the use of "based on" implies openness and inclusivity, as processes, steps, calculations, or other actions "based on" one or more conditions or values ​​may in practice be based on additional conditions or values ​​beyond those conditions.

[0025] The use of “configured as” in this article implies an open and inclusive language that does not exclude the applicability to or configuration of devices to perform additional tasks or steps.

[0026] With the rapid development of modern communication, medical imaging, and high-speed data acquisition systems, increasingly stringent requirements have been placed on the speed and accuracy of signal processing. In mixed-signal systems, the analog-to-digital converter (ADC), as the key interface connecting the physical world and the digital domain, directly determines the performance limit of the entire system.

[0027] Analog-to-digital converters (ADCs) are used to convert continuous analog signals into discrete digital codes, and the conversion rate and resolution are the core performance indicators in this process. Among the many ADC architectures, pipelined ADCs have become the mainstream choice for high-speed and high-precision applications due to their better balance between high sampling rate and high resolution.

[0028] The pipelined ADC architecture employs a multi-stage cascaded topology, dividing the complete analog-to-digital conversion process into multiple cascaded processing stages. Unlike successive approximation architectures that rely on iterative iterations with a single digital-to-analog converter, each stage in the pipeline structure is equipped with an independent analog processing channel, dedicated to completing a specific conversion step. This distributed processing mechanism effectively improves system throughput. Specifically, an N-bit resolution converter can be implemented using multiple cascaded processing structures, with each stage handling a portion of the quantization task (a common configuration is 1.5 bits per stage), achieving complete conversion through the coordinated operation of each stage.

[0029] A typical configuration of this system includes a sample-and-hold unit, a local analog-to-digital converter (ADC), a local digital-to-analog converter (DAC), and an interstage gain amplifier. Its signal processing flow is as follows: the input signal is sampled and then preliminarily quantized by the first-stage quantization module; subsequently, the corresponding analog quantity is reconstructed by the local DAC module; the difference between the original input and the reconstructed signal is used to obtain the error signal; this error signal is amplified and then sent to subsequent cascaded units to repeat the above process until the final stage circuit completes the final fine quantization.

[0030] For example, see Figure 1 The analog-to-digital converter shown includes a cascaded first-stage amplifier circuit and a second-stage amplifier circuit. The first-stage amplifier circuit includes an input buffer, a first-stage quantizer sampling capacitor (Cs1Q), a first-stage quantizer (AD / DA1), a first-stage feedback capacitor (Cf1), a parasitic capacitance (Cp1), a first-stage sampling capacitor (Cs1), and an amplifier (RA1). The second-stage amplifier circuit includes a second-stage amplifier (RA2), a second-stage sampling capacitor (Cs2), a second-stage feedback capacitor (Cf2), a parasitic capacitance (Cp2), and a second-stage quantizer (AD / DA2).

[0031] The input signal is first received through the input buffer and then sampled by the first-stage sampling switch (CLK). SA1Under the control of ), sampling is performed through the first-stage sampling capacitor (Cs1). During the sampling operation phase, the first-stage sampling switch (CLK) SA1 This ensures accurate sampling of the input signal and stores it in the first-stage sampling capacitor (Cs1), providing a stable sample value for subsequent signal processing.

[0032] The sampled signal is quantized by the first-stage quantization switch (CLK). Q1 Under the control of [unclear], the signal enters the first-stage quantizer (AD / DA1) for quantization, obtaining the quantized residual signal. The quantization switch (CLK) [unclear]. Q1 The quantizer is controlled to ensure the digital processing of the sampled signal and to obtain the discretized residual signal, which is then ready for subsequent amplification.

[0033] Then, the residual signal is amplified by the first stage switch (CLK). AMP1 Under the control of ), it is amplified by amplifier (RA1). Amplification switch (CLK) AMP1 The timing of the control amplifier ensures that the residual signal is correctly amplified. The first-stage amplifier (RA1) amplifies the residual signal appropriately based on the effects of the feedback capacitor (Cf1) and the parasitic capacitance (Cp1), enhancing the signal amplitude to ensure that it meets the requirements of subsequent processing.

[0034] The second-stage sampling circuit receives the amplified signal from the first-stage amplifier, and the first-stage sampling switch (CLK) SA2 The second-stage sampling capacitor (Cs2) controls the sampling of the signal from the first-stage amplifier. The sampling switch (CLKSA2) ensures accurate sampling of the signal in the second-stage circuit and stores it in the second-stage sampling capacitor (Cs2), ensuring signal stability.

[0035] Next, the sampled signal is quantized by the second-stage quantization switch (CLK). Q2 Under the control of the second stage quantizer (AD / DA2), the signal is quantized to obtain the second residual signal. The second quantization switch (CLK) Q2 It is responsible for starting the quantizer to digitize the second-level sampled signal and outputting the second residual signal.

[0036] Finally, the second-stage residual signal is amplified by the second-stage switch (CLK). AMP2 Under the control of ), it is amplified by the second-stage amplifier (RA2). The second-stage amplifier switch (CLK) AMP2 The timing of the second-stage amplifier (RA2) is controlled to ensure that the residual signal is properly amplified and finally outputs the second amplified signal, providing a high-quality signal for subsequent signal processing and conversion.

[0037] The control timing diagrams for each switch are as follows: Figure 2As shown, the operating phase of the first-stage amplifier circuit is somewhat limited due to the sampling and amplification times of the second-stage amplifier circuit. Specifically, the duty cycle of the first-stage amplification phase is limited to 50% due to the influence of the subsequent sampling and amplification stages. The purpose of this design is to ensure that the operation of the first-stage amplifier circuit does not overlap with the sampling and amplification operations of the second-stage circuit, thus guaranteeing system stability and synchronization. However, limiting the duty cycle of the first-stage amplification phase to 50% also introduces some potential drawbacks.

[0038] First, the duty cycle limitation may prevent the first-stage amplifier from fully amplifying the signal within a certain time, which limits its maximum amplification amplitude and thus affects the overall signal quality. Due to the short amplification time, the signal amplification process may be incomplete, which in turn affects the accuracy of the analog-to-digital converter. This is especially true in the processing of low-amplitude signals, where insufficient amplification may occur, affecting subsequent quantization and conversion processes.

[0039] To address the aforementioned issues, embodiments of this application provide a timing control method for an analog-to-digital converter, applicable to... Figure 1 The analog-to-digital converter shown is described in the reference document. Figure 3 The flowchart of the timing control method for the analog-to-digital converter shown may include steps S301 to S302.

[0040] S301: During the sampling operation phase of the first-stage amplifier circuit, the input signal is sampled to obtain the first sampled signal. During the quantization operation phase of the first-stage amplifier circuit, the first sampled signal is quantized to obtain the first residual signal. During the amplification operation phase of the first-stage amplifier circuit, the residual signal is amplified to obtain the first amplified signal.

[0041] First, during the sampling phase of the first-stage amplifier circuit, the signal is input into the system through the signal input terminal and enters the first-stage amplifier circuit. After being processed by the input buffer, the input signal passes through the first-stage sampling switch (CLK). SA1 The system controls the sampling process, sampling is performed on the first-stage sampling capacitor (Cs1) to obtain the first sampled signal. The sampled signal is stored in the first-stage sampling capacitor (Cs1) to ensure signal stability and provide a basis for subsequent processing.

[0042] Next, during the quantization phase of the first-stage amplifier circuit, the signal passes through the first-stage quantization switch (CLK). Q1 The input signal is controlled by the input signal and fed into the first-stage quantizer (AD / DA1) for digitization. The quantizer digitizes the sampled signal, and the digitized signal is subtracted from the input signal to generate the first residual signal. The residual signal represents the difference between the input signal and the digitized signal, and is a key signal for subsequent amplification.

[0043] During the amplification stage of the first-stage amplifier circuit, the first residual signal passes through the first-stage amplifier switch (CLK). AMP1 The signal is amplified by an amplifier (RA1) under the control of the feedback capacitor (Cf1) and the parasitic capacitance (Cp1). The first-stage amplifier (RA1) increases the signal amplitude based on the effects of the feedback capacitor (Cf1) and the parasitic capacitance (Cp1) to obtain the first amplified signal. At this time, the first-stage amplifier circuit adjusts the amplification stage time to ensure that the signal is properly amplified to meet the requirements of subsequent processing.

[0044] It should be noted that the amplification phase of the first-stage amplifier circuit includes a pre-amplification sub-phase and a main amplification sub-phase, with the pre-amplification sub-phase preceding the main amplification sub-phase. This means that by increasing the pre-amplification time in the first stage, the first and second-stage amplifier circuits can operate in parallel, thereby extending the signal settling time of the first-stage amplifier. By increasing the pre-amplification time, the first-stage amplifier circuit can more fully amplify the input signal initially without waiting for the second-stage amplifier circuit to complete the sampling and quantization process. In this way, the first and second-stage amplifier circuits can perform signal processing simultaneously, optimizing signal amplification efficiency and the overall system response speed. This design not only improves the operating time margin of the first-stage amplifier but also effectively enhances the overall performance of the analog-to-digital converter.

[0045] The load connected to the amplifier in the first-stage amplifier circuit differs between the preamplifier and main amplifier stages. In the preamplifier stage, the amplifier's load consists only of the quantizer capacitor from the second-stage amplifier circuit and the amplifier capacitor itself from the first stage. This relatively small equivalent load capacitance allows the amplifier to operate at a relatively high bandwidth. Although the phase margin is somewhat insufficient, this facilitates rapid signal establishment. However, upon entering the main amplifier stage, the sampler capacitor from the second-stage amplifier circuit is connected to the load network, significantly increasing the total load capacitance. While this change reduces the amplifier bandwidth, it effectively improves the system's phase margin, bringing it back to its stable operating range. By utilizing high bandwidth in the initial stage for rapid establishment and then transitioning to a stable state to ensure accuracy, a balance is struck between establishment speed and system stability.

[0046] The timing control method for an analog-to-digital converter provided in this application adds a pre-amplification sub-stage and advances it before the main amplification sub-stage, enabling the first-stage amplifier to operate in parallel with the second-stage amplifier during the pre-amplification stage. Furthermore, the first-stage amplifier gains a longer time margin during signal setup, improving signal amplification quality, reducing noise and distortion, and enhancing the overall accuracy and stability of the analog-to-digital converter.

[0047] S302: During the sampling phase of the second-stage amplifier circuit, the first amplified signal is sampled to obtain the second sampled signal. During the quantization phase of the second-stage amplifier circuit, the second sampled signal is quantized to obtain the second residual signal. During the amplification phase of the second-stage amplifier circuit, the residual signal is amplified to obtain and output the second amplified signal.

[0048] During the sampling phase of the second-stage amplifier circuit, the first amplified signal from the first stage passes through the second-stage sampling switch (CLK). SA2 The signal is controlled by the second-stage sampling capacitor (Cs2) to achieve precise sampling and obtain the second sampled signal. This process is completely synchronized with the main amplification sub-stage of the first stage, ensuring the timeliness of signal transmission.

[0049] After entering the quantization phase, the second sampled signal is processed by the second-stage quantization switch (CLK). Q2 The signal is controlled by the input signal and fed into the second-stage quantizer (AD / DA2) for digital processing. The quantizer generates a corresponding analog reconstructed signal by digitally reconstructing the sampled signal, and subtracts this signal from the original sampled signal to accurately obtain the second residual signal characterizing the conversion error.

[0050] In the subsequent amplification stage, the second residual signal is amplified by the second stage amplification switch (CLK). AMP2 Under the control of the first stage, the gain is boosted by the second-stage amplifier (RA2). The amplifier, with the combined effect of the feedback capacitor (Cf2) and the parasitic capacitance (Cp2), precisely amplifies the residual signal and finally outputs the second amplified signal.

[0051] It should be noted that if the analog-to-digital converter also includes a third-stage amplifier circuit, the second amplified signal is input into the third-stage amplifier circuit to perform the same processing operation, and the processing procedure will not be described in detail in this application.

[0052] The control timing diagrams for each switch are as follows: Figure 3 As shown, it can be seen that, firstly, at the macroscopic timing level, there is partial time overlap between the complete amplification phase of the first-stage amplifier circuit and the sampling phase of the second-stage amplifier circuit, and also partial overlap between the two phases. More importantly, the duty cycle of the amplification phase of the first-stage amplifier circuit is designed to be greater than a set duty cycle threshold, which provides the necessary time guarantee for sufficient signal establishment. For example, the duty cycle threshold can be 50%, while the duty cycle of the amplification phase of the first-stage amplifier circuit can be 60%, meaning the time corresponding to the amplification phase of the first-stage amplifier circuit is greater than half a cycle.

[0053] Secondly, the sub-stage division within the first-stage amplifier circuit ensures that its main amplification sub-stage (T2) is completely synchronized with the sampling sub-stage of the second-stage amplifier circuit. This guarantees that when the second-stage circuit samples, the first-stage amplifier is in its most stable operating state, thus providing a high-quality input signal to the next stage. For example, the time corresponding to the main amplification sub-stage and the sampling sub-stage of the second-stage amplifier circuit can be half a cycle. The pre-amplification sub-stage (T1) of the first-stage amplifier circuit partially overlaps with the amplification sub-stage of the second-stage amplifier circuit. This allows the critical operating periods of the two amplifier stages to be executed in parallel to the maximum extent, optimizing timing utilization and ensuring the continuity of signal processing, thereby achieving a significant improvement in system efficiency.

[0054] The timing control method for an analog-to-digital converter (ADC) provided in this application achieves parallel operation of the two amplifier stages by advancing the amplification phase of the first-stage amplifier circuit and partially overlapping it with the sampling and amplification phase of the second-stage amplifier circuit. This parallel operation can improve the overall conversion rate without adding extra duty cycles, thereby enhancing the system's conversion performance. By optimizing the timing arrangement, the conversion speed of the ADC can be effectively improved, and the data processing efficiency of the ADC can be enhanced.

[0055] This application embodiment also provides an analog-to-digital converter (ADC). The ADC includes a cascaded first-stage amplifier circuit and a second-stage amplifier circuit. The timing signal input terminals of the first-stage amplifier circuit and the second-stage amplifier circuit are coupled to a timing control circuit. The ADC is configured to: sample the input signal during the sampling operation phase of the first-stage amplifier circuit to obtain a first sampled signal; quantize the first sampled signal during the quantization operation phase of the first-stage amplifier circuit to obtain a first residual signal; amplify the first residual signal during the amplification operation phase of the first-stage amplifier circuit to obtain a first amplified signal; sample the first amplified signal during the sampling operation phase of the second-stage amplifier circuit to obtain a second sampled signal; quantize the second sampled signal during the quantization operation phase of the second-stage amplifier circuit to obtain a second residual signal; and amplify the second residual signal during the amplification operation phase of the second-stage amplifier circuit to obtain and output a second amplified signal. The amplification operation phase of the first-stage amplifier circuit and the sampling operation phase of the second-stage amplifier circuit partially overlap, and the duty cycle corresponding to the amplification operation phase of the first-stage amplifier circuit is greater than a duty cycle threshold.

[0056] In one possible implementation, the amplification operation stage of the first-stage amplifier circuit includes a pre-amplifier sub-operation stage and a main amplifier sub-operation stage, with the pre-amplifier sub-operation stage preceding the main amplifier sub-operation stage.

[0057] In one possible implementation, the main amplifier's operating phase completely overlaps with the sampling operating phase of the second-stage amplifier circuit.

[0058] In one possible implementation, the pre-amplification sub-operation phase of the first-stage amplifier circuit partially overlaps with the amplification operation phase of the second-stage amplifier circuit.

[0059] In one possible implementation, during the pre-amplifier operation phase, the amplifier input load of the first-stage amplifier circuit includes the quantizer capacitor of the second-stage amplifier circuit and the amplifier capacitor of the first-stage amplifier circuit. During the main amplifier operation phase, the amplifier input load of the first-stage amplifier circuit includes the quantizer capacitor of the second-stage amplifier circuit, the amplifier capacitor of the first-stage amplifier circuit, and the sampler capacitor of the second-stage amplifier circuit.

[0060] This application also provides a chip, including the analog-to-digital converter described in the above embodiments.

[0061] It should be noted that the above division of modules is only for the convenience of description and functional division. In actual implementation, a module can be implemented by multiple modules, and the functions of multiple modules can also be implemented by the same module. These modules can be located in the same device or in different devices.

[0062] The hardware modules in the implementation can be implemented mechanically or electronically. For example, a hardware module may include specially designed permanent circuitry or logic devices (such as dedicated processors, such as FPGAs or ASICs) to perform specific operations. For instance, specific operations can be performed within various types of chips (e.g., artificial intelligence chips). Hardware modules may also include programmable logic devices or circuitry (such as general-purpose processors or other programmable processors) temporarily configured by software to perform specific operations. The choice between mechanical implementation, dedicated permanent circuitry, or temporarily configured circuitry (e.g., software-configured) for the hardware module can be based on cost and time considerations.

[0063] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification. The above embodiments only illustrate several implementation methods of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of this application's patent. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

[0064] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features in the formula. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method of timing control for an analog-to-digital converter, characterized by, The method comprises: sampling an input signal in a sampling operation phase of a first-stage amplification circuit to obtain a first sampling signal, quantizing the first sampling signal in a quantization operation phase of the first-stage amplification circuit to obtain a first residual signal, and amplifying the first residual signal in an amplification operation phase of the first-stage amplification circuit to obtain a first amplified signal; sampling the first amplified signal in a sampling operation phase of a second-stage amplification circuit to obtain a second sampling signal, quantizing the second sampling signal in a quantization operation phase of the second-stage amplification circuit to obtain a second residual signal, and amplifying the second residual signal in an amplification operation phase of the second-stage amplification circuit to obtain and output a second amplified signal; the amplification operation phase of the first-stage amplification circuit partially overlaps with the sampling operation phase of the second-stage amplification circuit, the amplification operation phase of the first-stage amplification circuit partially overlaps with the amplification operation phase of the second-stage amplification circuit, and a duty cycle corresponding to the amplification operation phase of the first-stage amplification circuit is greater than a duty cycle threshold.

2. The method of timing control of an analog-to-digital converter according to claim 1, characterized in that, The amplification operation phase of the first-stage amplification circuit comprises a pre-amplification sub-operation phase and a main amplification sub-operation phase, and the pre-amplification sub-operation phase is before the main amplification sub-operation phase.

3. The method of timing control of an analog-to-digital converter according to claim 2, wherein, The main amplification sub-operation phase completely overlaps with the sampling operation phase of the second-stage amplification circuit.

4. The method of timing control of an analog-to-digital converter according to claim 2, wherein, The pre-amplification sub-operation phase of the first-stage amplification circuit partially overlaps with the amplification operation phase of the second-stage amplification circuit.

5. The method of timing control of an analog-to-digital converter according to claim 2, wherein, In the pre-amplification sub-operation phase, an amplifier of the first-stage amplification circuit accesses a load comprising a quantizer capacitor of the second-stage amplification circuit and an amplifier capacitor of the first-stage amplification circuit. In the main amplification sub-operation phase, the amplifier of the first-stage amplification circuit accesses a load comprising the quantizer capacitor of the second-stage amplification circuit, the amplifier capacitor of the first-stage amplification circuit, and a sampler capacitor of the second-stage amplification circuit.

6. An analog-to-digital converter, characterized by The analog-to-digital converter comprises a first-stage amplification circuit and a second-stage amplification circuit connected in cascade, and time sequence signal input ends of the first-stage amplification circuit and the second-stage amplification circuit are coupled with a time sequence control circuit; The analog-to-digital converter is configured to: sample an input signal in a sampling operation phase of a first-stage amplification circuit to obtain a first sampling signal, quantize the first sampling signal in a quantization operation phase of the first-stage amplification circuit to obtain a first residual signal, and amplify the first residual signal in an amplification operation phase of the first-stage amplification circuit to obtain a first amplified signal; sample the first amplified signal in a sampling operation phase of a second-stage amplification circuit to obtain a second sampling signal, quantize the second sampling signal in a quantization operation phase of the second-stage amplification circuit to obtain a second residual signal, and amplify the second residual signal in an amplification operation phase of the second-stage amplification circuit to obtain and output a second amplified signal; The amplification operation phase of the first-stage amplification circuit partially overlaps with the sampling operation phase of the second-stage amplification circuit, the amplification operation phase of the first-stage amplification circuit partially overlaps with the amplification operation phase of the second-stage amplification circuit, and the duty cycle corresponding to the amplification operation phase of the first-stage amplification circuit is greater than a duty cycle threshold.

7. The analog-to-digital converter of claim 6, wherein, The amplification operation phase of the first-stage amplification circuit includes a pre-amplification sub-operation phase and a main amplification sub-operation phase, and the pre-amplification sub-operation phase is prior to the main amplification sub-operation phase.

8. The analog-to-digital converter of claim 7, wherein, The main amplification sub-operation phase completely overlaps with the sampling operation phase of the second-stage amplification circuit, and the pre-amplification sub-operation phase of the first-stage amplification circuit partially overlaps with the amplification operation phase of the second-stage amplification circuit.

9. The analog-to-digital converter of claim 7, wherein, In the pre-amplification sub-operation phase, the amplifier of the first-stage amplification circuit accesses a load including the quantizer capacitor of the second-stage amplification circuit and the amplifier capacitor of the first-stage amplification circuit; In the main amplification sub-operation phase, the amplifier of the first-stage amplification circuit accesses a load including the quantizer capacitor of the second-stage amplification circuit, the amplifier capacitor of the first-stage amplification circuit, and the sampler capacitor of the second-stage amplification circuit.

10. A chip, characterized by An analog-to-digital converter as claimed in any one of claims 6 to 9.

Images