Multilayer electronic device package

Abstract

The invention relates to a multilayer electronic device package. An electronic device (100) includes a die (110), a ground die attach pad (104), and a power supply die attach pad (106). A wire bond (112) connects a ground grid from the die (110) to the ground die attach pad (104). Additional wire bonds (112) connect a power supply network from the die (110) to the power supply die attach pad (106). Additional wire bonds (112) connect a signal network from the die to pins (108) on the periphery of the electronic device (100).

Description

Technical Field

[0001] This disclosure relates to electronic devices, and more specifically to an electronic device having a plurality of die attachment pads. Background Technology

[0002] An integrated circuit (IC) package contains both signal and power grids. An IC package includes a large thermal or ground pad and input / output (I / O) pins surrounding the IC package perimeter. Each signal grid performs a specific function (e.g., enable, reset, etc.). The power grid includes a power supply (e.g., VDD) grid and a ground (GND) grid. In an IC package, the ground grid is routed to the ground pad. On the other hand, the power supply grid must be routed to the I / O pins, thereby reducing the number of I / O pins used for the signal grids, which limits the functionality of the IC package. The VDD power supply pins around the IC package require a significant amount of current, as well as low resistance and inductance, to maintain a stable and constant voltage. Any fluctuation in the VDD voltage will impair the performance of the IC package. Specifically, high inductance can cause VDD voltage instability and introduce noise in the signal I / O pins, thus degrading the performance of the IC package. Summary of the Invention

[0003] In the described example, an electronic device includes a die, a ground die attachment pad, and a power supply die attachment pad. Wire connectors connect a ground grid from the die to the ground die attachment pad, a power supply grid from the die to the power supply die attachment pad, and a signal grid from the die to pins on the periphery of the electronic device.

[0004] In another described example, an electronic device includes a first layer having at least two die attachment pads and a second layer having at least two first electrical pads, wherein the at least two first electrical pads are substantially aligned with the at least two die attachment pads. A third layer includes at least two second electrical pads, wherein the at least two second electrical pads are substantially aligned with the at least two first electrical pads. A die is disposed on the first layer, and wire connectors connect a power grid from the die to the at least two die attachment pads and a signal grid from the die to pins on the periphery of the electronic device.

[0005] In yet another described example, a method includes forming a first plating layer in a surface of a substrate and forming a second plating layer in an opposing surface of the substrate, wherein the first plating layer is electrically connected to the second plating layer via a via layer, wherein the inner walls of vias in the via layer are plated. A third plating layer is formed on the second plating layer. A wire bond provides a connection from a die disposed on the first plating layer to the first plating layer, and a molding compound is formed over the die and the wire bond. Attached Figure Description

[0006] Figure 1A and 1B These are the top and bottom views of the example electronic device.

[0007] Figure 2 yes Figure 1A and 1B A top view of the first layer of an example electronic device.

[0008] Figure 3 yes Figure 1A and 1B A top view of the second layer of an example electronic device.

[0009] Figure 4 yes Figure 1A and 1B A top view of the through-hole layer of an example electronic device.

[0010] Figure 5 yes Figure 1A and 1B A top view of the third layer of an example electronic device.

[0011] Figure 6 It shows the... Figure 1A and 1B A graph showing the effect of inductance on electronic devices.

[0012] Figure 7 It is an explanation Figure 1A and 1B A flowchart illustrating the manufacturing process of electronic devices.

[0013] Figure 8A A cross-sectional view of the substrate in the early stages of manufacturing is shown.

[0014] Figure 8B Showing the result after the through-hole is formed Figure 8A A cross-sectional view of the substrate.

[0015] Figure 8C This shows the process after the deposition of the seed layer. Figure 8B A cross-sectional view of the substrate.

[0016] Figure 8D This shows the patterning process after the first photoresist material layer is applied. Figure 8C A cross-sectional view of the substrate.

[0017] Figure 8E Showing the result after the first plating process Figure 8D A cross-sectional view of the substrate.

[0018] Figure 8F This shows the process after the removal of the first photoresist layer. Figure 8E A cross-sectional view of the substrate.

[0019] Figure 8G This shows the patterning process after the second photoresist material layer is applied. Figure 8F A cross-sectional view of the substrate.

[0020] Figure 8H This shows the result after the second plating process. Figure 8G A cross-sectional view of the substrate.

[0021] Figure 8I This shows the process after the removal of the second photoresist layer. Figure 8H A cross-sectional view of the substrate.

[0022] Figure 8J This shows the patterning process after the third photoresist material layer is applied. Figure 8I A cross-sectional view of the substrate.

[0023] Figure 8K This shows the result after the third plating process. Figure 8J A cross-sectional view of the substrate.

[0024] Figure 8L This shows the effect after the removal of the third photoresist layer. Figure 8K A cross-sectional view of the substrate.

[0025] Figure 8M This shows the process after placing the bare die on the first layer. Figure 8L A cross-sectional view of the substrate.

[0026] Figure 8N This is shown after the wire bonding component has been placed from the bare die onto the first layer. Figure 8M A cross-sectional view of the substrate.

[0027] Figure 8O This shows the process after the formation of the molding compound. Figure 8N A cross-sectional view of the substrate. Detailed Implementation

[0028] An integrated circuit (IC) package contains both signal and power grids. An IC package includes a large thermal or ground pad (e.g., a copper pad) and input / output (I / O) pins (e.g., copper pins) surrounding the IC package perimeter. Each signal grid performs a specific function (e.g., enable, reset, etc.). The power grid includes a power supply (e.g., VDD) grid and a ground (GND) grid. In an IC package, the ground grid is routed to the ground pad. On the other hand, the power supply grid must be routed to the I / O pins, thereby reducing the number of I / O pins used for the signal grids, which limits the functionality of the IC package. The VDD power supply pins around the IC package require a significant amount of current, as well as low resistance and inductance, to maintain a stable and constant voltage. Any fluctuation in the VDD voltage will impair the performance of the IC package. Specifically, high inductance can cause VDD voltage instability and introduce noise in the signal I / O pins, thus degrading the performance of the IC package.

[0029] Specifically, as inductance increases, the VDD power becomes unstable and therefore fluctuates (e.g., between 2.0 volts and 1.5 volts). This fluctuation generates ringing or noise on the I / O pins, interfering with the operation of the IC package. The inductance is affected by the volume of copper in the IC package. As mentioned earlier, the ground grid is connected to a large copper ground pad. Therefore, the volume of the large copper pad is sufficient to maintain the inductance at a low level. On the other hand, the VDD power supply grid is connected to the I / O pins. The volume of copper on the I / O pins is insufficient to maintain the inductance at the required low level. Therefore, in order to generate sufficient copper volume connected to the VDD power supply grid to maintain low inductance, a large amount of VDD power supply grid must be connected to a large number of I / O pins. Thus, a large number of I / O pins are dedicated to VDD power supply pins, which limits the number of signal grids that can be connected to the I / O pins, thereby limiting the functionality of the IC package.

[0030] This document discloses an electronic device (e.g., an integrated circuit (IC) package) that overcomes the aforementioned drawbacks. Specifically, this document discloses a multilayer substrate electronic device comprising multiple die attachment pads (DAPs). The multiple DAPs allow both the power supply network and the ground network to be bonded downwards from the die to their respective DAPs (i.e., VDD and ground). The configuration of the multiple DAPs frees up I / O pins on the periphery of the IC package to allow more I / O pins for the signal network, which increases functionality and / or reduces package size. Furthermore, the size of the multiple DAPs provides sufficient volume of copper for both the power network and the signal network to maintain a low inductance level (e.g., approximately 0.4–1.8 nH). It should be understood that the acceptable low range of inductance will vary based on the type of IC package. The DAPs are disposed on multiple layers of the substrate package, and the multiple layers are electrically interconnected via via layers. Depending on the application and package design, the vias can be cylindrical hollow vias with copper-plated walls, solid copper vias, or a combination of both. Provide an additional bottom layer as a cover area for electrical devices (e.g., printed circuit boards (PCBs)) attached to the end user.

[0031] Figure 1A and 1B These are top and bottom views of a multilayer substrate electronic device (e.g., an integrated circuit (IC)) 100 comprising multiple die attachment pads. The die attachment pads include a sufficient volume of conductive metal (e.g., copper) to reduce the inductance in the electronic device 100 and maintain the inductance at a low level (e.g., 0.4-1.8 nH). The electronic device 100 is a substrate-type device and may include any type of multilayer substrate integrated circuit (IC), including but not limited to area grid array (LGA), ball grid array (BGA) packages, etc. Therefore, Figure 1A and 1B The example electronic device 100 shown is for illustrative purposes only and is not intended to limit the scope of the invention.

[0032] Electronic device 100 is a multilayer multi-DAP substrate device comprising a first (top) layer 102 including a ground die attachment pad (GND DAP) 104 and a power supply die attachment pad (VDD DAP) 106, wherein the GND DAP 104 and VDD DAP 106 are on a first plane. The VDD DAP 106 includes two L-shaped strips disposed near the periphery of the first layer 102. Thus, the VDD L-shaped strips 106 surround the GND DAP 104. Pins 108 are disposed around the periphery of the first layer 102 outside the VDD L-shaped strips 106. A die 110 is disposed on the first layer. Wire connections 112 provide connections from the die 110 to the GND DAP 104, to the VDD DAP 106, and to the pins 108. Specifically, some wire connections 112 electrically connect a ground grid from the die 110 to the GND DAP 104. Other wire connections 112 electrically connect the power supply network from the die 110 to the VDD DAP 106. Finally, the remaining wire connections 112 electrically connect the signal network from the die 110 to pin 108. As described above, the presence of the VDD DAP 106 allows the power supply network to be connected from the die 110 to the VDD DAP 106 without connecting it to pin 108. This allows more signal networks to be connected from the die 110 to pin 108. Because the different signal networks have different functions (e.g., enable, reset, etc.), the functionality of the electronic device 100 is increased.

[0033] refer to Figure 1B The electronic device 100 further includes a second (intermediate) layer 114, which includes a first grounding pad 116 and a first power supply pad 118, wherein the first grounding pad 116 and the first power supply pad 118 are on a second plane. Figure 1A and 1B The via layer, not shown, electrically connects the first layer 102 and the second layer 114. Specifically, the via layer includes vias that electrically connect the GNDDAP 104 of the first layer 102 to a first ground pad 116 of the second layer 114, and vias that electrically connect the VDD DAP 106 of the first layer 102 to a first power supply pad 118 of the second layer 114. As will be further explained below, the via layer further includes vias on its periphery that electrically connect pin 108 from the first layer to a pin of the second layer 114.

[0034] Still referencing Figure 1B The electronic device 100 further includes a third (bottom) layer 120 comprising a second grounding pad 122 and a second power supply pad 124, wherein the second grounding pad 122 and the second power supply pad 124 are on a third plane. Figure 1BAs shown, the xy dimensions of the first ground pad 116 and the first power supply pad 118 are larger than the xy dimensions of the second ground pad 122 and the second power supply pad 124, respectively. The third layer 120 is attached to an electrical device (e.g., a printed circuit board (PCB)) via pins 108.

[0035] Return to reference Figure 1A A molding compound 126 is formed over the die 110 and the wire bond 112. Since the electronic device 100 is a substrate-type package, the aforementioned layers are disposed within a substrate (e.g., a dielectric). Therefore, the molding compound 126 is not formed over the plurality of layers and the substrate.

[0036] Figure 2-5 This is a top view of the first (top) layer 200, the second (middle) layer 300, the via layer 400, and the third (bottom) layer 500. Figure 2-5 The example shown, with layers 200 (first layer), 300 (second layer), and 500 (third layer), is similar to... Figure 1A and 1B The first layer 102, the second layer 114, and the third layer 120 are shown. Therefore, in Figure 2-5 Refer to the following description of the instances in the example. Figure 1A and 1B Examples.

[0037] refer to Figure 2 The first layer 200 includes power die attachment pads (DAPs) comprising a ground (GND) DAP 202 and a power supply (VDD) DAP 204, wherein the GND DAP 202 and VDD DAP 204 are on the same plane (first plane). The VDD DAP includes a strip surrounding the GND DAP 202 near the outer periphery of the first layer 200. Pins (leads) 206 are disposed around the outer periphery of the first layer 200. Wire connections provide connections from the power grid and signal grid on the die 208 disposed on the first layer 200 to the GND DAP 202, VDD DAP 204, and pins 206. Specifically, a first set of wire connections 210 provides a connection between the ground grid on the die 208 and the GND DAP 202. A second set of wire connections 212 provides a connection between the power grid on the die 208 and the VDD DAP 204. Finally, the third set of wire connectors 214 provides the connection between the signal mesh on the die 208 and the pins 206. Figure 2 In the example shown, only a small portion of the wire joint is shown for the sake of illustration and simplicity.

[0038] refer to Figure 3The second layer 300 is similar to the first layer 200. The second layer 300 includes a first ground pad 302 and a first power supply pad 304, wherein the first ground pad 302 and the first power supply pad 304 are on the same plane (second plane). The first power supply pad 304 extends around the first ground pad 302 near the periphery of the second layer 300. Leads 306 are disposed around the periphery of the second layer and are aligned with leads 206 on the first layer 200 during the fabrication of both the first layer 200 and the second layer 300.

[0039] refer to Figure 4 The via layer 400 includes vias providing electrical connections between the first layer 200 and the second layer 300. Specifically, the via layer 400 includes a first set of vias 402 providing electrical connections between the GND DAP 202 of the first layer 200 and the first ground pad 302 of the second layer 300. The via layer 400 further includes a second set of vias 404 providing electrical connections between the VDDDAP 204 of the first layer 200 and the first power supply pad 304 of the second layer 300. Finally, the via layer 400 includes a third set of vias 406 providing electrical connections between pins 206 of the first layer 200 and pins 306 of the second layer 300.

[0040] refer to Figure 5 The third or bottom layer 500 is connected to the second layer 300 via electroplating and has a configuration similar to that of the second layer 300. The third layer 500 includes a second ground pad 502 and a second power supply pad 504, wherein the second ground pad 502 and the second power supply pad 504 are on the same plane (the third plane). The second power supply pad 504 extends around the second ground pad 502 near the periphery of the third layer 500. The third layer 500 further includes contacts 506 electroplated on the bottom portion of the leads 306 of the second layer 300. During use, the contacts 506 are connected to an electrical device (e.g., a PCB).

[0041] Figure 6This is graph 600 illustrating the effect of implementing VDD DAP 106 on inductance. Graph 600 compares the inductance between a standard QFN package and an electronic device 100 containing VDD DAP 106. The left bar 602 represents the inductance in the QFN package, and the right bar 604 represents the inductance in the electronic device 100. Furthermore, VDD CORE is the main power supply network (VDD) of the die 110 connected to VDD DAP 106. As graph 600 shows, there is a significant improvement in inductance in the electronic device 100 compared to the QFN package. Additionally, additional testing related to the high-speed performance and thermal shock of the signal network yields comparable results between the electronic device and the QFN package. Therefore, the implementation of a separate DAP for the power supply (VDD) network has no negative impact on the operation or performance of the electronic device 100. Although the graph only shows the VDD CORE power supply network, other power supply networks (e.g., VDD XXX) can be wire-connected to other VDD DAPs. Therefore, theoretically, there could be several separate VDD DAPs to accommodate all VDD power supply networks on the die 110.

[0042] Figure 7 It is a flowchart illustrating the manufacturing process 700, and Figure 8A-8O Showing with Figure 1A and 1B The electronic device 100 shown is associated with a manufacturing process 800. Although depicted sequentially for convenience, at least some of the actions shown may be performed in a different order and / or in parallel. Alternatively, some embodiments may perform only some of the actions shown. Furthermore, although Figure 7 and 8A The example shown in -8O is an illustration Figure 1A and 1B The instance methods are configured for the instance, but other methods and configurations are also possible. It should be understood that, although... Figure 7 and 8A The method shown in -8O describes the manufacturing process of a single electronic device, but the process is applicable to arrays of electronic devices. Therefore, after manufacturing the array of electronic devices, the array is diced to separate each electronic device 100 from the array.

[0043] refer to Figure 7 and Figure 8A-8O , Figure 1A and 1B The manufacturing process 800 of the electronic device 100 shown begins at 702, where a substrate (e.g., a dielectric) 802 is provided. At 704, a through-hole 804 is formed in the substrate 802 via laser drilling, thereby producing... Figure 8BThe configuration is as follows. As explained above, through-hole 804 includes a first group, a second group, and a third group of through-holes. However, for simplicity, only two through-holes are shown. Therefore, Figure 8A-8O The examples provided are for illustrative purposes only and are not intended to limit the scope of the invention. At 706, a seed layer (e.g., a copper seed layer) 806 is applied to the surface of the substrate 802 and the inner wall of the via 804 via electroless plating, thereby producing Figure 8C Configuration.

[0044] At 708, a first photoresist material layer 808 is overlaid on the substrate 802 and patterned and developed to expose openings 810 in the first photoresist material layer 808 above the substrate 802, thereby creating Figure 8D The configuration of the first photoresist material layer 808 may have a thickness that varies corresponding to the wavelength of the radiation used to pattern the first photoresist material layer 808. The first photoresist material layer 808 may be formed on the substrate 802 via spin coating or spin casting deposition technology, and selectively irradiated (e.g., via deep ultraviolet (DUV) irradiation) and developed to form the opening 810.

[0045] At 710, Figure 8D The configuration in the first plating (electroplating) process 900 deposits a first layer (e.g., copper) 812 in the openings 810 of the first photoresist material layer 808 on the seed layer 806, thereby producing Figure 8E The configuration is as follows: A first layer 812 is plated onto the surface of the substrate 802, such that the surface of the first layer 812 is substantially flush with the surface of the substrate 802. As described above, the first layer 812 includes GND DAP and VDD DAP. Simultaneously, the inner wall of the via 804 is plated with the same material as the first layer 812. As mentioned above, the inner wall of the via 804 can be plated, or the via 804 can be filled with the plating material to form a solid via. At 712, the first photoresist material layer 808 is removed by a dry or wet etching process, thereby producing... Figure 8F Configuration.

[0046] At position 714, Figure 8F The configuration is rotated 180°, and the second photoresist material layer 814 is coated on the substrate 802 and patterned and developed to expose the openings 816 in the second photoresist material layer 814 above the substrate 802, thereby producing Figure 8GThe second photoresist material layer 814 may have a thickness that varies corresponding to the wavelength of the radiation used to pattern the second photoresist material layer 814. The second photoresist material layer 814 may be formed over the substrate 802 via spin coating or spin casting deposition techniques, and selectively irradiated (e.g., via deep ultraviolet (DUV) irradiation) and developed to form the opening 816.

[0047] At point 716, Figure 8G The configuration undergoes a second plating (electroplating) process 910 to plate a second layer (e.g., copper) 818 on the opening 816 of the second photoresist material layer 814 and the seed layer 806 disposed on the opposite surface of the substrate 802, thereby producing Figure 8H The configuration is as described above. The second layer 818 includes a grounding pad and a power supply pad. At 718, the second photoresist material layer 814 is removed via a dry or wet etching process, thereby producing... Figure 8I Configuration.

[0048] At position 720, a third photoresist material layer 820 is overlaid on the substrate 802 and patterned and developed to expose openings 822 in the third photoresist material layer 820 above the substrate 802, thereby producing Figure 8J The third photoresist material layer 820 may have a thickness that varies corresponding to the wavelength of the radiation used to pattern the third photoresist material layer 820. The third photoresist material layer 820 may be formed on the substrate 802 via spin coating or spin casting deposition techniques, and selectively irradiated (e.g., via deep ultraviolet (DUV) irradiation) and developed to form openings 822.

[0049] At 722, Figure 8J The configuration undergoes a third plating (electroplating) process 920 to plate a third layer (e.g., copper) 824 in the opening 822 of the third photoresist material layer 820 and on the second layer 818, thereby producing Figure 8K The third layer 824 is deposited on the second layer 818, such that the surface of the third layer 824 is substantially flush with the opposite surface of the substrate 802. As described above, the third layer 824 includes a second ground pad and a second power supply pad. At 724, the third photoresist material layer 820 is removed by a dry or wet etching process, thereby producing... Figure 8L Configuration.

[0050] At position 726, Figure 8L The configuration is rotated 180° and the bare die 826 is placed on the first layer 812, thereby producing Figure 8M The configuration. At 728, the wire connector 828 is attached from the die 826 to the first layer and pins, thereby creating... Figure 8NThe configuration is as follows. Specifically, as described above, the first and second sets of wire connectors are attached from the ground grid and power grid on die 826 to GND DAP and VDD DAP, respectively. The third set of wire connectors is connected from the signal grid on die 826 to the pins. At 730, a molding compound 830 is formed over die 826 and wire connectors 828, thereby producing... Figure 8O Configuration.

[0051] like Figure 8O As shown, the first layer 812, the second layer 818, and the third layer 824 include gaps or spaces 832. Specifically, the first layer includes one or more first gaps 832-1 that physically separate the GND DAP from the VDD DAP. The second layer 818 includes one or more second gaps 832-2 that physically separate the first ground pad from the first power supply pad. Finally, the third layer 824 includes one or more third gaps 832-3 that physically separate the second ground pad from the second power supply pad.

[0052] Examples of this disclosure have been described above. It is certainly impossible to describe every conceivable combination of components or methods for the purposes of describing this disclosure, but those skilled in the art will recognize that many other combinations and arrangements of this disclosure are possible. Therefore, this disclosure is intended to cover all such alterations, modifications, and variations that fall within the spirit and scope of the appended claims. Furthermore, where the disclosure or claims refer to an element or its equivalent, it should be interpreted as including one or more such elements, neither requiring nor excluding two or more such elements. Moreover, the term "comprising" as used in the embodiment or claims is intended to be inclusive in a manner similar to the term "including," as interpreted when "including" is used as a transition word in a claim. Finally, the term "based on" is interpreted as meaning at least partially based on.

Claims

1. An electronic device comprising: a die; a ground die attach pad; a power supply die attach pad; and wire bonds connecting a ground net from the die to the ground die attach pad, connecting a power supply net from the die to the power supply die attach pad, and connecting a signal net from the die to a pin on a periphery of the electronic device.

2. The electronic device of claim 1, wherein the ground die attach pad and the power supply die attach pad are on a first plane in a first layer.

3. The electronic device of claim 2, wherein the power supply die attach pad comprises an L-shaped strip that extends around a periphery of the first layer and substantially encircles the ground die attach pad.

4. The electronic device of claim 2, further comprising a second layer comprising a first ground pad and a first power supply pad, wherein the first ground pad and the first power supply pad are on a second plane.

5. The electronic device of claim 4, further comprising a via layer disposed between the first layer and the second layer, the via layer including a via electrically connecting the ground die attach pad to the first ground pad and a via electrically connecting the power supply die attach pad to the first power supply pad.

6. The electronic device of claim 5, further comprising a second ground pad disposed on a bottom of the first ground pad and a second power supply pad disposed on the first power supply pad, wherein the second ground pad and the second power supply pad are on a third plane.

7. The electronic device of claim 6, wherein x-y dimensions of the first ground pad and the first power supply pad are greater than x-y dimensions of the second ground pad and the second power supply pad, respectively.

8. An electronic device comprising: a first layer having at least two die attach pads; a second layer having at least two first electrical pads substantially aligned with the at least two die attach pads; a third layer having at least two second electrical pads substantially aligned with the at least two first electrical pads; a die disposed on the first layer; and wire bonds connecting a power net from the die to the at least two die attach pads and connecting a signal net from the die to a pin on a periphery of the electronic device.

9. The electronic device of claim 8, further comprising a via layer having vias connecting the at least two die attach pads of the first layer with the at least two first electrical pads of the second layer.

10. The electronic device of claim 9, wherein the at least two die attach pads comprise a ground die attach pad and a power supply die attach pad, wherein the ground die attach pad and the power die attach pad are on a first plane. ​ ​ 11. The electronic device of claim 10, wherein the at least two first electrical pads include a first ground pad substantially aligned with the ground die attach pad and a first power supply pad substantially aligned with the power supply die attach pad, wherein the first ground pad and the first power supply pad are on a second plane.

12. The electronic device of claim 11, wherein the at least two second electrical pads include a second ground pad substantially aligned with the first ground pad and a second power supply pad substantially aligned with the first power supply pad, wherein the second ground pad and the second power supply pad are on a third plane.

13. The electronic device of claim 12, wherein the ground die attach pad and the power supply die attach pad are physically separated by a first gap, wherein the first ground pad and the first power supply pad are physically separated by a second gap, and wherein the second ground pad and the second power supply pad are physically separated by a third gap.

14. The electronic device of claim 10, wherein the power supply die attach pad includes an L-shaped strip that extends around a perimeter of the first layer and substantially encircles the ground die attach pad.

15. The electronic device of claim 10, wherein the wire bonds include a first set of wire bonds connecting a ground net from the die to the ground die attach pad, a second set of wire bonds connecting a power supply net from the die to the power supply die attach pad, and a third set of wire bonds connecting the signal net from the die to the pins.

16. A method comprising: forming a first plating layer in a surface of a substrate; forming a second plating layer in an opposing surface of the substrate, the first plating layer electrically connected to the second plating layer via a via layer, wherein inner walls of vias in the via layer are plated; forming a third plating layer on the second plating layer; connecting wire bonds from a die disposed on the first plating layer to the first plating layer; and forming a molding compound over the die and wire bonds.

17. The method of claim 16, wherein forming the first plating layer includes forming a ground die attach pad via electroplating and forming a power supply die attach pad via electroplating, wherein the ground die attach pad and the power supply die attach pad are on a first plane and are physically separated by a first gap.

18. The method of claim 17, wherein forming a second plating layer includes forming a first ground pad and a first power supply pad via electroplating, wherein the first ground pad and the first power supply pad are on a second plane and are physically separated by a second gap.

19. The method of claim 18, wherein forming a third plating layer includes forming a second ground pad and a second power supply pad via electroplating, wherein the second ground pad and the second power supply pad are on a third plane and are physically separated by a third gap.

20. The method of claim 17, wherein connecting wire bonds from a die disposed on the first plated layer to the first plated layer includes connecting a first set of wire bonds from a ground net on the die to the ground die attach pad, connecting a second set of wire bonds from a power supply net on the die to the power supply die attach pad, and connecting a third set of wire bonds from a signal net on the die to pins on the substrate periphery.

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