Method for obtaining measurement of semiconductor structure from single wedge-shaped cut of examination volume

Abstract

The present invention relates to a method (68) for obtaining a measurement of a semiconductor structure (18) from a single wedge-shaped cut (34) of an inspection volume (10), the method (68) comprising: obtaining a wedge-shaped cut (34) by exposing a cross-sectional surface in the inspection volume (10) by milling to the inspection volume (10) using an FIB column (46) configured at an inclination angle GF, and imaging the cross-sectional surface with a charged particle beam imaging system (50); determining a position of a cross-sectional feature (72) of the semiconductor structure (18) in the wedge-shaped cut-out (34); determining a reference position of the cross-sectional feature (72) from at least one reference image (76) of the semiconductor structure (18); one or more measurements of the semiconductor structure (18) are obtained using a lateral displacement (74) between the position of the cross-sectional feature (72) and a reference position (78).

Description

[0001] This application claims priority to German Patent Application No. 10 2023 120462.9, filed August 1, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to a technique for three-dimensional circuit pattern inspection and measurement via cross-sectional measurements of integrated circuits. More specifically, this invention relates to a three-dimensional circuit pattern inspection technique involving cross-sectional measurements at an inspection volume within a semiconductor wafer containing integrated circuits. Even more specifically, this invention relates to a method, computer program, computer-readable medium, and corresponding dual-beam device for obtaining measurements of semiconductor structures from a wedge-shaped cut in the inspection volume at the measurement location of the semiconductor wafer. The method employs milling a cross-sectional surface into the inspection volume of the wafer at an inclined angle and imaging the inclined cross-sectional surface using a charged particle beam imaging system. The method, computer program, computer-readable medium, and corresponding dual-beam device can be used for quantitative metrology, defect detection, process monitoring, defect review, and inspection of integrated circuits within semiconductor wafers. Background Technology

[0003] The fabrication of wafers containing semiconductor structures involves a complex sequence of physical material deposition and removal at nanometer-scale resolution. Therefore, extracting measurements of the fabricated 3D structure is crucial for monitoring the manufacturing process.

[0004] Wafers, made from thin slices of silicon, serve as substrates for microelectronic devices containing semiconductor structures built into and on the wafer. Semiconductor structures are built layer-by-layer using repeated processing steps involving repetitive chemical, mechanical, thermal, and optical processes. A semiconductor wafer has a diameter of 300 mm and consists of multiple sites (so-called dies), each containing at least one integrated circuit pattern, such as for memory chips or processor chips. The semiconductor wafer undergoes approximately 1000 process steps to form about 100 or more parallel layers within it, including transistor layers, line intermediate layers, and interconnect layers, as well as a 3D array containing memory cells in the memory device.

[0005] The manufactured semiconductor structure corresponds to existing knowledge of its internal structure. The semiconductor structure is made of a series of layers parallel to the substrate. For example, in logic type samples, metal lines extend parallel to the metal layers or in HAR (High Aspect Ratio) structures, and metal vias extend perpendicular to the metal layers. The angle between metal lines in different layers is 0° or 90°. On the other hand, for VNAND type structures, it is known that their average cross-section is circular.

[0006] The size, shape, and layout of semiconductor structures and patterns are influenced by a variety of factors. One of the most critical steps is photolithography. Photolithography is the process used to create patterns on a substrate. The patterns to be printed on the substrate surface are generated using computer-aided design (CAD). Based on the design, a photomask is created for each layer, containing a magnified image of the computer-generated pattern to be etched into the substrate. The photomask can be further refined, for example, using optical proximity correction techniques. During the printing process, the illumination image projected from the photomask is focused onto a thin film of photoresist formed on the substrate. Semiconductor chips that power mobile phones or tablet computers contain, for example, about 80 to 120 patterned layers.

[0007] As the integration density of the semiconductor industry continues to increase, photolithography masks must image increasingly smaller structures onto wafers. The aspect ratio and number of layers in integrated circuits are constantly increasing, and structures are evolving towards a third (vertical) dimension. Currently, the height of memory stacks exceeds tens of micrometers. In contrast, feature sizes are becoming smaller. The smallest feature size, or critical size, is below 10 nm, for example, 7 nm or 5 nm, and will approach feature sizes below 3 nm in the near future. As the complexity and size of semiconductor structures evolve into the third dimension, the lateral dimensions of integrated semiconductor structures become smaller. Producing small structure sizes imaged onto wafers requires photolithography masks or templates for nanoimprint lithography with smaller structures or patterned elements.

[0008] Because this manufacturing process is complex and highly nonlinear, optimizing production process parameters is difficult. As a remedy, an iterative approach called Process Window Qualification (PWQ) can be applied. In each iteration, the test wafer is manufactured according to the current optimal process parameters, with different dies exposed to different manufacturing conditions. By using instruments for quantitative metrology and defect detection to inspect and analyze the test structure, the optimal manufacturing process parameters can be selected. In this way, production process parameters can be adjusted towards optimization.

[0009] Due to the minute structural dimensions of the patterned elements in photolithographic masks or templates and the complex manufacturing process of semiconductor structures, it is impossible to eliminate errors during wafer fabrication. Therefore, wafer inspection, review, and metrology play crucial roles in monitoring defects within semiconductor process control. Traditionally, measurements of two-dimensional semiconductor structures are performed manually by experts. However, due to the three-dimensional nature of semiconductor structures on wafers, three-dimensional measurements are necessary to allow for more accurate monitoring of the manufacturing process.

[0010] A common method for generating tomographic data (i.e., 3D imaging datasets) from nanoscale semiconductor samples is the so-called slicing and imaging method, which is performed, for example, using a dual-beam apparatus. In such an apparatus, two particle optics systems are configured at an angle. The first particle optics system can be a scanning electron microscope (SEM). The second particle optics system can be a focused ion beam optics (FIB) system using, for example, gallium (Ga) ions. The gallium ion focused ion beam (FIB) is used to slice layers at the edges of the semiconductor sample piece by piece, and each cross-section is imaged using a scanning electron microscope (SEM). The two particle optics systems can be oriented vertically or at an angle between 45° and 90°. The resulting imaging dataset is very dense (e.g., containing thousands of images), thus posing challenges in terms of measurement scalability, stability, and repeatability.

[0011] For example, WO 2021 / 083581 A1 discloses a method for measuring shape deviations of 3D HAR structures in FIB-SEM tomography. The method involves obtaining an imaging dataset of 2D cross-sectional images parallel to the wafer surface using slicing and imaging techniques. A template representing the cross-sectional image features of the HAR structure of interest is generated, and instances of this template are detected in the 2D cross-sectional images of the imaging dataset. For example, the detected instances are assigned to different 3D HAR structures based on the distance of the center coordinates of instances in adjacent 2D cross-sectional images. Based on the detected instances assigned to the same 3D HAR structure, the surface of the 3D HAR structure is reconstructed, and parameters characterizing the geometry of the entire semiconductor structure are obtained.

[0012] However, obtaining parallel slices of a wafer to measure semiconductor structure parameters requires a large amount of data and results in low yield. To reduce the amount of data required to measure semiconductor structure parameters, WO 2021 / 180600 A1 discloses a method for measuring parameters using multiple wedge cuts, i.e., obtaining cross-sectional images by milling into the wafer at an angle relative to the wafer support stage using a FIB SEM. In the wedge cut, the depth of a pixel can be obtained from its lateral position. To minimize runtime and increase yield, a single wedge cut is sufficient to produce measurements of repetitive semiconductor structures in the wafer. For this purpose, a representative semiconductor structure can be obtained from a single wedge cut by combining multiple cross-sectional surface features from different instances of the same semiconductor into a single representative semiconductor structure, as shown in Figures 24 and 25 of WO 2021 / 180600 A1. However, due to deformation in the wedge cut, the positional accuracy of the cross-sectional surface features, and therefore the positional accuracy of the representative semiconductor structure, and the measurements obtained, are often insufficient.

[0013] Therefore, an object of the present invention is to provide an accurate method for measuring 3D semiconductor structures from a single wedge notch. Another object of the present invention is to obtain measurements of 3D semiconductor structures rapidly and with increased throughput. Another object of the present invention is to provide a method for generating representative 3D semiconductor structures from a single wedge notch with improved accuracy. Another object of the present invention is to obtain measurements of 3D semiconductor structures with low memory requirements. Another object of the present invention is to provide a method for inspecting critical dimensions of semiconductor structures on a wafer. Another object of the present invention is to provide a method for process window authentication. Another object of the present invention is to increase throughput during wafer quality control or quality assurance processes. Another object of the present invention is to minimize the operation time of quality control or quality assurance methods.

[0014] These objectives are achieved by the invention as specified in the independent claims. Advantageous embodiments and further developments of the invention are clearly described in the dependent claims. Summary of the Invention

[0015] Embodiments of the present invention relate to methods, computer programs, computer-readable media, and dual-beam devices, which are implemented as methods for obtaining 3D representative semiconductor structures from a single wedge cut in an inspection volume.

[0016] A first embodiment includes a method for obtaining one or more measurements of a semiconductor structure from a single wedge cut in an inspection volume, the method comprising: obtaining a wedge cut in the inspection volume by milling a cross-sectional surface in the inspection volume using FIB pillars configured at an angle GF to the inspection volume; and imaging the cross-sectional surface with a charged particle beam imaging system to obtain the wedge cut; determining the position of a cross-sectional feature of the semiconductor structure in the wedge cut; determining a reference position of the cross-sectional feature based on at least one reference image of the semiconductor structure; and obtaining one or more measurements of the semiconductor structure in the inspection volume using a reference semiconductor structure and a lateral displacement between the position of the cross-sectional feature and the reference position.

[0017] A wedge notch refers to an image of the inclined cross-sectional surface of an inspection volume (e.g., a portion of a wafer). The cross-sectional surface is obtained by milling the inspection volume with a FIB pillar configured at an angle GF between 20° and 80° relative to the surface of the wafer support. Preferably, the angle GF relative to the wafer surface falls in the range of 25° to 45°, more preferably in the range of 30° to 36°. Any other delayering method can be used instead of milling, such as laser. The image of the cross-sectional surface (wedge notch) is obtained by imaging the cross-sectional surface using a charged particle beam imaging system, wherein the charged particle beam imaging system is configured with an angle GE relative to the normal of the wafer support surface, for example, between 0° and 50°, particularly between 0° and 30° or between 0° and 20°, such as 15°.

[0018] An inspection volume refers to a subset of a wafer containing semiconductor structures. Preferably, an inspection volume contains multiple semiconductor structures of the same design. A semiconductor structure refers to any type of structure on a wafer, particularly high aspect ratio structures such as VIAs or channels.

[0019] Cross-sectional features refer to the structures in a cross-sectional image of a volume. Cross-sectional features can come from groups including: points (e.g., centroid, center point, centroid, or contour point), lines (e.g., tangents, intersections, distances, normals, secants, bounding boxes), curves (e.g., contours, contour sections), edges, and geometries (e.g., polygons, circles, ellipses, etc.).

[0020] A reference image is an acquired or simulated image, such as a cross-sectional image of a reference volume obtained by milling at arbitrary angles and depths, a top view of a reference volume, a slice parallel to a wafer support, or a wedge cut of a reference volume. A reference volume may include different inspection volumes, such as inspection volumes obtained from the same or similar designs using the same or similar manufacturing processes. Alternatively, a reference volume may be simulated. At least one reference image can be obtained from a wafer design or model, such as a CAD model, or it can be simulated. For such artificial reference images, the appearance of the acquired image can be simulated, for example, using machine learning methods (e.g., training a generative adversarial network to mimic the appearance).

[0021] The reference position of a cross-sectional feature refers to the location of the cross-sectional feature in at least one reference image.

[0022] Measurements of semiconductor structures preferably refer to spatial measurements of 3D semiconductor structures that can be used for defect detection, such as length, size, diameter, angle, volume, shape, tilt, wobbling, deviation from a certain value (e.g., deviation from a standard value or average), or statistical measurements thereof (e.g., average measurements), variance of measurements obtained from the 3D semiconductor structure, or measurements at some other time, or certain quality measurements obtained from such measurement distribution.

[0023] Obtaining the reference location of a cross-sectional feature by using at least one reference image provides a more accurate reference location compared to, for example, assuming a regular hexagonal grid as the reference location. This is because at least one reference image may contain, for example, lateral or depth-related distortions or further imaging effects due to the imaging process, such as variations in contrast, sharpness, or brightness, noise, charging effects, and effects due to variations in the shape and size of the electron beam. Since distortion and further imaging effects are included in the examination volume and at least one reference image, the reference location contains the same error as the location of the cross-sectional feature. Therefore, one or more measurements representing a 3D semiconductor structure can be obtained more accurately.

[0024] The method uses only a single wedge cut for each inspection volume and at least one reference image to obtain measurements of the semiconductor structure. At least one reference image (or a subset thereof) can be reused to obtain measurements of different inspection volumes with essentially the same design. In this way, machine time, effort, resources, and computation time are saved.

[0025] A single reference image is sufficient to obtain the reference location of a cross-sectional feature. By using two or more reference images, the reference location can be obtained more accurately due to the additional information available. For example, the reference locations of all reference images can be averaged. Furthermore, different reference images can be used for cross-sectional features at different depths. In this way, 3D representative semiconductor structures of various shapes can be generated and inspected, such as shapes that vary with depth, causing their cross-sectional features to differ at different depths. Thus, the method can be applied to a wider range of inspection volumes.

[0026] Image analysis methods can be used to obtain the reference location of cross-sectional features in at least one reference image. These image analysis methods include edge detection, contour extraction (such as active contours), centroid calculation, geometric shape fitting, Hough transform, pattern matching, energy optimization methods (such as variational methods or graphic cutting), and machine learning methods (such as object detection, recognition, or segmentation methods).

[0027] In the example, the method further includes determining the depth of cross-sectional features within the volume to be examined. To do this, the location of additional cross-sectional features of other structures within the volume can be determined. Examples of other structures include isolator lines or layers, metal lines or layers, semiconductor lines or layers, or word lines, etc. Image analysis methods can be used to detect other structures in the wedge cut, such as edge detection, contour extraction (e.g., active contouring), centroid calculation, geometry fitting, energy minimization methods (e.g., variational methods or pattern cutting), and machine learning methods (e.g., object detection, recognition, or segmentation methods, etc.). For example, these other structures extend parallel to the wafer surface. Their depths are typically known with high accuracy. Using existing knowledge of the depths of other structures, the depth of cross-sectional features within the volume to be examined can be determined.

[0028] For example, as shown in WO 2021 / 180600 A1, using existing knowledge of the depths of these other structures, such as from the design, the depths of cross-sectional features can be obtained with high accuracy relative to other cross-sectional features, for example, using trigonometric functions and angles GF and GE. For instance, the depth of any boundary or surface of each layer parallel to the wafer surface can often be known with very high accuracy and remains constant over a large area of ​​the wafer due to the planar fabrication techniques involved in wafer manufacturing.

[0029] Alternatively, if the tilt angle of the FIB and CPB imaging systems and the location of the examination volume are known, the depth of the cross-sectional features can be determined based on their lateral position in the wedge-shaped incision.

[0030] In the example, image analysis methods or machine learning methods (such as registration methods) are used to assign cross-sectional features in the wedge cut to corresponding cross-sectional features of the same semiconductor structure in at least one reference image. Based on this assignment, the position of the cross-sectional feature in the wedge cut can be compared with a reference position of the cross-sectional feature in at least one reference image. Specifically, each cross-sectional feature in the wedge cut is assigned to a cross-sectional feature in at least one reference image. The deviation between the position of the cross-sectional feature and the corresponding (assigned) reference position can be used to obtain one or more measurements of the semiconductor structure in the examination volume. In this way, one or more measurements can be obtained more accurately.

[0031] In a preferred embodiment, cross-sectional features are clustered according to their depth within the inspection volume. Cross-sectional features at the same or similar depths within the inspection volume lie approximately on lines orthogonal to the FIB direction. Therefore, cross-sectional features can also be clustered according to their coordinates along the FIB direction. For each cluster, the lateral displacement of the specific cluster is obtained from the lateral displacement of the cross-sectional features within the cluster. The lateral displacement of the specific cluster can be the average lateral displacement of the cross-sectional features within the cluster. Therefore, for each cluster (relative to depth or coordinates along the FIB direction), the average lateral displacement within the wedge cut is determined. Alternatively, the median lateral displacement, or some lateral displacement obtained from the distribution of lateral displacements within each cluster, such as the average lateral displacement after removing outliers, can be used. The lateral displacement of the specific cluster can then be used instead of the lateral displacement to obtain one or more measurements of the semiconductor structure within the inspection volume. In this way, more accurate and reliable measurements can be obtained.

[0032] In a preferred embodiment, the method further includes generating a 3D representative semiconductor structure by incorporating a lateral displacement between one or more locations of a cross-sectional feature and its reference location to the location of the reference semiconductor structure at a corresponding depth. The 3D semiconductor structure can be measured by analyzing the deviation between one or more locations of the cross-sectional feature and its reference location. Using the 3D representative semiconductor structure, further measurements can be obtained from the semiconductor structure in the inspection volume, such as regarding the shape or path or cross-section of the 3D representative semiconductor structure. Since the distortion and further imaging effects contained in the wedge cut are also included in at least one reference image, the 3D representative semiconductor structure is determined with increased accuracy from a single wedge cut due to reduced distortion and further imaging effects. The 3D representative semiconductor structure can be used to obtain further measurements of the semiconductor structure in the inspection volume.

[0033] A 3D representative semiconductor structure refers to a virtual semiconductor structure that represents the semiconductor structure within an examination volume, such as the average semiconductor structure within the examination volume. For example, it can be constructed from cross-sectional features of different semiconductor structures at different depths within the examination volume. The representative semiconductor structure is generated using a reference semiconductor structure and the lateral displacement between the position of the cross-sectional features in the wedge cut and the reference position of the cross-sectional features in at least one reference image. Instead of generating a time-consuming 3D reconstruction of every semiconductor structure in the examination volume, the 3D representative semiconductor structure is reconstructed only from a single wedge cut. Therefore, computation time and memory requirements are reduced, and yield is increased.

[0034] According to one aspect of the invention, a reference semiconductor structure is obtained from a reference volume with the same design as the inspection volume. The reference semiconductor structure can be obtained, for example, by selecting one of the semiconductor structures in the reference volume, or by averaging two or more semiconductor structures in the reference volume. Preferably, the averaged semiconductor structures have the same design.

[0035] According to another aspect of the invention, a reference semiconductor structure is generated based on existing knowledge of the semiconductor structure in the inspection volume. When existing knowledge of the semiconductor structure in the inspection volume is available, the reference semiconductor structure can be simulated. For example, the reference semiconductor structure can be simulated as a channel extending perpendicularly to the wafer surface with a specific shape or diameter. Alternatively, cross-sections of the reference semiconductor structure with a specific shape or diameter, etc., at different depths can be simulated and interpolated, etc.

[0036] In the example, the lateral displacements between the positions of the cross-sectional features in the wedge-shaped cut and the reference position are clustered, producing lateral displacements for specific clusters as described above. Then, for each cluster, a 3D representative semiconductor structure is generated by modifying the position of the reference semiconductor structure at the corresponding cluster depth using the lateral displacements of the specific clusters. For example, a 3D representative semiconductor structure is generated by adding the lateral displacements of the specific clusters for each cluster to the position of the reference semiconductor structure at the corresponding cluster depth. The centroid of the 3D representative semiconductor structure can be obtained, for example, by interpolating the modified position of the reference semiconductor structure. The cross-sectional features can be mapped to the modified positions, and a 3D reconstruction of the 3D representative semiconductor structure is obtained through interpolation.

[0037] Reference images can be obtained from the inspection volume itself, particularly from cross-sectional images of the inspection volume parallel to a surface of the inspection volume or parallel to the wafer support at any depth, such as images of the surface of the inspection volume, like top-view or bottom-view images. The reference image does not contain another wedge cut in the inspection volume. Obtaining at least one reference image using the inspection volume itself eliminates the need for an additional reference volume, thus saving computation time, memory space, and user effort. Furthermore, distortions and further imaging effects in at least one reference image are obtained directly from the inspection volume and are therefore similar to deformations and further imaging effects in a wedge cut. However, defects or deviations from the standard may be contained within the inspection volume, which will not be represented by the following 3D representative semiconductor structure.

[0038] In a preferred embodiment of the invention, at least one reference image is obtained from a reference volume having at least substantially or substantially the same design as the inspection volume, or having the same design as the inspection volume and obtained under the same or similar manufacturing conditions as the inspection volume. The reference volume differs from the inspection volume. For example, it may be acquired using different acquisition settings, different machines, different lithographic masks, different time points, etc. In one example, at least one reference image comprises an image of the cross-sectional surface of the reference volume at any angle and depth, such as a slice parallel to the surface of the reference volume or wafer support, or a wedge cut of the reference volume, or an image of the surface of the reference volume, such as a top view or bottom view. By deriving the reference position of the cross-sectional feature from at least one reference image of the reference volume, the position of the cross-sectional feature in the wedge cut and the reference position are subject to the same distortion and further imaging effects as the inspection volume. Therefore, the distortion does not include the lateral displacement between the position of the cross-sectional feature in the wedge cut and the corresponding reference position. In this way, the accuracy of one or more measurements and the accuracy of the 3D representative semiconductor structure are improved.

[0039] In one example, the reference volume includes different inspection volumes, specifically those obtained using the same or similar design files and manufacturing processes as the inspection volumes. By using different reference volumes to obtain at least one reference image, it is ensured that at least one reference image does not contain any defects or deviations from the standard. Therefore, all defects or deviations from the standard are preserved in the following 3D representative semiconductor structure. However, distortion and further imaging effects are not necessarily the same as in the inspection volumes. Furthermore, generating reference volumes requires computation time, memory space, and user effort.

[0040] In another example, the reference volume can be simulated using a design such as a CAD file or some other model of the semiconductor structure within the reference volume. In this way, the reference volume can be defect-free. It can be free of distortion and further imaging effects. Alternatively, distortion and further imaging effects can be simulated within the reference volume.

[0041] In a preferred example, at least one reference image includes a cross-sectional image of the inspection volume parallel to the surface of the inspection volume and / or a top view image of the reference volume or a reference wedge cut of the reference volume, wherein the design of the reference volume is at least substantially the same as that of the inspection volume.

[0042] In the example, existing knowledge about the semiconductor structures in the reference volume is used to obtain the reference position. Specifically, the existing knowledge may include positional information, such as existing knowledge about the position, orientation, or angle of the semiconductor structures in the reference volume, or relative positional information, such as existing knowledge about the distance, relative orientation, minimum distance, or intersection of two or more semiconductor structures in the reference volume. In addition to at least one reference image, existing knowledge can also be used to determine the reference position of cross-sectional features. For example, image analysis can first be used to detect the reference position of cross-sectional features in at least one reference image. Then, the existing knowledge can be used to modify or optimize the detected reference position, for example, by fitting a regular grid to the detected reference position, or by using a regular grid as a soft constraint so that the reference position is close to the regular grid, but not necessarily located on the regular grid. In this way, a more accurate reference position can be obtained.

[0043] In a preferred embodiment, at least one reference image comprises a top-view image of a reference volume. The top-view image is an image of the surface of the reference volume obtained using a cross-beam imaging system with the surface oriented perpendicular to the wafer support stage (i.e., oriented at angle GE=0°). The top-view image is obtained under the same conditions as the inspection volume and therefore contains the same lateral distortion. The reference position of the cross-sectional feature can then be determined based on the lateral position of the cross-sectional feature in the top-view image. By deriving the reference position of the cross-sectional feature from the top-view image, the position of the cross-sectional feature in the wedge notch and the reference position are affected by the same distortion and further imaging effects. Therefore, distortion and further imaging effects are reduced, and the accuracy of one or more measurements and the accuracy of the 3D representative semiconductor structure are improved. For example, under the assumption that the reference position of the cross-sectional feature is the same at every depth of the inspection volume, the position of the cross-sectional feature in the top-view image can be used as the reference position at all depths. Alternatively, a mesh can be fitted to the position of the cross-sectional feature in the top-view image, such as a regular hexagonal mesh or a mesh obtained from a design file. In this way, mesh parameters can be adjusted to achieve higher accuracy in the reference position of the cross-sectional feature. This, in turn, improves the accuracy of measurements and the accuracy of 3D representation of semiconductor structures. Even if the assumption that there is the same reference position at all depths does not hold, the deviation of the position of the cross-sectional features in the top view image from the reference position provides information about lateral distortion, which can also be used to adjust the reference position at other depths of the inspected volume.

[0044] According to a preferred embodiment of the invention, at least one reference image includes a reference wedge cutout of a reference volume. The reference volume is generated under the same or similar manufacturing conditions as the inspection volume, based on the same or similar design. The reference wedge cutout is generated using the same imaging process as that used to obtain the wedge cutout of the inspection volume for study. Since the reference wedge cutout is generated under the same or similar manufacturing conditions, it contains the same or similar lateral and depth-related distortions, as well as further imaging effects. A reference location for a cross-sectional feature can then be determined within the reference wedge cutout. By using the reference wedge cutout to determine the reference location, the reference location is affected by the same lateral and depth-related distortions and other imaging effects as the location of the cross-sectional feature. Therefore, distortion and other imaging effects are reduced, and the accuracy of one or more measurements, as well as the accuracy of the 3D representative semiconductor structure, is improved.

[0045] In the example, the depth range of the wedge cut is the same as that of one or more of the reference images. When refocusing at the same depth range, the distortion is more similar compared to using different depth ranges. In this way, the accuracy of the measurement and the accuracy of the 3D representative semiconductor structure can be improved.

[0046] In the example, at least one reference image comprises two or more reference images, such as a top view of the reference volume and a reference wedge cut of the reference volume. For example, the mesh parameters can then be adjusted to conform to the reference locations of the cross-sectional features obtained from all two or more reference images. In another example, the reference locations obtained from two or more reference images can be averaged. In this way, the accuracy of the measurement and the accuracy of the 3D representative semiconductor structure can be further improved.

[0047] In this example, the reference locations for the cross-sectional features are determined by solving an optimization problem. This optimization problem may, for example, involve a system of equations or a regression problem. The optimization problem may, for example, fit a mesh to a set of reference locations obtained from at least one reference image. Solving the optimization problem improves the accuracy of the measurement and the accuracy of the 3D representative semiconductor structure.

[0048] According to embodiments of the present invention, a method for obtaining a 3D representative semiconductor structure from a single wedge cut further includes obtaining one or more measurements from the 3D representative semiconductor structure. Measurements may include, for example, tilting or wobbling of the representative semiconductor structure, measuring diameter variations in the thickness of the representative semiconductor structure, variations in other parameters of the representative semiconductor structure, defects, etc. Depending on the measurements, a 3D reconstruction of the 3D representative semiconductor structure is required, or specific properties of the 3D representative semiconductor structure (e.g., centroid line) are sufficient to obtain the measurements. For example, measurements can be obtained using predefined measurement specifications (e.g., critical values ​​indicating specific parameters such as maximum or minimum diameter) or by applying machine learning. For example, a machine learning model can be trained to use a representation of the 3D representative semiconductor structure as input and the measurements as output, such as diameter, defect type, defect segmentation, or defect detection.

[0049] In the example, the method further includes detecting defects based on one or more measurements of a 3D representative semiconductor structure. For example, defects can be detected by comparing the obtained measurements with standard measurements (e.g., predefined measurements, target measurements, probability distributions of measurements, or intervals indicating acceptable values, minimum values, or maximum values). Alternatively, a machine learning model can be trained to detect defects from the measurements. Standard measurements can be obtained from sample data that is primarily defect-free.

[0050] A computer program according to an embodiment of the present invention includes instructions that, when executed by a computer, cause the computer to perform any of the methods described in the above embodiments or examples.

[0051] A computer-readable medium according to an embodiment of the present invention stores thereon a computer program executable by a computing device, the computer program comprising code for performing the method as described in any of the above embodiments or examples.

[0052] The dual-beam device according to embodiments of the present invention is configured to perform any of the methods described in any of the above embodiments or examples.

[0053] The invention described by way of examples and embodiments is not limited to the embodiments and examples described, but can be practiced by those skilled in the art through various combinations or modifications thereof. Attached Figure Description

[0054] Figure 1a A schematic diagram of the 3D memory structure is shown;

[0055] Figure 1b This demonstrates the required measurements for the HAR structure in metrology applications;

[0056] Figure 2aThe imaging setup for imaging a cross-section parallel to the wafer surface is shown.

[0057] Figure 2b The sparse imaging setup used for imaging a wedge-shaped cut in a 3D memory structure is shown.

[0058] Figure 3 A dual-beam device for obtaining wedge-shaped cuts in wafers is shown;

[0059] Figure 4 A flowchart is shown for a method of obtaining measurements of semiconductor structures in an inspection volume from a wedge-shaped cut;

[0060] Figure 5 This demonstrates how cross-sectional features from a single wedge-shaped cut can generate a 3D representative semiconductor structure.

[0061] Figure 6 This demonstrates how a 3D representative semiconductor structure is generated from the lateral displacement between the location of a reference semiconductor structure and the location of a cross-sectional feature and the reference location.

[0062] Figure 7 A top-view image of the inspected volume is displayed;

[0063] Figure 8 The reference volume and reference wedge cut are shown; and

[0064] Figure 9 A dual-beam apparatus according to an embodiment of the present invention is schematically shown, which can be used to obtain measurements of semiconductor structures in an examination volume. Detailed Implementation

[0065] In the following description, advantageous exemplary embodiments of the invention are described and schematically illustrated in the accompanying drawings. Throughout the drawings and description, the same reference numerals are used to describe the same features or parts. Dashed lines indicate optional features.

[0066] Figure 1a A schematic diagram of an inspection volume 10 in a 3D memory structure (NAND structure) in the form of a wafer is shown. The top and bottom portions of the structure belong to the gate logic and include bit lines 12, source lines 14, select gates 16, and back gates 22. Throughout the memory structure 10, densely arranged semiconductor structures 18 in the form of HAR structures (channels) extend perpendicularly to the wafer surface. Word lines 20 extend parallel to the wafer surface (along the xy direction) at a specific depth. Figure 1b The desired measurements 26 of the semiconductor structure 18 for metrology applications are shown, such as channel position or channel diameter at different depths, or channel tilt, channel orientation, or wobbling (deviation of the semiconductor structure from its target position).

[0067] To measure 3D semiconductor structures, cross-sectional images can be used. These cross-sectional images can be generated using a dual-beam setup that includes at least a FIB column and a charged particle beam imaging system (e.g., a scanning electron microscope (SEM)).

[0068] Figure 2a A common imaging setup is shown for imaging a cross-section 28 parallel to the wafer surface in slicing and imaging techniques. A FIB pillar mills the wafer surface in a FIB direction 30 parallel to the wafer surface (i.e., along the slicing plane), thus forming the cross-section 28. A charged particle beam imaging system (e.g., in the form of a SEM) images the cross-sectional surface 28 in a SEM direction 32 orthogonal to the wafer surface, thus forming a cross-sectional image. The cross-sectional image may be parallel to the wafer surface or oriented at any other angle relative to the wafer surface.

[0069] Figure 2b A sparse imaging setup for imaging a wedge notch is shown. FIB pillars mill the wafer surface along FIB direction 30, which forms an angle of approximately 45° with respect to the wafer surface. The SEM is oriented perpendicular to the wafer surface. Desired measurements 26 of semiconductor structures 18 at different depths within the wafer can be derived from different lateral positions of the semiconductor structures 18 within a single wedge notch 34. However, due to distortion in the wedge notch, measurements 26 can only be obtained with limited accuracy.

[0070] Figure 3 A dual-beam apparatus 36 for obtaining a wedge-shaped notch in wafer 38 is shown. Wafer 38 is provided having several measurement positions 40 and 40', defined, for example, in a positional diagram generated by an inspection tool or from design information. Wafer 38 is placed on wafer support stage 42. The measurement positions 40 of wafer 38 are aligned with a five-axis wafer stage (not shown) at the intersection 44 of the dual-beam apparatus 36, which includes an FIB column 46 with a FIB optical axis 48 and a charged particle beam (CPB) imaging system 50 with a CPB optical axis 52. At the intersection 44 of the two optical axes of the FIB and CPB imaging systems, the wafer surface is configured to be tilted at an angle GF to the FIB optical axis 48. The CPB optical axis 52 forms an angle GE with the z-axis perpendicular to the wafer plane. The FIB optical axis 48 and the CPB optical axis 52 may lie in a plane orthogonal to the surface of the wafer support stage 42. When the FIB 54 strikes the surface of wafer 38 at an angle GF, the inclined cross-sectional surface is milled into wafer 38 at inspection position 40 at an angle GF between approximately 20° and 60° by ion beam milling. Figure 3In the example, the tilt angle GF is approximately 30°. Due to the beam divergence of focused ion beams (such as gallium ion beams), the actual tilt angle can deviate from the tilt angle GF by 1° to 4°. When the charged particle beam imaging system tilts the wafer normals 50 at an angle GE, an image of the milled surface will be obtained. Figure 3 In the example, the angle GE is less than 15°. During imaging, a charged particle beam is scanned by the scanning unit of the CPB imaging system 50 along a scanning path on the cross-sectional surface of the wafer 38 at measurement position 40, generating secondary particles and scattered particles. A particle detector 56 collects at least some of the secondary and scattered particles and transmits the particle count to a control unit 58. The control unit 58 controls the charged particle beam imaging system 50, the FIB pillar 46, and the FIB 54, and is connected to a control unit 60 to control the position of the wafer 38 mounted on the wafer support stage 42 via a wafer stage (not shown). The control unit 58 communicates with an operation unit 62, which moves via the wafer stage to trigger, for example, the placement and alignment of the measurement position 40 of the wafer 38 at intersection 44, and repeatedly triggers operations such as FIB milling, image acquisition, and platform movement. Each intersecting surface is imaged using a substantially vertical charged particle imaging beam 64, generated by, for example, a scanning electron microscope or any other charged particle beam microscope (e.g., a helium ion microscope (HIM)). This process is further described in WO 2021 / 180600 A1, which is incorporated herein by reference.

[0071] Figure 4 A flowchart of a method 68 for obtaining one or more measurements of a semiconductor structure from a single wedge cut in an inspection volume according to an embodiment of the present invention is shown. The method includes: in step M1, obtaining a wedge cut in the inspection volume by milling a cross-sectional surface in the inspection volume using a FIB pillar configured at an angle GF into the inspection volume, and imaging the cross-sectional surface using a charged particle beam imaging system to obtain the wedge cut; in step M2, determining the position of a cross-sectional feature of the semiconductor structure in the wedge cut; in step M3, determining a reference position of the cross-sectional feature from at least one reference image of the semiconductor structure; and in step M4, obtaining one or more measurements of the semiconductor structure in the inspection volume using a lateral displacement between the position of the cross-sectional feature and the reference position.

[0072] The positions of the cross-sectional features of the semiconductor structure in the wedge-shaped cut 34 and the reference positions in at least one reference image are lateral positions. The positions relative to a certain coordinate system can be obtained. Image analysis methods can be used to detect the cross-sectional features in the wedge-shaped cut 34 and at least one reference image, such as edge detection, contour extraction (e.g., active contours), centroid calculation, geometric shape fitting, Hough transform, pattern matching, energy optimization methods (e.g., variational methods or graphic cutting), machine learning methods (e.g., object detection, recognition, or segmentation methods), etc.

[0073] Figure 5 One or more measurements of semiconductor structures 18, 18', 18'', 18''' in inspection volume 10 are shown, generated from a single wedge cut 34. The wedge cut 34 is obtained by milling along the FIB direction 30 at an angle GF using FIB pillars. The positions 73 of the cross-sectional features 72, 72', 72'', 72''' can be obtained using image analysis. Furthermore, at least one reference image 76 can be used to obtain reference positions 78, 78', 78'', 78''' of the cross-sectional features. Lateral displacement in the xy-plane can be obtained using the deviations of the positions of the cross-sectional features 72, 72', 72''', 72''' in the wedge cut 34 from the reference positions 78, 78', 78''' of the cross-sectional features in at least one reference image 76. Measurements of the semiconductor structures can be obtained from the lateral displacement, particularly when the semiconductor structures 18, 18', 18'', 18''' in inspection volume 10 have the same vertical profile or a predefined variation in vertical profile. When at least one reference image 76 is obtained using the same or similar design and manufacturing conditions as the inspection volume, the reference positions 78, 78', 78'', 78''' can be obtained by using at least one reference image 76 instead of using, for example, a predefined regular hexagonal grid, which can reduce distortion and further imaging effects.

[0074] Using the positions of the cross-sectional features 72, 72', 72'', 72''' in the wedge-shaped notch 34, a 3D representative semiconductor structure 70 can be reconstructed by stacking the cross-sectional features 72, 72', 72'', 72''' of different semiconductor structures 18, 18', 18''' to form a single representative semiconductor structure 70. This requires the assumption that all semiconductor structures 18, 18', 18'', 18''' within the examination volume 10 have the same vertical profile or a predefined variation of the vertical profile. Lateral displacement can be used to modify the reference semiconductor structure 69 to obtain the 3D representative semiconductor structure 70. Further measurements of, for example, the shape or cross-section of the 3D representative semiconductor structure can be obtained using the 3D representative semiconductor structure.

[0075] More specifically, for each cross-sectional feature 72, 72', 72'', 72''' in the form of a channel cross-section in the wedge-shaped cut 34, the centroid form in the wedge-shaped cut 34 can be measured. The location (for the i=1...N cross-sectional features of the HAR channel). As mentioned above, the cross-sectional centroid can be determined using additional semiconductor structures (e.g., word lines) or trigonometric functions, angles GE and GF, and the location of the examined volume. The depth. Assuming that all semiconductor structures 18, 18', 18'', 18''' (e.g., channels) in the field of view have the same shape and orientation, a 3D representative semiconductor structure 70 can be obtained.

[0076] set up and This represents the reference position of the centroid of the i-th semiconductor structure. Then, offset or lateral displacement can be used. To obtain a representative 3D semiconductor structure.

[0077] In the example, these lateral displacements can be clustered relative to their depth within the examined volume. For each cluster, the lateral displacement of that specific cluster can then be obtained, as described below regarding... Figure 6 Further description.

[0078] In order to obtain measurements of semiconductor structure 70, the function and This can be defined, for example, as describing the lateral displacement 74 of a representative semiconductor structure 70 at depth z. The centroid of the channel cross-section at a given depth z... The lateral position can be defined as

[0079]

[0080]

[0081] According to the function and This can determine the tilt and oscillation of the representative semiconductor structure 70 (especially the representative channel) in the field of view. Function and This can be obtained by solving optimization problems (such as regression problems) to obtain the function. and Fit to deviation

[0082]

[0083] Regression Problem Assumptions and The parametric functions, such as polynomials of a specific degree (e.g., quadratic), spline functions, or any other parametric functions, are fitted to the lateral displacement between the cross-sectional feature location and the reference location.

[0084]

[0085] Adding information about the function can be done by applying restrictions or using Lagrange multipliers. and Existing knowledge, such as maximum, start, or end values, is available. Therefore, for a sufficient number of measurement locations of the cross-sectional features 72, 72', 72'', 72''' (i.e., the channel centroid), and the corresponding reference locations 78, 78', 78'', 78''', the function can be estimated. and To obtain a representative 3D semiconductor structure, the function... and It can be used to modify the reference semiconductor structure 69, especially by modifying the centroid of the reference semiconductor structure 69.

[0086] Therefore, a single wedge-shaped notch 34 can be used to obtain measurements of the semiconductor structure within an inspection volume. It can also be used to generate a 3D reconstruction of a representative semiconductor structure 70, such as reconstructing the 3D geometry of a representative channel of a 3D memory stack. For example, further measurements can be obtained from the 3D representative semiconductor structure 70, such as using defect profiling or machine learning to identify defect types or defect markers. For example, functions can be used... and Alternatively, a 3D representative semiconductor structure can be used as input data, and defect detection, segmentation, or classification can be used as output to train a machine learning model to detect or classify defects.

[0087] Reference positions can be obtained in various ways. One approach is to use existing knowledge, such as assuming the reference location lies on a predefined grid, like a regular hexagonal grid or some irregular grid. For example, the grid could be defined by the single points, orientation, and distances between semiconductor structures 18, 18', 18'', and 18'''. These parameters can be related to functions... and Together, they were optimized. However, due to distortion in the wedge notch 34 and further imaging effects, the measurement and 3D representation of the semiconductor structure 70 lacked accuracy.

[0088] Alternatively, reference positions 78, 78', 78'', 78''' can be obtained from at least one reference image 76 of semiconductor structures 18, 18', 18''', such as... Figure 5As shown. Reference image 76 refers to an acquired image or a simulated image. At least one reference image 76 can be acquired using the same imaging system as used to acquire inspection volume 10 or a different imaging system. At least one reference image 76 can be simulated, for example, using a wafer design file. The appearance of the simulated reference image 76 can be adapted to the appearance of the acquired image, for example, by using machine learning techniques (such as generative adversarial models). At least one reference image 76 can be obtained from reference volume 80, wherein reference volume 80 has the same or at least substantially the same or similar design as inspection volume 10 and uses the same or similar manufacturing process as inspection volume 10. Alternatively, reference volume 80 may contain artificial volumes, such as simulated semiconductor structures, like polygons obtained from design files.

[0089] Reference positions 78, 78', 78'', 78''' in at least one reference image 76 can be optimized by solving an optimization problem (e.g., an overdetermined system of equations). For example, a mesh can be fitted to at least one reference image by adjusting, for example, the mesh spacing (distance between reference positions), scale, and / or offset. By using at least one reference image 76, imaging conditions, the layout of the semiconductor structure, and depth-dependent effects within the volume can be represented by at least one reference image 76. Therefore, the influence of lateral or depth-dependent distortion or further imaging effects is reduced in the measurement and 3D representation of the semiconductor structure. In this way, the determination of reference positions 78, 78', 78'', 78''' of the cross-sectional features 72, 72', 72''' can be improved, and thus the accuracy of the measurement and the accuracy of the 3D representative semiconductor structure 70 can be improved.

[0090] The cross-sectional features 72, 72', 72'', 72''' in the wedge-shaped cut 34 can then be assigned to cross-sectional features 72, 72', 72'', 72''' in at least one reference image 76, for example, by comparing the positions of the cross-sectional features 72, 72', 72'', 72''' in the wedge-shaped cut 34 with reference positions 78, 78', 78'', 78''' in at least one reference image 76. For example, the cross-sectional features 72, 72', 72'', 72''' in the wedge-shaped cut 34 can be assigned to the nearest cross-sectional features 72, 72', 72'', 72''' in at least one reference image 76. Alternatively or additionally, image analysis methods can be applied to find the cross-sectional features 72, 72', 72'', 72''' in the wedge-shaped cut 34 and the reference image 76.

[0091] Figure 6 This shows the lateral displacement between the position 73 of the cross-sectional feature 72 and the reference position of the cross-sectional feature 78, from which the 3D representative semiconductor structure 70 is generated from the reference semiconductor structure 69.

[0092] Figure 6 a shows a reference volume 80 containing a reference semiconductor structure 69. The reference volume may be a different inspection volume containing a semiconductor structure of the same or at least substantially the same or similar design obtained under the same or similar manufacturing conditions. Alternatively, the reference volume 80 may be simulated or obtained from a design, particularly from the design of inspection volume 10.

[0093] Figure 6 b shows the wedge-shaped cut 34 of the examined volume 10. The wedge-shaped cut 34 contains cross-sectional features 72. The location 73 of the cross-sectional features 72 is indicated by a cross. The cross-sectional features 72 are derived from the centroid of the cross-section of a group of points, lines, curves, edges, and geometric shapes, such as HAR structures (like channels). The location 73 of the cross-sectional features 72 can be obtained using image analysis techniques, such as pattern recognition methods, segmentation methods, or machine learning methods.

[0094] Figure 6 c shows reference image 76, which includes reference position 78 corresponding to position 73 of cross-sectional feature 72 in wedge-shaped notch 34. Reference image 76 can be obtained from reference volume 80, as shown in reference... Figure 6 As described in a. The reference image 76 may, for example, include a top view image of the reference volume 80 or a reference wedge cutout of the reference volume 80. The depth range of the wedge cutout 34 is the same as the depth range of at least one reference image.

[0095] The reference location of the cross-sectional feature 72 can be determined with increased accuracy by solving an optimization problem. For example, existing knowledge about the reference location 78 of the cross-sectional feature 72 in at least one reference image 76 can be used. Such existing knowledge can be obtained, for example, by assuming that the semiconductor structures 18 are configured on a grid. For example, they can be configured on a regular hexagonal grid in the xy plane of the inspection volume 10 and / or extend perpendicularly to the wafer surface (in the z direction). The optimization problem can minimize the deviation of the position of the cross-sectional feature 72 in at least one reference image 76 from the grid, for example, by optimizing the grid parameters (e.g., scaling, offset, and spacing (distance) between grid points). The grid can also be used as a soft constraint in the optimization problem, which encourages the reference locations to be on the grid, but does not require them to be.

[0096] Figure 6Figure d shows the cross-sectional features 72 in the wedge notch 34 assigned to the cross-sectional features in the reference image 76. However, sometimes the semiconductor structure is missing in the wedge notch 34 or the reference image 76. In this case, almost all the cross-sectional features 72 in the wedge notch 34 are assigned to the cross-sectional features in the reference image 76. The lateral displacement 74 between the position 73 of the cross-sectional feature 72 and the reference position 78 is calculated. The cross-sectional features are generally configured on a line in the x-direction. Positions in the wedge notch 34 with the same x-coordinate have the same depth in the inspection volume 10. To increase the robustness of the method, the lateral displacement 74 is clustered relative to the depth of the cross-sectional features 72 in the inspection volume 10. In this case, the clustering can be completed relative to the x-coordinate of the position 73 of the cross-sectional feature 72. Therefore, the cluster 77 contains the cross-sectional features 72 that are generally configured at the same depth in the inspection volume 10. For each cluster 77, the lateral displacement 75 of the specific cluster is obtained from the lateral displacement 74 of the cross-sectional features 72 in the cluster 77. The lateral displacement 75 of a specific cluster may include the average lateral displacement, the median lateral displacement, or the lateral displacement obtained from the distribution of lateral displacements within the cluster 77, such as the average lateral displacement after removing outliers.

[0097] Figure 6 e illustrates how a 3D representative semiconductor structure 70 is generated by modifying the position of a reference semiconductor structure 69 at the corresponding cluster depth for each cluster 77 using a lateral displacement 75 of that specific cluster. For example, the 3D representative semiconductor structure 70 can be obtained by interpolating the modified position of the reference semiconductor structure 69. A cross-sectional feature 72 can be mapped to the modified position of the reference semiconductor structure 69. A parameterized 3D surface or parameterized function can be fitted to the stacked cross-sectional feature 72 to obtain a 3D reconstruction of the 3D representative semiconductor structure 70. For example, to obtain a measurement, the centerline of the 3D representative semiconductor structure 70 can be calculated as a function of depth Z. For example, this function represents the tilt or wobbling of the representative semiconductor structure 70 in the Z direction.

[0098] according to Figure 7In the illustrated embodiment of the invention, at least one reference image 76 comprises a top view image 79 of a reference volume 80 (e.g., inspection volume 10). The top view image 79 is obtained relative to a wafer support stage at an angle GE = 0° using a charged particle beam imaging system. From the top view image 79 of the reference volume 80 (e.g., inspection volume 10), the layout of cross-sectional features 72 on the wafer surface can be derived under the same imaging conditions as the inspection volume, and therefore includes the same lateral distortion. The positions of the cross-sectional features 72 in the top view image 79 can be obtained, for example, using image analysis, such as edge detection, centroid detection, contour detection, geometry detection methods (e.g., active contouring), Hough transform, or machine learning methods for object detection, recognition, or segmentation. Therefore, due to (partial) compensation for lateral distortion, the reference position 78 of the cross-sectional features 72 detected from the top view image 79 can be obtained with greater accuracy.

[0099] In the example, a mesh (specifically a regular hexagonal mesh) can be fitted to the detection location of the cross-sectional feature 72 in the top view image 79 of the reference volume 80 to obtain a reference location 78 for the cross-sectional feature 72. This can be done by solving a system of equations, for example, using the least squares method. Where existing knowledge about the semiconductor structures 18 in the inspection volume is available, for example, all semiconductor structures 18 are oriented perpendicular to the wafer surface, the reference location 78 obtained from the top view image 79 can be directly used as a reference location 78 for all depths of the inspection volume, thereby compensating for lateral distortion and further imaging effects. Otherwise, information about lateral distortion can be derived from the deviation between the cross-sectional feature 72 detected in the top view image 79 and the fitted regular mesh. This information can be used to adjust the reference location 78 at greater depths in the inspection volume 10, which may be obtained, for example, from a design file.

[0100] according to Figure 8 In the illustrated embodiment of the invention, at least one reference image 76 includes a reference wedge cutout 81 of a reference volume 80. The reference volume 80 is produced using the same design as the inspection volume and the same or similar manufacturing process as the inspection volume, and the reference wedge cutout 81 is produced using the same imaging process as the wedge cutout 34. Since the reference volume 80 and the reference wedge cutout 81 are obtained using the same imaging process, the same lateral and depth-related distortions, as well as further imaging effects, will affect both the reference volume 80 and the reference wedge cutout 81. Therefore, the reference wedge cutout 81 can be used to improve the accuracy of measurements and the accuracy of the 3D representative semiconductor structure 70.

[0101] The accuracy of the measurement and the accuracy of the 3D representative semiconductor structure 70 can be improved by using at least one reference image 76 that includes distortion and other imaging effects.

[0102] Figure 9 A system 84 according to an embodiment of the present invention is schematically shown, which can be used to obtain one or more measurements of a semiconductor structure in an inspection volume from a single wedge cut 34, or to generate a 3D representative semiconductor structure from a single wedge cut 34 of an inspection volume. System 84 includes a dual-beam device 36 and a processing device 86. The dual-beam device 36 is coupled to the processing device 86, for example via cable or wirelessly. The dual-beam device 36 includes a FIB pillar 46 and a charged particle beam imaging system 50, and is configured to obtain the wedge cut 34 of a wafer 38.

[0103] The dual-beam device 36 can provide a wedge-shaped notch 34 to the processing device 86. The processing device 86 includes one or more processors 88, such as a CPU or GPU. The one or more processors 88 can receive the wedge-shaped notch 34 via an interface 90. The one or more processors 88 can load program code from one or more machine-readable hardware storage devices 92. The one or more processors 88 can execute the program code. When executing the program code, the one or more processors 88 perform techniques such as those described herein, such as obtaining measurements from a semiconductor structure in an inspection volume, generating a 3D representative semiconductor structure, detecting the wedge-shaped notch, top-view images, or cross-sectional features in an inspection volume, calculating measurements of the 3D representative semiconductor structure, detecting defects, etc. For example, when loading program code from one or more machine-readable hardware storage devices 92, the one or more processors 88 can execute... Figure 4 The method is illustrated. System 84 may optionally include a user interface 94, for example, for setting parameters, indicating measurement specifications, for natural language processing, and for viewing cross-sectional features. System 84 may optionally include a database 96. Database 96 may be used, for example, to load groups of measurement specifications. System 84 may optionally include a visualization device 98 for visualizing to the user 3D representative semiconductor structures, cross-sectional features, measurements, measurement specifications, etc.

[0104] For example, the methods disclosed herein can be used during wafer research and development or during wafer mass production, or for process window verification or enhancement. Additionally, the methods disclosed herein can also be used for defect detection in X-ray imaging datasets of wafers, for example, after packaging semiconductor devices for delivery.

[0105] The terms "embodiment," "example," or "aspect" used throughout this specification mean that a particular feature, structure, or characteristic described in connection with an embodiment, example, or aspect is included in at least one embodiment, example, or aspect. Therefore, the phrases "according to an embodiment," "according to an example," or "according to an aspect" appearing in various places in this specification do not necessarily all refer to the same embodiment, example, or aspect, but may refer to the same embodiment, example, or aspect. Furthermore, in one or more embodiments, as will be apparent to those skilled in the art according to the present invention, particular features or characteristics can be combined in any suitable manner.

[0106] Furthermore, while some embodiments, examples, or aspects described herein contain some but not all other features found in other embodiments, examples, or aspects, combinations of features from different embodiments, examples, or aspects should be within the scope of the claims and form different specific implementations, as will be understood by those skilled in the art.

[0107] This invention may be described by the following terms:

[0108] 1. A method 68 for obtaining one or more measurements of a semiconductor structure 18 from a single wedge-shaped cut 34 of an inspection volume 10, the method 68 comprising:

[0109] - A wedge-shaped cut 34 in the inspection volume 10 is obtained by milling a FIB post 46 configured at an angle GF into the inspection volume 10, thereby exposing a cross-sectional surface in the inspection volume 10, and the cross-sectional surface is imaged by a charged particle beam imaging system 50 to obtain the wedge-shaped cut 34.

[0110] -Determines the position of the cross-sectional feature 72 of the semiconductor structure 18 in the wedge-shaped cut 34;

[0111] - The reference position of the cross-sectional feature 72 is determined based on at least one reference image 76 of the semiconductor structure 18;

[0112] - Use the lateral displacement 74 between the position of the cross-sectional feature 72 and the reference position 78 to obtain one or more measurements of the semiconductor structure 18 in the inspection volume 10.

[0113] 2. The method described in Clause 1 further includes determining the depth of the cross-sectional feature 72 in the inspection volume 10.

[0114] 3. The method as described in any of the preceding clauses, wherein the cross-sectional feature 72 in the wedge cut 34 is assigned to the cross-sectional feature 72 in at least one reference image 76.

[0115] 4. The method as described in any of the preceding clauses, wherein the cross-sectional features 72 are clustered according to their depth in the inspection volume 10, wherein for each cluster 77, a lateral displacement 75 of a particular cluster is obtained from the lateral displacement 74 of the cross-sectional features 72 in the cluster 77, and wherein the lateral displacement 75 of the particular cluster is used instead of the lateral displacement 74.

[0116] 5. The method as described in Clause 4, wherein the lateral displacement 75 of a particular cluster is the average lateral displacement of the cross-sectional feature 72 in the cluster 77.

[0117] 6. The method as described in any of the preceding clauses further comprises generating a 3D representative semiconductor structure 70 by incorporating a lateral displacement between one or more locations of the cross-sectional feature 72 and its reference location into the location of the reference semiconductor structure at a corresponding depth.

[0118] 7. The method as described in Clause 6, wherein the reference semiconductor structure is obtained from a reference volume 80 of the same design as the inspection volume 10.

[0119] 8. The method as described in Clause 6 or 7, wherein the reference semiconductor structure is generated based on existing knowledge of the semiconductor structure in the examination volume 10.

[0120] 9. The method of any one of Clauses 6 to 8, wherein one or more measurements are obtained using a 3D representative semiconductor structure 70.

[0121] 10. The method as described in any of the preceding clauses, wherein at least one reference image 76 is obtained from a reference volume 80 of the same design as the inspection volume 10.

[0122] 11. The method as described in Clause 10, wherein the reference volume 80 includes the inspection volume 10 or one or more portions thereof.

[0123] 12. The method as described in Clause 10 or 11, wherein at least one reference image comprises a top view image 79 of reference volume 80.

[0124] 13. The method of any one of clauses 10 to 12, wherein at least one reference image includes a reference wedge cut 81 of a reference volume 80.

[0125] 14. The method as described in any of the preceding clauses, wherein the depth range of the wedge cut 34 is the same as the depth range of at least one reference image.

[0126] 15. The method as described in any of the preceding clauses, wherein the reference position of the cross-sectional feature 72 is determined by solving an optimization problem.

[0127] 16. The method as described in any of the preceding clauses, wherein existing knowledge about the semiconductor structure 18 in the reference volume 80 is used to determine the reference location of the cross-sectional feature 72.

[0128] 17. The method as described in any of the preceding clauses, wherein the semiconductor structure 18 is a high aspect ratio structure.

[0129] 18. The method as described in any of the preceding clauses, wherein the cross-sectional feature 72 is derived from a group comprising points, lines, curves, edges, and geometries.

[0130] 19. The method as described in any of the preceding clauses further comprises detecting defects from one or more measurements of the semiconductor structure 18.

[0131] 20. The method as described in any of the preceding clauses, wherein the tilt angle GF is measured relative to the surface of the wafer support stage 42 and falls between 20° and 80°, preferably between 25° and 45°, and most preferably between 30° and 36°.

[0132] 21. A computer program containing instructions that, when executed by a computer, cause the computer to perform the method as described in any one of clauses 1 to 20.

[0133] 22. A computer-readable medium having stored thereon a computer program executable by a computing device, the computer program comprising code for performing the method as described in any one of clauses 1 to 20.

[0134] 23. A dual-beam device configured to perform any of the methods described in any one of Clauses 1 to 20.

[0135] In summary, the present invention relates to a method 68 for obtaining one or more measurements of a semiconductor structure from a single wedge-shaped cutout 34 of an inspection volume 10. The method 68 includes: obtaining a wedge-shaped cutout 34 of the inspection volume 10 by milling a cross-sectional surface in the inspection volume 10 using FIB pillars 46 configured at an angle GF into the inspection volume 10; imaging the cross-sectional surface with a charged particle beam imaging system 50; determining the position of a cross-sectional feature 72 of a semiconductor structure 18 in the wedge-shaped cutout 34; determining a reference position of the cross-sectional feature 72 based on at least one reference image 76 of the semiconductor structure 18; and obtaining one or more measurements of the semiconductor structure 18 in the inspection volume 10 using a lateral displacement 74 between the position of the cross-sectional feature 72 and the reference position 78.

[0136] List of reference numerals

[0137] 10. Check volume

[0138] 12-bit line

[0139] 14 source lines

[0140] 16 Select Gate

[0141] 18, 18', 18'', 18''' Semiconductor Structure

[0142] 20 Interference Structures

[0143] 22 back gate

[0144] 26 Measurements

[0145] 28 Undisturbed cross section

[0146] 30FIB direction

[0147] 32SEM direction

[0148] 34 wedge-shaped incision

[0149] 36 dual-beam device

[0150] 38 chips

[0151] 40 Measurement location

[0152] 42-chip support platform

[0153] 44 intersections

[0154] 46FIB column

[0155] 48 optical axes

[0156] 50 charged particle beam imaging system

[0157] 52 optical axes

[0158] 54FIB

[0159] 56-particle detector

[0160] 58 control unit

[0161] 60 control unit

[0162] 62 operating units

[0163] 64 charged particle imaging beams

[0164] 68 methods

[0165] 69 Reference Semiconductor Structure

[0166] 703D representative semiconductor structure

[0167] 72, 72', 72'', 72''' Cross-sectional Features

[0168] 73 position

[0169] 74 Lateral displacement

[0170] Lateral displacement of 75 specific clusters

[0171] 76 reference images

[0172] Cluster 77

[0173] 78, 78', 78'', 78''' Reference positions

[0174] 79 Top View Images

[0175] 80 reference volume

[0176] 81 Reference wedge cut

[0177] 84 system

[0178] 86 processing unit

[0179] 88 processor

[0180] 90 interface

[0181] 92 Hardware Storage Devices

[0182] 94 User Interface

[0183] 96 Database

Claims

1. A method (68) for obtaining one or more measurements of a semiconductor structure (18) from a single wedge cut (34) of an inspection volume (10), the method (68) comprising: - exposing a cross-sectional surface in the inspection volume (10) by milling into the inspection volume (10) using an FIB column (46) configured at an inclination angle GF to obtain the wedge cut (34) of the inspection volume (10), and imaging the cross-sectional surface with a charged particle beam imaging system (50) to obtain the wedge cut (34); - determining a position of a cross-sectional feature (72) of the semiconductor structure (18) in the wedge cut (34); - determining a reference position of the cross-sectional feature (72) from at least one reference image (76) of the semiconductor structure (18); - using a lateral displacement (74) between the position of the cross-sectional feature (72) and the reference position (78) to obtain the one or more measurements of the semiconductor structure (18) in the inspection volume (10).

2. The method of claim 1, further comprising determining a depth of the cross-sectional feature (72) in the inspection volume (10).

3. The method of any of the preceding claims, wherein the cross-sectional feature (72) in the wedge cut (34) is assigned to a cross-sectional feature (72) in the at least one reference image (76).

4. The method of any of the preceding claims, wherein the cross-sectional features (72) are clustered according to their depth in the inspection volume (10), wherein for each cluster (77) a cluster-specific lateral displacement (75) is obtained from the lateral displacements (74) of the cross-sectional features (72) in the cluster (77), and wherein the cluster-specific lateral displacement (75) is used instead of the lateral displacement (74).

5. The method of claim 4, wherein the cluster-specific lateral displacement (75) is an average lateral displacement of the cross-sectional features (72) in the cluster (77).

6. The method of any of the preceding claims, further comprising generating a 3D representative semiconductor structure (70) by adding the lateral displacement between one or more positions of a cross-sectional feature (72) and its reference position to the position of a reference semiconductor structure at the respective depth.

7. The method of claim 6, wherein the reference semiconductor structure is obtained from a reference volume (80) of the same design as the inspection volume (10).

8. The method of claim 6 or 7, wherein the reference semiconductor structure is generated from existing knowledge of the semiconductor structure in the inspection volume (10).

9. The method of any of claims 6 to 8, wherein the one or more measurements are obtained using the 3D representative semiconductor structure (70).

10. The method of any of the preceding claims, wherein the at least one reference image comprises a cross-sectional image of the inspection volume parallel to a surface of the inspection volume (10).

11. The method according to any of the preceding claims, wherein the at least one reference image comprises an overhead view image (79) of the examination volume (10).

12. The method according to any of the preceding claims, wherein the at least one reference image (76) is obtained from a reference volume (80) of at least substantially identical design as the examination volume (10).

13. The method according to claim 12, wherein the at least one reference image comprises an overhead view image (79) of the reference volume (80).

14. The method according to any of claims 12 or 13, wherein the at least one reference image comprises a reference wedge cutout (81) of the reference volume (80).

15. The method according to any of the preceding claims, wherein the depth range of the wedge cutout (34) is identical to the depth range of the at least one reference image.

16. The method according to any of the preceding claims, wherein the reference position of the cross-sectional feature (72) is determined by solving an optimization problem.

17. The method according to any of the preceding claims, wherein the reference position of the cross-sectional feature (72) is determined using existing knowledge about the semiconductor structure (18) in the reference volume (80).

18. The method according to any of the preceding claims, the semiconductor structure (18) being a high aspect ratio structure.

19. The method according to any of the preceding claims, wherein the cross-sectional feature (72) is from the group comprising a point, a line, a curve, an edge, a geometric shape.

20. The method according to any of the preceding claims, further comprising detecting a defect from the one or more measurements of the semiconductor structure (18).

21. The method according to any of the preceding claims, wherein the tilt angle GF is measured with respect to the surface of the wafer support table (42) and falls between 20° and 80°, preferably between 25° and 45°, most preferably between 30° and 36°.

22. A computer program comprising instructions which, when the program is executed by a computer, cause the computer to carry out the method according to any of the preceding claims.

23. A computer readable medium having stored thereon a computer program, which can be executed by a computing device, the computer program comprising code for performing the method according to any of claims 1 to 21.

24. A dual beam apparatus configured to perform any of the methods according to any of claims 1 to 21.

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