Three-dimensional physical quantity decoupling monitoring system and method based on heterogeneous oscillator array

Abstract

This application discloses a three-dimensional physical quantity decoupling monitoring system and method based on a heterogeneous oscillator array, relating to the field of integrated circuit technology. The system includes: a heterogeneous sensor array, a dual-mixer signal processing chain, a prescaler, a selector, a time-division multiplexed hardware statistical accelerator, and a decoupling algorithm module. This application designs a heterogeneous sensor array, including a logic-dominated aging-sensitive oscillator, a reference oscillator, and an interconnect-dominated oscillator. Utilizing the interconnect delay's insensitivity to voltage but sensitivity to temperature, an orthogonal sensitivity matrix is ​​constructed. A dual-mixer signal processing chain generates beat frequency signals, and the time-division multiplexed hardware statistical accelerator calculates the signal mean and variance in real time, separating temperature and voltage fluctuations. A differential structure is used to suppress common-mode interference to extract aging signals, thereby achieving decoupling monitoring of internal chip parameters and improving monitoring accuracy.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a three-dimensional physical quantity decoupling monitoring system and method based on heterogeneous oscillator arrays. Background Technology

[0002] Currently, the industry and academia mainly use the following three technical solutions for monitoring the internal physical parameters of chips: Solution 1: Odometer technology based on ring oscillator (RO); Solution 2: Critical Path Monitor (CPM) or Canary Flip-flop; Solution 3: On-Chip Analog Sensor / ADC.

[0003] Although the above technologies have been applied, they face three major defects in deep submicron processes: inaccuracy in measurement, inability to separate, and inability to capture, which cannot meet the needs for refined management of chip health status. Summary of the Invention

[0004] The main objective of this application is to propose a three-dimensional physical quantity decoupling monitoring system and method based on heterogeneous oscillator arrays, so as to improve the monitoring accuracy of internal physical parameters of chips.

[0005] To achieve the above objectives, one aspect of this application proposes a three-dimensional physical quantity decoupling monitoring system based on a heterogeneous oscillator array. The system includes: a heterogeneous sensor array, a dual-mixer signal processing chain, a prescaler, a selector, a time-division multiplexing hardware statistical accelerator, and a decoupling algorithm module.

[0006] The heterogeneous sensor array includes a logic-dominated oscillator and an interconnect-dominated oscillator; wherein the logic-dominated oscillator includes an aging-sensitive oscillator and a reference oscillator.

[0007] The dual-mixer signal processing chain includes mixer A and mixer B;

[0008] The aging-sensitive oscillator is connected to the first terminal of the mixer A, and the reference oscillator is connected to the second terminal of the mixer A; the second terminal of the mixer A is also connected to the first terminal of the prescaler.

[0009] The second terminal of the prescaler is connected to the first terminal of the mixer B, and the interconnect-dominant oscillator is connected to the second terminal of the mixer B.

[0010] The third terminal of mixer A is connected to the first terminal of the selector, and the third terminal of mixer B is connected to the second terminal of the selector.

[0011] The third terminal of the selector is connected to the first terminal of the time-division multiplexing hardware statistical accelerator, and the second terminal of the time-division multiplexing hardware statistical accelerator is connected to the decoupling algorithm module.

[0012] In some embodiments, the time-division multiplexing hardware statistical accelerator includes a period measurement unit, an accumulator, a square accumulator, a DSP multiplication unit, and a control state machine;

[0013] The input terminal of the period measurement unit is used to receive the beat frequency signal output by the selector; the first output terminal of the period measurement unit is connected to the input terminal of the accumulator, the second output terminal of the period measurement unit is connected to the input terminal of the DSP multiplication unit, the third output terminal of the period measurement unit is connected to the first terminal of the control state machine, and the fourth output terminal of the period measurement unit is used to output the sample count value.

[0014] The output of the DSP multiplication unit is connected to the input of the square accumulator;

[0015] The second terminal of the control state machine is interconnected with the accumulator, and the third terminal of the control state machine is interconnected with the square accumulator.

[0016] The output of the accumulator is used to output the summation term;

[0017] The output of the square accumulator is used to output the square summation term.

[0018] In some embodiments, the period measurement unit is used to count the number of clock cycles between two rising edges of the beat frequency signal to obtain a count value of the sampling period. x i ;

[0019] The accumulator is used to perform a single accumulation: Acc1 = Acc1 + ... x i ;

[0020] The DSP multiplication unit is used to calculate x i 2 ;

[0021] The square accumulator is used to perform a quadratic accumulation: Acc2 = Acc2 + ... x i 2 ;

[0022] The decoupling algorithm module is used to execute:

[0023] Read Acc1 and Acc2;

[0024] Calculate μ = Acc1 / N; using the temperature coefficient K of the interconnect-dominated oscillator. WireT The current temperature T of the chip under test is obtained by inverse solving; N is the total number of samples;

[0025] Calculate σ 2 = (Acc2 / N) - μ 2 ;Utilizing the voltage sensitivity S of the aforementioned reference oscillator RefV The voltage ripple amplitude is obtained by inverse solving. .

[0026] In some embodiments, the interconnect-dominated oscillator is driven by logic gates and includes metal interconnects reaching a set length threshold;

[0027] More than 90% of the path delay of the interconnect-dominated oscillator is achieved by the delay caused by the resistance and capacitance of the metal wires.

[0028] In some embodiments, in an FPGA, by making the signal wound around or run across columns of multiple logic array blocks, more than 90% of the path delay of the interconnect-dominated oscillator is achieved by the delay of the resistance and capacitance of the metal lines.

[0029] In some embodiments, the aging-sensitive oscillator is composed of CMOS logic gates connected end to end; wherein the CMOS logic gates are lookup tables (LUTs) or inverters in an FPGA;

[0030] The aging-sensitive oscillator operates in normally open mode.

[0031] In some embodiments, the reference oscillator is composed of CMOS logic gates connected end to end; wherein the CMOS logic gates are lookup tables (LUTs) or inverters in an FPGA;

[0032] The reference oscillator operates in a gated mode.

[0033] To achieve the above objectives, another aspect of this application proposes a three-dimensional physical quantity decoupling monitoring method based on a heterogeneous oscillator array. This method is applied to the three-dimensional physical quantity decoupling monitoring system based on a heterogeneous oscillator array as described above. The method includes the following steps:

[0034] By leveraging the physical differences between logic-dominated oscillators and interconnect-dominated oscillators, the following set of equations is established to decouple the measured temperature T and measured voltage V of the chip under test:

[0035] ;

[0036] in,y Logic The frequency normalization variation of the logic-dominated oscillator, y Wire This is the normalized frequency variation of the interconnect-dominated oscillator. S L,T , S L,V These are the sensitivity coefficients of the logic-dominant oscillator to temperature and voltage, respectively. S W,T , S W,V These are the sensitivity coefficients of the interconnect-dominated oscillator to temperature and voltage, respectively.

[0037] The aging parameters of the chip under test are calculated using the differential structure of an aging-sensitive oscillator and a reference oscillator, specifically including:

[0038] ;

[0039] in, A represents the aging parameter to be measured. This represents the initial beat frequency value measured during the calibration phase, used to compensate for fixed offsets caused by process deviations; This indicates that the difference frequency signal processed by mixer A is obtained by subtracting the frequency of the reference oscillator from the frequency of the aging-sensitive oscillator. This represents the output frequency of the reference oscillator under V,T conditions. This indicates the output frequency of the aging-sensitive oscillator under V, T, A conditions;

[0040] The average value of the sampling period counts of the heterogeneous sensor array is used as the temperature to be measured for the chip under test.

[0041] The variance of the sampling period count values ​​of the heterogeneous sensor array is calculated as the voltage under test of the chip under test.

[0042] In some embodiments, calculating the average of the sampling period counts of the heterogeneous sensor array as the temperature to be measured for the chip under test includes the following steps:

[0043] The mean value μ is calculated as the temperature to be measured for the chip under test using the following expression;

[0044] ;

[0045] in, x i For the first i The count value for each sampling period. N The total number of samples;

[0046] The step of calculating the variance of the sampling period count values ​​of the heterogeneous sensor array as the voltage under test for the chip under test includes the following steps:

[0047] The variance σ is calculated using the following expression. 2 The voltage to be measured for the chip under test;

[0048] ;

[0049] in, E [ x 2 ] represents the average of the squared counts over the sampling period. E [ x ] represents the average value of the count values ​​during the sampling period.

[0050] In some embodiments, the method further includes an in-situ self-calibration step, specifically comprising the following steps:

[0051] The three-dimensional physical quantity decoupling monitoring system is calibrated in situ for process deviation, temperature coefficient, and voltage sensitivity.

[0052] The embodiments of this application include at least the following beneficial effects:

[0053] This application provides a three-dimensional physical quantity decoupling monitoring system and method based on a heterogeneous oscillator array. The system of this application includes: a heterogeneous sensor array, a dual-mixer signal processing chain, a prescaler, a selector, a time-division multiplexed hardware statistical accelerator, and a decoupling algorithm module. This application designs a heterogeneous sensor array, including a logic-dominated aging-sensitive oscillator, a reference oscillator, and an interconnect-dominated oscillator. Utilizing the interconnect delay's insensitivity to voltage but sensitivity to temperature, an orthogonal sensitivity matrix is ​​constructed. A dual-mixer signal processing chain generates beat frequency signals, and the time-division multiplexed hardware statistical accelerator calculates the signal mean and variance in real time, separating temperature and voltage fluctuations. A differential structure is used to suppress common-mode interference to extract aging signals, thereby achieving decoupling monitoring of internal chip parameters and improving monitoring accuracy. Attached Figure Description

[0054] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0055] Figure 1A schematic diagram of the structure of a three-dimensional physical quantity decoupling monitoring system based on a heterogeneous oscillator array provided in an embodiment of this application;

[0056] Figure 2 A schematic diagram comparing the structures of a logic-dominated oscillator and an interconnect-dominated oscillator in a heterogeneous oscillator array provided in an embodiment of this application;

[0057] Figure 3 This is a schematic diagram of the structure of a time-division multiplexing hardware statistical accelerator provided in an embodiment of this application. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0060] Before providing a detailed description of the embodiments of this application, some related technologies involved in the embodiments of this application will be described first, as follows:

[0061] This application can be used as a fully digital health monitoring IP built into a chip / FPGA / SoC to independently decouple and monitor temperature T, supply voltage ripple V (including transient drops / glitches) and aging A during operation, providing input for DVFS, adaptive frequency reduction / power limiting, fault prediction and PHM, and online reliability grading.

[0062] The application scope of this application covers: FPGA devices and accelerator cards, CPU / MCU / SoC / GPU / AI accelerators, communication and automotive / industrial control chips, data center server motherboards and power management systems; in terms of process technology and form factor, it is suitable for on-chip / in-package monitoring and positioning in 2.5D / 3D packaging (including interposer / TSV) scenarios.

[0063] Terminology Explanation:

[0064] Three-dimensional physical quantities (T / V / A): Temperature / Voltage / Aging, representing the chip's internal temperature, supply voltage, and aging degree (caused by NBTI / HCI, etc.).

[0065] Three-dimensional decoupled monitoring is a monitoring method that separates and estimates the effects of temperature T, voltage V (including ripple), and aging A.

[0066] In-situ monitoring: acquires physical quantity information in real time or near real time inside the chip without the need for external measuring instruments.

[0067] Underdetermined system of equations: a parameter separation problem in which the number of unknowns exceeds the number of equations, resulting in a lack of unique solutions.

[0068] Heterogeneous sensor array: A sensor array consists of multiple sensor oscillators with different structural mechanisms but adjacent physical locations, used to obtain linearly independent sensitivity responses.

[0069] Ring Oscillator (RO): A circuit that forms a closed-loop oscillation by connecting an odd number of inverters / logic gates end to end.

[0070] Serpentine routing is a wiring method that forces signals to circulate back and forth between multiple logic blocks through forced constraints, thereby significantly increasing interconnect length and RC delay ratio.

[0071] Long-line / Inter-column Routing: Long-distance interconnect resources that span multiple columns / regions in FPGAs / ICs.

[0072] Mixer: A circuit or logic module that multiplies or performs an equivalent nonlinear transformation on two input signals to produce sum / difference frequency components.

[0073] Dual-mixer Processing Chain: This chain uses two mixing channels to generate signal processing links for aging monitoring beat frequencies and PVT monitoring beat frequencies, respectively.

[0074] Beat frequency: The difference frequency component generated after mixing two signals with similar frequencies.

[0075] Time-Division Multiplexing (TDM) is a multiplexing method in which different signals / channels share the same hardware resources in different time slices.

[0076] A full-rank matrix is ​​a matrix whose column vectors are linearly independent, guaranteeing that a system of equations has a unique solution.

[0077] In-situ calibration is the process of calibrating sensitivity and bias parameters in a real-world operating environment using the chip's own resources.

[0078] DVFS: Dynamic Voltage and Frequency Scaling, which balances performance with power consumption and reliability by adjusting the V / F ratio.

[0079] FPGA: Field Programmable Gate Array.

[0080] ASIC: Application Specific Integrated Circuit.

[0081] LUT: Look-Up Table, a lookup table resource in an FPGA that implements combinational logic functions.

[0082] CLB: Configurable Logic Block, a configurable logic block / logic array block for FPGAs.

[0083] The relevant technical details are as follows:

[0084] As semiconductor manufacturing processes advance to deep sub-micron and nanometer nodes (such as 7nm, 5nm), integrated circuits (ICs) and field-programmable gate arrays (FPGAs) face severe reliability challenges. Chips are affected by a variety of physical factors during operation, primarily including:

[0085] 1. Environmental factors: dynamic changes in temperature (T) and ripple noise in voltage (V).

[0086] 2. Aging factors: Negative bias temperature instability (NBTI) and hot carrier injection (HCI) effects cause transistor threshold voltage drift, which in turn leads to circuit performance degradation (Aging).

[0087] The three physical quantities (T, V, A) mentioned above can all increase the timing delay of the circuit, which can lead to timing violations or even system failures. Therefore, achieving in-situ, real-time monitoring of T, V, and A inside the chip is crucial for dynamic voltage-frequency adjustment (DVFS), fault prediction, and health management (PHM).

[0088] Currently, industry and academia mainly employ the following three technical solutions for monitoring the internal physical parameters of chips:

[0089] Option 1: Odometer technology based on ring oscillator (RO).

[0090] Technical principle: Two sets of ROs with identical physical structures are used. One set is a "stress oscillator (StressRO)," which is normally open and continuously withstands current and temperature stress to simulate circuit aging; the other set is a "reference oscillator (Reference RO)," which is normally closed and only turns on at the moment of measurement, and is considered to have no aging loss.

[0091] Implementation: Input the output signals of the two ROs into a mixer or counter, and calculate the frequency difference (D) between them. f = f Ref - f Stress Since the two are physically adjacent, assume that their instantaneous temperature ( T ) and voltage ( V If they are the same, they can be canceled out through difference operations. T and V The influence of this effect was investigated, thereby extracting the aging frequency drift caused by the NBTI / HCI effect.

[0092] Option 2: Critical Path Monitor (CPM) or Canary Flip-flop.

[0093] Technical principle: Copy a circuit with a structure similar to the timing-critical path (critical path) in the design near the user logic, or connect a "canary flip-flop" with additional delay in parallel at the end of the actual path.

[0094] Implementation: The timing slack is detected using this replication path. When the timing slack is compressed to the point of setup time violation, the canary trigger will cause a toggle error before the main logic, thus issuing a warning signal.

[0095] Option 3: On-Chip Analog Sensor / ADC.

[0096] Technical principle: The voltage and temperature values ​​are directly measured by using the analog circuit modules integrated inside the chip (such as bandgap reference source, thermal diode, ADC).

[0097] Although the above technologies have been applied, they face three major drawbacks in deep submicron processes: inaccuracy in measurement, inability to separate, and inability to capture, thus failing to meet the requirements for fine-grained management of chip health status.

[0098] 1. Complex coupling problems involving multiple physical quantities:

[0099] Defect Description: The frequency variation of a standard RO converter is a nonlinear mixture of three variables: temperature, voltage, and aging (D... f ≈ K T △ T + K V △ V + K A △ A While existing Odometer technology uses differential cancellation to offset T and V, this results in it only seeing aging (A) and completely losing the current temperature (T) and voltage (V) information.

[0100] Consequence: When a chip malfunctions, the system cannot determine whether it is caused by heat dissipation failure (T too high), power integrity issues (V too low), or the end of its lifespan (A too high). This is an underdetermined system of equations where the number of equations is less than the number of unknowns, and current technology cannot find a unique solution in a single digital system.

[0101] 2. Bandwidth blind zone for high-frequency voltage noise:

[0102] Defect Description: Existing RO measurements typically rely on a counter to count pulses within a fixed time window (e.g., 1 ms). From a signal processing perspective, the counter is essentially a mean filter. It smooths out rapid voltage drops (Voltage Droop / Glitch) on the microsecond or even nanosecond scale. While on-chip analog ADCs (such as SYSMON) are accurate, their sampling rate is typically only a few hundred kSPS (thousands of samples per second), and the number of channels is limited, making it unable to capture transient high-frequency noise that causes timing violations.

[0103] Consequences: The system may crash due to a voltage spike that lasts only 10ns, but existing monitoring methods show that the average voltage is normal, making it impossible to reproduce and locate the fault.

[0104] 3. Linear correlation in sensitivity due to simple structure:

[0105] Defect Description: Whether it's a timing monitor or a standard reverse oscillator (RO), its delay cells are primarily composed of transistors (MOSFETs). Physically, transistors exhibit consistent response trends to voltage and temperature (e.g., a decrease in voltage leads to a slowdown, and an increase in temperature typically also leads to a slowdown). This means that even if multiple ROs of different lengths are deployed, their sensitivity vectors are often mathematically linearly related, making it impossible to construct a full-rank matrix for decoupling operations.

[0106] Consequence: Additional sensors with completely different physical mechanisms (such as the interconnect-dominated oscillator in this application) must be introduced to break this linear correlation, which is a bottleneck that existing technologies have failed to overcome.

[0107] To address the shortcomings of existing technologies that cannot simultaneously and independently decouple temperature, voltage, and aging in a single digital system, this application proposes a three-dimensional physical quantity decoupling monitoring system and method based on a heterogeneous oscillator array.

[0108] The purpose of this application includes:

[0109] 1. Achieve three-dimensional decoupling: By designing heterogeneous sensors with different sensitivities to voltage / temperature (logic-driven vs. interconnect-driven), physical decoupling is achieved. T and V The separation.

[0110] 2. Low-cost all-digital monitoring: No analog ADC circuit is required; microsecond-level monitoring of voltage ripple can be achieved using only the standard logic gates (LUTs) and wiring resources inside the chip.

[0111] 3. High-precision aging extraction: Utilizing beat frequency architecture and common-mode rejection principle, it can still accurately extract minute aging signals even under severe temperature / voltage fluctuations.

[0112] Reference Figure 1 This application provides a three-dimensional physical quantity decoupling monitoring system based on a heterogeneous oscillator array. The system includes: a heterogeneous sensor array, a dual-mixer signal processing chain, a prescaler, a selector, a time-division multiplexing hardware statistical accelerator, and a decoupling algorithm module.

[0113] The heterogeneous sensor array includes a logic-dominated oscillator and an interconnect-dominated oscillator; wherein the logic-dominated oscillator includes an aging-sensitive oscillator and a reference oscillator.

[0114] The dual-mixer signal processing chain includes mixer A and mixer B;

[0115] The aging-sensitive oscillator is connected to the first terminal of the mixer A, and the reference oscillator is connected to the second terminal of the mixer A; the second terminal of the mixer A is also connected to the first terminal of the prescaler.

[0116] The second terminal of the prescaler is connected to the first terminal of the mixer B, and the interconnect-dominant oscillator is connected to the second terminal of the mixer B.

[0117] The third terminal of mixer A is connected to the first terminal of the selector, and the third terminal of mixer B is connected to the second terminal of the selector.

[0118] The third terminal of the selector is connected to the first terminal of the time-division multiplexing hardware statistical accelerator, and the second terminal of the time-division multiplexing hardware statistical accelerator is connected to the decoupling algorithm module.

[0119] Optionally, the time-division multiplexing hardware statistical accelerator includes a period measurement unit, an accumulator, a square accumulator, a DSP multiplication unit, and a control state machine;

[0120] The input terminal of the period measurement unit is used to receive the beat frequency signal output by the selector; the first output terminal of the period measurement unit is connected to the input terminal of the accumulator, the second output terminal of the period measurement unit is connected to the input terminal of the DSP multiplication unit, the third output terminal of the period measurement unit is connected to the first terminal of the control state machine, and the fourth output terminal of the period measurement unit is used to output the sample count value.

[0121] The output of the DSP multiplication unit is connected to the input of the square accumulator;

[0122] The second terminal of the control state machine is interconnected with the accumulator, and the third terminal of the control state machine is interconnected with the square accumulator.

[0123] The output of the accumulator is used to output the summation term;

[0124] The output of the square accumulator is used to output the square summation term.

[0125] Optionally, the period measurement unit is used to count the number of clock cycles between two rising edges of the beat frequency signal to obtain a count value of the sampling period. x i ;

[0126] The accumulator is used to perform a single accumulation: Acc1 = Acc1 + ... xi ;

[0127] The DSP multiplication unit is used to calculate x i 2 ;

[0128] The square accumulator is used to perform a quadratic accumulation: Acc2 = Acc2 + ... x i 2 ;

[0129] The decoupling algorithm module is used to execute:

[0130] Read Acc1 and Acc2;

[0131] Calculate μ = Acc1 / N; using the temperature coefficient K of the interconnect-dominated oscillator. WireT The current temperature T of the chip under test is obtained by inverse solving; N is the total number of samples;

[0132] Calculate σ 2 = (Acc2 / N) - μ 2 ;Utilizing the voltage sensitivity S of the aforementioned reference oscillator RefV The voltage ripple amplitude is obtained by inverse solving. .

[0133] Optionally, the interconnect-dominated oscillator is driven by logic gates and includes metal interconnects that reach a set length threshold;

[0134] More than 90% of the path delay of the interconnect-dominated oscillator is achieved by the delay caused by the resistance and capacitance of the metal wires.

[0135] Alternatively, in an FPGA, by routing signals around or across columns of multiple logic array blocks, more than 90% of the path delay of the interconnect-dominated oscillator is achieved by the delay of the resistance and capacitance of the metal lines.

[0136] Optionally, the aging-sensitive oscillator is composed of CMOS logic gates connected end to end; wherein the CMOS logic gates are lookup tables (LUTs) or inverters in an FPGA;

[0137] The aging-sensitive oscillator operates in normally open mode.

[0138] Optionally, the reference oscillator is composed of CMOS logic gates connected end to end; wherein the CMOS logic gates are lookup tables (LUTs) or inverters in an FPGA;

[0139] The reference oscillator operates in a gated mode.

[0140] This application also provides a method for decoupling and monitoring three-dimensional physical quantities based on a heterogeneous oscillator array. The method is applied to the aforementioned three-dimensional physical quantity decoupling and monitoring system based on a heterogeneous oscillator array. The method includes the following steps:

[0141] By leveraging the physical differences between logic-dominated oscillators and interconnect-dominated oscillators, the following set of equations is established to decouple the measured temperature T and measured voltage V of the chip under test:

[0142] ;

[0143] in, y Logic The frequency normalization variation of the logic-dominated oscillator, y Wire This is the normalized frequency variation of the interconnect-dominated oscillator. S L,T , S L,V These are the sensitivity coefficients of the logic-dominant oscillator to temperature and voltage, respectively. S W,T , S W,V These are the sensitivity coefficients of the interconnect-dominated oscillator to temperature and voltage, respectively.

[0144] The aging parameters of the chip under test are calculated using the differential structure of an aging-sensitive oscillator and a reference oscillator, specifically including:

[0145] ;

[0146] in, A represents the aging parameter to be measured. This represents the initial beat frequency value measured during the calibration phase, used to compensate for fixed offsets caused by process deviations; This indicates that the difference frequency signal processed by mixer A is obtained by subtracting the frequency of the reference oscillator from the frequency of the aging-sensitive oscillator. This represents the output frequency of the reference oscillator under V,T conditions. This indicates the output frequency of the aging-sensitive oscillator under V, T, A conditions;

[0147] The average value of the sampling period counts of the heterogeneous sensor array is used as the temperature to be measured for the chip under test.

[0148] The variance of the sampling period count values ​​of the heterogeneous sensor array is calculated as the voltage under test of the chip under test.

[0149] Optionally, the calculation of the average of the sampling period counts of the heterogeneous sensor array as the measured temperature of the chip under test includes the following steps:

[0150] The mean value μ is calculated as the temperature to be measured for the chip under test using the following expression;

[0151] ;

[0152] in, x i For the first i The count value for each sampling period. N The total number of samples;

[0153] The step of calculating the variance of the sampling period count values ​​of the heterogeneous sensor array as the voltage under test for the chip under test includes the following steps:

[0154] The variance σ is calculated using the following expression. 2 The voltage to be measured for the chip under test;

[0155] ;

[0156] in, E [ x 2 ] represents the average of the squared counts over the sampling period. E [ x ] represents the average value of the count values ​​during the sampling period.

[0157] Optionally, the method further includes an in-situ self-calibration step, specifically comprising the following steps:

[0158] The three-dimensional physical quantity decoupling monitoring system is calibrated in situ for process deviation, temperature coefficient, and voltage sensitivity.

[0159] The following sections will provide a detailed description and explanation of some optional embodiments of this application, using specific application examples.

[0160] Still refer to Figure 1 The monitoring system in this embodiment adopts a time-space-structure orthogonal decoupling (STOD) architecture. The system mainly consists of a heterogeneous sensor array, a dual-mixer signal processing chain, a time-division multiplexing hardware statistical accelerator (TDM-HASP), and a decoupling algorithm module.

[0161] Figure 1The system includes heterogeneous sensor arrays (Stress-RO, Ref-RO, Wire-RO), dual-mixer signal processing chains (Mixer A, Mixer B), prescalers, time-division multiplexers / selectors (MUX), TDM-HASP hardware statistical accelerators, and software decoupling modules, clearly demonstrating the separation path of T / V / A.

[0162] 1.1 Design of heterogeneous sensor array.

[0163] This is the core hardware foundation of this embodiment, consisting of three physically adjacent but structurally different oscillators:

[0164] 1.1 First Oscillator (Stress-RO, Aging-Sensitive Type):

[0165] Structure: It consists of standard CMOS logic gates (such as lookup tables (LUTs) or inverters in FPGAs) connected end to end.

[0166] Operating mode: Always-on. It is always in a high-frequency oscillation state, simulating the actual aging process of the user's circuit.

[0167] Characteristics: Frequency It is sensitive to voltage (V) and temperature (T), and its value decreases monotonically over time (t) due to aging (A).

[0168] 1.2 Second Oscillator (Ref-RO, Reference Type):

[0169] Structure: The physical structure, layout and routing are completely consistent with Stress-RO.

[0170] Operating mode: Gated. It is only activated during sampling and remains in a dormant state for the remaining 99.9% of the time.

[0171] Characteristics: Due to its extremely short operating time, it is considered to be aging-free. Its frequency... f ref Sensitive only to V and T, serving as a baseline for aging comparison.

[0172] 1.3 Third Oscillator (Wire-RO, Interconnect-Dominated Type):

[0173] Structure: This is the key innovation. Although the oscillator is also driven by logic gates, it deliberately introduces extremely long metal interconnect wires. More than 90% of its path delay is contributed by the RC (resistance-capacitance) delay of the metal wires, rather than the transistor switching delay.

[0174] Implementation method: In FPGA, signals are forced to make serpentine routing or cross-column long traces between multiple logic array blocks (CLBs) through forced constraints.

[0175] characteristic:

[0176] Voltage insensitivity: The resistance R and capacitance C of the metal wire are physical geometric parameters that hardly change with the supply voltage V. Therefore, Wire-RO is much less sensitive to voltage fluctuations than Logic-RO (it can even be approximated as 0).

[0177] Temperature sensitive: The resistivity of metals (such as copper / aluminum) increases linearly with temperature, therefore its frequency... A good indicator of temperature.

[0178] For example, Figure 2 This is a schematic diagram comparing the structures of logic-dominated oscillators and interconnect-dominated oscillators in a heterogeneous oscillator array.

[0179] Figure 2 The physical structure differences between Logic-RO (Ref / Stress RO mentioned above) and Wire-RO were compared: Logic-RO mainly uses logic gate delay, while Wire-RO mainly uses long metal interconnect RC delay, which is used to explain the physical basis for the different voltage and temperature sensitivities of the two.

[0180] 2. Mathematical decoupling principle and physical modeling.

[0181] The core problem solved in this embodiment lies in constructing a full-rank sensitivity matrix. This embodiment uses the oscillator's frequency change rate... The model is a linear combination of temperature change ΔT, voltage change ΔV, and aging degree ΔA.

[0182] 2.1 Orthogonality of structural dimensions (T / V separation).

[0183] Based on the differences in physical characteristics between Logic-RO and Wire-RO, the following system of equations is established:

[0184] ;

[0185] in:

[0186] y Logic and y Wire These are the normalized frequency variations of the logic oscillator and the interconnect oscillator, respectively.

[0187] S L,T ,S L,V This represents the sensitivity coefficient of Logic-RO to temperature and voltage. Logic gate delay is mainly affected by the transistor saturation current Ids and is extremely sensitive to voltage V.

[0188] S W,T , S W,V This represents the sensitivity coefficient of Wire-RO to temperature and voltage.

[0189] Key characteristics: Interconnect delay is primarily determined by the RC constant, while in deep submicron processes, the resistance R and capacitance C of the metal wires hardly change with the supply voltage, i.e. S W,V ≈ 0.

[0190] Meanwhile, the resistivity of a metal changes linearly with temperature, that is... S W,T ≠ 0.

[0191] Therefore, the coefficient matrix of the equation system is approximately a triangular matrix, which guarantees that the equation system has a unique solution, thus achieving decoupling of T and V at the physical level.

[0192] 2.2 Spatial Dimensional Differentiation (Aging Separation).

[0193] Using the difference structure of Stress-RO and Ref-RO:

[0194] ;

[0195] in, A represents the aging parameter to be measured. This represents the initial beat frequency value measured during the calibration phase (such as the initial power-on of the chip), used to compensate for fixed offsets caused by process variations; This indicates that the difference frequency signal processed by mixer A is obtained by subtracting the frequency of the reference oscillator (Ref-RO) from the frequency of the stress-sensitive oscillator (Stress-RO). This represents the output frequency of the reference oscillator under V,T conditions. This indicates the output frequency of the aging-sensitive oscillator under V, T, A conditions.

[0196] Since the two are physically adjacent, they are considered to withstand the same common-mode voltage V and temperature T. After subtraction, the common-mode terms cancel each other out, and the remaining terms are only related to aging: .

[0197] 3. The principle of T / V separation algorithm based on frequency domain statistical characteristics.

[0198] For the PVT monitoring channel (Mixer B), this embodiment proposes to use the statistical moments of the signal within the time window to separate temperature and voltage.

[0199] 3.1 Theoretical basis.

[0200] Temperature (T): This is a quantity of thermal inertia, changing slowly (on the order of milliseconds to seconds). Within a single sampling window (e.g., 100 μs), temperature can be considered a constant T0. Therefore, temperature primarily affects the DC component of the beat frequency signal, i.e., its mean.

[0201] Voltage (V): Includes DC voltage drop (IR drop) and rapid AC switching noise. Voltage ripple is the main cause of rapid frequency jitter within the window. Therefore, the voltage noise amplitude primarily affects the AC component of the beat frequency signal, i.e., the variance.

[0202] 3.2 Hardware calculation principle (cumulative sum and square cumulative sum).

[0203] To efficiently compute the mean (μ) and variance (σ) in FPGA hardware 2 This embodiment utilizes the following statistical identity:

[0204] 3.2.1 Formula for calculating the mean:

[0205] ;

[0206] in x i For the first i The count value for each sampling period. N The total number of samples.

[0207] 3.2.2 Variance calculation formula:

[0208] ;

[0209] Technical advantages: Traditional variance calculation First, the mean μ needs to be calculated by iterating through the data, then subtraction needs to be performed, requiring storage of all samples, resulting in huge hardware overhead. The formula described above allows the hardware to calculate the "cumulative sum of the data" in parallel as the data flows through. "and "the sum of squares of the data" "The variance can be calculated in software by a single subtraction operation simply by reading the values ​​of these two registers at the end of the sampling process, without the need for on-chip memory (RAM) to cache the waveform data."

[0210] 4. Implementation scheme of Time Division Multiplexing Hardware Statistical Accelerator (TDM-HASP).

[0211] For example, Figure 3 This is a schematic diagram of the Time Division Multiplexing Hardware Statistical Accelerator (TDM-HASP).

[0212] Figure 3 The TDM-HASP internal modules are shown in detail, including the period measurement unit, accumulator (∑x), square accumulator (∑x²), DSP multiplication unit, and control state machine, highlighting the hardware parallel statistics implementation.

[0213] To put the above theory into practice, this embodiment designs a time-division multiplexing hardware statistical accelerator.

[0214] 4.1 Input Multiplexing:

[0215] The front end of the time-division multiplexing hardware statistical accelerator is equipped with a 2:1 MUX.

[0216] State A (PVT Mode): Enables Mixer B (Wire vs Ref) output.

[0217] Status B (Aging Mode): Enables Mixer A (Stress vs Ref) output.

[0218] 4.2 Statistics Acceleration Engine (HASP Core):

[0219] It contains two 64-bit accumulators and one DSP multiplication unit.

[0220] Period measurement: The number of clock cycles between two rising edges of the input signal is counted using a high-frequency system clock (e.g., 300MHz). x i .

[0221] One-time accumulation: Acc1 = Acc1 + x i .

[0222] Double accumulation: calculated using DSP unit x i 2 And execute Acc2= Acc2+ x i 2 .

[0223] 4.3 Decoupling Algorithm Flow:

[0224] Step 1: Read Acc1 and Acc2.

[0225] Step 2 (Calculate Temperature): Calculate μ = Acc1 / N. Use the temperature coefficient K of Wire-RO. WireT The current temperature T can be obtained by inverse solving.

[0226] Step 3 (Calculate voltage): Calculate σ 2 = (Acc2 / N) - μ 2 Utilizing the voltage sensitivity S of Ref-RO RefV The voltage ripple amplitude is obtained by inverse solving. .

[0227] 5. In-Situ Calibration Procedure.

[0228] Due to process variation, the sensor characteristic parameters (such as sensitivity coefficient) of each chip are different. This embodiment utilizes the existing resources of the chip for in-situ calibration, eliminating the need for expensive external instruments.

[0229] 5.1 Process Deviation Calibration (Offset Calibration):

[0230] Timing: When the chip is powered on for the first time, t=0.

[0231] Operation: In idle state, turn on Mixer A and measure the initial difference frequency between Stress-RO and Ref-RO. f offset .

[0232] Function: This serves as the zero point for aging measurements; subsequent measurements must be subtracted from this offset.

[0233] 5.2 Temperature coefficient calibration (T-Calibration):

[0234] Timing: During system maintenance or idle periods.

[0235] operate:

[0236] 5.2.1 Use the low-speed temperature sensor integrated on the FPGA chip (such as Xilinx SYSMON) to read the current cold temperature T. cold Record Wire-RO frequency .

[0237] 5.2.2 Run a high-load heating program to raise the chip temperature and read the hot temperature T. hot Record Wire-RO frequency .

[0238] calculate: .

[0239] 5.3 Voltage sensitivity calibration (V-Calibration):

[0240] Timing: System startup phase.

[0241] Operation: Use the power management bus (such as PMBus) to fine-tune the FPGA core voltage (e.g., from 0.85V to 0.84V).

[0242] Observation: Record the change in the average frequency of Mixer B output. .

[0243] calculate: This coefficient is used to subsequently map the variance (frequency jitter) to voltage noise (mV).

[0244] Through the above calibration, the system constructs an accurate coefficient matrix, ensuring the accuracy of three-dimensional decoupling.

[0245] In summary, this embodiment includes the following key technical solutions:

[0246] 1. Heterogeneous Sensor Array Architecture: A combined sensor architecture comprising "Logic-Dominated Oscillator (Logic-RO)" and "Wire-Dominated Oscillator (Wire-RO)" is proposed. Its core lies in utilizing the physical characteristic that interconnect delay is insensitive to voltage but sensitive to temperature, constructing a sensitivity matrix different from that of logic gate delays, thereby achieving decoupling between voltage and temperature.

[0247] 2. A three-dimensional decoupling method based on dual mixing: Aging information is extracted by the mixing difference between two logic oscillators (Stress / Ref) with the same structure but different operating modes, thus eliminating PVT common-mode interference. PVT mixing information is extracted by the mixing difference between the logic oscillator and the interconnect oscillator.

[0248] 3. T / V Separation Algorithm Based on Frequency Domain Statistical Characteristics: A method for separating voltage and temperature in a single digital signal stream is proposed. Specifically, the statistical variance of the signal within a time window is used to characterize rapidly changing voltage ripple, while the statistical mean is used to characterize slowly changing temperature drift.

[0249] 4. Specific implementation structure of Wire-RO: In FPGA or IC, a closed-loop oscillation structure containing a large number of long-distance metal interconnects and a small number of drive buffers is constructed by forcibly constraining the layout and routing. The RC delay of this structure accounts for more than a set threshold of the total delay (such as 90%).

[0250] 5. Time-Division Multiplexed Hardware Statistical Accelerator (TDM-HASP): This includes a multiplexer, a period measurement unit, and a square accumulation unit. The TDM-HASP is controlled by a state machine, using the same set of computational logic to process aging monitoring signals and PVT monitoring signals separately, and directly outputs the accumulated statistical value at the hardware level.

[0251] Compared with existing ring oscillator (RO) odometer technology and on-chip analog-to-digital converter (ADC) monitoring technology, this embodiment has the following significant and substantial features and advancements:

[0252] 1. Achieved true orthogonal decoupling of multiple physical quantities:

[0253] Existing RO sensor output frequencies are coupled functions of temperature, voltage, and aging, failing to distinguish the root cause of frequency degradation (e.g., timing violations due to voltage drops or performance degradation due to chip aging). This embodiment introduces an interconnect-dominated oscillator (Wire-RO), leveraging the temperature-sensitive but voltage-insensitive physical characteristic of metal interconnects to construct a sensitivity matrix linearly independent of logic gate oscillators (Logic-RO). Combined with a dual-mixer architecture, this embodiment achieves, for the first time, independent and precise separation of temperature, voltage ripple, and circuit aging in the entire digital domain, solving the problem of traditional sensors accurately measuring frequencies but failing to identify the root cause.

[0254] 2. Extremely low overhead and high integration:

[0255] Existing voltage ripple monitoring typically relies on off-chip oscilloscopes or expensive on-chip analog ADC modules, making high-density deployment within the chip difficult. This embodiment, based entirely on standard digital logic gates (LUTs) and routing resources, achieves "oscilloscope-level" voltage noise monitoring without any analog circuitry. Furthermore, the proposed TDM-HASP (Time Division Multiplexing Hardware Statistical Acceleration) architecture offloads complex statistical calculations to hardware, reducing bus bandwidth usage and CPU load by 99% compared to pure software solutions. This enables microsecond-level real-time monitoring without affecting the system's main tasks.

[0256] 3. Extremely high signal-to-noise ratio for aging monitoring:

[0257] Existing Odometer technology introduces a large noise floor in its difference frequency signal when voltage fluctuations are severe, masking minute aging drift. This embodiment utilizes the differential structure of Mixer A to naturally suppress common-mode voltage noise, while using real-time voltage data provided by Mixer B to perform secondary compensation (residual correction) on the aging measurement results, thus enabling the capture of aging frequency drift at the 0.01% level even under harsh power supply environments.

[0258] It should be noted that this embodiment may include the following alternatives:

[0259] Alternative Option 1: Structural alternatives for heterogeneous sensors (reconfigurable architecture).

[0260] Original solution: Use three independent physical oscillators (Stress-RO, Ref-RO, Wire-RO) in parallel.

[0261] Alternative solution: Use a reconfigurable single oscillator structure. This involves dynamically changing the feedback path of the same oscillator using a multiplexer (MUX).

[0262] At time T1, the configuration path passes through pure logic gates (simulating Logic-RO mode);

[0263] At time T2, the configured path traverses a long cable (simulating Wire-RO mode).

[0264] At time T3, the oscillation loop is disconnected, and only a DC bias voltage is applied for aging (simulating Stress mode).

[0265] Effect: It can also use the sensitivity difference between logic path and wiring path to establish a decoupling equation set. Although it sacrifices real-time performance (cannot be measured simultaneously), it saves chip area.

[0266] Alternative Solution 2: Alternative implementation of Wire-RO.

[0267] Original solution: Use serpentine traces or long cross-column traces to construct RC delay-dominated paths within the FPGA plane.

[0268] Alternative solution:

[0269] Cross-layer interconnect (TSV): In 2.5D / 3D stacked chips, long traces on through silicon vias (TSVs) or interposers are used to build Wire-ROs for monitoring temperature / stress inside the 3D package.

[0270] Capacitor load chain: In ASIC design, it is not necessary to use long metal lines. Large metal capacitors (MIM Cap / MOM Cap) can be artificially connected between inverter chains to artificially increase the RC delay ratio, which can also achieve voltage insensitivity.

[0271] Alternative Solution 3: Alternative methods for signal readout and processing.

[0272] Original solution: Use a mixer to generate a beat frequency, and then measure the period / frequency of the beat frequency.

[0273] Alternative solution:

[0274] Time-to-Digital Conversion (TDC): Instead of using oscillator mode, it sends a single pulse and uses the carry chain to directly measure the propagation time difference of the pulse through the Logic chain and the Wire chain.

[0275] Duty Cycle Modulation (PWM): Design an asymmetric oscillator that uses logic delay to determine the high-level width and wire delay to determine the low-level width. Decouple the voltage by measuring the duty cycle change of the output waveform (because the voltage mainly affects the high-level width caused by logic, not the low-level width caused by wire).

[0276] Alternative Solution 4: Alternative algorithms for statistical features.

[0277] Original plan: Use the mean to represent temperature and the variance to represent voltage.

[0278] Alternative solution:

[0279] The voltage ripple amplitude is characterized by the maximum / minimum value or peak-to-peak value.

[0280] Temperature is characterized by the value or median after low-pass filtering.

[0281] Although these statistical variations have different calculation formulas, they are essentially still based on the frequency domain distribution characteristics of the signal (low-frequency components vs. high-frequency components) to separate T and V, and should fall within the scope of protection of this patent.

[0282] Alternative Option 5: Alternatives to the application platform.

[0283] Original plan: Use FPGA (Field Programmable Gate Array) as the implementation platform.

[0284] Alternative: The circuit structure and method of this embodiment are also fully applicable to ASICs (Application-Specific Integrated Circuits), SoCs (System-on-Chip), GPGPUs, or microprocessors. As long as the digital chip is based on CMOS technology, differences in the physical characteristics of its transistors and interconnects will exist, and this solution can be used for monitoring.

[0285] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0286] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0287] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0288] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A three-dimensional physical quantity decoupling monitoring system based on a heterogeneous oscillator array, characterized in that, The system includes: a heterogeneous sensor array, a dual-mixer signal processing chain, a prescaler, a selector, a time-division multiplexing hardware statistical accelerator, and a decoupling algorithm module; The heterogeneous sensor array includes a logic-dominated oscillator and an interconnect-dominated oscillator; wherein the logic-dominated oscillator includes an aging-sensitive oscillator and a reference oscillator. The dual-mixer signal processing chain includes mixer A and mixer B; The aging-sensitive oscillator is connected to the first terminal of the mixer A, and the reference oscillator is connected to the second terminal of the mixer A; the second terminal of the mixer A is also connected to the first terminal of the prescaler. The second terminal of the prescaler is connected to the first terminal of the mixer B, and the interconnect-dominant oscillator is connected to the second terminal of the mixer B. The third terminal of mixer A is connected to the first terminal of the selector, and the third terminal of mixer B is connected to the second terminal of the selector. The third terminal of the selector is connected to the first terminal of the time-division multiplexing hardware statistical accelerator, and the second terminal of the time-division multiplexing hardware statistical accelerator is connected to the decoupling algorithm module. The time-division multiplexing hardware statistical accelerator includes a period measurement unit, an accumulator, a square accumulator, a DSP multiplication unit, and a control state machine. The input terminal of the period measurement unit is used to receive the beat frequency signal output by the selector; the first output terminal of the period measurement unit is connected to the input terminal of the accumulator, the second output terminal of the period measurement unit is connected to the input terminal of the DSP multiplication unit, the third output terminal of the period measurement unit is connected to the first terminal of the control state machine, and the fourth output terminal of the period measurement unit is used to output the sample count value. The output of the DSP multiplication unit is connected to the input of the square accumulator; The second terminal of the control state machine is interconnected with the accumulator, and the third terminal of the control state machine is interconnected with the square accumulator. The output of the accumulator is used to output the summation term; The output of the square accumulator is used to output the square summation term; The period measurement unit is used to count the number of clock cycles between two rising edges of the beat frequency signal, and obtain the count value of the sampling period. x i ; The accumulator is used to perform a single accumulation: Acc1 = Acc1 + ... x i ; The DSP multiplication unit is used to calculate x i 2 ; The square accumulator is used to perform a quadratic accumulation: Acc2 = Acc2 + ... x i 2 ; The decoupling algorithm module is used to execute: Read Acc1 and Acc2; Calculate μ = Acc1 / N; utilize the temperature coefficient K of the interconnect-dominated oscillator. WireT The current temperature T of the chip under test is obtained by inverse solving; N is the total number of samples; Calculate σ 2 = (Acc2 / N) - μ 2 ;Utilizing the voltage sensitivity S of the aforementioned reference oscillator RefV The voltage ripple amplitude is obtained by inverse solving. .

2. The three-dimensional physical quantity decoupling monitoring system based on heterogeneous oscillator array according to claim 1, characterized in that, The interconnect-dominated oscillator is driven by logic gates and includes metal interconnects that reach a set length threshold. More than 90% of the path delay of the interconnect-dominated oscillator is achieved by the delay caused by the resistance and capacitance of the metal wires.

3. The three-dimensional physical quantity decoupling monitoring system based on heterogeneous oscillator array according to claim 2, characterized in that, In FPGAs, by routing signals around or across columns of logic array blocks, more than 90% of the path delay of the interconnect-dominated oscillator is achieved by the delay of the resistance and capacitance of the metal lines.

4. The three-dimensional physical quantity decoupling monitoring system based on heterogeneous oscillator array according to claim 1, characterized in that, The aging-sensitive oscillator is composed of CMOS logic gates connected end to end; wherein, the CMOS logic gates are LUTs or inverters in the FPGA; The aging-sensitive oscillator operates in normally open mode.

5. The three-dimensional physical quantity decoupling monitoring system based on heterogeneous oscillator array according to claim 1, characterized in that, The reference oscillator is composed of CMOS logic gates connected end to end; wherein, the CMOS logic gates are lookup tables (LUTs) or inverters in an FPGA; The reference oscillator operates in a gated mode.

6. A three-dimensional physical quantity decoupling monitoring method based on heterogeneous oscillator arrays, characterized in that, The method is applied to the three-dimensional physical quantity decoupling monitoring system based on heterogeneous oscillator array as described in claim 1, and the method includes the following steps: By leveraging the physical differences between logic-dominated oscillators and interconnect-dominated oscillators, the following set of equations is established to decouple the measured temperature T and measured voltage V of the chip under test: ； in, y Logic This is the normalized frequency variation of the logic-dominant oscillator. y Wire This is the normalized frequency variation of the interconnect-dominated oscillator. S L,T , S L,V These are the sensitivity coefficients of the logic-dominant oscillator to temperature and voltage, respectively. S W,T , S W,V These are the sensitivity coefficients of the interconnect-dominated oscillator to temperature and voltage, respectively. The aging parameters of the chip under test are calculated using the differential structure of an aging-sensitive oscillator and a reference oscillator, specifically including: ； in, A represents the aging parameter to be measured. This represents the initial beat frequency value measured during the calibration phase, used to compensate for fixed offsets caused by process deviations; This indicates that the difference frequency signal processed by mixer A is obtained by subtracting the frequency of the reference oscillator from the frequency of the aging-sensitive oscillator. This represents the output frequency of the reference oscillator under V,T conditions. This indicates the output frequency of the aging-sensitive oscillator under V, T, A conditions; The average value of the sampling period counts of the heterogeneous sensor array is used as the temperature to be measured for the chip under test. The variance of the sampling period count values ​​of the heterogeneous sensor array is calculated as the voltage under test of the chip under test.

7. The three-dimensional physical quantity decoupling monitoring method based on heterogeneous oscillator array according to claim 6, characterized in that, The calculation of the average value of the sampling period counts of the heterogeneous sensor array as the temperature to be measured for the chip under test includes the following steps: The mean value μ is calculated as the temperature to be measured for the chip under test using the following expression; ； in, x i For the first i The count value for each sampling period. N The total number of samples; The step of calculating the variance of the sampling period count values ​​of the heterogeneous sensor array as the voltage under test for the chip under test includes the following steps: The variance σ is calculated using the following expression. 2 The voltage to be measured for the chip under test; ； in, E [ x 2 ] represents the average of the squared count values ​​over the sampling period. E [ x ] represents the average value of the count values ​​during the sampling period.

8. The three-dimensional physical quantity decoupling monitoring method based on heterogeneous oscillator array according to claim 6, characterized in that, The method also includes an in-situ self-calibration step, specifically comprising the following steps: The three-dimensional physical quantity decoupling monitoring system is calibrated in situ for process deviation, temperature coefficient, and voltage sensitivity.

Images