All-digital verification method for motor control system

Abstract

The invention discloses an all-digital verification method for a motor control system. The verification method comprises the following steps: S1, defining a verification object and control core parameters; s2, constructing a high-granularity processor digital model; s3, a DSP software operation environment is built, and DSP program zero-modification direct application is achieved; s4, designing to realize the universality and expansibility of the model, supporting the development and debugging of multiple types of DSP programs, and adapting to different control systems; s5, establishing real-time data interaction and system closed-loop control simulation; and S6, running the simulation system to carry out multi-dimensional function verification, and realizing automatic testing, limit testing and result output of the DSP program. According to the method, the zero-modification direct application and convenient development of the DSP program of the motor control system are realized, the pain points of traditional hardware tests such as complex program algorithm verification, sequential logic guarantee, limit scene test and the like are solved through the flexibility and the safety of a full-digital environment, and an efficient development closed loop is really formed.

Description

Technical Field

[0001] This invention relates to the field of control or motor system technology, and in particular to a fully digital verification method for a motor control system. Background Technology

[0002] In the field of motor control system development, algorithm iteration and functional verification are core links, but they have long been limited by industry pain points such as reliance on physical hardware, insufficient simulation accuracy, and lack of full-link verification, which has given rise to the need for the research and development method of this invention.

[0003] On the one hand, traditional motor control development relies on physical hardware such as motors, power supplies, and DSP chips. This not only results in high hardware procurement costs, long debugging cycles, and significant equipment wear and tear risks, but also makes it difficult to quickly conduct multi-scenario, multi-parameter algorithm iteration tests due to hardware resource limitations. On the other hand, existing simulation solutions have significant shortcomings. For example, a motor drive simulation system built using traditional simulation methods includes establishing a finite element model of the motor mechanism and importing it into the simulation environment; establishing a dynamic model in the simulation environment; building a motor drive system model based on the finite element model and the dynamic model; obtaining data input and output simulation information from the motor drive system model; and introducing data processing models such as filtering circuits and control signals based on the data input to obtain data output simulation information. The data input and output simulation information includes bus transmission methods, control signal protocols, and data transmission timing. This type of solution only focuses on the detailed simulation of motor hardware and does not cover the characteristic simulation of the core control unit DSP, thus failing to achieve full-link verification from the motor system to the control chip.

[0004] Other methods involve controllers, but only simplify the implementation of basic signal conversion without considering key control system characteristics such as the response of the controller's core component, the DSP processor kernel, interrupt conflicts, and timing delays (such as precision below milliseconds). Furthermore, they rely on mathematical formula calculations, which leads to a disconnect between the running logic and algorithm accuracy of the motor control program in the simulation and the physical DSP environment. When the algorithm is ported to the physical device, it is prone to failure.

[0005] Other existing motor system simulation methods mostly perform simple verification at the motor algorithm level, often only ensuring the basic trend of the waveform is correct. For example, the simulation of a hybrid virtual-real electric drive control system experimental device includes PWM and DC power supplies, a frequency converter AC power supply, a DC motor, an AC motor, a load, a real-time speed and torque acquisition and transmission module, a real-time control output unit, a virtual PID controller, and a digital PID controller. The PWM and DC power supply powers the DC motor, using analog voltage input to control the output voltage; the frequency converter AC power supply powers the AC motor, using external analog voltage to control the output voltage frequency and amplitude; the DC motor, AC motor, load, and speed and torque acquisition and transmission module are coaxially mounted, along with a flywheel device, to simulate the operating characteristics of a high-power motor with a low-power motor. The real-time speed and torque acquisition and transmission module is used to acquire the output speed and torque of the DC and AC motors. This device features a hybrid virtual-real approach, using hardware-supported simulation, virtual components of the DC and AC electric drive systems, and digital PID debugging.

[0006] This method has many limitations and practical problems. Hardware design flaws directly lead to experimental data deviations and equipment wear and tear risks, which is the core issue. Furthermore, there are control logic and coordination problems; the virtual-physical integrated control architecture fails to resolve the key contradiction of "virtual-digital" coordination, affecting control real-time performance and debugging effectiveness. The interaction delay between virtual and digital PID controllers: The system includes both a software-level "virtual PID controller" and a hardware-level "digital PID controller," which need to exchange data in real time, such as collected speed and torque, and control output commands. If the software processing speed or hardware communication interface bandwidth is insufficient, data transmission delays will occur, leading to lag in control response and even system oscillations, such as fluctuating motor speed.

[0007] The lack of calibration for virtual and real environment parameters means that virtual PID relies on the motor model in the software, while digital PID operates on a real motor, which cannot guarantee the effectiveness and real-time performance of the simulated control signal. If the parameters of the virtual model are inconsistent with the actual parameters of the real motor, and there is no unified calibration process, the "virtually debugged PID parameters" cannot be directly applied to the real hardware, requiring repeated adjustments and resulting in low efficiency.

[0008] At the same time, the industry has an increasingly urgent need for a development model that is "free from physical hardware dependence"—it is necessary to accurately reproduce the entire life cycle logic of motor control without physical objects, so as to ensure that the effectiveness of algorithms and programs can be verified in a simulation environment, thereby reducing the cost and risk of hardware debugging in the later stage.

[0009] Against this backdrop, a fully digital verification method based on DSP instruction-level virtualization simulation technology and clock cycle-level event-driven model has emerged, aiming to solve the core pain points of traditional development and simulation, and to achieve high efficiency, accuracy and hardware-independent development of motor control algorithms and system function verification. Summary of the Invention

[0010] In view of the above problems, the present invention is proposed to provide a fully digital verification method for a motor control system that overcomes or at least partially solves the above problems.

[0011] According to one aspect of the present invention, a fully digital verification method for a motor control system is provided, the verification method comprising: Step S1: Define the verification object and control core parameters; Step S2: Construct a high-granularity processor digital model; Step S3: Set up the DSP software runtime environment to enable direct application of the DSP program with zero modifications; Step S4: Design and implement the model to ensure its versatility and scalability, support the development and debugging of multiple types of DSP programs, and adapt to different control systems; Step S5: Establish real-time data interaction and system closed-loop control simulation; Step S6: Run the simulation system to perform multi-dimensional functional verification, and realize automated testing, extreme testing and result output of the DSP program.

[0012] Optionally, step S1: defining the verification object and control core parameters specifically includes: Identifying the core components and key parameters of the system to be verified lays the foundation for the direct application of DSP programs and adaptation to the simulation environment. Simultaneously determine the development environment for the DSP program to ensure seamless compatibility between the subsequent virtual environment and the program development environment; The core functional modules of the DSP program are identified, and the hardware resource requirements are clarified, including timer interrupt frequency and ADC sampling channels, to provide a basis for resource configuration in the virtual environment. By accurately matching program development dependencies with hardware parameters, a prerequisite is provided for the program to be directly loaded and run.

[0013] Optionally, the key parameters include specific processor architecture, clock speed, and peripheral hardware parameters.

[0014] Optionally, step S2: constructing a high-granularity processor digital model specifically includes: Modeling with instruction-level and clock cycle-level precision ensures that the timing logic and real-time performance of the DSP program are fully reproduced in the simulation. In addition to replicating the processor's instruction set processing logic and peripheral functions, the focus is on simulating the timing characteristics of DSP programs during runtime to ensure the instruction execution cycle for complex algorithms is accurate to the time consumption of a single instruction. Simulate context switching latency during multi-task scheduling and response priority during interrupt nesting as needed to ensure conflict handling between PWM interrupts and fault interrupts; Timing constraints for modeling the interaction between the DSP program and peripherals: Synchronize the timing of the ADC sampling trigger signal and the PWM update signal to ensure that the closed-loop cycle of sampling-calculation-output in the program is consistent with the real system.

[0015] Optionally, step S3: setting up the DSP software runtime environment to enable direct application of the DSP program with zero modifications specifically includes: A binary compatibility layer for control system software is built, supporting the direct loading of binary files (.out and .hex files) generated by DSP program compilation into the all-digital system without modifying the code or adapting function interfaces. The library functions called in the program, such as trigonometric functions, filtering functions, and peripheral drivers from the math library, are executed according to the actual hardware logic, which is consistent with the real-world development experience. An integrated debugger toolchain supports direct debugging of DSP programs in simulated control systems, providing real-time register monitoring, variable tracing, and breakpoint debugging functions, allowing developers to locate program logic errors as if debugging real hardware. Developers do not need to learn new simulation interface specifications and can directly use their existing DSP program development habits.

[0016] Optionally, step S4: designing and implementing the model's versatility and scalability to support the development and debugging of multiple types of DSP programs and adapt to different control systems specifically includes: Modular design supports program function expansion. When developing new types of motor control programs, peripheral modules can be added or removed to adapt to the new hardware resource requirements of the program without reconstructing the entire simulation system. The core simulation based on the processor instruction set is compatible with multiple program architectures, supporting the development and debugging of bare-metal programs, real-time operating system programs, and multi-core collaborative programs. It ensures that control programs with different functional characteristics can run stably in the virtual environment to meet the program development needs of diverse motor control scenarios.

[0017] Optionally, step S5: establishing real-time data interaction and system closed-loop control simulation specifically includes: The virtual environment operates in real time in a closed loop of "perception-decision-execution": the virtual sensor module inputs data such as current, voltage, and angle to the DSP program according to the required timing; the program outputs control signals after running complex control algorithms; the virtual drive module responds in real time and feeds back the motor status, forming a closed loop link consistent with the real system; Supports interactive verification of complex logic in programs: such as fault diagnosis algorithms in programs, which can be triggered by injecting fault signals in a virtual environment to verify the response speed and processing logic of the algorithm; for multi-loop control algorithms, the effectiveness of inter-loop coupling processing can be verified by adjusting virtual load disturbances. The interaction logic of the program and system is fully reproduced in a virtual environment.

[0018] Optionally, step S6: running the simulation system to perform multi-dimensional functional verification, and realizing automated testing, limit testing, and result output of the DSP program, specifically includes: Through automated test integration, it supports the writing of test scripts to achieve full automation of the "program loading → scenario configuration → data collection → result analysis" process; Digital systems can be subjected to extreme testing without worry, setting up extreme scenarios that cannot be achieved in hardware systems to safely verify the stability of DSP programs under extreme conditions. After the simulation is completed, the test results are output in real time, and a visual report containing waveforms, data tables, and error analysis is generated directly, marking the problem points in the program; By conducting extreme tests to cover scenarios that hardware cannot reach, the entire process of "development-debugging-verification" is ultimately accelerated.

[0019] Optionally, the extreme scenarios specifically include: continuous power supply exceeding the rated voltage, excessive instantaneous load torque, and injection of high-frequency interference signals.

[0020] This invention provides a fully digital verification method for a motor control system, the verification method comprising: step S1: defining the verification object and control core parameters; step S2: constructing a high-granularity processor digital model; Step S3: Set up the DSP software runtime environment to enable direct application of the DSP program with zero modification; Step S4: Design and implement the model's universality and scalability, supporting the development and debugging of multiple types of DSP programs and adapting to different control systems; Step S5: Establish real-time data interaction and system closed-loop control simulation; Step S6: Run the simulation system to perform multi-dimensional functional verification, realizing automated testing, extreme testing, and result output of the DSP program. This achieves direct application and convenient development of the motor control system DSP program with zero modification. Furthermore, through the flexibility and security of the fully digital environment, it solves the pain points of traditional hardware testing, such as complex program algorithm verification, timing logic protection, and extreme scenario testing, truly forming an efficient development closed loop.

[0021] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A flowchart of a fully digital verification method for a motor control system provided in an embodiment of the present invention. Detailed Implementation

[0024] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0025] The terms "comprising" and "having," and any variations thereof, in the specification, embodiments, claims, and drawings of this invention are intended to cover non-exclusive inclusion, such as including a series of steps or units.

[0026] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0027] like Figure 1 As shown, a fully digital verification method for a motor control system includes: Step S1: Define the verification object and control core parameters; Step S2: Construct a high-granularity processor digital model; Step S3: Set up the DSP software runtime environment to enable direct application of the DSP program with zero modifications; Step S4: Design and implement the model to ensure its versatility and scalability, support the development and debugging of multiple types of DSP programs, and adapt to different control systems; Step S5: Establish real-time data interaction and system closed-loop control simulation; Step S6: Run the simulation system to perform multi-dimensional functional verification, and realize automated testing, extreme testing and result output of the DSP program.

[0028] A fully digital verification method for motor control systems based on virtualized DSP processor simulation: Step 1: Precisely define the verification object and control core parameters.

[0029] Identifying the core components and key parameters of the system to be verified lays the foundation for the direct application of the DSP program and its adaptation to the simulation environment. This includes defining hardware parameters such as processor architecture, clock speed, and peripherals, and simultaneously determining the DSP program's development environment, including compiler version, linker script configuration, and runtime dependencies such as memory allocation strategies and peripheral driver interface specifications, ensuring seamless compatibility between the virtual environment and the program development environment. The core functional modules of the DSP program, such as the current loop algorithm and fault diagnosis logic, are identified, clarifying their hardware resource requirements, including timer interrupt frequencies and ADC sampling channels, providing a basis for resource configuration in the virtual environment. By accurately matching program development dependencies with hardware parameters, compatibility issues during program porting in subsequent verification processes are avoided, providing a prerequisite for "direct program loading and execution."

[0030] Step 2: Construct a high-granularity digital model of the processor, that is, perform processor core modeling.

[0031] Modeling with "instruction-level + clock cycle-level" precision ensures the complete reproduction of the timing logic and real-time performance of the DSP program in simulation. Besides replicating the processor's instruction set processing logic and peripheral functions, the simulation focuses on the timing characteristics of the DSP program during runtime, guaranteeing the instruction execution cycle for complex algorithms, accurate to the time consumption of a single instruction. Further simulations are made to handle context switching latency during multi-task scheduling and response priorities during interrupt nesting, better simulating control systems such as those running RTOS, and ensuring conflict handling between PWM interrupts and fault interrupts. The modeling also addresses the timing constraints of the interaction between the DSP program and peripherals, such as the timing synchronization of the ADC sampling trigger signal and the PWM update signal, ensuring the closed-loop cycle of "sampling-calculation-output" in the program is consistent with the real system. This provides a foundation for verifying the timing logic of complex program algorithms, solving the problem of "correct program logic but substandard timing" in traditional simulations.

[0032] Step 3: Set up the DSP software runtime environment to enable the direct application of DSP programs with "zero modification", which greatly improves the convenience of control system development and verification.

[0033] This system implements a binary compatibility layer for control system software, supporting the direct loading of binary files (.out and .hex files) generated by DSP program compilation into the all-digital system without code modification or function interface adaptation. Library functions called in the program, such as trigonometric functions, filtering functions, and peripheral drivers, are executed according to real hardware logic, providing a consistent development experience with physical systems. An integrated debugger toolchain allows direct debugging of DSP programs within the simulated control system, providing real-time register monitoring, variable tracing, and breakpoint debugging capabilities. Developers can pinpoint program logic errors as if debugging real hardware. Developers do not need to learn new simulation interface specifications; they can directly utilize their existing DSP program development habits, achieving "write once, use in both virtual and physical systems," significantly reducing migration costs.

[0034] Step 4: Design and implement the model to ensure its versatility and scalability, improving the compatibility and reusability of the simulation system. Support the development and debugging of multiple types of DSP programs, adapting to different control systems.

[0035] Modular design supports program functionality expansion. When developing new types of motor control programs, peripheral modules can be added or removed to quickly adapt to the program's new hardware resource requirements without refactoring the entire simulation system. Furthermore, the processor instruction set-based core simulation is compatible with multiple program architectures, supporting the development and debugging of bare-metal programs, real-time operating system programs, and multi-core collaborative programs. This ensures that control programs with different functional characteristics can run stably in the virtual environment, meeting the program development needs of diverse motor control scenarios and improving the reusability of the simulation platform.

[0036] Step 5: Establish real-time data interaction and system closed-loop control simulation to provide a realistic control closed-loop environment for DSP program operation and support the application testing of complex algorithms.

[0037] The virtual environment operates in real time in a closed loop of "perception-decision-execution": the virtual sensor module inputs data such as current, voltage, and angle to the DSP program according to the required timing; the program outputs control signals after running complex control algorithms; the virtual drive module responds in real time and feeds back the motor status, forming a closed loop link consistent with the real system.

[0038] It supports interactive verification of complex logic in programs: for example, fault diagnosis algorithms in programs can be triggered by injecting fault signals in a virtual environment to verify the algorithm's response speed and processing logic; for multi-loop control algorithms, the effectiveness of inter-loop coupling processing can be verified by adjusting virtual load disturbances. It completely reproduces the interaction logic of programs and systems in a virtual environment, solving the problem of "difficulty in reproducing test scenarios for complex algorithms" in traditional hardware testing.

[0039] Step 6: Run the simulation system to perform multi-dimensional functional verification, realize automated testing, extreme testing and result output of DSP programs, and accelerate development iteration.

[0040] Through automated testing integration, it supports the writing of test scripts, such as Python scripts, to automate the entire process from "program loading → scenario configuration → data acquisition → result analysis." For example, a script can batch run 100 test cases with different loads and speed commands, automatically generating quantitative reports on algorithm accuracy and computational efficiency, replacing manual testing. Digital systems can undergo stress testing without worry, setting extreme scenarios that cannot be achieved in the hardware system, such as continuous power supply exceeding the rated voltage, excessive instantaneous load torque, and injection of high-frequency interference signals. This safely verifies the stability of the DSP program under extreme conditions, such as whether protection is triggered or whether program crashes occur, avoiding the risk of equipment damage during hardware testing.

[0041] After the simulation is completed, the test results can be output in real time, and a visual report containing waveforms, data tables, and error analysis can be generated directly, marking the problem points in the program and providing accurate basis for program optimization.

[0042] By improving verification efficiency through automated testing and covering scenarios that hardware cannot reach through extreme testing, the entire process of "development-debugging-verification" is accelerated, shortening the development cycle by more than 50% compared to the traditional hardware-dependent model.

[0043] Through the above process, this method not only enables the direct application and convenient development of DSP programs for motor control systems with "zero modification", but also solves the pain points of traditional hardware testing such as complex program algorithm verification, timing logic protection, and extreme scenario testing through the flexibility and security of the all-digital environment, truly forming an efficient development closed loop of "design is verification, verification is deployment".

[0044] Beneficial effects: 1. Significantly improves the accuracy of control program and algorithm verification, and solves the problems of missed fault detection and timing distortion in traditional simulation. The core improvement of this invention is "based on DSP instruction-level virtualization simulation technology + clock cycle-level event-driven model", which can accurately reproduce DSP processor core response, interrupt conflict and timing delay as low as ten nanoseconds.

[0045] Traditional simulations cannot simulate the details of DSP hardware (such as nested interrupt logic and nanosecond-level timing), resulting in a failure rate of up to 90% for faults such as PWM pulse loss, and timing errors are only at the level of hundreds of nanoseconds. However, this invention, through clock cycle-level modeling, can realistically reproduce the program running state under nested interrupt scenarios, thus effectively detecting the aforementioned hidden faults. At the same time, it compresses the timing simulation error from the level of hundreds of nanoseconds to the level of tens of nanoseconds, ensuring that the running logic and algorithm execution effect of the control program in the simulation environment are completely matched with the physical DSP, avoiding the problem of "simulation qualified but physical faulty".

[0046] 2. Eliminating dependence on physical hardware, significantly reducing verification costs and improving testing flexibility and iteration efficiency. The technical solution eliminates dependence on physical control boards, motors, power supplies and other hardware through a "fully digital closed-loop simulation loop + virtualized DSP board and peripheral environment".

[0047] Traditional verification requires purchasing hardware (high cost), waiting for hardware debugging (long cycle), and can only test one control strategy at a time (low efficiency). This solution eliminates the need for physical hardware, saving on hardware procurement and maintenance costs and avoiding the risk of equipment damage. Furthermore, it supports parallel simulation of multiple control strategies in a virtualized environment, allowing for direct quantitative comparison of control accuracy, response speed, and other indicators of different strategies. Engineers can conduct verification without waiting for the hardware to arrive, significantly improving testing iteration efficiency compared to traditional methods.

[0048] 3. Simplify the modeling process, focus on core control logic verification, solve the problem of complex physical parameter simulation in traditional simulation, and clarify that "the physical parameters of motor mechanisms and devices are not simulated, but abstracted into excitation input and control output modules", and logic verification is achieved only through digital twin external connection or data simulation.

[0049] Traditional simulations require complex modeling of physical parameters such as motor rotor inertia and device dielectric properties, which not only has a long modeling cycle but is also prone to affecting control logic verification due to simulation deviations of physical parameters. This invention abstracts non-core physical parameter modules, retaining only the core link of "control system-DSP-peripheral interface", which reduces the complexity and time cost of modeling and allows engineers to focus on the verification of core links such as control algorithm logic and DSP program interaction, avoiding interference with the core verification target due to simulation distortion of physical parameters.

[0050] 4. Achieve a fully digital closed loop of "algorithm design - virtual verification - hardware deployment", significantly shortening the development cycle. The technical solution constructs a fully digital closed loop and supports "rapid testing and comparison of motor algorithm functions and mathematical libraries".

[0051] In traditional development processes, algorithm design requires waiting for hardware production / debugging before verification, and comparing the effects of different algorithm functions and mathematical libraries requires multiple hardware tests (long cycle and low efficiency). This invention, through a fully digital closed loop, allows for immediate verification in a virtualized environment after algorithm design, and enables rapid switching between different algorithm functions or mathematical libraries for performance comparison (such as testing the effects of PID algorithm variants and filtering mathematical libraries). Early verification can be completed without relying on hardware, and hardware deployment is only required in the final stage, thus significantly shortening the entire "design-verification-deployment" cycle and greatly improving development efficiency.

[0052] 5. It has scalability, taking into account the needs of both fully digital simulation and semi-physical verification, and improving the applicability of the solution. The technical solution mentions that it can be "expanded to a semi-physical interface to realize the verification of the combination of simulation control system and motor motion mechanism".

[0053] Traditional all-digital simulation or semi-physical simulation solutions are mostly single-mode and difficult to flexibly adapt to the needs of different development stages (such as rapid all-digital iteration in the early stage and semi-physical simulation to closely resemble real-world scenarios in the later stage). This invention, by reserving a semi-physical interface, not only meets the need for efficient simulation without hardware in the early stage, but also allows for the connection of real motor motion mechanisms for semi-physical verification in the later stage of development, achieving a seamless connection between "all-digital and semi-physical". It adapts to the needs of motor control systems from the early stage of algorithm development to the later stage of system integration and debugging, and has a wider range of applicable scenarios.

[0054] The above specific embodiments further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A fully digital verification method for a motor control system, characterized in that, The verification method includes: Step S1: Define the verification object and control core parameters; Step S2: Construct a high-granularity processor digital model; Step S3: Set up the DSP software runtime environment to enable direct application of the DSP program with zero modifications; Step S4: Design and implement the model to ensure its versatility and scalability, support the development and debugging of multiple types of DSP programs, and adapt to different control systems; Step S5: Establish real-time data interaction and system closed-loop control simulation; Step S6: Run the simulation system to perform multi-dimensional functional verification, and realize automated testing, extreme testing and result output of the DSP program.

2. The all-digital verification method for a motor control system according to claim 1, characterized in that, Step S1, defining the verification object and control core parameters, specifically includes: Identifying the core components and key parameters of the system to be verified lays the foundation for the direct application of DSP programs and adaptation to the simulation environment. Simultaneously determine the development environment for the DSP program to ensure seamless compatibility between the subsequent virtual environment and the program development environment; The core functional modules of the DSP program are identified, and the hardware resource requirements are clarified, including timer interrupt frequency and ADC sampling channels, to provide a basis for resource configuration in the virtual environment. By accurately matching program development dependencies with hardware parameters, a prerequisite is provided for the program to be directly loaded and run.

3. The all-digital verification method for a motor control system according to claim 2, characterized in that, The key parameters include specific processor architecture, clock speed, and peripheral hardware parameters.

4. The all-digital verification method for a motor control system according to claim 1, characterized in that, Step S2: Constructing a high-granularity processor digital model specifically includes: Modeling with instruction-level and clock cycle-level precision ensures that the timing logic and real-time performance of the DSP program are fully reproduced in the simulation. In addition to replicating the processor's instruction set processing logic and peripheral functions, the focus is on simulating the timing characteristics of DSP programs during runtime to ensure the instruction execution cycle for complex algorithms is accurate to the time consumption of a single instruction. Simulate context switching latency during multi-task scheduling and response priority during interrupt nesting as needed to ensure conflict handling between PWM interrupts and fault interrupts; Timing constraints for modeling the interaction between the DSP program and peripherals: Synchronize the timing of the ADC sampling trigger signal and the PWM update signal to ensure that the closed-loop cycle of sampling-calculation-output in the program is consistent with the real system.

5. The all-digital verification method for a motor control system according to claim 1, characterized in that, Step S3: Setting up the DSP software runtime environment to enable direct application of the DSP program with zero modification specifically includes: A binary compatibility layer for control system software is built, which supports the direct loading of binary files generated by DSP program compilation, such as .out and .hex files, into the all-digital system without modifying the code or adapting function interfaces. The library functions called in the program, such as trigonometric functions, filtering functions, and peripheral drivers from the math library, are executed according to the actual hardware logic, which is consistent with the real-world development experience. An integrated debugger toolchain supports direct debugging of DSP programs in simulated control systems, providing real-time register monitoring, variable tracing, and breakpoint debugging functions, allowing developers to locate program logic errors as if debugging real hardware. Developers do not need to learn new simulation interface specifications and can directly use their existing DSP program development habits.

6. The all-digital verification method for a motor control system according to claim 1, characterized in that, Step S4: Designing and implementing the model's versatility and scalability to support the development and debugging of multiple types of DSP programs and adapt to different control systems specifically includes: Modular design supports program function expansion. When developing new types of motor control programs, peripheral modules can be added or removed to adapt to the new hardware resource requirements of the program without reconstructing the entire simulation system. The core simulation based on the processor instruction set is compatible with multiple program architectures, supporting the development and debugging of bare-metal programs, real-time operating system programs, and multi-core collaborative programs. It ensures that control programs with different functional characteristics can run stably in the virtual environment to meet the program development needs of diverse motor control scenarios.

7. The fully digital verification method for a motor control system according to claim 1, characterized in that, Step S5: Establishing real-time data interaction and system closed-loop control simulation specifically includes: The virtual environment operates in real time in a closed loop of "perception-decision-execution": the virtual sensor module inputs data such as current, voltage, and angle to the DSP program according to the required timing; the program outputs control signals after running complex control algorithms; the virtual drive module responds in real time and feeds back the motor status, forming a closed loop link consistent with the real system; Supports interactive verification of complex logic in programs: such as fault diagnosis algorithms in programs, which can be triggered by injecting fault signals in a virtual environment to verify the response speed and processing logic of the algorithm; for multi-loop control algorithms, the effectiveness of inter-loop coupling processing can be verified by adjusting virtual load disturbances. The interaction logic of the program and system is fully reproduced in a virtual environment.

8. The all-digital verification method for a motor control system according to claim 1, characterized in that, Step S6: Running the simulation system to perform multi-dimensional functional verification, realizing automated testing, stress testing, and result output of the DSP program, specifically includes: Through automated test integration, it supports the writing of test scripts to achieve full automation of the "program loading → scenario configuration → data collection → result analysis" process; Digital systems can be subjected to extreme testing without worry, setting up extreme scenarios that cannot be achieved in hardware systems to safely verify the stability of DSP programs under extreme conditions. After the simulation is completed, the test results are output in real time, and a visual report containing waveforms, data tables, and error analysis is generated directly, marking the problem points in the program; By conducting extreme tests to cover scenarios that hardware cannot reach, the entire "development-debugging-verification" process is ultimately accelerated.

9. The all-digital verification method for a motor control system according to claim 1, characterized in that, The extreme scenarios specifically include: continuous power supply exceeding the rated voltage, excessive instantaneous load torque, and injection of high-frequency interference signals.

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