Verification method, system and equipment for logic system design and storage medium

Abstract

The invention provides a verification method for logic system design and related equipment. The method comprises the steps that global analysis is conducted on source codes of the logic system design; generating a grouping system task based on a plurality of continuous non-blocking assignment statements meeting a preset grouping condition; updating an interface signal name based on modport definition and clock block definition; generating a virtual interface system task in a reference module where the non-blocking assignment statement is located so as to update the non-blocking assignment statement; constructing a mapping relation between the interface signal and the non-blocking assignment information; allocating a temporary storage space for the interface signal referenced by the non-blocking assignment statement in the interface module; based on the mapping relation and the temporary storage space, determining a non-blocking assignment write-in function and a non-blocking assignment cache function, and generating a target code; and transmitting a target value of the non-blocking assignment expression of the temporary storage space to an interface signal in the operation process of the target code so as to simulate the logic system design.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of verification, in particular to a logic system design verification method, system, device and storage medium. BACKGROUND

[0002] Virtual interface provides a communication pipeline for communication between testbench and DUT (Design Under Test), which can flexibly connect DUT to testbench without passing signals through module ports one by one. Through virtual interface, signals in physical interface can be accessed and read and written, and one typical usage is to update the value of signals in physical interface through non-blocking assignment of virtual interface.

[0003] At present, the event-driven digital simulator is not different from general non-blocking assignment when implementing non-blocking assignment involving virtual interface. For example, when encountering non-blocking assignment statement, first calculate the expression (RHS) on the right side of non-blocking statement, then store the value, propagation, chip selection information and other related information of RHS in a piece of memory space (such as Dynamic NBA memory pool or the memory of current module instance) applied for RHS by current module instance, then execute event-driven operation (representing NBA assignment write operation), put the event into NBA event queue (NBA event region), and finally the simulator updates the expression (LHS) on the left side of non-blocking statement according to the value in the above-mentioned VI NBA reserved space when the event is scheduled to the event in the NBA event queue. However, this way has the problems of long simulation time, low efficiency and large memory space occupation. SUMMARY

[0004] Therefore, the purpose of the present application is to provide a logic system design verification method, system, device and storage medium.

[0005] In a first aspect, the present application provides a logic system design verification method, comprising: performing global analysis on source code of the logic system design to determine non-blocking assignment statement of virtual interface and interface signal referenced by the non-blocking assignment statement; based on a plurality of continuous non-blocking assignment statements satisfying a preset grouping condition, generating a grouping system task in an interface module where the interface signal is located in the source code, to obtain first intermediate code; the grouping system task is used to indicate grouping information of the interface signal; updating an interface signal name of the interface signal in the first intermediate code based on a modport definition and a clock block definition in the interface module, to obtain a second intermediate code; generating a virtual interface system task in a reference module where the non-blocking assignment statement is located based on the grouping information, to update the non-blocking assignment statement of the second intermediate code, to obtain a third intermediate code; the virtual interface system task includes a virtual interface signal in the non-blocking assignment statement and a corresponding non-blocking assignment expression; constructing a mapping relationship between the non-blocking assignment information of the interface signal and the virtual interface signal; the non-blocking assignment information includes non-blocking assignment write function information, whether it is a single non-blocking assignment statement, and an expression of the virtual interface signal; allocating temporary storage space for the interface signal referenced by the non-blocking assignment statement in the interface module; generating a non-blocking assignment write function in the interface module of the third intermediate code, generating a non-blocking assignment cache function in the reference module, and generating a corresponding non-blocking assignment trigger event based on the mapping relationship and the temporary storage space, to obtain a fourth intermediate code; generating target code based on the fourth intermediate code; in response to detecting the non-blocking assignment trigger event during the running process of the target code, transmitting a target value corresponding to the non-blocking assignment expression stored in the temporary storage space to the interface signal, to simulate the logical system design.

[0006] In a second aspect, the application provides a verification system for a logical system design, comprising: a compiler, configured to: perform global analysis on source code of the logical system design, to determine a non-blocking assignment statement of a virtual interface and an interface signal referenced by the non-blocking assignment statement; generate a grouping system task in an interface module where the interface signal is located in the source code based on a plurality of continuous non-blocking assignment statements satisfying a preset grouping condition, to obtain a first intermediate code; the grouping system task is used to indicate grouping information of the interface signal; update an interface signal name of the interface signal in the first intermediate code based on a modport definition and a clock block definition in the interface module, to obtain a second intermediate code; generate a virtual interface system task in a reference module where the non-blocking assignment statement is located based on the grouping information, to update the non-blocking assignment statement of the second intermediate code, to obtain a third intermediate code; the virtual interface system task includes a virtual interface signal in the non-blocking assignment statement and a corresponding non-blocking assignment expression; mapping relationship between the interface signals and non-blocking assignment information of the virtual interface signals is constructed; the non-blocking assignment information includes non-blocking assignment write function information, whether it is a single non-blocking assignment statement and an expression of the virtual interface signal; allocating temporary storage space for the interface signals referenced by the non-blocking assignment statement in the interface module; based on the mapping relationship and the temporary storage space, generating a non-blocking assignment write function in the interface module of the third intermediate code, generating a non-blocking assignment cache function in the reference module, and generating a corresponding non-blocking assignment trigger event, to obtain a fourth intermediate code; generating target code based on the fourth intermediate code; an emulator configured to, in response to detecting the non-blocking assignment trigger event during execution of the target code, pass a target value corresponding to the non-blocking assignment expression stored in the temporary storage space to the interface signal, to simulate the logical system design.

[0007] In a third aspect, an electronic device is provided, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the method of the first aspect when executing the program.

[0008] In a fourth aspect, a non-transitory computer-readable storage medium is provided, which stores computer instructions for causing a computer to execute the method of the first aspect.

[0009] It can be seen from the above that the application provides a logic system design verification method, system, device and storage medium. By global analysis, non-blocking assignment statements and their referenced interface signals are identified, and grouped system tasks are generated in the interface module for continuous assignment statements that meet the grouping conditions to clarify the signal grouping information; then, the interface signal name is updated in combination with the modport and clock block definition, and virtual interface system tasks are generated in the referenced module to reconstruct the assignment logic. Next, the compiler builds the mapping relationship between the interface signal and the non-blocking assignment information, allocates temporary storage space to cache the RHS value, and generates write / cache functions and trigger events, and finally outputs the optimized target code. When the trigger event is detected during the running of the target code, the temporarily stored target value is transmitted to the interface signal to ensure the timing correctness. The NBA events corresponding to the VIs in the same group are no longer driven by events one by one, but are driven by events in groups, which reduces the number of events added to the NBA event queue, thereby reducing the simulation time required for event-driven queue traversal and event processing. In addition, since the VIs in the same group have similar prefixes, the virtual interface expression in the LHS expression and the interface instance pointer obtained according to the virtual interface do not need to be calculated repeatedly, and the null check of the virtual interface also does not need to be performed repeatedly, but can be processed at one time, further improving the performance of the simulation. In addition, multiple VINBA assignments are performed on the same interface signal, and the same memory space is reused before the VINBA assignment is completed, thereby reducing the memory space occupied by the VINBA during simulation. BRIEF DESCRIPTION OF DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the application or the related art, the following will briefly introduce the drawings needed to be used in the embodiments or the related art description. Obviously, the drawings in the following description only belong to the embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0011] Figure 1 A structural schematic diagram of an exemplary electronic device according to an embodiment of the application is shown.

[0012] Figure 2A A schematic diagram of an exemplary simulation tool according to an embodiment of the disclosure is shown.

[0013] Figure 2B A schematic diagram of an exemplary compiler of the application is shown.

[0014] Figure 3 A schematic flowchart of a logic system design verification method according to an embodiment of the application is shown. DETAILED DESCRIPTION

[0015] For the purpose of making the purpose, technical solutions and advantages of the present application more clear, the present application is further described in detail below with reference to specific embodiments and drawings.

[0016] It should be noted that, unless otherwise defined, technical terms or scientific terms used in the embodiments of the present application should be understood as their common meanings to those skilled in the art to which the present application belongs. The terms "first", "second" and similar terms used in the embodiments of the present application do not represent any order, number or importance, but are only used to distinguish different components. The terms "include" or "contain" and similar terms mean that the elements or objects before the terms cover the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0017] In the field of chip verification, the concept of virtual interface is introduced in the SystemVerilog language reference manual (LRM) to solve the problem that interface cannot be instantiated in object-oriented programming (OOP) test platform. The virtual interface is essentially a pointer to an interface instance, and the virtual interface is often instantiated as a class property in SystemVerilog class, allowing users to access the signals and other members (such as functions) in the interface through the pointer of the virtual interface. The virtual interface provides a communication pipeline for the communication between the test platform and the DUT, and can flexibly connect the DUT to the test platform without passing signals through module ports one by one. Through the virtual interface, the signals in the interface can be accessed and read and written, and one typical use is to update the value of the signals in the interface through the non-blocking assignment of the virtual interface.

[0018] Currently, the event-driven digital simulator is not different from the general non-blocking assignment in implementing the non-blocking assignment involving the virtual interface. The main implementation idea is as follows: when a non-blocking assignment statement is encountered, the right side expression (RHS) of the non-blocking statement is calculated first, then the value, propagation, slice selection information and other related information of the RHS are stored in a piece of memory space (for example, Dynamic NBA memory pool, or the memory of the current module instance) applied by the current module instance for the RHS, then the event-driven operation (representing NBA assignment write operation) is executed, the event is put into the NBA event queue (NBA event region), and finally the simulator updates the right side expression (LHS) of the non-blocking statement according to the value in the above VI NBA reserved space when the event is scheduled to the event in the NBA event queue.

[0019] However, the event-driven simulator has the following problems when implementing the non-blocking assignment involving the virtual interface: When multiple non-blocking assignments involving the virtual interface are simple and similar in form (the NBA prefixes are the same virtual interface expression, only the accessed interface member signal is different, and no slice selection is involved, refer to the form in the example), the management (application, initialization, deinitialization, release, etc.) of the memory space for caching the value of the RHS will consume certain simulation time, and the event-driven operation is executed multiple times, which will increase the number of NBA events in the NBA event queue, and the simulation time will also be consumed more for event-driven queue traversal, LHS expression calculation, calculation of interface instance pointer according to the virtual interface, null value check of the virtual interface expression in the LHS expression, and event processing. In particular, when such non-blocking assignments involving the virtual interface occur more in the design, the simulation time consumed will also increase significantly.

[0020] After calculating the value of the RHS of the non-blocking assignment involving the virtual interface, the RHS value and its related information need to be stored in a piece of memory space (for example, Dynamic NBA memory pool) applied by the current module instance for the RHS. When multiple VI NBA assignments (even for the same interface signal access) are performed, more memory space needs to be occupied before the VI NBA assignment ends, which may cause a problem of large memory space occupation during simulation.

[0021] Therefore, how to reduce the simulation time, improve the simulation efficiency, and reduce the memory space occupation has become a technical problem to be solved.

[0022] Figure 1 The structure schematic diagram of an electronic device 100 according to an embodiment of the present application is shown. The electronic device 100 can be an electronic device running a simulation system. As shown inFigure 1 As shown, the electronic device 100 can include a processor 102, a memory 104, a network interface 106, a peripheral interface 108, and a bus 110. Among them, the processor 102, the memory 104, the network interface 106, and the peripheral interface 108 are communicatively connected to each other inside the electronic device through the bus 110.

[0023] The processor 102 can be a Central Processing Unit (CPU), a graphics processor, a neural network processor (NPU), a microcontroller (MCU), a programmable logic device, a digital signal processor (DSP), an Application Specific Integrated Circuit (ASIC), or one or more integrated circuits. The processor 102 can be configured to perform functions related to the techniques described in the present application. In some embodiments, the processor 102 can also include multiple processors integrated as a single logical component. As Figure 1 As shown, the processor 102 can include multiple processors 102a, 102b, and 102c.

[0024] The memory 104 can be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). In some embodiments, a simulation test system for simulating a test design can be a computer program stored in the memory 104. As Figure 1 As shown, the memory-stored data can include program instructions (e.g., program instructions for implementing a verification system of the present application) and data to be processed (e.g., the memory can store temporary code generated in a compilation process). The processor 102 can also access the memory-stored program instructions and data, and execute the program instructions to operate on the data to be processed. The memory 104 can include volatile storage devices or non-volatile storage devices. In some embodiments, the memory 104 can include Random Access Memory (RAM), Read-Only Memory (ROM), optical discs, magnetic discs, hard discs, Solid State Drives (SSDs), flash memories, memory sticks, etc.

[0025] The network interface 106 can be configured to provide communication with other external devices to the electronic device 100 via a network. The network can be any wired or wireless network capable of transmitting and receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, Near Field Communication (NFC), etc.), a cellular network, the Internet, or a combination of the above. It can be understood that the type of network is not limited to the above specific examples. In some embodiments, the network interface 106 can include any combination of any number of Network Interface Controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, etc.

[0026] The peripheral interface 108 can be configured to connect the electronic device 100 with one or more peripheral devices to enable information input and output. For example, the peripheral devices can include input devices such as keyboards, mice, touchpads, touchscreens, microphones, various sensors, and the like, and output devices such as displays, speakers, vibrators, indicator lights, and the like.

[0027] The bus 110 can be configured to transfer information between various components (e.g., the processor 102, the memory 104, the network interface 106, and the peripheral interface 108) of the electronic device 100, such as an internal bus (e.g., a processor-memory bus), an external bus (a USB port, a PCI-E bus), and the like.

[0028] It should be noted that although the above electronic device architecture only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108, and the bus 110, in a specific implementation process, the electronic device architecture can also include other components necessary for normal operation. In addition, those skilled in the art can understand that the above electronic device architecture can also only contain components necessary for implementing the embodiments of the present application, and does not necessarily contain all the components shown in the figure.

[0029] Figure 2A A schematic diagram of an example simulation tool 200 according to embodiments of the present disclosure is shown. The simulation tool 200 can be a computer program running on the electronic device 100 or a hardware (e.g., a prototype verification board or a hardware emulator) connected to the electronic device 100 as a host.

[0030] In the field of chip design, a design can generally be simulated using a simulation tool. The simulation tool can be, for example, a software simulation tool or a hardware simulation tool, etc. Figure 2A The example software simulation tool 200 shown can include a compiler 210 and a simulator 220. The compiler 210 can receive source code 204 (e.g., a hardware description language such as VHDL, Verilog, SystemVerilog, etc.) and compile it into execution code 206 (e.g., machine code, assembly code, software code, etc.). It can be understood that the description of a logic system design can be described in a hardware description language (HDL), a register transfer level (RTL) language, binary code, assembly code, or machine code, etc. The simulator 220 can simulate according to the execution code 206 and output the simulation result 208. For example, the simulation tool 200 can output the simulation result 208 to an output device (e.g., displayed on a display) via the peripheral interface 108 of the electronic device 100. Figure 1 ​

[0031] Figure 2B FIG. 1 illustrates an exemplary compiler 210 according to an embodiment of the present application. As shown, the compiler 210 can include a front-end 212, a middle-end 214, and a back-end 216. Figure 2B

[0032] The front-end 212 can be configured to analyze the source code in terms of its lexical, syntactic, and semantic according to a specific source language.

[0033] After the lexical, syntactic, and semantic analysis of the source code, the middle-end 214 can convert the source code into an intermediate representation (or intermediate code), and can optimize the intermediate representation. The intermediate language (or intermediate code) is a syntax-oriented, equivalent internal representation code of the source code that is easy to translate into an object program. Its understandability and ease of generating execution code are between the source code and the execution code. Common intermediate codes include reverse Polish notation, four-operand form, three-operand form, and tree representation, etc. For example, the middle-end 214 can remove useless code, remove inaccessible code, clean up unused variables, etc. The optimization can include machine-dependent optimization and machine-independent optimization. The machine-dependent optimization, for example, can be optimization for a test platform (TB), and can utilize some characteristics of the test platform to help the optimization. The machine-independent optimization, for example, can be optimization for a design under test (DUT). The optimized intermediate representation can then be passed to the back-end 126 for further processing.

[0034] The back-end 216 can further optimize the intermediate representation according to the architecture of the target processor (e.g., the processor 102), and generate execution code. Generally, the execution code is machine code. Figure 1

[0035] It can be understood that the structure of the compiler is not limited to the example of Figure 2B The front-end 212 and the middle-end 214 can be collectively referred to as the front-end of the compiler.

[0036] The compiler 210 can generate execution code based on computer code to be compiled. The computer code to be compiled can also be referred to as source code, such as a written logic system design. Generally, the source language of the written source code is a high-level programming language. The high-level programming language can be the software programming language or the hardware programming language described above. The execution code can be, for example, assembly code, machine code, etc. Generally, the compiler 210 can be stored in a computer readable medium, such as a computer disk, a CD-ROM, a DVD, a USB flash disk, a memory card, etc. Figure 1 ​​The compiler 210 is shown in the memory 104 and is executed by the processor 102 to compile the logic system design into execution code. The compiler 210 can convert the description of the logic system design from a high-level language description (e.g., an HDL language) to a lower-level description (e.g., an RTL language or binary code) so that the underlying hardware can execute the logic system design.

[0037] It can be appreciated that software, including the compiler 210, is still necessary for the hardware emulation tool. The software can be executed on the electronic device 100 that is connected to the hardware emulation tool as a host.

[0038] In SystemVerilog, a virtual interface usually provides a connection point in the form of a class so that the signals in a physical interface can be passed through the virtual interface. Since the nature of the physical interface is static and the class and program are dynamic, the physical interface cannot be defined in the class or program, but only the virtual interface can be defined in the class or program as a parameter to pass the signals to the physical interface. The definition of the program can further include the definition of the virtual interface, the connection of the virtual interface to the physical interface, and the assignment of the virtual interface. The connection of the virtual interface to the physical interface can be the connection between the first port of the virtual interface and the second port of the physical interface so that the first port of the virtual interface can pass the signals to the second port of the physical interface. In some embodiments, the assignment of the virtual interface can be the assignment to the first port of the virtual interface, and the assignment can be further divided into writing data to the virtual interface and reading data from the virtual interface. Through these codes, the actual physical interface is connected to the virtual interface, and the signals of the physical interface can be read or output to the physical interface through the virtual interface.

[0039] To implement the function of passing the signals between the virtual interface and the physical interface through the passing of the parameters, the compiler 120 can further create a mirror class corresponding to the virtual interface when compiling the code. For example, when the compiler processes the virtual interface, a definition of a mirror class can be generated accordingly and an instance of the mirror class can be instantiated. After the definition and instantiation of the mirror class are completed, the compiler 120 can implement the connection process of the virtual interface to the physical interface through the system task of the compiler 120 when compiling the test program.

[0040] Referring to Figure 3 , Figure 3 A schematic flowchart of a method for verifying a logic system design is shown. The method for verifying a logic system design according to an embodiment of the present disclosure can be deployed on a terminal or a server. Figure 3 In the method for verifying a logic system design 300, the method for verifying a logic system design can further include the following steps.

[0041] In step S310, global analysis is performed on the source code of the logic system design to determine the non-blocking assignment statements of the virtual interface and the interface signals referenced by the non-blocking assignment statements.

[0042] Wherein, through global analysis on the source code of the logic system design, the system systematically identifies all non-blocking assignment (VI NBA) statements of the virtual interface, accurately locates the interface signals referenced by these statements, and comprehensively perceives and marks the related design structures (such as modport, clocking block, etc.). This method effectively solves the problem of invisible interface signal reference in the split compilation environment, ensures the complete identification and processing of VI NBA by the compiler, thereby laying a foundation for subsequent grouping optimization, temporary space allocation and runtime event scheduling, significantly improving the accuracy and efficiency of design verification, and guaranteeing the functional and timing correctness of complex chip design.

[0043] Specifically, considering that the interface signal cannot be perceived whether it has a VI NBA reference when the interface is split and compiled, global analysis of the VI NBA is required for the entire design. The interface signals involved in the left-hand side expression (LHS) of the VI NBA statement are marked (for example, IS_VINTF_NBA_REFEREE, the interface signals involving modport and clocking blocks will be marked in the subsequent steps), indicating that the interface signal is referenced by the VI NBA.

[0044] In step S320, based on a plurality of continuous non-blocking assignment statements satisfying a preset grouping condition, a grouping system task is generated in the interface module where the interface signal is located in the source code, to obtain a first intermediate code; the grouping system task is used to indicate grouping information of the interface signal.

[0045] Wherein, by identifying a plurality of virtual interface non-blocking assignment (VI NBA) statements that are continuous and satisfy a preset grouping condition (such as similar form, quantity standard, containing specific control signals, etc.), a grouping system task is automatically generated in the interface module to which the interface signal belongs, the grouping attribution of the interface signal is determined, and a first intermediate code is formed. In this way, by aggregating related assignment operations, the signal management efficiency is optimized, the overhead of independent operations in subsequent processing is reduced, and the grouping information provides a basis for temporary space sharing and event scheduling merging, thereby improving the performance and resource utilization rate of large-scale design in the compilation and simulation stages.

[0046] In some embodiments, based on a plurality of continuous non-blocking assignment statements satisfying a preset grouping condition, a grouping system task is generated in the interface module where the interface signal is located in the source code, to obtain a first intermediate code, comprising: determining signal node information in the left expression of the non-blocking assignment statement, the signal node information including interface signal name, modport node name, clock block node name, modport port node name, and node type; in response to a plurality of the non-blocking assignment statements satisfying the preset grouping condition, determining the interface signals corresponding to the plurality of the non-blocking assignment statements as the same group of signals; generating the grouped system tasks in the corresponding interface modules based on the signal node information associated with the same group of signals; wherein the grouped system tasks of the same interface module are generated in the same initialization statement; grouping the plurality of the non-blocking assignment statements satisfying the preset grouping condition in the source code and generating the corresponding grouped system tasks to obtain the first intermediate code.

[0047] In the method, detailed signal node information (such as interface signal name, modport node name, etc.) in the left expression of the non-blocking assignment statement is extracted, it is judged whether the continuous statements satisfy the preset grouping condition, the interface signals meeting the condition are classified into the same group, and the grouped system tasks are generated in the same initialization statement of the interface module to record the grouping information. Finally, all the statements meeting the condition are grouped and processed to output the first intermediate code. In this way, through the detailed signal classification and task aggregation, the organization and management of the interface signals are optimized, the number of independent tasks is reduced, the compiling efficiency is improved, and the foundation is laid for subsequent temporary space sharing and event scheduling optimization, thereby improving the resource utilization rate and simulation performance in large-scale design.

[0048] Specifically, the process analyzes consecutive VI NBA statements, collecting information such as interface signals, modport nodes, clocking block nodes, and modport port nodes (ports) involved in the left-hand side expression (LHS) of the VI NBA statements. It checks whether consecutive VI NBA statements meet preset grouping conditions (whether the forms are relatively fixed and similar, whether the number of VI NBA statements reaches a certain number, whether chip select is included, etc.). If satisfied, a grouped system task is created. This grouped system task can include interface signal names, modport node names, clocking block node names, modport port node names (ports), and the type of each node (signal / modport / clocking block / port, etc.). Multiple consecutive VI NBA statements will be assigned to different grouped system tasks, potentially creating multiple grouped system tasks. All grouped system tasks within the same interface are created in the same initialization statement, and this initialization statement will have corresponding markers (such as attribute or user flag) to indicate that all statements under this initialization statement are grouped system tasks.

[0049] In step S330, the interface signal name of the interface signal in the first intermediate code is updated based on the modport definition and clock block definition in the interface module to obtain the second intermediate code.

[0050] Specifically, by parsing the modport and clocking block definitions in the interface module, the interface signal names in the first intermediate code are normalized and updated. The original signal names are replaced with complete path names containing modport context and clock domain information (such as interface_name.modport_name.signal_name or a qualified name combined with the clock block). This ensures the uniqueness of signal references and the accuracy of context, eliminating naming ambiguities caused by module instantiation or clock domain overlap, thus obtaining the second intermediate code. This improves code readability and maintainability, and provides a precise signal identification basis for subsequent grouping optimization, temporary space allocation, and simulation event scheduling, avoiding simulation errors caused by naming conflicts.

[0051] In some embodiments, the interface signal name of the interface signal in the first intermediate code is updated based on the modport definition and clock block definition in the interface module to obtain the second intermediate code, including: Update the interface signal name in the first intermediate code based on the modport definition; Asynchronous signals and asynchronous mask signals are determined based on the clock block definition, and the interface signal name, clock block node name, and node type in the first intermediate code are updated based on the asynchronous signals and asynchronous mask signals.

[0052] Specifically, based on the modport definition, the interface signal names in the first intermediate code are expanded to fully qualified names including the modport context (e.g., interface.modport.signal), ensuring the uniqueness of signals across different modports under the same interface. Furthermore, asynchronous signals and their mask signals are identified based on clock block definitions, and signal names, clock block node names, and node types are updated synchronously, ensuring that signal naming accurately reflects clock domains and synchronization attributes. This effectively resolves naming ambiguities in scenarios with multiple clock domains and interface reuse, improves code readability and simulation accuracy, and provides structured signal identifiers for subsequent non-blocking assignment grouping optimization and event scheduling, enhancing the reliability of large-scale design verification.

[0053] Specifically, during the modport rewriting phase, in addition to performing normal modport rewriting on the modports within the interface, it is also necessary to update the old signal names in the system tasks of the Interface Member NBA group based on the changes in signal names before and after the rewriting, and mark the rewritten interface signals (e.g., IS_VINTF_NBA_REFEREE) to indicate that the internal interface signals rewritten by the modport are referenced by VI NBA. During the clocking blocks rewriting phase, in addition to performing normal rewriting on the clocking blocks within the interface, it is also necessary to update the corresponding clocking block nodes and old signal names in the system tasks of the Interface Member NBA group using the asynchronous signals (imm sig) and asynchronous mask signals (imm mask sig) rewritten by the clocking blocks, based on the changes in signal names before and after the rewriting. The corresponding node types will also be updated (clocking block type updated to signal type). The interface signals rewritten by the clocking blocks (e.g., IS_VINTF_NBA_REFEREE) are also marked to indicate that the internal interface signals rewritten by the clocking blocks are referenced by VI NBA.

[0054] In step S340, a virtual interface system task is generated in the reference module where the non-blocking assignment statement is located based on the grouping information, so as to update the non-blocking assignment statement of the second intermediate code and obtain the third intermediate code; the virtual interface system task includes the virtual interface signal and the corresponding non-blocking assignment expression in the non-blocking assignment statement.

[0055] Based on grouping information, a system task containing virtual interface signals and their non-blocking assignment expressions is automatically generated in the referencing module. This reconstructs the original scattered non-blocking assignment statements into a structured task call format, thereby updating the second intermediate code and generating the third intermediate code. By aggregating multiple related non-blocking assignments into a single system task, code redundancy is significantly reduced and readability is improved. Simultaneously, the system task encapsulates signal grouping and expression logic, providing a unified execution unit for subsequent temporary storage allocation and event scheduling. This effectively optimizes resource utilization and operational efficiency during the simulation phase, and is particularly suitable for centralized management of high-frequency non-blocking assignment operations in large-scale designs.

[0056] In some embodiments, a virtual interface system task is generated in the reference module where the non-blocking assignment statement is located based on the grouping information, so as to update the non-blocking assignment statement of the second intermediate code and obtain the third intermediate code, including: Based on the grouping information, determine the non-blocking assignment statements in the same group; The virtual interface system task is generated based on the virtual interface signal on the left and the non-blocking assignment expression on the right in the same set of non-blocking assignment statements; The third intermediate code is obtained by replacing the same group of non-blocking assignment statements in the second intermediate code based on the virtual interface system task.

[0057] Specifically, by grouping information, the left-hand virtual interface signals and right-hand assignment expressions of the same group of non-blocking assignment statements are encapsulated into a unified virtual interface system task. This task then replaces the corresponding multiple assignment statements in the second intermediate code, thereby generating the third intermediate code. This aggregation of multiple assignment operations into a structured task call not only simplifies the code structure and improves maintainability, but also provides a unified execution unit for subsequent temporary storage allocation and event scheduling through task-level encapsulation. This effectively reduces redundant operations and resource overhead during simulation, making it particularly suitable for large-scale design verification in high-frequency non-blocking assignment scenarios, significantly improving compilation efficiency and simulation performance.

[0058] Specifically, in the referrer module where the VI NBA is referenced, the continuous VI NBA statements satisfying the VI NBA group condition are rewritten to create a vi nba group system task, which contains the VI NBA left value expression, VI NBA right value expression and other corresponding information of each VI NBA assignment statement.

[0059] In step S350, a mapping relationship between the interface signal and the non-blocking assignment information of the virtual interface signal is constructed; the non-blocking assignment information includes non-blocking assignment write function information, whether it is a single non-blocking assignment statement and an expression of the virtual interface signal.

[0060] Among them, for the interface signal referenced by the non-blocking assignment statement, that is, the marked interface signal (for example, IS_VINTF_NBA_REFEREE), the non-blocking assignment details (such as write function pointer, assignment expression, statement type mark, etc.) between the interface signal and the virtual interface signal can be extracted, and a structured mapping relationship is constructed to clearly show the corresponding virtual interface assignment behavior characteristics (whether it is a single assignment, expression content, etc.) of each interface signal. This mapping relationship can assist in generating non-blocking assignment information table, and at the same time, through the statement type mark, the event scheduling strategy is optimized (such as simplifying the trigger logic when it is not a single non-blocking assignment), finally realizing the fine management and efficient execution of the non-blocking assignment operation, and improving the timing accuracy and resource utilization in large-scale design simulation.

[0061] Specifically, the system task information of the grouping system task in the interface can be cached, that is, the parameter information in the grouping system task in the interface is collected and cached in a certain memory data structure. After the caching is completed, the grouping system task in the interface is deleted.

[0062] Further, the system task information of the grouping system task cached in the memory can be analyzed, a mapping relationship from the interface signal to the VI NBA information (including NBA write function information, whether it is a single VI NBA, LHS side interface signal expression, etc.) is established, and is stored in an intermediate representation (IR) data structure, which is used to assist the code analysis and code generation of the back end.

[0063] In step S360, temporary storage space is allocated for the interface signal referenced by the non-blocking assignment statement in the interface module.

[0064] The mapping relationship between the virtual interface signal and the non-blocking assignment expression is used to allocate independent temporary storage space for the referenced interface signal, which is used to buffer the calculation result of the right side expression in the non-blocking assignment operation, so that the left side interface signal can be correctly updated at the clock edge or at the trigger of a specific event. In this way, by explicitly allocating temporary storage, the data race and overwrite problems between multiple non-blocking assignment statements are avoided, and the step-by-step calculation and delayed writing of complex expressions are supported, thereby effectively improving the reliability and timing accuracy of data update in the simulation process, and providing a stable data foundation for subsequent event scheduling and waveform verification. Specifically, according to the LHS side interface signal of the VI NBA, temporary space is reserved for the RHS expression of the VI NBA, which is used to buffer the RHS value.

[0065] In step S370, based on the mapping relationship and the temporary storage space, a non-blocking assignment write function is generated in the interface module of the third intermediate code, a non-blocking assignment cache function is generated in the reference module, and a corresponding non-blocking assignment trigger event is generated, to obtain a fourth intermediate code.

[0066] In the interface module, a non-blocking assignment write function is generated (responsible for writing the calculation result to the temporary storage of the target signal), in the reference module, a non-blocking assignment cache function is generated (used to temporarily store the right side expression result to the temporary space), and a trigger event is generated (associated with the clock edge or the condition signal to drive the write operation), and finally integrated into the fourth intermediate code. Through function encapsulation and event-driven mechanism, the decoupling and asynchronous execution of non-blocking assignment are realized, ensuring the timing correctness of data update, optimizing the memory access efficiency in the simulation process, and improving the maintainability and simulation performance of the code.

[0067] In some embodiments, based on the mapping relationship and the temporary storage space, a non-blocking assignment write function is generated in the interface module of the third intermediate code, a non-blocking assignment cache function is generated in the reference module, and a corresponding non-blocking assignment trigger event is generated, to obtain a fourth intermediate code, including: For a single non-blocking assignment statement, a first write function number of a first non-blocking assignment write function, a first write function pointer of the first non-blocking assignment write function, and the first non-blocking assignment write function are allocated in the interface module of the third intermediate code, and the first non-blocking assignment write function is used to update the target value in the temporary storage space to the corresponding interface signal in the running process of the target code. In the reference module, a first cache function number of the first non-blocking assignment cache function is allocated and a first non-blocking assignment cache function is generated, which is used to cache the target value of the non-blocking assignment expression into the temporary storage space.

[0068] In the interface module, a unique function number and pointer are allocated for the write operation for a single non-blocking assignment statement, and a dedicated write function is generated to realize the directed update of the temporary storage to the interface signal. At the same time, in the reference module, a cache function number is allocated and a cache function is generated, which is responsible for temporarily storing the assignment expression result to the temporary space. Through the explicit management of the function number and the pointer, the decoupling and precise control of the assignment process are realized, which not only guarantees the timing reliability of data update (the write function strictly depends on the trigger event for execution), but also optimizes the memory access efficiency (the cache function independently processes the expression calculation), especially suitable for high-frequency non-blocking assignment scenarios, effectively improving the parallel processing capability and code maintainability of large-scale design simulation.

[0069] Specifically, for a single VI NBA, a function number of a non-blocking assignment write function and a function pointer of the non-blocking assignment write function are allocated in a referee module (interface) of the VI NBA, and a non-blocking assignment write function (e.g., VI NBA WRITE ROUTINE) is generated, which is used to update the RHS value in the temporary space to a certain interface signal in the LHS. In the referrer module of the VI NBA, a function number of a non-blocking assignment cache function is allocated and a non-blocking assignment cache function (e.g., VI NBA CACHE ROUTINE) is generated, which is used to cache the RHS value into the temporary space of the interface (corresponding to the LHS side interface signal of the VI NBA). Then, an NBA event is created and added to the NBA event queue, which is used to execute the non-blocking assignment write function (VI NBA WRITE ROUTINE) at the end time of the VI NBA, thereby completing the function of the non-blocking assignment statement of the virtual interface.

[0070] In some embodiments, based on the mapping relationship and the temporary storage space, a non-blocking assignment write function is generated in the interface module of the third intermediate code, a non-blocking assignment cache function is generated in the reference module, and a corresponding non-blocking assignment trigger event is generated, to obtain a fourth intermediate code, comprising: For a plurality of non-blocking assignment statements in the same group, a second write function number of a second non-blocking assignment write function, a second write function pointer of the second non-blocking assignment write function, and a second non-blocking assignment write function are allocated in the interface module of the third intermediate code, which is used to update a plurality of target values cached in the temporary storage space to a plurality of corresponding interface signals in sequence. In the reference module, a second cache function number is assigned to the second non-blocking assignment cache function, and the second non-blocking assignment cache function is generated to sequentially cache multiple target values ​​corresponding to the non-blocking assignment expressions in the same group to the temporary storage space corresponding to the virtual interface signals in the same group.

[0071] Specifically, for multiple non-blocking assignment statements within the same group, a unique second write function number and pointer are assigned in the interface module to generate batch write functions that sequentially update multiple target values ​​in the temporary storage space to the corresponding interface signals. Simultaneously, a second cache function number is assigned in the reference module to generate batch cache functions that sequentially store the calculation results of the same group of assignment expressions into the corresponding temporary storage areas. Through centralized management of function numbers and a batch operation mechanism, atomic processing of assignments within a group is achieved. This reduces function call overhead (processing multiple assignments in a single call) and ensures the temporal consistency of data updates (caching and writing are strictly executed in group order). It is particularly suitable for high-density non-blocking assignment scenarios, significantly improving the execution efficiency and resource utilization of large-scale design simulations.

[0072] Specifically, for non-blocking assignment statements of groups, the function number and function pointer of the non-blocking assignment write function of the group are allocated in the referee module (i.e., interface) of the non-blocking assignment of the group, and a non-blocking assignment write function of the group (e.g., VI NBA GROUP WRITEROUTINE) is generated to update the RHS value in the temporary space corresponding to the interface signal cached in the non-blocking assignment statement of the group to the corresponding interface signal in the LHS. In the referrer module for non-blocking assignments within a group, function numbers for the non-blocking assignment cache functions of the group are generated, along with a non-blocking assignment cache function for the group (e.g., VI NBA GROUP CACHE ROUTINE). This function sequentially caches the RHS values ​​of all non-blocking assignment statements within the group to the temporary space of the interface (corresponding to the LHS-side interface signal of VI NBA). Then, a shared NBA event is created within the group and added to the NBA event queue. This event is used to execute the group's non-blocking assignment write function (e.g., VI NBA GROUP WRITE ROUTINE) at the end of the VI NBA event, thus completing the functionality of the group's non-blocking assignment statements. When processing virtual interface system tasks, since multiple non-blocking assignment statements within a group share the same prefix expression and other information, optimization can be performed during code generation. The calculation of the LHS expression, the calculation of obtaining the interface instance pointer from the virtual interface, and the null value check of the virtual interface expression in the LHS can all be processed only once, avoiding redundant calculations and checks, thereby improving simulation performance to a certain extent.

[0073] In step S380, target code is generated based on the fourth intermediate code.

[0074] Specifically, based on the structured non-blocking assignment write functions, cache functions, and trigger event definitions already present in the fourth intermediate code, a code generator converts them into target code executable by a specific hardware description language (such as SystemVerilog) or simulation tools. During this process, function call order, memory layout, and event scheduling strategies are optimized to ensure that the generated code accurately reflects the design intent and conforms to the execution specifications of the target platform. Through layered abstraction and automated conversion of the intermediate code, the error rate of manual coding is significantly reduced. Simultaneously, the optimization capabilities of the toolchain improve the running efficiency of the target code, effectively shortening the development cycle and enhancing code portability.

[0075] In some embodiments, method 300 further includes: In the interface module, a non-blocking assignment information table for the virtual interface is generated. The non-blocking assignment information table includes: the function pointer offset of the non-blocking assignment write function and the offset of the temporary storage space of the virtual interface signal; the non-blocking assignment write function includes the first non-blocking assignment write function or the second non-blocking assignment write function. The temporary storage space and the non-blocking assignment write function are determined based on the input parameters and the non-blocking assignment information table; the input parameters include the interface instance pointer of the virtual interface, and the non-blocking assignment information table sequence number corresponding to the interface signal referenced by the non-blocking assignment statement, or the group sequence number of the grouped non-blocking assignment statements.

[0076] Specifically, by constructing a non-blocking assignment information table based on interface signals in the interface module, the offsets of temporary storage space addresses for virtual interface signals and the pointer offsets of corresponding write functions can be centrally managed. In this way, by utilizing the non-blocking assignment information table, non-blocking assignments for partitioned compilation (or domain compilation) and non-partitioned compilation can share a single codebase, achieving code reuse and decoupling between referencing and referenced modules.

[0077] Whenever an interface signal is referenced by an NBA assignment statement of a virtual interface (e.g., with the IS_VINTF_NBA_REFEREE flag), a temporary storage area is allocated for that interface signal for NBA caching and writing. The target temporary storage area can be dynamically located based on the input interface instance pointer and the VI NBA information table sequence number of the non-blocking assignment statement interface signal. The corresponding write function (first / second non-blocking assignment write function) can be dynamically located and called based on the input interface instance pointer and the VI NBA information table sequence number of the non-blocking assignment statement interface signal (e.g., the VI NBA information table sequence number for a single VI NBA assignment) or the group sequence number (determined according to the group's interface signal set, e.g., the group sequence number for a grouped VI NBA assignment). For example, during split compilation, the corresponding VI NBA information table sequence number can be queried based on the interface signal name; during non-split compilation, the corresponding VI NBA information table sequence number can be queried based on the interface signal name or the signal pointer offset. This achieves decoupling and efficient indexing of assignment operations. It reduces the complexity of function calls through unified management of information tables, and supports flexible assignment scenarios (single or batch) using ordinal parameters. It is especially suitable for dynamically configured simulation environments, and significantly improves the generation efficiency and execution reliability of target code.

[0078] Specifically, considering segmented compilation, a VI NBA information table is generated in the VI NBA referenced module during code generation. This table includes the offset of the function pointer for the VI NBA write function and the temporary space for interface signals (corresponding to the LHS-side interface signals of the VI NBA). Both individual VI NBAs and VI NBA Groups use the VI NBA information table at runtime. Specifically, the process of generating VI NBA cache functions (e.g., VI NBA CACHE ROUTINE) on the VI NBA referencing module side, obtaining the temporary space corresponding to the LHS-side interface signals of the VI NBA, and obtaining VI NBA write functions (e.g., VI NBA WRITE ROUTINE), are all completed through runtime library functions. Input parameters include interface instance pointers and VI NBA information table serial numbers, used to index and query the VI NBA information table on the interface side (the query complexity is constant). A VI NBA Group information table is also generated in the VI NBA referenced module during code generation, including the offset of the function pointer for the VI NBA Group write function. In the process of generating the VI NBA Group cache route on the VI NBA reference module side, obtaining the temporary space corresponding to the LHS side interface signal of VI NBA and obtaining the VI NBA Group write route are both completed through runtime library functions. The input parameters include the interface instance pointer, the VI NBA information table sequence number, and the VI NBA Group sequence number, which are used to index and query the VI NBA information table and VI NBA Group information table on the interface side (the query complexity is constant).

[0079] In step S390, in response to the detection of the non-blocking assignment trigger event during the execution of the target code, the target value corresponding to the non-blocking assignment expression stored in the temporary storage space is passed to the interface signal to simulate the logic system design.

[0080] During the execution of the target code, an event detection mechanism listens for non-blocking assignment trigger events in real time. When an event is triggered, the calculation result of the corresponding non-blocking assignment expression is automatically read from the pre-allocated temporary storage space and accurately transmitted to the target interface signal, completing the simulation update of the logic system design. This decoupling design of event-driven and temporary storage ensures the timing accuracy of data updates while avoiding the race conditions that may be caused by direct assignment. It is particularly suitable for simulation scenarios triggered by asynchronous clock domains or complex conditions, improving the reliability of simulation results and the coverage of design verification.

[0081] This disclosure also provides a verification system for logic system design, including: Compiler, used for: A global analysis is performed on the source code of the logic system design to determine the non-blocking assignment statements of the virtual interface and the interface signals referenced by the non-blocking assignment statements; Based on a series of non-blocking assignment statements that satisfy preset grouping conditions, a grouping system task is generated in the interface module where the interface signal is located in the source code to obtain the first intermediate code; the grouping system task is used to indicate the grouping information of the interface signal. Based on the modport definition and clock block definition in the interface module, update the interface signal name of the interface signal in the first intermediate code to obtain the second intermediate code; Based on the grouping information, a virtual interface system task is generated in the reference module where the non-blocking assignment statement is located, so as to update the non-blocking assignment statement of the second intermediate code and obtain the third intermediate code; the virtual interface system task includes the virtual interface signal and the corresponding non-blocking assignment expression in the non-blocking assignment statement; Construct a mapping relationship between the interface signals and the non-blocking assignment information of the virtual interface signals; the non-blocking assignment information includes non-blocking assignment write function information, whether it is a single non-blocking assignment statement, and the expression of the virtual interface signal; Within the interface module, temporary storage space is allocated for the interface signal referenced by the non-blocking assignment statement; Based on the mapping relationship and the temporary storage space, a non-blocking assignment write function is generated in the interface module of the third intermediate code, a non-blocking assignment cache function is generated in the reference module, and a corresponding non-blocking assignment trigger event is generated to obtain the fourth intermediate code. The target code is generated based on the fourth intermediate code; The simulator is used to respond to the non-blocking assignment trigger event detected during the execution of the target code, and to pass the target value corresponding to the non-blocking assignment expression stored in the temporary storage space to the interface signal to simulate the logic system design.

[0082] It should be noted that the above description describes some embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0083] Based on the same inventive concept, corresponding to the methods of any of the above embodiments, this application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement a method for verifying a logic system design as described in any of the above embodiments.

[0084] Based on the same inventive concept, corresponding to the methods of any of the above embodiments, this application also provides a non-transitory computer-readable storage medium storing computer instructions for causing the computer to perform a method for verifying a logic system design as described in any of the above embodiments.

[0085] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0086] The computer instructions stored in the storage medium of the above embodiments are used to cause the computer to execute a method for verifying a logic system design as described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0087] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application (including the claims) is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this application as described above, which are not provided in the details for the sake of brevity.

[0088] Additionally, to simplify the description and discussion, and to avoid obscuring the embodiments of this application, the well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. Furthermore, the apparatus may be shown in block diagram form to avoid obscuring the embodiments of this application, and this also takes into account the fact that the details of the implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this application will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuits) have been set forth to describe exemplary embodiments of this application, it will be apparent to those skilled in the art that the embodiments of this application can be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0089] Although this application has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0090] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.

Claims

1. A verification method for a logic system design, comprising: A global analysis is performed on the source code of the logic system design to determine the non-blocking assignment statements of the virtual interface and the interface signals referenced by the non-blocking assignment statements; Based on a series of non-blocking assignment statements that satisfy preset grouping conditions, a grouping system task is generated in the interface module where the interface signal is located in the source code to obtain the first intermediate code; the grouping system task is used to indicate the grouping information of the interface signal. Based on the modport definition and clock block definition in the interface module, update the interface signal name of the interface signal in the first intermediate code to obtain the second intermediate code; Based on the grouping information, a virtual interface system task is generated in the reference module where the non-blocking assignment statement is located, so as to update the non-blocking assignment statement of the second intermediate code and obtain the third intermediate code; the virtual interface system task includes the virtual interface signal and the corresponding non-blocking assignment expression in the non-blocking assignment statement; Construct a mapping relationship between the interface signals and the non-blocking assignment information of the virtual interface signals; the non-blocking assignment information includes non-blocking assignment write function information, whether it is a single non-blocking assignment statement, and the expression of the virtual interface signal; Within the interface module, temporary storage space is allocated for the interface signal referenced by the non-blocking assignment statement; Based on the mapping relationship and the temporary storage space, a non-blocking assignment write function is generated in the interface module of the third intermediate code, a non-blocking assignment cache function is generated in the reference module, and a corresponding non-blocking assignment trigger event is generated to obtain the fourth intermediate code. The target code is generated based on the fourth intermediate code; In response to the detection of the non-blocking assignment trigger event during the execution of the target code, the target value corresponding to the non-blocking assignment expression stored in the temporary storage space is passed to the interface signal to simulate the logic system design.

2. The method according to claim 1, wherein, Based on a series of non-blocking assignment statements that satisfy preset grouping conditions, a grouping system task is generated in the interface module where the interface signal is located in the source code, resulting in first intermediate code, including: Determine the signal node information in the left-hand expression of the non-blocking assignment statement. The signal node information includes the interface signal name, modport node name, clock block node name, modport port node name, and node type. In response to a series of consecutive non-blocking assignment statements satisfying the preset grouping condition, the interface signals corresponding to the multiple non-blocking assignment statements are determined to be the same group of signals; Based on the signal node information associated with the same group of signals, the grouping system task is generated in the corresponding interface module; wherein, the grouping system task of the same interface module is generated in the same initialization statement; The first intermediate code is obtained by grouping consecutive non-blocking assignment statements in the source code that satisfy the preset grouping conditions and generating corresponding grouping system tasks.

3. The method according to claim 2, wherein, Based on the modport definition and clock block definition in the interface module, update the interface signal name of the interface signal in the first intermediate code to obtain the second intermediate code, including: Update the interface signal name in the first intermediate code based on the modport definition; Asynchronous signals and asynchronous mask signals are determined based on the clock block definition, and the interface signal name, clock block node name, and node type in the first intermediate code are updated based on the asynchronous signals and asynchronous mask signals.

4. The method according to claim 1, wherein, Based on the grouping information, a virtual interface system task is generated in the reference module where the non-blocking assignment statement is located to update the non-blocking assignment statement in the second intermediate code, resulting in the third intermediate code, including: Based on the grouping information, determine the non-blocking assignment statements in the same group; The virtual interface system task is generated based on the virtual interface signal on the left and the non-blocking assignment expression on the right in the same set of non-blocking assignment statements; The third intermediate code is obtained by replacing the same group of non-blocking assignment statements in the second intermediate code based on the virtual interface system task.

5. The method according to claim 1, wherein, Based on the mapping relationship and the temporary storage space, a non-blocking assignment write function is generated in the interface module of the third intermediate code, a non-blocking assignment cache function is generated in the reference module, and a corresponding non-blocking assignment trigger event is generated, resulting in the fourth intermediate code, including: For a single non-blocking assignment statement, a first write function number and a first write function pointer of the first non-blocking assignment write function are allocated in the interface module of the third intermediate code, and a first non-blocking assignment write function is generated to update the target value in the temporary storage space to the corresponding interface signal during the execution of the target code. In the reference module, a first cache function number is allocated for the first non-blocking assignment cache function, and a first non-blocking assignment cache function is generated to cache the target value of the non-blocking assignment expression in the temporary storage space.

6. The method according to claim 1, wherein, Based on the mapping relationship and the temporary storage space, a non-blocking assignment write function is generated in the interface module of the third intermediate code, a non-blocking assignment cache function is generated in the reference module, and a corresponding non-blocking assignment trigger event is generated, resulting in the fourth intermediate code, including: For multiple non-blocking assignment statements in the same group, the second write function number and the second write function pointer of the second non-blocking assignment write function are allocated in the interface module of the third intermediate code, and a second non-blocking assignment write function is generated to update multiple target values ​​of the same group cached in the temporary storage space to the corresponding multiple interface signals in sequence. In the reference module, a second cache function number is assigned to the second non-blocking assignment cache function, and the second non-blocking assignment cache function is generated to sequentially cache multiple target values ​​corresponding to the non-blocking assignment expressions in the same group to the temporary storage space corresponding to the virtual interface signals in the same group.

7. The method according to claim 1, further comprising: In the interface module, a non-blocking assignment information table for the virtual interface is generated. The non-blocking assignment information table includes: the function pointer offset of the non-blocking assignment write function and the offset of the temporary storage space of the virtual interface signal; the non-blocking assignment write function includes the first non-blocking assignment write function or the second non-blocking assignment write function. The temporary storage space and the non-blocking assignment write function are determined based on the input parameters and the non-blocking assignment information table; the input parameters include the interface instance pointer of the virtual interface, and the non-blocking assignment information table sequence number corresponding to the interface signal referenced by the non-blocking assignment statement, or the group sequence number of the grouped non-blocking assignment statements.

8. A verification system for a logic system design, comprising: Compiler, used for: A global analysis is performed on the source code of the logic system design to determine the non-blocking assignment statements of the virtual interface and the interface signals referenced by the non-blocking assignment statements; Based on a series of non-blocking assignment statements that satisfy preset grouping conditions, a grouping system task is generated in the interface module where the interface signal is located in the source code to obtain the first intermediate code; the grouping system task is used to indicate the grouping information of the interface signal. Based on the modport definition and clock block definition in the interface module, update the interface signal name of the interface signal in the first intermediate code to obtain the second intermediate code; Based on the grouping information, a virtual interface system task is generated in the reference module where the non-blocking assignment statement is located, so as to update the non-blocking assignment statement of the second intermediate code and obtain the third intermediate code; the virtual interface system task includes the virtual interface signal and the corresponding non-blocking assignment expression in the non-blocking assignment statement; Construct a mapping relationship between the interface signals and the non-blocking assignment information of the virtual interface signals; the non-blocking assignment information includes non-blocking assignment write function information, whether it is a single non-blocking assignment statement, and the expression of the virtual interface signal; Within the interface module, temporary storage space is allocated for the interface signal referenced by the non-blocking assignment statement; Based on the mapping relationship and the temporary storage space, a non-blocking assignment write function is generated in the interface module of the third intermediate code, a non-blocking assignment cache function is generated in the reference module, and a corresponding non-blocking assignment trigger event is generated to obtain the fourth intermediate code. The target code is generated based on the fourth intermediate code; The simulator is used to respond to the non-blocking assignment trigger event detected during the execution of the target code, and to pass the target value corresponding to the non-blocking assignment expression stored in the temporary storage space to the interface signal to simulate the logic system design.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the method as claimed in any one of claims 1 to 7.

10. A non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform the method of any one of claims 1 to 7.

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