Adhesive tape for wafer processing and wafer processing method

Abstract

The invention relates to an adhesive tape for wafer processing and a wafer processing method. The purpose of the present invention is to provide an adhesive tape for wafer processing, which can suppress the adhesion of cutting chips generated in a dicing step by static electricity, can suppress the contamination of a chip by an antistatic agent in a step where heating is required, and can be used throughout semiconductor processing. And a wafer processing method capable of integrating a plurality of semiconductor processing steps by using the adhesive tape. The wafer processing tape includes: a base material layer; an adhesive layer; and an antistatic layer disposed between the base material layer and the adhesive layer, in which the ratio (R1 / R0) of the surface resistivity (R1) on the adhesive layer side after heating at 250 DEG C for 5 minutes to the surface resistivity (R0) on the adhesive layer side before heating is 0.001-10, and the surface resistivity (R1) is 1.0 * 1012 or less.

Description

TECHNICAL FIELD

[0001] The present application relates to a wafer processing tape and a wafer processing method. BACKGROUND

[0002] In processing a semiconductor wafer, an adhesive sheet is attached in order to protect the semiconductor wafer from damage. For example, in a backgrinding (backgrinding) process in processing a semiconductor wafer, an adhesive sheet is attached to protect the pattern surface of the semiconductor wafer. In addition, in semiconductor processing, various tapes are used in each process, such as a backgrinding tape, a heat-resistant tape, a conductive tape, a scribe tape, a pick-up tape, and the like.

[0003] As an example, it is known that in order to improve the adhesion of the base material to the stage in the semiconductor wafer processing process, a base material used in an adhesive sheet for processing a semiconductor wafer, in which the thermal shrinkage rate in MD and TD after heating at 130°C for 10 minutes is each 0% or more, is used (Patent Literature 1).

[0004] Prior Art Documents

[0005] Patent Literature

[0006] Patent Literature 1: WO2023 / 068088 SUMMARY

[0007] Problems to be Solved by the Invention

[0008] In semiconductor processing, the characteristics required of the wafer processing tape differ in each process, and therefore different tapes are used depending on the process. However, since the wafer processing tape is reattached after each process, there is a problem in that the number of processes in the semiconductor processing process increases and becomes complicated.

[0009] The present application was completed in view of the above-described problems, and aims to provide a wafer processing tape that can suppress the attachment of cutting chips generated in a scribing process due to static electricity, and can suppress the contamination of a chip by an antistatic agent in a process requiring heating, and can be used throughout semiconductor processing, and a wafer processing method that can integrate a plurality of semiconductor processing processes by using the tape.

[0010] Means for Solving the Problems

[0011] That is, the present application is as described below.

[0012] (1)

[0013] A wafer processing tape, comprising:

[0014] a base material layer;

[0015] an adhesive layer; and

[0016] an antistatic layer disposed between the base material layer and the adhesive layer,

[0017] a ratio R1 / R0 of a surface resistivity R1 on the adhesive layer side after heating at 250°C for 5 minutes to a surface resistivity R0 on the adhesive layer side before heating is 0.001 to 10 or less,

[0018] the surface resistivity R1 is 1.0 x 10 12 or more.

[0019] 〔2〕

[0020] The tape for wafer processing according to any one of the items 1 to 7, wherein

[0021] the surface resistivity R0 is 1.0 x 10 12 or more.

[0022] 〔3〕

[0023] The tape for wafer processing according to any one of the items 1 to 2, wherein

[0024] the antistatic layer contains a carbon material.

[0025] 〔4〕

[0026] The tape for wafer processing according to any one of the items 1 to 3, wherein

[0027] the antistatic layer contains an acrylic urethane resin.

[0028] 〔5〕

[0029] The tape for wafer processing according to any one of the items 1 to 4, wherein

[0030] an adhesive force N0 of the adhesive layer to a silicon wafer at 25°C is 0.2 to 5.0 N / 25 mm.

[0031] 〔6〕

[0032] The tape for wafer processing according to any one of the items 1 to 5, wherein

[0033] an adhesive force N1 of the adhesive layer to a silicon wafer at 25°C after heating at 250°C for 5 minutes is 0.5 to 6.0 N / 25 mm.

[0034] 〔7〕

[0035] The tape for wafer processing according to any one of the items 1 to 6, wherein

[0036] the base material layer contains a polyamide resin.

[0037] 〔8〕

[0038] According to any one of [1] to [7], the wafer processing tape, wherein,

[0039] The substrate layer does not have a yield point.

[0040] [9]

[0041] According to any one of [1] to [8], the wafer processing tape, wherein,

[0042] The substrate layer has an ultraviolet transmittance of over 70% at 365nm.

[0043]

[10]

[0044] A wafer processing method comprising: a processing step of attaching a wafer processing tape described in any one of [1] to [9] to a wafer and performing wafer processing.

[0045] Invention Effects

[0046] According to the present invention, a wafer processing tape is provided that can suppress the adhesion of cutting chips generated in the dicing process due to static electricity, and can suppress the chip from being contaminated by antistatic agents in processes requiring heating, and can be used throughout in semiconductor processing, and a wafer processing method is provided that can integrate multiple semiconductor processing processes by using the tape. Attached Figure Description

[0047] Figure 1 This is a schematic cross-sectional view showing the wafer processing tape of this embodiment.

[0048] Figure 2 This is a flowchart illustrating the wafer fabrication method of this embodiment.

[0049] Explanation of reference numerals in the attached figures

[0050] 10…Wafer processing tape; 11…Substrate layer; 11a…Surface; 12…Adhesive layer; 12a…Surface; 12b…Back side; 13…Antistatic layer; 20…Wafer; 20a…Component forming surface; 20b…Non-component forming surface; 21…Metal layer; 22…Optional surface treatment layer; 30…Semiconductor chip; S1…Lamination process; S2…Back side grinding process; S3…Metal layer forming process; S4…Dictation process; S5…Processing process; S6…Peeling process. Detailed Implementation

[0051] The embodiments of the present invention (hereinafter referred to as "this embodiment") will be described in detail below, but the present invention is not limited thereto, and various modifications can be made without departing from its spirit. It should be noted that in the accompanying drawings, the same reference numerals are used to label the same elements, and repeated descriptions are omitted. In addition, unless otherwise specified, the positional relationships such as up, down, left, and right are based on the positional relationships shown in the accompanying drawings. Moreover, the scale of the accompanying drawings is not limited to the scale shown in the illustrations.

[0052] 1. Adhesive tape for wafer processing

[0053] The wafer processing tape of this embodiment has a substrate layer, an adhesive layer, and an antistatic layer disposed between the substrate layer and the adhesive layer. The ratio (R1 / R0) of the surface resistivity R1 of the adhesive layer side after heating at 250°C for 5 minutes to the surface resistivity R0 of the adhesive layer side before heating is 0.001 to 10 or less, and the surface resistivity R1 is 1.0 × 10⁻⁶. 12 the following.

[0054] Figure 1 A schematic cross-sectional view of the wafer processing tape according to this embodiment is shown. Figure 1 As shown, the wafer processing tape 10 of this embodiment includes a substrate layer 11, an adhesive layer 12, and an antistatic layer 13 disposed between the substrate layer 11 and the adhesive layer 12. By making the surface 12a (exposed surface) of the adhesive layer 12 closely adhere to the element formation surface 20a of the wafer 20 where semiconductor elements are formed, the semiconductor elements on the element formation surface 20a of the wafer 20 can be protected. It should be noted that, in this embodiment, in the wafer processing tape and its layers, the surface on the side in contact with the wafer is referred to as the surface, and the surface on the opposite side is referred to as the back surface.

[0055] Figure 2 A flowchart illustrating one embodiment of the wafer fabrication method is shown, using a schematic cross-sectional view. For example... Figure 2 As shown, the wafer processing method may include: a bonding step S1 in which the wafer processing tape 10 is bonded to the component forming surface 20a of the wafer 20; a back-side grinding step S2 in which the non-component forming surface 20b of the wafer 20 bonded to the wafer processing tape 10 is ground using a grinding machine 40; a metal layer forming step S3 in which a metal layer 21 is formed on the non-component forming surface 20b opposite to the side where the wafer processing tape 10 is bonded; a dicing step S4 in which the wafer 20 bonded to the wafer processing tape 10 is diced to form a chip 30; a processing step S5 in which the back side of the chip 30 is surface treated by etching, sputtering or reflow soldering; and a peeling step S6 in which the wafer processing tape is peeled off.

[0056] It should be noted that, Figure 2This is an example of a wafer fabrication method where it is not necessary to perform all steps S2 to S5, and the order in which the steps are performed is not limited. Figure 2 The prescribed order. Therefore, for example, the metal layer formation process S3 may be omitted, or the processing process S5 may be omitted, or the processing process S5 may be performed before the dicing process S4.

[0057] Here, in the dicing process S4, when the wafer attached to the wafer processing tape is diced and monolithized, cutting shavings are generated. If such cutting shavings adhere to the periphery of the monolithized chip 30 due to static electricity, not only will the chip 30 be contaminated, but it will also hinder subsequent processing steps S5 and stripping steps S6. Therefore, in order to suppress the adhesion of cutting shavings, it is considered to provide an antistatic layer on the wafer processing tape. However, on the other hand, when the antistatic layer is provided on the surface 12a side of the adhesive layer 12, the conductive material that provides the antistatic effect adheres to the element formation surface 20a of the wafer 20 or the chip 30, which may reduce the electrical characteristics of the chip. On the other hand, if the antistatic layer is provided on the back side 11b side of the substrate layer 11, the antistatic effect cannot be fully utilized, and the adhesion of cutting shavings cannot be sufficiently suppressed.

[0058] In contrast, the wafer processing tape 10 of this embodiment has an antistatic layer 13 disposed between the substrate layer 11 and the adhesive layer 12. This allows for the effective application of antistatic properties while suppressing the adhesion of conductive materials to the element formation surface 20a of the wafer 20 and the chip 30.

[0059] Furthermore, in processes such as metal layer formation S3 and processing S5, during the process where the wafer processing tape 10 is exposed to high temperatures, it is anticipated that the antistatic agent in the antistatic layer 13 will migrate towards the surface 12a of the adhesive layer 12. When this migration occurs, although the antistatic effect is further improved, the antistatic agent may adhere to the device formation surface 20a of the wafer 20 and the chip 30, thereby reducing the electrical characteristics of the chip.

[0060] In contrast, regarding the wafer processing tape 10 of this embodiment, from the viewpoint of ensuring that the antistatic agent does not easily migrate to the surface 12a side of the adhesive layer 12, the change in surface resistivity of the adhesive layer side before and after heating is specified. Therefore, it is possible to suppress the migration of the antistatic agent from the antistatic layer 13 located between the substrate layer 11 and the adhesive layer 12 to the surface 12a side of the adhesive layer 12, and to suppress contamination of the device formation surface 20a of the wafer 20 by the antistatic agent.

[0061] As described above, the wafer processing tape of this embodiment can prevent the adhesion of cutting chips generated during the dicing process due to static electricity, and can also prevent the chip from being contaminated by antistatic agents during processes requiring heating. Therefore, it is not necessary to replace the wafer processing tape with one corresponding to each process in the wafer processing, and it can be used in various wafer processing steps. Figure 2 This method is used throughout the wafer fabrication process shown. The structure of each layer is described in detail below.

[0062] 1.1. Antistatic layer

[0063] The antistatic layer preferably contains an antistatic agent and a resin, and may also contain other components as needed.

[0064] There are no particular limitations on antistatic agents. Examples include: magnesium silicate, chlorophyllite (such as montmorillonite, bedesulfurite, chloropyrite, hydropyrite, talc), carbon nanotubes, fullerenes, graphene, graphite, quaternary ammonium salts, guanidine compounds, imidazoline compounds, pyridinium compounds, sulfonates, sulfate esters, phosphate esters, ionic liquids, polythiophene, phosphorus-doped tin oxide, spherical ATO, etc.

[0065] Among them, carbon materials such as carbon nanotubes, fullerenes, graphene, and graphite are preferred. By using such antistatic agents, there is a tendency to further inhibit the migration of antistatic agents and further inhibit chip contamination caused by antistatic agents at high temperatures.

[0066] The content of the antistatic agent relative to the total amount of the antistatic layer is preferably 20-80% by mass, 30-70% by mass, or 40-60% by mass. By setting the content of the antistatic agent within the above range, in addition to further suppressing the adhesion of cutting chips caused by static electricity, it further suppresses the migration of the antistatic agent and further suppresses the tendency of chip contamination caused by the antistatic agent at high temperatures.

[0067] As a resin, there are no particular limitations; examples include: polysiloxane, polyurethane resin, acrylic resin, urethane acrylate resin, polyvinyl chloride resin, ethylene-vinyl acetate resin, polyester resin, polyolefin resin, styrene resin, and acrylic-modified polyester resin.

[0068] Preferably, the resin contains urethane acrylate resin. Using such a resin further inhibits the migration of antistatic agents and further suppresses chip contamination caused by antistatic agents at high temperatures.

[0069] The resin content relative to the total amount of the antistatic layer is preferably 20-80% by mass, 30-70% by mass, or 40-60% by mass. By setting the resin content within the above range, there is a tendency to further suppress the migration of the antistatic agent and further suppress chip contamination caused by the antistatic agent at high temperatures.

[0070] The thickness of the antistatic layer is preferably 0.05–2 μm, 0.10–1.5 μm, or 0.25–1.0 μm. By setting the thickness of the antistatic layer within the above range, the migration of the antistatic agent is further suppressed, and the tendency for chip contamination caused by the antistatic agent at high temperatures is further suppressed.

[0071] The total light transmittance of the antistatic layer is preferably 70–99%, 75–98%, 80–97%, or 85–96%. By setting the total light transmittance of the antistatic layer to within the above range, there is a tendency to further increase the transmittance when ultraviolet light is irradiated onto the adhesive layer 12 from the back side 11b of the substrate layer. Therefore, the adhesive layer 12 can be cured by ultraviolet irradiation, and there is a tendency to further improve the peelability of the wafer 20 from the adhesive layer 12 during the peeling process.

[0072] It should be noted that the total light transmittance can be measured according to JIS K 7375. Furthermore, the total light transmittance can be adjusted by the content and type of the aforementioned antistatic agent and resin.

[0073] 1.2. Substrate layer

[0074] The substrate layer 11 is configured to follow the bumps and depressions of the wafer 20, protect the bumps and depressions from damage due to the wafer processing technology, and prevent gaps from being generated between the adhesive layer and the component forming surface 20a, thereby also contributing to improved adhesion.

[0075] The substrate layer preferably comprises a resin, which is not particularly limited, but may include, for example, polyamide resin, ionomer resin, polyolefin resin, vinyl chloride resin, polyester resin, polystyrene resin, phenolic resin, and acrylic resin. These resins may be used alone or in combination of two or more. More specifically, it may also be a mixture, copolymer, or laminate of one of these resins with other resins.

[0076] Among these, polyamide resins, ionomer resins, and polyolefin resins are preferred, with polyamide resins being more preferred. By using such resins, there is a tendency to further improve the conformability to the unevenness of the wafer, heat resistance, and ultraviolet transmittance.

[0077] There are no particular limitations on polyamide resins. Examples include aliphatic polyamides such as polyamide 6 and polyamide 66; semi-aromatic polyamides such as polyamide 6T, polyamide 9T, and polyamide 10T; and fully aromatic polyamides obtained from aromatic dicarboxylic acids and aromatic diamines. It should be noted that aliphatic polyamides can also have alicyclic groups in addition to aliphatic groups.

[0078] As for ionomer resins, there are no particular restrictions as long as they are obtained by intermolecular bonding of a specified polymer with metal ions. Examples include: polyolefin-based ionomer resins, (meth)acrylic acid-based ionomer resins, polystyrene-based ionomer resins, and polyester-based ionomer resins. There are also no particular restrictions on the metal ions that constitute the salts of the ionomer resins. Examples include: monovalent metal ions such as sodium ions and lithium ions; divalent metal ions such as zinc ions, calcium ions, and magnesium ions; and trivalent metal ions such as aluminum ions.

[0079] There are no particular limitations on polyolefin resins; examples include polyethylene, polypropylene, and their copolymers.

[0080] The resin content relative to the total amount of the substrate layer is preferably 80-100% by mass, 85-100% by mass, or 90-100% by mass.

[0081] The substrate layer may also contain additives other than resin, as needed. There are no particular limitations on additives; examples include: plasticizers, heat stabilizers, colorants, organic lubricants, inorganic lubricants, surfactants, processing aids, and antistatic agents. Additives may be used alone or in combination of two or more.

[0082] The substrate layer preferably does not have a yield point. In this embodiment, "yield point" refers to the initial point in the stress-strain curve where the strain increases without an increase in stress. Furthermore, "not having a yield point" means that there is no point in the stress-strain curve where the strain increases without an increase in stress. The stress-strain curve can be determined according to JIS K 7161, and the yield point can be determined from the stress-strain curve thus determined.

[0083] There are no particular limitations on resins that have no yield point; examples include polystyrene resin, acrylic resin, phenolic resin, and polyamide resin.

[0084] The ultraviolet transmittance of the substrate layer at 365 nm is preferably 70% or more, 80-99.5%, or 85-99%. By making the ultraviolet transmittance 70% or more, the adhesive layer 12 can be cured by irradiating the adhesive layer 12 with ultraviolet light from the back side 11b of the substrate layer, which tends to further improve the peelability of the wafer 20 from the adhesive layer 12 during the peeling process.

[0085] The ultraviolet transmittance at 365 nm can be determined by measuring the light transmittance of the substrate in the wavelength range of 300 nm to 800 nm using an ultraviolet-visible spectrophotometer, and then reading the light transmittance at 365 nm from the measurement results.

[0086] The thickness of the substrate layer is preferably 10–500 μm, 15–250 μm, or 25–100 μm. By keeping the thickness of the substrate layer within the above range, the following tendencies are achieved: the ability to follow the contours of the wafer is further improved, and gaps and the like become less likely to enter between the wafer processing tape and the device forming surface, thus improving the adhesion.

[0087] 1.3. Adhesive layer

[0088] The adhesive layer 12 is a layer stacked on the surface 11a of the substrate layer 11, with the antistatic layer 13 in between. In the semiconductor processing, the adhesive layer 12 adheres closely to the wafer 20, protects the device formation surface 20a, and can be peeled off without leaving any residue after semiconductor processing.

[0089] The surface resistivity R0 of the adhesive layer side before heating is preferably 1.0 × 10⁻⁶. 12 Ω / □ or less, 1.0×10 3 ~1.0×10 11 Ω / □、1.0×10 4 ~1.0×10 10 Ω / □、1.0×10 5 ~1.0×10 9 Ω / □、1.0×10 6 ~1.0×10 8 Ω / □. By keeping the surface resistivity R0 within the above range, the tendency for cutting chips generated in processes such as dicing to adhere due to static electricity can be further suppressed.

[0090] The surface resistivity R1 of the adhesive layer side after heating at 250℃ for 5 minutes is 1.0×10⁻⁶. 12 Ω / □ or less, preferably 1.0 × 10 3 ~1.0×10 11 Ω / □、1.0×10 4 ~1.0×10 10 Ω / □、1.0×10 5 ~1.0×10 9 Ω / □、1.0×10 6 ~1.0×10 8 Ω / □. It can suppress chip contamination caused by antistatic agents at high temperatures. By keeping the surface resistivity R1 within the above range, it further suppresses the tendency of cutting chips generated in processes such as dicing to adhere due to static electricity.

[0091] The ratio (R1 / R0) of the surface resistivity R1 of the adhesive layer side to the surface resistivity R0 of the adhesive layer side after heating at 250°C for 5 minutes is 0.001 to 10 or less, preferably 0.01 to 7.5, 0.10 to 5.0, or 0.25 to 2.5.

[0092] Surface resistivity R0 and R1 can be measured using an ACL Staticide ACL800 instrument based on ASTM D257. Furthermore, the surface resistivity R0 and R1, and their ratio, can be adjusted by the composition of the antistatic layer, particularly the type of antistatic agent, the type of resin used in the antistatic layer, the thickness of the adhesive layer, and its constituent components. Moreover, the surface resistivity R0 and R1, and their ratio, can also be adjusted by the method of forming the adhesive layer. For example, by heat treatment at 100–200°C for 1–30 minutes followed by aging treatment at 30–70°C for 1–7 days, the reaction between the base polymer and the crosslinking agent is fully carried out, resulting in a tendency for antistatic agent migration to be less likely during processes exposed to high temperatures.

[0093] The adhesion force NO of the adhesive layer to the silicon wafer is preferably 0.2–5.0 N / 25 mm, 0.3–2.5 N / 25 mm, 0.4–1.0 N / 25 mm, or 0.5–0.8 N / 25 mm at 25°C. By ensuring that the adhesion force NO of the adhesive layer to the silicon wafer is within the above range, the device formation surface of the wafer 20 can be more appropriately protected.

[0094] The adhesion force N1 of the adhesive layer to the silicon wafer after heating at 250°C for 5 minutes is preferably 0.5–6.0 N / 25 mm, 0.7–5.0 N / 25 mm, 1.0–2.5 N / 25 mm, or 1.1–1.5 N / 25 mm at 25°C. By keeping the adhesion force N1 of the adhesive layer to the silicon wafer within the above range, the adhesion can be maintained even at high temperatures, and the device formation surface of the wafer 20 can be more properly protected.

[0095] Adhesive strengths N0 and N1 can be measured according to JIS Z 0237 (2009). Furthermore, adhesive strengths N0 and N1 can be adjusted by the type and amount of the base polymer and crosslinking agent, as described later. Additionally, adhesive strengths N0 and N1 can also be adjusted by the method of forming the adhesive layer. For example, by heat treatment at 100–200°C for 1–30 minutes followed by aging treatment at 30–70°C for 1–7 days, the reaction between the base polymer and the crosslinking agent is fully carried out, thereby adjusting adhesive strengths N0 and N1.

[0096] The thickness of the adhesive layer is preferably 0.2–100 μm, 0.5–50 μm, 0.7–25 μm, or 1.0–20 μm. By making the thickness within the above range, it is less likely to damage the conformability and the tendency to leave adhesive residue is suppressed.

[0097] The adhesive layer is preferably subjected to ultraviolet irradiation to reduce its adhesive strength. Thus, from the bonding process S1 to the dicing process S4, it can be closely bonded to the wafer 20 to protect the component forming surface 20a. In the subsequent peeling process, the adhesive strength is reduced by irradiation with ultraviolet light, and the chip can be picked up without adhesive residue.

[0098] From the perspective of reducing adhesive strength through ultraviolet irradiation, the adhesive layer can contain: a base polymer with polymeric double bonds and crosslinking groups; a photopolymerization initiator; and a crosslinking agent, and may also include other components as needed. Furthermore, in the adhesive layer, the crosslinking groups of the base polymer can react with the crosslinking agent to form a three-dimensional crosslinked structure.

[0099] The base polymer constituting the main component of the adhesive layer is not particularly limited; examples include (meth)acrylate copolymers. The shape of the (meth)acrylate copolymer is not particularly limited; examples include linear, branched, or cross-linked shapes. A cross-linked shape is preferred. By using such a base polymer, the physical properties of the adhesive layer can be adjusted. The base polymer having a cross-linked or branched shape can be a polymer formed by bonding epoxy groups of a base polymer having a linear or branched shape via a cross-linking agent described later.

[0100] The monomers constituting (meth)acrylate copolymers are not particularly limited, and examples include: alkyl (meth)acrylates having alkyl groups with 1 to 3 carbon atoms, (meth)acrylates having glycidyl groups, (meth)acrylates having hydroxyl groups, and monomers having aromatic groups. Furthermore, (meth)acrylate copolymers may also contain other copolymerizable vinyl monomers besides acrylic monomers.

[0101] Alkyl methacrylates having an alkyl group having 1 to 3 carbon atoms are not particularly limited, and examples include methyl methacrylate, ethyl methacrylate, and propyl methacrylate.

[0102] The (meth)acrylate having a glycidyl group is not particularly limited, and examples include glycidyl (meth)acrylate, allyl glycidyl ether, etc. The structural units from (meth)acrylates having a glycidyl group can be used to introduce epoxy groups into the base polymer. Through the reaction of the epoxy groups introduced into the base polymer with the crosslinking agent described later, the base polymer bonds to each other and is crosslinked in three dimensions.

[0103] The (meth)acrylates containing hydroxyl groups are not particularly limited, and examples include: 2-hydroxyethyl (meth)acrylate, 2-hydroxypropyl (meth)acrylate, 2-hydroxybutyl (meth)acrylate, pentaerythritol triacrylate, glycidyl di(meth)acrylate, dipentaerythritol pentaacrylate, etc. For structural units derived from (meth)acrylates containing hydroxyl groups, these units can be used to introduce epoxy groups into the base polymer. Through the reaction of the hydroxyl groups introduced into the base polymer with the crosslinking agent described later, the base polymers are bonded together and crosslinked in three dimensions.

[0104] As monomers with aromatic groups, there are no particular limitations; examples include styrene, phenoxyethyl methacrylate, benzyl methacrylate, etc.

[0105] Among these, acrylic resin is preferred as the base polymer, and the acrylic resin has: hydroxyl or carboxyl groups; and polymerizable double bonds. By including such a base polymer, there is a tendency to further improve adhesion before ultraviolet irradiation and further improve peelability after ultraviolet irradiation.

[0106] The glass transition temperature of the base polymer is preferably -90 to -30°C, -80 to -40°C, or -70 to -50°C. Furthermore, by keeping the glass transition temperature of the base polymer within the above ranges, it is easier to adjust the adhesive forces N0 and N1 to these ranges.

[0107] The content of the base polymer relative to the total amount of the adhesive layer is preferably 85-99% by mass, 90-98% by mass, or 92-97% by mass.

[0108] There are no special restrictions as long as the crosslinking agent has two or more functional groups that can react with the carboxyl, hydroxyl, or other crosslinking groups of the base polymer.

[0109] There are no particular limitations on such crosslinking agents, and examples include: 2,4-toluene diisocyanate, 2,6-toluene diisocyanate, hydrogenated toluene diisocyanate, 1,3-phenylenedimethyl diisocyanate, 1,4-phenylenedimethyl diisocyanate, diphenylmethane-4,4-diisocyanate, isophorone diisocyanate, 1,3-bis(isocyanate methyl)cyclohexane, isocyanurate form of hexamethylene diisocyanate, and tetramethylphenyl diisocyanate. Isocyanate crosslinking agents such as 1,5-naphthalene diisocyanate, toluene diisocyanate adduct of trimethylolpropane, phenyl diisocyanate adduct of trimethylolpropane, triphenylmethane triisocyanate, and methylene bis(4-phenylmethane) triisocyanate; N,N,N',N'-tetraglycidyl-m-phenylenediamine, 1,3-bis(N,N'-diglycidylaminomethyl)cyclohexane, bisphenol A·epimyl chlorohydrin type epoxy resin, N,N'-[1,3] Epoxy crosslinking agents such as bis(methylene)-bis[bis(ethylene oxide-2-ylmethyl)amine], ethylene glycol diglycidyl ether, polyethylene glycol diglycidyl ether, glycerol diglycidyl ether, glycerol triglycidyl ether, 1,6-hexanediol diglycidyl ether, trimethylolpropane triglycidyl ether, sorbitol polyglycidyl ether, polyglycerol polyglycidyl ether, pentaerythritol polyglycidyl ether, diglycerol polyglycidyl ether, etc.; tetramethylolmethane-tris-β-aziridinyl Aziridine crosslinking agents such as propionate, trimethylolpropane-tri-β-aziridine propionate, N,N'-diphenylmethane-4,4'-bis(1-aziridinecarboxamide), and N,N'-hexamethylene-1,6-bis(1-aziridinecarboxamide); and melamine crosslinking agents such as hexamethoxymethylmelamine, hexaethoxymethylmelamine, hexapropoxymethylmelamine, hexabutoxymethylmelamine, hexapentoxymethylmelamine, and hexoxymethylmelamine.

[0110] Among them, epoxy crosslinking agents and isocyanate crosslinking agents are preferred, with epoxy crosslinking agents being more preferred. By using epoxy crosslinking agents, the base polymers can be crosslinked with each other using ester bonds with high heat resistance. As a result, even in processes exposed to high temperatures, such as the metal layer formation process S3, the adhesive layer can exhibit good heat resistance.

[0111] The content of the crosslinking agent is preferably 1.0 to 6.0 parts by mass, 2.0 to 5.0 parts by mass, or 3.0 to 4.0 parts by mass relative to 100 parts by mass of the base polymer. By keeping the content of the crosslinking agent within the above range, it is easier to adjust the adhesive forces N0 and N1 to the above range. In addition, by adjusting the crosslinking density using the content of the crosslinking agent, it is easier to adjust the surface resistivity R1 and R1 / R0 to the above range.

[0112] There are no particular limitations on photopolymerization initiators. Examples include: benzophenone and its derivatives; benzoin-type photopolymerization initiators such as benzoin, benzoin methyl ether, benzoin ethyl ether, benzoin propyl ether, benzoin isobutyl ether, and benzyl dimethyl ketal; acetophenone-type photopolymerization initiators such as diethoxyacetophenone and 4-tert-butyltrichloroacetophenone; thioxanthone and its derivatives; camphorquinone, 7,7-dimethyl-2,3-dioxobicyclo[2.2.1] Camphorquinone-type photopolymerization initiators such as heptane-1-carboxylic acid, 7,7-dimethyl-2,3-dioxobicyclo[2.2.1]heptane-1-carboxy-2-bromoethyl ester, 7,7-dimethyl-2,3-dioxobicyclo[2.2.1]heptane-1-carboxy-2-methyl ester, and 7,7-dimethyl-2,3-dioxobicyclo[2.2.1]heptane-1-carboxylic acid chloride; 2-methyl-1-[4-(methylthio)phenyl]- α-Aminoalkylphenyl ketone type photopolymerization initiators such as 2-morpholinopropane-1-one and 2-benzyl-2-dimethylamino-1-(4-morpholinophenyl)-butanone-1; benzoyl diphenylphosphine oxide, 2,4,6-trimethylbenzoyl-diphenylphosphine oxide, benzoyl diethoxyphosphine oxide, 2,4,6-trimethylbenzoyl dimethoxyphenylphosphine oxide, 2,4,6-trimethylbenzoyl diethoxyphenylphosphine oxide, bis( Acylphosphine oxide type photopolymerization initiators such as 2,4,6-trimethylbenzoyl)-phenylphosphine oxide; α-hydroxyalkylphenyl ketone type photopolymerization initiators such as 2-hydroxy-2-methyl-1-phenylpropane-1-one, 2-hydroxy-2-methyl-1-[4-(2-hydroxyethoxy)phenyl]propane-1-one, 1-hydroxycyclohexylphenyl ketone, and 2-hydroxy-2-methyl-1-[4-(1-methylvinyl)phenyl]propane-1-one.

[0113] Among them, acylphosphine oxide type photopolymerization initiators are preferred. Using such photopolymerization initiators results in excellent polymerizability and a tendency to reduce adhesion when exposed to ultraviolet light.

[0114] The content of the photopolymerization initiator is preferably 1.0 to 5.0 parts by weight, 1.5 to 4.0 parts by weight, or 2.0 to 3.0 parts by weight relative to 100 parts by weight of the base polymer. By setting the content of the photopolymerization initiator within the above range, there is a tendency for the curing reaction to proceed effectively under ultraviolet irradiation, and for the adhesion to be further reduced.

[0115] 2. Manufacturing method of tape for wafer processing

[0116] The manufacturing method of the wafer processing tape in this embodiment is not particularly limited. For example, it is not particularly limited as long as it includes the process of forming an antistatic layer 13 and an adhesive layer 12 on the surface 11a of the substrate layer 11.

[0117] The method for forming the adhesive layer 12 and the antistatic layer 13 is not particularly limited. For example, the films can be dry-laminated together, or a composition can be coated on the surface of the substrate layer 11 and dried or photocured to form the adhesive layer 12 and the antistatic layer 13. Alternatively, the adhesive layer 12 and the antistatic layer 13 can be bonded to the substrate layer 11 with an adhesive layer different from the adhesive layer 12 in between.

[0118] 3. Wafer processing methods

[0119] The wafer processing method of this embodiment includes a processing step of attaching the above-mentioned wafer processing tape to the wafer for wafer processing.

[0120] like Figure 2 As shown, the wafer processing method may include: a bonding step S1 in which the wafer processing tape 10 is bonded to the component forming surface 20a of the wafer 20; a back-side grinding step S2 in which the non-component forming surface 20b of the wafer 20 bonded to the wafer processing tape 10 is ground using a grinding machine 40; a metal layer forming step S3 in which a metal layer 21 is formed on the non-component forming surface 20b opposite to the surface on which the wafer processing tape 10 is bonded; a dicing step S4 in which the wafer 20 bonded to the wafer processing tape 10 is diced to form a chip 30; a processing step S5 in which the back side of the chip 30 is surface treated by etching, sputtering or reflow soldering; and a peeling step S6 in which the wafer processing tape is peeled off.

[0121] 3.1. Bonding process

[0122] The bonding process S1 is a process of bonding the aforementioned wafer processing tape 10 onto the component forming surface 20a of the wafer 20. It should be noted that the surface of the wafer 20 onto which the wafer processing tape 10 is bonded may also be a non-component forming surface 20b.

[0123] In the bonding process, the wafer processing tape 10 can be bonded to the wafer main surface 20a while it is preheated, or it can be bonded to the wafer main surface 20a before heating. Alternatively, the wafer processing tape 10 can be bonded to the wafer main surface 20a without heating. By bonding the surface 11a of the adhesive layer 12 to the component forming surface 20a of the wafer while it is heated, bonding can be performed with the surface 11a of the adhesive layer 12 following the component forming surface 20a of the wafer (see [link]). Figure 2 (S2). In this way, by embedding the protrusion into the wafer processing tape 10, the component forming surface 20a of the wafer with the protrusion can be protected.

[0124] The heating temperature is preferably 60–150°C, more preferably 70–140°C, and even more preferably 80–130°C. Furthermore, the heating time for the wafer processing tape 10 is preferably 3–120 seconds, more preferably 5–90 seconds. By keeping the heating conditions within the above range, the conformability of the wafer processing tape 10 tends to be further improved.

[0125] 3.2. Processing steps

[0126] There are no particular restrictions on the processing steps of processing the wafer 20 while the wafer processing tape 10 is bonded to the wafer 20; any wafer processing technology can be appropriately applied. For example, back-side grinding step S2, metal layer formation step S3, dicing step S4, and processing step S5 can be cited as processing steps.

[0127] In addition, as a processing technology that combines the above-mentioned elements, such as Figure 2 Examples include a metal layer formation process S3 that forms the metal layer 21 and a dicing process S4 that dices the thinned wafer using a blade or similar method after the back-side grinding process S2. Hereinafter, a process in which the metal layer formation process S3 and the dicing process S4 are performed after the back-side grinding process S2 will be shown, but this embodiment is not limited to this.

[0128] 3.2.1. Backside Grinding Process

[0129] The back-side grinding process S2 is a process of grinding the non-component forming surface 20b of the wafer 20 that is adhered to the wafer processing tape 10. Specifically, from the viewpoint of protecting the component forming surface 20a, with the component forming surface 20a adhered to the wafer processing tape 10 as the back-side grinding tape, the non-component forming surface 20b of the wafer 20 is ground (back-side grinding) to the desired thickness.

[0130] There are no particular limitations on the specific method of back-side grinding; any known method can be used. For example, a method in which grinding is performed while supplying a slurry containing abrasive grains to the back side 20b of the wafer 20 is given. The thickness of the thinned wafer obtained in this way is not particularly limited as long as it meets the processing purpose; as an example, it is preferably 300 μm or less, 150 μm or less, or 50 μm or less.

[0131] In back-side grinding, a load is applied in the thickness direction of the wafer 20, which can easily cause damage to protrusions and other parts, leading to a decrease in yield. In contrast, by using the wafer processing tape 10 of this embodiment, processing can be performed while at least a portion of the protrusions is embedded in the wafer processing tape 10, thus avoiding damage to the protrusions and other parts.

[0132] In the wafer processing method of this embodiment, when performing back-side grinding processing to thin the wafer 20 from the back side 20b of the wafer 20, on a wafer whose surface has pre-formed modified portions and grooves for monolithization, the wafer 20 can be thinned to the same depth as the modified portions and grooves. Therefore, thinning based on back-side grinding and monolithization can be performed simultaneously.

[0133] 3.2.2. Metal layer formation process

[0134] The metal layer formation process S3 is a process in which a metal layer 21 is formed on the surface 20b of the wafer 20 opposite to the surface 20a to which the wafer processing tape 10 is attached. There are no particular limitations on the method for forming the metal layer; examples include ALD (atomic layer deposition) and CVD (chemical vapor deposition). There are no particular limitations on the formation conditions for the metal layer using these methods; for example, processing at 200–300°C for 3–10 minutes is possible.

[0135] 3.2.3. Slicing process

[0136] The dicing process S4 is the process of dicing the wafer 20. There is no particular limitation on the dicing method; for example, a dicing blade can be used to cut the wafer into semiconductor chips 30.

[0137] 3.2.4. Processing Procedures

[0138] In processing step S5, the back side of the chip 30 can also be surface-treated by etching, sputtering, or reflow soldering to form an optional surface treatment layer 22. There are no particular limitations on the processing method; any treatment can be selected depending on the application of the chip.

[0139] 3.3. Stripping Process

[0140] The stripping process S6 is the process of stripping the wafer processing tape 10 from the wafer 20 or semiconductor chip 30. It should be noted that the stripping process of collecting the semiconductor chip 30 from the wafer processing tape is also called the stripping process.

[0141] In the peeling process S6, the wafer processing tape 10 can be peeled off at room temperature or under heat. Furthermore, in the peeling process S6, if the adhesive layer 12 contains a base polymer with polymerizable double bond groups and a photopolymerization initiator, the adhesive layer 12 can be cured by irradiating it with ultraviolet light before peeling, thereby reducing the adhesion force to the wafer 20. This results in further improved release properties and further suppression of contamination caused by residue from the tape. It should be noted that when the substrate is transparent, ultraviolet irradiation can be performed from the substrate 11 side towards the adhesive layer 12.

[0142] In addition, there are no particular limitations when picking up the semiconductor chip 30 from the wafer processing tape. For example, the semiconductor chip 30 can be pushed up with a pin or picked up with a suction clamp.

[0143] Alternatively, during pickup, a stretching device can be used to stretch the wafer processing tape 10 along the surface direction, and the chip can be picked up by the pickup device while the semiconductor chips 30 are separated.

[0144] Example

[0145] The present invention will now be described in more detail using examples and comparative examples. The present invention is not limited to any of the examples described below. It should be noted that all physical property values ​​are measured at room temperature unless otherwise specified. Furthermore, the amount of each raw material used is described in terms of solid content unless otherwise specified. Therefore, in the case where 100 parts by weight of a raw material with a solid content of 40% is described as used, the total amount used, including its liquid content, is 250 parts by weight.

[0146] (Comparative Example 1)

[0147] A composition for adhesive layers is prepared by mixing 100 parts by weight of an acrylic resin (VINYROL ELX-6512 manufactured by Resonac, glass transition temperature: -60°C) containing polymerizable carbon double bonds, carboxyl groups, and hydroxyl groups, 2.5 parts by weight of an acylphosphine oxide type photopolymerization initiator (Omnirad 819 manufactured by IGM Resins BV), and 3.5 parts by weight of an epoxy crosslinking agent (TETRAD-X manufactured by Mitsubishi Gas Chemical Co., Ltd.).

[0148] A 50 μm thick transparent polyamide film (Uniamide EX-50, manufactured by UNITIKA, with 85% UV transmittance at 365 nm and no yield point) was used as a substrate layer, and the adhesive layer composition prepared as described above was coated on one surface of the film. Then, after heating at 150°C for 2 minutes, an aging treatment was performed at 40°C for 3 days to allow the carboxyl and hydroxyl groups of the acrylic resin to react with the epoxy groups of the epoxy crosslinking agent and crosslink. Thus, the wafer processing tape of Comparative Example 1 was produced. The thickness of the adhesive layer was 15 μm.

[0149] (Example 1)

[0150] A 50 μm thick transparent polyamide film (Uniamide EX-50 manufactured by UNITIKA, 85% UV transmittance at 365 nm, no yield point) was used as the substrate layer. On one surface of the substrate, Colcoat CS-5309 (manufactured by Colcoat) containing urethane acrylate resin and carbon nanotubes was coated and dried to form an antistatic layer (0.5 μm thick, 85% total light transmittance).

[0151] Then, the same adhesive layer composition as in Comparative Example 1 was coated onto the antistatic layer, heated at 150°C for 2 minutes, and then aged at 40°C for 3 days to allow the carboxyl and hydroxyl groups of the acrylic resin to react with the epoxy groups of the epoxy crosslinking agent and crosslink, forming an adhesive layer (15 μm thick). Thus, the wafer processing tape of Example 1, having a laminated structure in which the antistatic layer is sandwiched between the substrate layer and the adhesive layer, was produced.

[0152] (Comparative Example 2)

[0153] An antistatic layer was made using Colcoat (manufactured by Colcoat Corporation, product name: Colcoat PS-903), which contains polysiloxane and polystyrene sulfonic acid compounds. Otherwise, the wafer processing tape of Comparative Example 2 was made in the same manner as in Example 1.

[0154] (Comparative Example 3)

[0155] To prepare adhesive layer composition 2, 1% by mass of an ionic liquid (manufactured by Carlit Corporation, Japan, product name: CIL-312) was added to the adhesive layer composition of Comparative Example 1. The wafer processing tape of Comparative Example 3 was prepared in the same manner as in Comparative Example 1, except that adhesive layer composition 2 was used instead of adhesive layer composition 1.

[0156] (Adhesive force)

[0157] Adhesive strength was measured according to JIS Z 0237. Specifically, wafer processing tape was placed on the mirror surface of a silicon wafer, and a 2 kg roller was used to press it back and forth once. After standing at 23°C for 30 minutes, the surface of the adhesive layer of the wafer processing tape was adhered to the mirror surface of the silicon wafer. Then, without heating, the adhesive strength N0 (N / 25 mm) was calculated when the wafer processing tape was peeled at a peel angle of 180° and a peel speed (tension speed) of 300 mm / min.

[0158] In addition, after attaching the adhesive layer of the wafer processing tape to the mirror surface of the silicon wafer, it is heated at 250°C for 5 minutes, and then the adhesive force N1 (N / 25mm) is measured when the wafer processing tape is peeled off at a peel angle of 180° and a peel speed (stretch speed) of 300mm / min.

[0159] (Surface resistivity)

[0160] Surface resistivity was measured according to JIS K 6911. Specifically, the surface resistivity R0 (Ω / □) of the adhesive layer of the wafer processing tape before heating was measured using a digital ultra-high resistance / micro-current meter (ADC 5451).

[0161] In addition, the wafer processing tape was heated at 250°C for 5 minutes, and then the surface resistivity R1 (Ω / □) of the adhesive layer of the wafer processing tape was measured.

[0162] (Processing technology)

[0163] The bonding process involves attaching the surface of the adhesive layer of the wafer processing tape to the silicon wafer, followed by heating at 250°C for 5 minutes to simulate the metal layer formation process. Then, the wafer is diced, and the adhesive layer is bonded using a high-pressure mercury lamp at 900 mJ / cm² from the back side of the substrate layer of the wafer processing tape. 2 Irradiation with ultraviolet light cures the adhesive layer, allowing the wafer processing tape to be peeled off the wafer, resulting in a monolithic chip.

[0164] (Low pollution)

[0165] For 100 chips that have undergone the above processing, the surface after being peeled off from the wafer processing tape was observed using a digital microscope (KEYENCE VHX-900) to evaluate contamination.

[0166] A: Over 95% of the chips showed no observed patchy contamination.

[0167] B: The percentage of chips with no observed mottled contamination was above 85% and below 95%.

[0168] C: The percentage of chips with no observed mottled contamination is above 75% and below 85%.

[0169] D: The percentage of chips with no observed mottled contamination is less than 75%.

[0170] (Antistatic properties)

[0171] For 100 chips that have undergone the above processing, the adhesion of polishing debris was visually confirmed. Based on the results, the antistatic properties were evaluated according to the following evaluation criteria.

[0172] A: The percentage of chips with no observed grinding debris adhesion was over 98%.

[0173] B: The percentage of chips with no observed grinding debris adhesion is above 95% and below 98%.

[0174] C: The percentage of chips with no observed grinding debris adhesion is above 90% and below 95%.

[0175] D: The percentage of chips with no observed grinding debris adhesion is less than 90%.

[0176] [Table 1]

[0177]

[0178] Furthermore, instead of forming an antistatic agent layer between the substrate layer and the adhesive layer, a wafer processing tape with an antistatic agent layer on the back side 11b of the substrate layer was fabricated. As a result, the antistatic properties were poor, and chip adhesion was observed. Furthermore, instead of forming an antistatic agent layer between the substrate layer and the adhesive layer, a wafer processing tape with an antistatic agent layer on the back side 12a of the adhesive layer was fabricated. As a result, although the antistatic properties were excellent, the electrical characteristics of the chip were reduced, and contamination was confirmed.

[0179] In addition, the same adhesive layer composition as in Example 1 was prepared, coated onto a transparent polyamide film, and heated at 150°C for 60 minutes without aging to produce a wafer processing tape. The surface resistivity R1 of the adhesive layer side of this wafer processing tape after heating at 250°C for 5 minutes was 1.0 × 10⁻⁶. 12 In the following examples, the ratio (R1 / R0) is also 0.001 to 10 or less, but the ratio (R1 / R0) of the surface resistivity R0 before heating to the surface resistivity R0 after heating is slightly higher than that in Example 1. Therefore, it is believed that by allowing the reaction between the base polymer and the crosslinking agent to proceed sufficiently, the migration of the antistatic agent is less likely to occur even during processes where the wafer processing tape is exposed to high temperatures. Therefore, from the viewpoint of adjusting the surface resistivity R0 and the ratio (R1 / R0), it is considered preferable to perform a prescribed aging treatment.

[0180] In addition, the wafer processing tape of Example 1 also has excellent chemical resistance, heat resistance, dicing ability, spreadability and pick-up ability, and can be used as a wafer processing tape that can be used throughout in semiconductor processing.

[0181] Industrial availability

[0182] The present invention can suppress the adhesion of cutting chips generated in the dicing process due to static electricity, and can also suppress the chip from being contaminated by antistatic agents in processes that require heating, such as the metal layer formation process S3 and the processing process S5. Therefore, it is industrially applicable as a wafer processing tape that can be used throughout semiconductor processing and a processing method using it.

Claims

1. A wafer processing tape, which has the following characteristics: Substrate layer; Adhesive layer; and An antistatic layer disposed between the substrate layer and the adhesive layer. The ratio of the surface resistivity R1 of the adhesive layer side after heating at 250°C for 5 minutes to the surface resistivity R0 of the adhesive layer side before heating, i.e., R1 / R0, is 0.001 to 10 or less. The surface resistivity R1 is 1.0 × 10⁻⁶. 12 the following.

2. The wafer processing tape according to claim 1, wherein, The surface resistivity R0 is 1.0 × 10⁻⁶. 12 the following.

3. The wafer processing tape according to claim 1, wherein, The antistatic layer contains carbon material.

4. The wafer processing tape according to claim 1, wherein, The antistatic layer comprises urethane resin.

5. The wafer processing tape according to claim 1, wherein, The adhesion force N0 of the adhesive layer to the silicon wafer is 0.2 to 5.0 N / 25 mm at 25°C.

6. The wafer processing tape according to claim 1, wherein, The adhesion force N1 of the adhesive layer to the silicon wafer after heating at 250°C for 5 minutes is 0.5 to 6.0 N / 25 mm at 25°C.

7. The wafer processing tape according to claim 1, wherein, The substrate layer comprises polyamide resin.

8. The wafer processing tape according to claim 1, wherein, The substrate layer does not have a yield point.

9. The wafer processing tape according to claim 1, wherein, The substrate layer has an ultraviolet transmittance of over 70% at 365nm.

10. A wafer processing method comprising: a processing step of attaching a wafer processing tape according to any one of claims 1 to 9 to a wafer and performing wafer processing.

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