Airtight failure monitoring system and method for aging process of non-airtight packaged chip

Abstract

The invention provides a non-airtight packaging chip aging process airtight failure monitoring system and method, and the system comprises a high-temperature and high-humidity aging oven which is used for accommodating a plurality of to-be-tested non-airtight packaging chips which are arranged in an array form; the chip bearing unit is arranged in the aging oven and is used for bearing the chip array to be tested at a fixed interval; the structured light projection unit is used for projecting regular dot matrix patterns to the surface of the chip array; the image acquisition unit is used for acquiring a dot matrix image reflected by the surface of the chip; the deformation field resolving unit is used for comparing the position of each dot matrix feature point in the currently acquired image with a pre-stored reference position; and the failure judgment unit is used for carrying out statistical analysis on the offset vector field of each sub-region. According to the method, different types of air tightness failures such as an overall bulge type, a local bulge type and an edge warping type can be automatically identified according to the space distribution mode of the offset vector field, and data support is provided for failure mechanism analysis and packaging process improvement.

Description

Technical Field

[0001] This invention relates to the field of chip testing and reliability assessment technology, specifically to a system and method for monitoring hermeticity failure during the aging process of non-hermetic packaged chips. Background Technology

[0002] With the rapid development of consumer electronics, automotive electronics, and the Internet of Things (IoT) industries, the application scenarios of integrated circuit chips are becoming increasingly diversified, and the working environments are becoming more complex and demanding. To reduce packaging costs while ensuring reliability, non-hermetic packaging technology is widely used in over 90% of commercial chip products. Unlike traditional metal or ceramic hermetic packaging, non-hermetic packaging typically uses organic polymer materials such as epoxy resin and silicone as the packaging matrix. While these materials are inexpensive and have mature manufacturing processes, their molecular structure inherently contains microscopic pores, making it impossible to completely prevent the penetration of external moisture. When a chip operates in a high-temperature and high-humidity environment for extended periods, water molecules in the environment gradually diffuse into the chip through microscopic defects in the packaging material itself or the packaging interface, causing a series of reliability problems, including electrochemical corrosion of metal interconnects, oxidation and deterioration of solder joints, decreased insulation performance of the dielectric layer, and delamination of the passivation layer on the chip surface. Ultimately, this leads to degradation of the chip's electrical performance or even complete failure.

[0003] To assess the resistance of non-hermetic packaged chips to moisture intrusion and screen for potential early failures, the industry commonly uses high-temperature, high-humidity aging tests as a reliability assessment method. Typical test conditions are 85°C and 85% RH, with durations ranging from hundreds to thousands of hours. These tests accelerate the moisture intrusion process to simulate the cumulative moisture exposure a chip might experience during its actual lifespan. After the aging test, hermeticity testing is typically performed on all or a sample of chips to determine if package integrity has deteriorated.

[0004] Traditional methods for testing chip airtightness mainly include helium mass spectrometry (HMS), bubble method, and gravimetric method. Helium mass spectrometry (HMS) leak detection pre-fills the package with helium and then detects the leakage rate in a vacuum environment to determine the airtightness level. This method has high sensitivity but is only applicable to packages with internal cavities, and the equipment is expensive and complex, making it difficult to use for large-scale screening. The bubble method immerses the chip in a heated liquid and observes whether bubbles escape from the package. This method is simple and intuitive but has low sensitivity, only detecting severely failed samples with large leakage channels. The gravimetric method calculates moisture absorption by measuring the weight change of the chip before and after moisture exposure, thus indirectly assessing airtightness. This method requires a high-precision balance and is easily affected by fluctuations in ambient humidity, resulting in poor measurement repeatability. A common limitation of these methods is that they are all offline testing methods, requiring the chip to be removed from the aging environment for individual testing, making it impossible to obtain real-time dynamic information on the chip's airtightness during the aging process. In addition, these methods can usually only detect one or a few samples at a time, which is inefficient when dealing with large batches of chips, and repeated chip handling may introduce additional mechanical stress damage.

[0005] In view of the problems existing in the above background technology, there is an urgent need in the field for an optical inspection system and method that can perform real-time, parallel, non-contact airtightness monitoring of a large number of non-hermetic packaged chips during high temperature and high humidity aging process. Summary of the Invention

[0006] To overcome the shortcomings of existing technologies, this invention proposes a hermeticity failure monitoring system for the aging process of non-hermetic packaged chips, comprising: A high-temperature and high-humidity aging chamber is used to contain multiple non-hermetic packaged chips to be tested arranged in an array. The aging chamber can maintain preset temperature and humidity conditions and has an observation window on the chamber wall for optical measurement. A chip carrier unit is disposed inside the aging chamber and is used to carry the array of chips under test at fixed intervals and record the row and column position information of each chip in the array. A structured light projection unit is disposed outside the observation window and is used to project a regular dot matrix pattern onto the surface of the chip array through the observation window. The regular dot matrix pattern is composed of multiple discrete light spots arranged regularly at a preset spacing. The preset spacing matches the package feature size of a single chip, so that each chip surface is covered with at least a minimum number of dot matrix light spots that can characterize its surface deformation state. An image acquisition unit is located outside the observation window and is used to acquire a dot pattern image reflected by the surface of the chip array through the observation window, and transmit the acquired image data to the deformation field calculation unit. The deformation field calculation unit is used to receive the dot matrix image transmitted by the image acquisition unit, process the image to extract the feature point coordinates of each dot matrix spot, compare the coordinate position of each feature point in the current acquired image with the reference position of the corresponding feature point in the pre-stored reference image, calculate the two-dimensional offset vector of each feature point in the image plane along the horizontal and vertical directions, and divide the full-field two-dimensional offset vector field covering the entire chip array into multiple sub-region offset vector fields corresponding to each chip according to the chip position information recorded by the chip carrier unit. The failure determination unit is used to perform statistical analysis on the offset vector field of the sub-region corresponding to each chip, extract deformation indicators that can characterize abnormal bulging or depression on the chip packaging surface, compare the deformation indicators with a preset failure threshold, and determine that the chip has suffered an airtightness failure when the deformation indicator of a certain chip exceeds the failure threshold, and output alarm information containing the location identifier of the failed chip.

[0007] Furthermore, the deformation index is the root mean square value of the offset vector magnitudes of all feature points within the sub-region, and the calculation formula is as follows: Where N is the total number of feature points in the sub-region. and These are the offsets of the i-th feature point relative to the reference position in the horizontal and vertical directions, respectively. The method for determining the preset threshold is as follows: based on the moisture absorption expansion coefficient of the chip packaging material, the thickness of the package body, and the thickness of the passivation layer, calculate the theoretical bulge height of the package surface when the moisture intrusion reaches the critical failure level, and then convert the theoretical bulge height into the offset pixel value in the image plane according to the geometric magnification relationship between the projection and imaging system, and use the offset pixel value as the reference benchmark for the failure threshold. The failure determination unit uses a time filtering mechanism when determining failure. It only confirms failure when the deformation index of a chip exceeds the threshold for multiple consecutive sampling periods, so as to avoid misjudgment caused by image noise or transient disturbances.

[0008] Furthermore, the deformation field calculation unit also has a failure type identification function, used to identify different types of airtightness failures based on the spatial distribution pattern of the sub-region offset vector field, including: For overall bulging failure identification, calculate the radial and tangential components of the offset vector of each feature point in the sub-region relative to the geometric center of the sub-region. When the radial component is dominant and shows a spatial distribution pattern that decreases from the center to the edge, it is determined to be an overall bulging failure. This type of failure is characterized by the uniform intrusion of moisture into the interior of the package, leading to an increase in overall internal pressure. For the identification of local bulging failure, the rate of change of the distance between all adjacent feature point pairs in a sub-region is calculated. When the rate of change of the distance between adjacent points in a certain local region is significantly greater than the average level of the sub-region and exceeds the preset local anomaly threshold, it is determined to be a local bulging failure. This type of failure is characterized by regional bulging caused by the local intrusion of moisture along the passivation layer defect. Edge warping failure identification involves calculating the average offset vector direction of the edge strip region and the central region of the sub-region. When the offset vector of the edge region exhibits a consistent outward warping direction and there is a significant angle difference with the offset direction of the central region, it is determined to be an edge warping failure. This type of failure characterizes edge delamination caused by moisture intrusion along the chip-package interface.

[0009] Furthermore, it also includes an environmental deformation compensation module, which comprises: The temperature acquisition submodule includes at least one temperature sensor located inside the aging chamber near the chip array, for real-time acquisition of the ambient temperature of the area where the chip array is located. The thermal expansion calculation submodule is used to store the thermal expansion coefficient of the packaging material of the chip under test. Based on the temperature difference between the current temperature obtained by the temperature acquisition submodule and the reference temperature when the reference image was acquired, it calculates the theoretical displacement of each point on the chip surface caused by the thermal expansion of the material and generates a thermal expansion theoretical offset vector field. The compensation execution submodule is used to subtract the thermal expansion theoretical offset vector field from the measured offset vector field calculated by the deformation field solution unit to obtain the net offset vector field after eliminating the influence of thermal expansion. The failure determination unit performs subsequent deformation index calculation and failure determination based on the net offset vector field.

[0010] Furthermore, the light source of the structured light projection unit adopts a near-infrared light-emitting device with a working wavelength range of 750nm to 950nm, so as to reduce the interference of visible light illumination changes in the aging chamber on the measurement. The observation window is made of optical glass material with high transmittance to the near-infrared band, with a transmittance of not less than 90%, and the inner surface of the window is provided with an anti-condensation coating or a heating device. The imaging device of the image acquisition unit is equipped with a bandpass filter at the front end, the center wavelength of which matches the working wavelength of the structured light projection unit, and the bandpass width is 20nm to 50nm, which is used to filter out ambient stray light. The failure determination unit also has a trend monitoring function, which is used to record the historical data of the deformation index of each chip as it ages and generate a deformation curve. The deformation growth rate is obtained by calculating the slope of the deformation curve. When the deformation growth rate of a chip exceeds a preset rate threshold, the chip is marked as a high-risk chip, and an instruction is sent to the image acquisition unit to increase the image acquisition frequency or acquisition resolution of the chip area.

[0011] A method for monitoring the hermeticity failure of a non-hermetic packaged chip during high-temperature and high-humidity aging process, implemented using the system described above, includes the following steps: S1: Place multiple non-hermetic packaged chips to be tested in an array according to a preset row and column spacing on the chip carrier unit in the high temperature and high humidity aging chamber. Record the row number, column number and corresponding physical coordinate range of each chip in the array and establish a physical position mapping table of the chip array. Set the target temperature and target humidity of the aging chamber and start the aging chamber to gradually bring its internal environment to the set high temperature and high humidity conditions. S2: After the temperature and humidity inside the aging chamber stabilize to the set value and remain stable for the preset time, the structured light projection unit is controlled to project a regular dot matrix pattern onto the surface of the chip array. Simultaneously, the image acquisition unit is triggered to acquire the dot matrix reflection image at this time as a reference image. The reference image is processed to identify all the dot matrix spots in the image and extract the feature point coordinates of each spot. All feature point coordinates are stored as a reference position set, and the relationship between each feature point and its corresponding chip is established. S3: During the aging test, structured light projection and image acquisition are periodically triggered according to a preset sampling time interval to obtain the monitoring image at the current moment; for each frame of monitoring image, the following processing is performed: the image is preprocessed, including noise reduction and contrast enhancement, the current coordinates of the feature points of each dot matrix spot in the image are identified and extracted, the current coordinates are matched one by one with the corresponding feature points in the reference position set, the offset Δx in the horizontal direction and the offset Δy in the vertical direction of each feature point relative to its reference position are calculated to obtain the two-dimensional offset vector of the feature point, and the offset vectors of all feature points are summarized to form a full-field offset vector field covering the entire chip array; according to the physical position mapping table established in step S1, the full-field offset vector field is divided according to the physical coordinate range of each chip to obtain the sub-region offset vector field corresponding to each chip; the offset vectors in each sub-region are statistically analyzed to calculate the deformation index characterizing the degree of deformation of the chip surface; S4: Compare the current deformation index of each chip with the preset failure threshold. If the deformation index of a chip exceeds the failure threshold, start the confirmation timer. When the deformation index of the chip continues to exceed the threshold for a preset number of confirmation cycles, the chip is finally determined to have suffered an airtightness failure. Record the array position of the failed chip, the failure determination time, the cumulative aging time, and the deformation index value at the time of failure, and generate a failure alarm signal. For chips that have not failed, record their current deformation index for subsequent trend analysis.

[0012] Furthermore, in step S3, the extraction of feature point coordinates adopts the gray-scale centroid method to achieve sub-pixel precision positioning. Specifically, firstly, the various dot matrix light spot regions in the image are identified by threshold segmentation or connected component analysis. For each light spot region, the gray value of each pixel in the region is used as the weight to calculate the weighted average of all pixel coordinates. The obtained weighted average coordinates are the sub-pixel precision center coordinates of the feature point of the light spot, and the positioning accuracy can reach the level of 0.1 pixels. In step S3, the feature point matching adopts a fast matching strategy based on spatial neighborhood constraints. Specifically, the maximum allowable offset is set in advance according to system calibration or experience. For each feature point in the set of reference positions, a search window is defined in the current monitoring image with the reference position of the feature point as the center and the maximum allowable offset as the radius. All candidate feature points are searched within the search window. The candidate point closest to the reference position is selected as the matching point. If there is no candidate point in the search window, the reference point is marked as a missing matching point. When the number of missing points exceeds the preset missing tolerance ratio, an exception handling process is triggered, including expanding the search window to rematch or marking the frame image as a low-quality frame.

[0013] Furthermore, the preset threshold mentioned in step S4 is determined using a method based on reference sample statistics, specifically including the following sub-steps: S4a: Select several chips from the same batch and package type as the chip under test, and whose airtightness has been confirmed to be qualified by factory inspection, as reference samples. The number of reference samples shall not be less than 10% of the number of chips under test or not less than 5. S4b: Place the reference sample and the chip under test together in the aging chamber, and perform the same monitoring process on the reference sample as on the chip under test under the same aging conditions to obtain the deformation index values ​​of the reference sample at each moment during the entire aging cycle. S4c: Statistically analyze the distribution characteristics of deformation indices of all reference samples, calculate their mean μ and standard deviation σ, and determine the upper limit of the natural fluctuation range of deformation indices caused by normal process fluctuations. Usually, μ+3σ is taken as the upper limit of natural fluctuation. S4d: Multiply the upper bound of the natural fluctuation by the safety factor k to obtain the failure judgment threshold. The safety factor k is set according to the chip reliability level requirements and has a value range of 1.2 to 2.0. S4e: During the aging test, the deformation index of the reference sample is continuously monitored. If the reference sample shows abnormalities, the rationality of the threshold setting is reassessed.

[0014] Furthermore, it also includes a failure location and root cause analysis step S5 performed after step S4, specifically as follows: S5a Deformation Peak Location: For chips determined to have airtightness failure, extract the magnitude of the offset vector of each feature point in the offset vector field of the corresponding sub-region, perform spatial interpolation within the sub-region to generate a continuous offset amplitude distribution map, search for the extreme point position of the distribution map, and mark the extreme point with the largest offset amplitude as the suspected moisture intrusion point. S5b Deformation Evolution Retrospective: Retrieve all historical deformation data of the failed chip from the start of aging to the time of failure determination, analyze the evolution curve of deformation index over time, identify the inflection point when deformation begins to accelerate, and the aging time corresponding to this inflection point can be used as a characterization parameter of the chip's ability to resist moisture intrusion. S5c Failure Mode Classification: According to the failure type identification method described in claim 3, determine whether the failure type of the failed chip is overall bulge type, local bulge type, or edge warping type; S5d Correlation Analysis: If multiple chips in the same aging batch experience the same type of failure and the suspected intrusion points show a regular distribution, they are marked as suspected batch-related process defects and a process feedback report is generated.

[0015] Furthermore, step S3 also includes an image validity verification and anomaly handling mechanism, specifically: The total number of feature points successfully extracted in the current monitored image is counted, and the proportion of the number of feature points in the reference location set is calculated. If the proportion is lower than the preset effective feature point proportion threshold (e.g., 80%), the image frame is determined to be a low-quality frame. For low-quality frames, the data of that frame is not used for deformation index calculation. Instead, the deformation index of the most recent valid frame is used as the replacement value for the current moment, and the data record is marked as interpolated data for that moment. If multiple consecutive frames are determined to be low-quality frames, the system alarm will be triggered to indicate that there may be abnormalities such as light path obstruction, condensation or equipment failure, and automatic monitoring will be suspended and manual intervention will be requested. When changes in environmental conditions cause a systematic decline in image quality that is still acceptable, image processing parameters, including spot detection threshold and matching search window size, are automatically adjusted to adapt to the changed imaging conditions.

[0016] Compared with the prior art, the beneficial effects of the present invention are: 1. This invention provides a system and method for monitoring the airtightness failure of non-hermetic packaged chips during the aging process. It adopts a non-contact optical measurement method that combines structured light projection and image acquisition, which can monitor the chip in real time during the high temperature and high humidity aging process without interrupting the aging test or removing the chip. This overcomes the limitations of traditional offline detection methods such as helium mass spectrometry leak detection, bubble method, and weighing method, which cannot obtain information on dynamic changes in airtightness.

[0017] 2. This invention provides a system and method for monitoring the hermeticity failure of non-hermetic packaged chips during the aging process. By performing full-field measurements on the chip array, only one set of projection and imaging equipment is needed to monitor hundreds of chips simultaneously. Compared with the traditional method of detecting each chip individually, the detection efficiency is improved by two orders of magnitude. It is suitable for the reliability screening of large batches of chips and avoids the additional mechanical stress damage that may be introduced by repeated chip handling.

[0018] 3. This invention provides a system and method for monitoring hermetic failure during the aging process of non-hermetic packaged chips. It can record the evolution trend of deformation indicators of each chip with aging time, provide early warning of high-risk chips by analyzing the deformation growth rate, and automatically increase the monitoring frequency of high-risk chips to achieve early prediction and key attention of failure. Attached Figure Description

[0019] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the method flow of the present invention.

[0021] Figure 2 This is a schematic diagram of the system architecture. Detailed Implementation

[0022] The technical solution of the present invention will be more clearly and completely explained below with reference to the accompanying drawings and through the description of preferred embodiments of the present invention.

[0023] like Figure 1 As shown, the monitoring method of the present invention includes the following steps: Step 1: Chip Array Placement and Aging Chamber Startup. Place multiple non-hermetic packaged chips to be tested in an array on the carrier unit inside the high-temperature and high-humidity aging chamber, record the position information of each chip, and set and start the aging chamber to reach the preset temperature and humidity conditions.

[0024] Step 2: Projecting a dot matrix pattern and acquiring a reference image. After the environment inside the aging chamber has stabilized, a regular dot matrix pattern is projected onto the surface of the chip array through the structured light projection unit, and the image acquisition unit is simultaneously triggered to acquire the dot matrix reflection image at this time as the reference image.

[0025] Step 3: Extract feature point coordinates and store reference positions. Process the reference image to identify and extract the feature point coordinates of each dot matrix spot, store all feature point coordinates as a reference position set, and establish the relationship between feature points and corresponding chips.

[0026] Step 4: Periodically acquire monitoring images. During the aging test, structured light projection and image acquisition are periodically triggered at preset sampling time intervals to obtain the monitoring image at the current moment.

[0027] Step 5: Calculate the feature point offset vector. Process the monitoring image, extract the current coordinates of each feature point, match and compare them with the reference position, and calculate the two-dimensional offset vector of each feature point in the horizontal and vertical directions.

[0028] Step 6: Calculate the deformation index of each chip. Based on the chip position information, the full-field offset vector field is divided into sub-regions corresponding to each chip. The offset vectors in each sub-region are statistically analyzed to calculate the deformation index that characterizes the degree of deformation on the chip surface.

[0029] Step 7: Threshold Determination and Failure Alarm. The deformation index of each chip is compared with the preset failure threshold. If the threshold is not exceeded, return to Step 4 to continue periodic monitoring. If the threshold is exceeded, it is determined that the chip has suffered an airtightness failure, and an alarm message containing the location of the failed chip is output.

[0030] like Figure 2 As shown, the monitoring system of the present invention includes the following components: High temperature and high humidity aging chamber: used to contain the chip under test and maintain preset temperature and humidity conditions. The chamber is equipped with a chip carrier unit for holding the chip under test in an array. The chamber wall is provided with an observation window for optical measurement.

[0031] Structured light projection unit: Located outside the observation window, it is used to project a regular dot matrix pattern onto the surface of the chip array through the observation window.

[0032] Image acquisition unit: Located outside the observation window, it is used to acquire dot pattern images reflected from the surface of the chip array through the observation window and transmit the image data to the deformation field calculation unit.

[0033] Environmental deformation compensation module: includes temperature acquisition submodule, thermal expansion calculation submodule and compensation execution submodule, used to eliminate the influence of thermal expansion caused by temperature changes on the measurement results and provide compensation data to the deformation field solution unit.

[0034] Deformation field calculation unit: used to receive image data and compensation data, extract the coordinates of feature points of each dot matrix spot, calculate the offset vector of the feature points relative to the reference position, and generate the sub-region offset vector field corresponding to each chip.

[0035] Failure determination unit: used to perform statistical analysis on the offset vector field of each chip, calculate the deformation index and compare it with the preset threshold. When the deformation index exceeds the threshold, the chip is determined to have an airtightness failure.

[0036] Alarm information output: Used to output alarm information containing the location identifier of the failed chip.

[0037] As a specific embodiment, the monitoring system includes a high-temperature and high-humidity aging chamber, a chip carrier unit, a structured light projection unit, an image acquisition unit, a deformation field calculation unit, a failure determination unit, and an environmental deformation compensation module. The high-temperature and high-humidity aging chamber is a programmable constant temperature and humidity test chamber with an internal volume of 800mm × 600mm × 600mm. The temperature control range is room temperature to 150℃ with a temperature control accuracy of ±0.5℃, and the humidity control range is 30%RH to 98%RH with a humidity control accuracy of ±2%RH. A 200mm × 200mm observation window is provided on the side wall of the aging chamber. The observation window is made of 10mm thick borosilicate optical glass, which has a 92% transmittance for near-infrared light at a wavelength of 850nm and exhibits good high-temperature and humidity resistance. The inner surface of the observation window is coated with a transparent conductive indium tin oxide film. By electrically heating this film, the surface temperature of the window can be kept 3℃ to 5℃ higher than the dew point temperature inside the chamber, effectively preventing condensation from affecting optical measurements.

[0038] The chip carrier unit uses an anodized aluminum alloy tray with regularly arranged chip positioning slots on its surface. These slots are arranged in a 10x10 array, with a center-to-center spacing of 15mm between adjacent slots. Each slot measures 12mm x 12mm x 2mm, accommodating various non-hermetic packaged chips with side lengths not exceeding 10mm. Positioning pin holes at the four corners of the tray, working in conjunction with the positioning pins inside the aging chamber, ensure a positional repeatability of better than 0.1mm after each placement. A reference calibration block is positioned at each of the four corners of the tray edge. These calibration blocks are made of the same packaging material as the chip under test, with a precision-ground surface possessing known flatness parameters, used for real-time calibration by the subsequent imaging system.

[0039] The structured light projection unit employs a near-infrared dot matrix projector based on digital micromirror devices (DVMs), with a near-infrared light-emitting diode array having a center wavelength of 850 nm and a bandwidth of 30 nm as the light source. The projector generates a regularly arranged dot matrix pattern using DVMs. The dot matrix pattern consists of circular light spots with a diameter of approximately 0.3 mm arranged in a square grid, with a center-to-center spacing of 1.5 mm between adjacent light spots. When the dot matrix pattern is projected onto the surface of the chip carrier tray, approximately 36 dot matrix spots can cover each 10 mm × 10 mm chip surface, meeting the minimum sampling requirement for characterizing the deformation field of a single chip surface. The projector is mounted directly in front of the observation window of the aging chamber, with the projection optical axis forming a 15° angle with the normal to the chip carrier tray surface, and a projection distance of 400 mm. With this configuration, the dot matrix pattern can clearly cover the entire array area of ​​100 chips.

[0040] The image acquisition unit employs a near-infrared industrial camera with a resolution of 2048×2048 pixels and a pixel size of 5.5μm×5.5μm. It is equipped with a low-distortion industrial lens with a focal length of 50mm. A near-infrared bandpass filter with a center wavelength of 850nm and a bandpass width of 40nm is mounted at the front of the lens to filter out stray light interference from visible light illumination and other wavelengths within the aging chamber. The camera is mounted to one side of the projector, with its imaging optical axis forming a 10° angle with the normal to the chip carrier tray surface. The imaging distance is 450mm. In this configuration, a single pixel corresponds to approximately 0.08mm of space on the chip surface, and the diameter of a single dot matrix spot in the image is approximately 4 pixels. This ensures reliable spot identification while avoiding overlap between adjacent spots. The camera's frame rate is set to 1 frame per second, and the exposure time is automatically adjusted based on the intensity of reflected light, ranging from 5ms to 50ms.

[0041] The deformation field calculation unit and failure determination unit are hosted by an industrial computer equipped with a multi-core processor and a graphics processing unit, running the monitoring software specifically developed for this invention. After receiving the dot matrix image transmitted by the image acquisition unit, the deformation field calculation unit first performs image preprocessing, including dark current subtraction, flat-field correction, and Gaussian filtering for noise reduction. Then, an adaptive threshold segmentation method is used to identify all dot matrix spot regions in the image. For each spot region, the gray-scale centroid method is used to calculate its feature point coordinates. Specifically, the net gray value (resulting from subtracting the background gray value from the gray value of each pixel within the spot region) is used as a weight to perform a weighted average of the pixel coordinates, obtaining the spot center coordinates with sub-pixel precision. This method achieves a positioning accuracy of 0.05 pixels, corresponding to a spatial resolution of approximately 4 μm on the chip surface. After feature point extraction, a matching strategy based on spatial neighborhood constraints is used to match the feature points in the current image with those in the reference image one-to-one. The matching search window radius is set to 20 pixels, corresponding to a maximum allowable offset of approximately 1.6 mm on the chip surface. This setting can cover most of the packaging deformation range caused by moisture intrusion. After matching is completed, the two-dimensional offset vector of each feature point relative to its reference position is calculated and summarized to form a full-field offset vector field. Then, according to the chip position mapping table, the full-field data is divided into 100 sub-region offset vector fields, and each sub-region corresponds to a chip under test.

[0042] The environmental deformation compensation module includes a platinum resistance temperature sensor mounted in the center of the chip carrier tray. This sensor collects the ambient temperature of the chip array area in real time at a sampling frequency of 1Hz. The compensation module pre-stores the coefficient of thermal expansion of the chip's packaging material. For the epoxy resin-encapsulated chip tested in this embodiment, its linear coefficient of thermal expansion is 15 × 10⁻⁻⁻⁶. 6 / ℃. When the temperature inside the aging chamber changes relative to the reference temperature, the compensation module calculates the theoretical displacement of each feature point due to thermal expansion based on the coefficient of thermal expansion and the temperature difference, and subtracts the theoretical displacement from the measured offset vector to obtain the net offset vector field after eliminating the influence of thermal expansion. Subsequent deformation index calculations and failure determinations are all based on this net offset vector field.

[0043] The failure determination unit performs statistical analysis on the net offset vector field of the sub-region corresponding to each chip, and calculates the root mean square value of the offset vector magnitude of all feature points in the sub-region as the deformation index of the chip. In this embodiment, the failure threshold is determined by the reference sample statistical method. Specifically, 10 chips that have passed the factory inspection and are confirmed to be airtight are selected from the same batch of chips as reference samples. These chips are placed in an aging chamber together with the chip under test for monitoring. The mean and standard deviation of the deformation index of the reference samples are statistically analyzed throughout the aging cycle. The mean plus three times the standard deviation is used as the upper limit of natural fluctuation, and then multiplied by a safety factor of 1.5 to obtain the failure determination threshold. For the chip batch tested in this embodiment, the calibrated failure threshold is 0.8 pixels, corresponding to an equivalent protrusion height of approximately 64μm on the chip surface. When the deformation index of a chip exceeds the threshold, the failure determination unit starts the confirmation timer. If the deformation index of the chip remains above the threshold for 5 consecutive sampling cycles, the chip is finally determined to have suffered an airtightness failure. The array position number of the failed chip, the failure determination time, the cumulative aging time, and the deformation index value at the time of failure are recorded. At the same time, an audible and visual alarm is triggered to remind the operator.

[0044] The failure determination unit also has a failure type identification function. For chips determined to be failed, the spatial distribution pattern of the offset vector field in its sub-region is analyzed. If the offset vector exhibits a radial distribution characteristic that decreases from the center to the edge, it is determined to be an overall bulge failure, which indicates that moisture uniformly invades the package interior, leading to an increase in overall internal pressure. If the rate of change of the distance between adjacent feature points in a local area is significantly higher than the average level of the sub-region, it is determined to be a local bulge failure, which indicates that moisture intrusion along local defects in the passivation layer causes regional bulging. If the offset vector in the edge region exhibits a consistent outward warping direction and is significantly different from the offset direction in the center region, it is determined to be an edge warping failure, which indicates that moisture intrusion along the chip-package interface causes edge delamination. Failure type information, along with failure location information, is recorded for subsequent failure analysis and process improvement reference.

[0045] The failure determination unit also has failure location and root cause analysis functions. For chips determined to be failed, spatial interpolation is performed on the offset vector magnitude within its sub-region to generate a continuous offset amplitude distribution map. The location with the largest offset amplitude in this distribution map is searched and marked as a suspected moisture intrusion point. At the same time, all historical deformation data of the chip from the start of aging to the failure determination time are retrieved, and the evolution curve of deformation index with aging time is plotted to identify the inflection point when deformation begins to accelerate. This inflection point can be used as the starting point of the chip's hermeticity degradation. If multiple chips in the same aging batch experience the same type of failure and the suspected intrusion point locations show a regular distribution, the system automatically marks it as a suspected batch process defect and generates a process feedback report, indicating possible packaging process problems.

[0046] The failure determination unit also has a trend monitoring function, continuously recording historical data of deformation indicators for all chips and calculating the growth rate of each chip's deformation indicator through linear fitting. When the deformation growth rate of a chip exceeds a preset rate threshold, even if its current deformation indicator has not yet exceeded the failure threshold, the system will mark the chip as a high-risk chip, highlight it in yellow on the monitoring interface, and automatically increase the monitoring attention to that chip according to the configuration.

[0047] The monitoring software also includes an image validity verification module. After each image frame is acquired, the proportion of successfully extracted feature points to the total number of baseline feature points is counted. If this proportion is less than 80%, the frame is determined to be a low-quality frame, and its data is discarded. The deformation index value of the previous valid frame is used as a substitute, and this is noted in the data record. If 10 consecutive images are determined to be low-quality frames, the system triggers an abnormal alarm, indicating possible issues such as condensation on the observation window, light path obstruction, or equipment malfunction. Automatic monitoring is suspended, and manual intervention is requested. The software also has a parameter adaptive adjustment function. When a systematic change in the overall brightness or contrast of the image is detected, the spot detection threshold and matching search window size are automatically adjusted to adapt to the changed imaging conditions.

[0048] The specific monitoring process in this embodiment is as follows. The operator first places 90 non-hermetic packaged chips to be tested and 10 reference sample chips into 100 positioning slots on a chip carrier tray according to a numbering rule, recording the position number and batch information of each chip. The tray is placed in the aging chamber and secured with positioning pins. The chamber door is closed, and the aging conditions are set in the monitoring software to a temperature of 85°C and a relative humidity of 85%RH. The aging chamber is then started. After approximately 30 minutes of heating and humidification to reach the set conditions, the chamber is stabilized for another 10 minutes to ensure that the chip temperature reaches equilibrium with the ambient temperature. At this point, the monitoring software automatically triggers structured light projection and image acquisition to obtain a reference image, extract and store the reference coordinates of approximately 3600 feature points, establish the mapping relationship between feature points and chips, and complete the establishment of the reference state.

[0049] Once the baseline is established, the monitoring software enters a periodic monitoring mode, automatically triggering projection and acquisition every 60 seconds to obtain monitoring images and execute deformation field calculations and failure determination processes. The monitoring interface displays a pseudo-color cloud map of the full-field offset vector field in real time, with each chip area marked by a box. Normal chips are displayed in green, high-risk chips in yellow, and failed chips in red. A curve showing the deformation index changing over time is displayed at the bottom of the interface, allowing operators to select individual chips to view their detailed deformation evolution history.

[0050] This embodiment conducted a 1000-hour accelerated aging test at 85℃ / 85%RH, monitoring a total of 90 chips under test. During the test, the system detected that the deformation index of the chip numbered in row 5, column 7 began to rise rapidly at hour 387. At hour 412, the deformation index of this chip first exceeded the failure threshold of 0.8 pixels. After confirmation for 5 consecutive cycles, it was determined to be an airtight failure at hour 412.5. The system identified the failure type of this chip as local bulging, with the suspected moisture intrusion point located in the lower left quadrant of the chip. Subsequently, at hours 518, 623, and 756, three more chip failures were detected, with failure types of overall bulging, edge warping, and local bulging, respectively. The deformation index of the 10 reference sample chips remained below 0.3 pixels throughout the entire 1000-hour aging cycle, without any abnormalities, verifying the rationality of the threshold setting. After the test, the system automatically generates a test report, which summarizes the location, failure time, failure type and deformation evolution data of all failed chips, providing detailed data support for chip reliability assessment and packaging process improvement.

[0051] The monitoring system in this embodiment has a simple structure, requiring only one projection and imaging device to simultaneously monitor 100 chips, improving efficiency by two orders of magnitude compared to traditional individual detection methods. The system uses a near-infrared light source and matching filters to effectively suppress interference from visible light illumination variations and the high temperature and humidity environment within the aging chamber. The deformation analysis method based on the lattice offset vector field has low computational complexity, with a single-frame image processing time of no more than 0.5 seconds, fully meeting real-time monitoring requirements. The environmental deformation compensation module eliminates the influence of thermal expansion on the measurement results, ensuring that the detected deformation truly originates from moisture intrusion. Failure type identification and failure location functions provide valuable clues for failure analysis, helping to trace the root cause of packaging process defects.

[0052] The above-described specific embodiments are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Various modifications, substitutions, and improvements made by those skilled in the art to the technical solutions of the present invention based on the provided textual description and drawings, without departing from the design concept and spirit of the present invention, should all fall within the scope of protection of the present invention. The scope of protection of the present invention is determined by the claims.

Claims

1. A system for monitoring the hermeticity failure of a non-hermetic packaged chip during aging, characterized in that, include: High temperature and high humidity aging chamber, used to contain multiple non-hermetic packaged chips to be tested arranged in an array; A chip carrier unit is disposed inside the aging chamber and is used to carry the array of chips under test at fixed intervals and record the row and column position information of each chip in the array. The structured light projection unit is used to project a regular dot matrix pattern onto the surface of the chip array. The spacing between adjacent points in the regular dot matrix pattern matches the feature size of a single chip, so that the number of dots covering the surface of each chip meets the minimum sampling requirement for deformation field reconstruction. The image acquisition unit is used to acquire a dot matrix image reflected from the chip surface. The deformation field calculation unit is used to compare the position of each feature point in the currently acquired image with the pre-stored reference position, calculate the two-dimensional offset vector of each feature point, and divide the two-dimensional offset vector field into sub-region offset vector fields corresponding to each chip according to the physical layout of the chip array. The failure determination unit is used to perform statistical analysis on the offset vector field of each sub-region, extract deformation indicators that characterize abnormal bulges or depressions on the packaging surface, and determine that the corresponding chip has suffered a hermeticity failure when the deformation indicators exceed a preset threshold.

2. The hermeticity failure monitoring system for the aging process of a non-hermetic packaged chip according to claim 1, characterized in that, The deformation index is the root mean square value of the offset vector magnitude of all feature points in the sub-region; the preset threshold is determined by calibration experiments based on the moisture absorption and expansion characteristics of the chip packaging material and the thickness of the package.

3. The hermeticity failure monitoring system for the aging process of a non-hermetic packaged chip according to claim 1, characterized in that, The deformation field calculation unit is also used to identify the failure type based on the spatial distribution pattern of the sub-region offset vector field, including: By determining whether the offset vector exhibits a radial distribution characteristic that decreases from the center to the edge, overall bulging failure can be identified; By calculating the rate of change of the relative distance between adjacent feature points, when the rate of change of the relative distance in a local area is significantly higher than that in the surrounding area, a local bulge-type failure is identified. By calculating the average offset vector direction of the edge region and the center region of the sub-region respectively, edge warping failure is identified when the offset vector of the edge region shows a consistent outward tilting direction and has a significant angle difference with the offset direction of the center region.

4. The hermeticity failure monitoring system for the aging process of a non-hermetic packaged chip according to claim 1, characterized in that, It also includes an environmental deformation compensation module, which is used to calculate the theoretical offset caused by thermal expansion based on the real-time temperature in the aging chamber, the thermal expansion coefficient of the chip packaging material, and the deviation of the current temperature from the reference temperature, and to subtract the theoretical offset from the measured offset vector.

5. The hermeticity failure monitoring system for the aging process of a non-hermetic packaged chip according to claim 1, characterized in that, The structured light projection unit uses a near-infrared light source, the high temperature and high humidity aging chamber is equipped with an observation window that is transparent to the near-infrared band, and the image acquisition unit is equipped with a filter that matches the near-infrared band. The failure determination unit is also used to record the change curve of each chip's deformation index with aging time. When the growth rate of a chip's deformation index exceeds a preset rate threshold, the monitoring frequency of that chip is increased.

6. A method for monitoring the hermeticity failure of a non-hermetic packaged chip during aging, applicable to the hermeticity failure monitoring system for the aging process of a non-hermetic packaged chip as described in any one of claims 1-5, characterized in that, Includes the following steps: S1: Place multiple non-hermetic packaged chips to be tested in an array inside a high-temperature and high-humidity aging chamber, and establish a physical location mapping table for the chip array; set the target temperature and target humidity of the aging chamber, and start the aging chamber to make its internal environment reach the set high-temperature and high-humidity conditions. S2: After the temperature and humidity inside the aging chamber have stabilized to the set value, a regular dot matrix pattern is projected onto the surface of the chip array and a reference image is acquired. The coordinates of each dot matrix feature point in the reference image are extracted as the reference position set. S3: During the aging process, periodically acquire monitoring images and perform the following processing on each frame of monitoring image: extract the current coordinates of each matrix feature point, match them with the corresponding points in the reference position set and calculate the two-dimensional offset vector, divide the full field offset vector field into sub-regions corresponding to each chip according to the physical position mapping table, and statistically analyze the offset vectors of each sub-region to calculate the deformation index. S4: When the deformation index of a certain chip's corresponding sub-region continuously exceeds the preset threshold and reaches the preset confirmation cycle number, the chip is determined to have an airtightness failure and the failure information is recorded.

7. The method for monitoring hermeticity failure during the aging process of a non-hermetic packaged chip according to claim 6, characterized in that, In step S3, the feature point coordinates are extracted using the gray-scale centroid method. The center coordinates of the points are obtained with sub-pixel precision by weighting the gray-scale distribution of the dot matrix spot area. The feature point matching adopts a spatial neighborhood constraint strategy. For each point in the reference position set, the nearest neighbor feature point is found in the monitoring image within a search window centered on the reference position of the point and with the maximum allowable offset as the radius.

8. The method for monitoring hermeticity failure during the aging process of a non-hermetic packaged chip according to claim 6, characterized in that, The method for determining the preset threshold in step S4 is as follows: select several qualified chips of the same batch and model as reference samples, monitor the natural fluctuation range of the deformation index of the reference samples over time under the same aging conditions, and multiply the upper boundary value of the natural fluctuation range by the safety factor as the failure judgment threshold.

9. A method for monitoring hermeticity failure during the aging process of a non-hermetic packaged chip according to claim 6, characterized in that, It also includes a failure location step: for a chip that is determined to be faulty, the location of the point of maximum deformation is determined based on the spatial distribution of the offset vector amplitude in its sub-region, and this location is marked as a suspected moisture intrusion point.

10. A method for monitoring hermeticity failure during the aging process of a non-hermetic packaged chip according to claim 6, characterized in that, Step S3 also includes validity verification: when the number of feature points that can be successfully extracted in a single frame image is lower than a preset ratio, the image quality of that frame is determined to be unqualified, and the deformation index of the previous valid frame is used as a substitute.

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