Chip tin ball logic information acquisition method and system

Abstract

The application provides a chip tin ball logic information acquisition method and system, which listens to and captures mouse click events and screen pixel coordinates of a user in a video display area, the video display area displays the overall appearance of a chip, the mouse click event refers to clicking a target tin ball position on the chip; based on an affine transformation matrix M, the screen pixel coordinates of the target tin ball are converted into design physical coordinates; according to the design physical coordinates of the target tin ball, the target tin ball is searched in a chip design information database to obtain the logic information of the target tin ball, the logic information of the target tin ball includes a pin name corresponding to the target tin ball and network relationship information corresponding to the target tin ball. The application automatically completes the association from the screen pixel coordinates of the tin ball to the overall logic information through simple interaction, that is, when an operator sees a suspicious tin ball in a microscope picture, the operator automatically reveals the complete logic identity and network relationship of the tin ball in the field of view through a simple interactive action (such as clicking).

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and more specifically, to a method and system for acquiring logic information from chip solder balls. Background Technology

[0002] In integrated circuit manufacturing and failure analysis, especially for chips using ball grid array (BGA) packages, visual inspection of the solder balls at the bottom of the chip package using an electron microscope is a crucial step. The purpose of this inspection is to detect various physical defects in the solder balls, such as bridging, cold solder joints, voids, contamination, or oxidation. After a defect is found, the pin name and corresponding signal network of the defective solder ball are manually determined by comparing it with schematics, allowing designers to analyze the impact of the defect on circuit functionality.

[0003] Currently, the commonly used technical solution in the industry is a process that relies on manual comparison and cross-tool querying: ① Manual positioning: After discovering a suspicious solder ball in the electron microscope field of view, the operator determines the row and column coordinates of the solder ball in the microscope field of view by manually counting; ② Chart comparison: Open the chip's pin distribution diagram file (Ball Map file), which is a chart that marks the correspondence between the position (row and column coordinates) of each solder ball and its pin name; ③ Manual query: Find the corresponding pin name by counting the same row and column positions on the chart; ④ Secondary tracing: For further analysis, the operator also needs to manually query the signal network to which the pin belongs and the internal functional modules it is connected to in another design file (such as a netlist or schematic diagram) based on the pin name; ⑤ Manual recording: Finally, the operator manually enters the defect image, location information, pin name, etc. into the report.

[0004] Existing solder ball detection methods for chips have the following disadvantages:

[0005] (1) Disadvantage 1: Extremely low efficiency and prone to errors.

[0006] Reason: The process relies entirely on the operator's visual counting and manual switching and searching between different documents and tools.

[0007] Reasoning: Manually counting rows and columns is prone to fatigue and errors; under a high-powered microscope, the field of view is narrow and lacks global reference, greatly increasing the difficulty of counting. This directly leads to slow positioning speed and the risk of misjudgment.

[0008] (2) Disadvantage 2: Information fragmentation makes analysis and tracing difficult.

[0009] Cause: Physical defect information (microscope images) and logic design information (pin diagrams, netlists) are stored on different media, processed by different tools, and are isolated from each other.

[0010] Reasoning: Operators or analysts cannot quickly obtain circuit-level information when defects are discovered. This makes it impossible to record and evaluate defects in a timely manner, requiring a separate, specialized design document retrieval process, which severely hinders analysis efficiency. Summary of the Invention

[0011] This invention addresses the technical problems existing in the prior art by providing a method and system for obtaining logic information of chip solder balls, overcoming the shortcomings of low efficiency and error-proneness in manually searching for solder ball-related information.

[0012] According to a first aspect of the present invention, a method for obtaining logic information of chip solder balls is provided, comprising:

[0013] Listen for and capture user mouse click events and screen pixel coordinates in the video display area, where the video display area shows the entire chip, and the mouse click event refers to clicking on a target solder ball on the chip;

[0014] Based on the affine transformation matrix M, the screen pixel coordinates of the target tin ball are converted into the design physical coordinates;

[0015] Based on the physical coordinates of the target solder ball, the chip design information database is searched to obtain the logic information of the target solder ball. The logic information of the target solder ball includes the pin name corresponding to the target solder ball and the network relationship information of the target solder ball. The network relationship information of the target solder ball includes the signal network to which the target solder ball belongs, the network electrical attributes, and the global network pin member list.

[0016] Based on the above technical solution, the present invention can also be improved as follows.

[0017] Optional, also includes:

[0018] Obtain the chip standard design file, which includes a pinout diagram file and a network connection table file. The pinout diagram file records the correspondence between the physical coordinates of each solder ball and the pin name. The network connection table file records the network relationship information of each pin, including the signal network to which the pin belongs, the network electrical attributes, and the global network pin member list.

[0019] The pin distribution diagram file and the network connection table file are parsed to construct a coordinate-pin lookup table and a pin-network relationship lookup table. The coordinate-pin lookup table is constructed using the pin design physical coordinates as the key and the pin name as the value, and a KD tree is used to construct the pin-network relationship lookup table. The pin-network relationship lookup table is constructed using the pin name as the key and network relationship information as the value. The network relationship information includes the signal network, network electrical attributes, and a list of all pins in the same network as the value.

[0020] The coordinate-pin lookup table and the pin-network relationship lookup table constitute a chip design information database.

[0021] Optionally, establish the mathematical correspondence between the microscope video pixel coordinate system and the chip design physical coordinate system to obtain the affine transformation matrix M, including:

[0022] By clicking on multiple solder balls in the video frame with the mouse, the screen pixel coordinates of each solder ball can be obtained, forming a set of screen pixel coordinates for multiple solder balls;

[0023] Based on the pin name of each click location, the corresponding physical coordinates of the design are retrieved from the chip design information database to form a set of physical coordinates of multiple solder balls.

[0024] Based on the screen pixel coordinates and design physical coordinates of multiple solder balls, a two-dimensional affine transformation model is used to describe the transformation relationship between the screen pixel coordinates and the design physical coordinates, resulting in the affine transformation matrix M from the screen pixel coordinates to the design physical coordinates.

[0025] Optionally, the screen pixel coordinates and design physical coordinates of the plurality of solder balls are described using a two-dimensional affine transformation model, including:

[0026] The screen pixel coordinates and design physical coordinates of each solder ball are treated as a coordinate pair. Based on multiple coordinate pairs, the optimal affine transformation matrix M is solved using the least squares method.

[0027] Optionally, the step of converting the screen pixel coordinates of the target solder ball into design physical coordinates based on the affine transformation matrix M includes:

[0028] ;

[0029] Where (u, v) represents the screen pixel coordinates of the target solder ball, and (x, y) is the design physical coordinates of the target solder ball.

[0030] Optionally, the step of retrieving the logic information of the target solder ball from the chip design information database based on the design physical coordinates of the target solder ball includes:

[0031] Based on the design physical coordinates of the target solder ball, the pin name of the target solder ball is retrieved from the coordinate-pin lookup table;

[0032] Based on the pin name of the target solder ball, the network relationship information of the target solder ball is found in the pin-network relationship lookup table;

[0033] The pin names and network relationship information of the target solder ball constitute the logical information of the target solder ball.

[0034] Optionally, the step of retrieving the logic information of the target solder ball from the chip design information database based on the design physical coordinates of the target solder ball further includes:

[0035] Draw a semi-transparent information box near the mouse click position in the video display area as an independent graphics layer, and render the pin name and signal network name of the target solder ball in the graphics layer;

[0036] In the chip's global thumbnail navigation window, all pin positions contained in the global network pin member list in the target solder ball's network relationship information are highlighted to present the signal path of the target solder ball.

[0037] According to a second aspect of the present invention, a logic information acquisition system for chip solder balls is provided, comprising:

[0038] The monitoring module is used to monitor and capture user mouse click events and screen pixel coordinates in the video display area. The video display area shows the entire chip, and the mouse click event refers to clicking on the target solder ball position on the chip.

[0039] The transformation module is used to convert the screen pixel coordinates of the target tin ball into the design physical coordinates based on the affine transformation matrix M.

[0040] The retrieval module is used to retrieve the logic information of the target solder ball from the chip design information database based on the design physical coordinates of the target solder ball. The logic information of the target solder ball includes the pin name corresponding to the target solder ball and the network relationship information of the target solder ball. The network relationship information of the target solder ball includes the signal network to which the target solder ball belongs, the network electrical attributes, and the global network pin member list.

[0041] According to a third aspect of the present invention, an electronic device is provided, including a memory and a processor, wherein the processor is configured to execute a computer management program stored in the memory to implement a method for obtaining logical information of chip solder balls.

[0042] According to a fourth aspect of the present invention, a computer-readable storage medium is provided, on which a computer management class program is stored, wherein when the computer management class program is executed by a processor, the steps of a method for obtaining logical information of chip solder balls are implemented.

[0043] This invention provides a method and system for acquiring the logic information of a chip solder ball. It monitors and captures user mouse click events and screen pixel coordinates in a video display area; based on an affine transformation matrix M, it converts the screen pixel coordinates of the target solder ball into design physical coordinates; and retrieves the logic information of the target solder ball from a chip design information database according to the design physical coordinates of the target solder ball. The logic information of the target solder ball includes the pin name corresponding to the solder ball and the network relationship information corresponding to the solder ball. This invention automatically completes the association from the screen pixel coordinates of the solder ball to all logic information through simple interaction. That is, when an operator sees a suspicious solder ball in a microscope image, a simple interactive action (such as clicking) automatically reveals the complete logical identity and network relationship of the solder ball within their field of view. Attached Figure Description

[0044] Figure 1 A flowchart illustrating a method for obtaining logic information of a chip solder ball according to an embodiment of the present invention;

[0045] Figure 2 This is a diagram illustrating the location of the target solder ball clicked by the user.

[0046] Figure 3 A schematic diagram highlighting the associated solder balls of the target solder ball;

[0047] Figure 4 This is a schematic diagram of a logic information acquisition system for chip solder balls provided in one embodiment of the present invention;

[0048] Figure 5 This is an overall structural diagram of a logic information acquisition system for chip solder balls;

[0049] Figure 6 A schematic diagram of a possible hardware structure of an electronic device provided by the present invention;

[0050] Figure 7 This is a schematic diagram of the hardware structure of a possible computer-readable storage medium provided by the present invention. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. In addition, the technical features of the various embodiments or individual embodiments provided by the present invention can be arbitrarily combined with each other to form feasible technical solutions. Such combinations are not constrained by the order of steps and / or structural composition patterns, but must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0052] Before describing the method for obtaining logic information of chip solder balls provided by the present invention, the technical terms and concepts that may be involved in the present invention will be explained.

[0053] Solder balls: These are spherical or near-spherical conductive bumps on the bottom of a chip package used for soldering to a printed circuit board. They are a key interconnect structure in package types such as ball grid arrays.

[0054] Pin: Also known as a "pin" or "pad", it refers to the logic endpoint that enables electrical connection between the internal circuitry of a chip and the external environment. Physically, one pin corresponds to one solder ball.

[0055] Pinout diagram: A chart file that defines the correspondence between the physical location (row / column or X / Y coordinates) of each solder ball and its logic pin name.

[0056] Netlist: A data file that describes the connections between circuits, recording which signal network each pin is connected to and which other pins are included in that network.

[0057] Signal network: In circuit design, a set of pins that have the same electrical connection relationship, such as a data bus, a clock line, or a power domain.

[0058] Figure 1 A flowchart illustrating a method for obtaining logic information of a chip solder ball according to an embodiment of the present invention is shown, as follows: Figure 1 As shown, the method includes the following steps:

[0059] Step 1: Listen for and capture the user's mouse click events and screen pixel coordinates in the video display area. The video display area shows the entire chip, and the mouse click event refers to clicking on the target solder ball position on the chip.

[0060] Understandably, the entire chip is displayed on the screen's video display area, including the location of each solder ball (pin) and the network connections of the pins. The process involves detecting physical defects in the solder balls. When a defective solder ball is detected, the user clicks on its location with the mouse to obtain its screen pixel coordinates.

[0061] It should be noted that before step 1, the standard chip design files (such as pin distribution diagrams containing pin coordinates, netlist files describing circuit connections, etc.) are converted into a queryable structured database.

[0062] The chip standard design file includes two types of standard files: ① Pin distribution diagram file, in CSV format, which records the correspondence between the physical coordinates of each solder ball and the pin name; ② Network connection table file, in JSON format, which records the signal network to which each pin belongs, the network electrical attributes, and a list of all pins in the network.

[0063] Based on two types of standard files for the chip, two key data structures are constructed in computer storage: ① Coordinate-Pin Lookup Table: Using the design physical coordinates as the key and the pin name as the value, implemented using a KD-tree, supporting millisecond-level or nearest-neighbor queries by coordinates. ② Pin-Network Relationship Table: Using the pin name as the key and the pin's network relationship information as the value, it allows for quick retrieval of the signal network to which a pin belongs, its electrical attributes, and other pin members within the same network.

[0064] And to establish a precise mathematical correspondence between the microscope video pixel coordinate system (two-dimensional screen coordinates) and the chip design physical coordinate system, that is, the affine transformation matrix M from the screen pixel coordinates to the design physical coordinates.

[0065] During the acquisition of the affine transformation matrix M, the user, in calibration mode, provides at least two sets (four sets recommended) of known correspondences, namely: the set of screen pixel coordinates P obtained by clicking on solder balls with certain characteristics (such as the four corner solder balls) in the video frame, as shown in the figure. Figure 2 Each time the correct pin name is selected, the design physical coordinate set D of each solder ball is retrieved from the design information database.

[0066] The screen pixel coordinates and design physical coordinates of each solder ball are treated as a coordinate pair. A two-dimensional affine transformation model is used to describe the coordinate transformation relationship between the screen pixel coordinates and the design physical coordinates. Using the least squares method, the optimal affine transformation matrix M (including rotation, scaling, and translation parameters) is solved based on multiple sets of (P, D) corresponding coordinate pairs. This algorithm ensures that globally optimal mapping accuracy can still be obtained even with slight click errors.

[0067] The two-dimensional affine transformation model is expressed as follows: Let the screen pixel coordinates be (u, v), the physical coordinates be (x, y), and the affine transformation matrix be M.

[0068] ;

[0069] ;

[0070] Calibration process: Users only need to click on any two (diagonal) or four feature spheres in the field of view to calculate the six parameters a, b, c, d, e, and f using the least squares method, forming an affine transformation matrix M to achieve overall mapping of translation, rotation, and scaling.

[0071] Step 2: Based on the affine transformation matrix M, convert the screen pixel coordinates of the target tin ball into the design physical coordinates.

[0072] Understandably, when the user's mouse click event in the video display area and the screen pixel coordinates of the target solder ball are listened to and captured, the screen pixel coordinates (u, v) of the target solder ball are instantly converted into the design physical coordinates (x, y) through the affine transformation matrix M.

[0073] .

[0074] Step 3: Based on the physical coordinates of the target solder ball, retrieve the logic information of the chip design information database to obtain the logic information of the target solder ball. The logic information of the target solder ball includes the pin name corresponding to the target solder ball and the network relationship information of the target solder ball. The network relationship information of the target solder ball includes the signal network to which the target solder ball belongs, the network electrical attributes, and the global network pin member list.

[0075] Understandably, the physical coordinates (x, y) of the target solder ball are input into the design information database. In the coordinate-pin lookup table of the design information database, a fast search is performed using nearest neighbor retrieval technology to return the corresponding pin name. Subsequently, using this pin name as the key, a lookup is performed in the pin-network relationship table to return complete signal network names, electrical attributes, and a global network member list, among other network relationship information. Finally, the pin name and network relationship information corresponding to the target solder ball are encapsulated into a structured logical information package.

[0076] After obtaining the logic information packet of the target solder ball, the logic information packet is visualized as graphics and text on the screen, and an annotation interface is provided.

[0077] Specifically, in an independent graphics layer (such as using a graphics interface), a semi-transparent information box is dynamically drawn near the screen click position (i.e., the target solder ball position) on the original video frame. The rendering core association result includes the pin name and signal network name of the target solder ball, such as "C1: DDR_DQ

[31] ", where C1 represents the pin name corresponding to the target solder ball, and DDR_DQ

[31] represents the signal network name corresponding to the target solder ball. In addition, in the global thumbnail navigation window of the chip, all pin positions contained in the global network member list in the logic information packet of the target solder ball are highlighted to intuitively present the signal path of the target solder ball. See Figure 3 .

[0078] It should be noted that the method provided by this invention is not limited to the automatic mapping of solder ball screen pixel coordinates to logic information, but can also include other "feature structures" on the chip package that have a positional-logical correspondence (such as pads and thermal bumps). Furthermore, "design data" is not limited to pinout diagrams and netlists, but can also encompass chip layout files, test vectors, etc. Anything that can provide positional-functional correlation information can be considered an equivalent replacement.

[0079] See Figure 4 The present invention also provides a logic information acquisition system for chip solder balls, the system comprising:

[0080] The monitoring module 401 is used to monitor and capture the user's mouse click events and screen pixel coordinates in the video display area. The video display area displays the entire chip, and the mouse click event refers to clicking on the target solder ball position on the chip.

[0081] The conversion module 402 is used to convert the screen pixel coordinates of the target solder ball into the design physical coordinates based on the affine transformation matrix M.

[0082] The retrieval module 403 is used to retrieve the logic information of the target solder ball from the chip design information database based on the design physical coordinates of the target solder ball. The logic information of the target solder ball includes the pin name corresponding to the target solder ball and the network relationship information of the target solder ball. The network relationship information of the target solder ball includes the signal network to which the target solder ball belongs, the network electrical attributes, and the global network pin member list.

[0083] Among them, see Figure 5 The diagram shows the overall architecture of a logic information acquisition system for chip solder balls. This system architecture mainly includes a design data interface module 404, a coordinate mapping and calibration module 405, an information association and query engine 406, and an augmented reality information overlay module 407.

[0084] The design data interface module 404 is primarily responsible for importing and parsing standard chip design files (such as pinout diagrams containing pin coordinates, netlist files describing circuit connections, etc.), and converting them into a structured design information database that can be queried within the system. For details on how to construct the chip's design information database, please refer to the preceding text.

[0085] The coordinate mapping and calibration module 405 is primarily responsible for establishing the precise mathematical correspondence between the microscope video pixel coordinate system (two-dimensional screen coordinates) and the chip design physical coordinate system, i.e., the affine transformation matrix M. The specific method for calculating the affine transformation matrix M can be found above.

[0086] The information association and query engine 406 includes a monitoring module 401, a conversion module 402, and a retrieval module 403. It is mainly responsible for automatically associating the logical information of the target solder ball with the target solder ball through the design information database based on the screen pixel coordinates of the target solder ball on the video frame.

[0087] The augmented reality information overlay module 407 is mainly responsible for overlaying the logic information of the target solder ball onto the chip in the video display area. This mainly includes overlay display and visual extension display. Specifically, the overlay display involves dynamically drawing a semi-transparent information box near a screen click on the original video frame in an independent graphics layer (e.g., using a graphics interface). This box renders the core association results, including the pin names and signal network names corresponding to the target solder ball.

[0088] Visualization Extension: In the global thumbnail navigation window, all pin positions contained in the global network member list of the target solder ball's logic information packet are highlighted, visually presenting the signal path of the target solder ball.

[0089] Please see Figure 6 , Figure 6 This is a schematic diagram illustrating an embodiment of the electronic device provided in this invention. For example... Figure 6 As shown, an embodiment of the present invention provides an electronic device, including a memory 610, a processor 620, and a computer program 611 stored in the memory 610 and executable on the processor 620. When the processor 620 executes the computer program 611, it implements the steps of the above-described method for obtaining the logic information of the chip solder balls.

[0090] Please see Figure 7 , Figure 7 This is a schematic diagram illustrating an embodiment of a computer-readable storage medium provided by the present invention. (See diagram below.) Figure 7 As shown, this embodiment provides a computer-readable storage medium 700, on which a computer program 711 is stored. When the computer program 711 is executed by a processor, it implements the steps of the above-described method for obtaining the logic information of the chip solder balls.

[0091] The present invention provides a method and system for obtaining logic information of chip solder balls, which has the following advantages: (1) Regarding "low efficiency and easy to make mistakes": Since the entire process of manual counting and cross-tool query is compressed into a "click-view" action, the operation efficiency is greatly improved and the errors that may be introduced by manual counting and searching are completely avoided.

[0092] (2) Addressing the problem of “information fragmentation and difficulty in analysis”: Because physical defects are presented in real time and automatically with the complete design context (network, module) at the testing site, analysts can immediately understand the potential circuit impact of defects, upgrading the testing tool to a basic analysis assistant and opening up the link from observation to analysis.

[0093] It should be noted that the descriptions of each embodiment in the above embodiments have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0094] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0095] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0096] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0097] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0098] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0099] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A method for obtaining logic information of chip solder balls, characterized in that, include: Listen for and capture user mouse click events and screen pixel coordinates in the video display area, where the video display area shows the entire chip, and the mouse click event refers to clicking on a target solder ball on the chip; By clicking on multiple solder balls in the video frame with the mouse, the screen pixel coordinates of each solder ball can be obtained, forming a set of screen pixel coordinates for multiple solder balls; Based on the pin name of each click location, the corresponding physical coordinates of the design are retrieved from the chip design information database to form a set of physical coordinates of multiple solder balls. Based on the screen pixel coordinates and design physical coordinates of multiple solder balls, a two-dimensional affine transformation model is used to describe the transformation relationship between the screen pixel coordinates and the design physical coordinates, and the affine transformation matrix M from the screen pixel coordinates to the design physical coordinates is obtained. Based on the affine transformation matrix M, the screen pixel coordinates of the target tin ball are converted into the design physical coordinates; Obtain the chip standard design file, which includes a pinout diagram file and a network connection table file. The pinout diagram file records the correspondence between the physical coordinates of each solder ball and the pin name, and the network connection table file records the network relationship information of each pin. The pin distribution diagram file and the network connection table file are parsed to construct a coordinate-pin lookup table and a pin-network relationship lookup table, which together constitute a chip design information database. Based on the physical coordinates of the target solder ball, the chip design information database is searched to obtain the logic information of the target solder ball. The logic information of the target solder ball includes the pin name corresponding to the target solder ball and the network relationship information of the target solder ball. The network relationship information of the target solder ball includes the signal network to which the target solder ball belongs, the network electrical attributes, and the global network pin member list.

2. The method for obtaining logic information of chip solder balls according to claim 1, characterized in that, The network relationship information includes the signal network to which the pin belongs, the network electrical attributes, and a global list of network pin members. The coordinate-pin lookup table is constructed using the pin design physical coordinates as keys and the pin names as values, and a KD tree is used to construct the pin-pin lookup table. The pin-network relationship lookup table is constructed using the pin names as keys and network relationship information as values. The network relationship information includes the signal network, network electrical attributes, and a list of all pins in the same network as values.

3. The method for obtaining logic information of chip solder balls according to claim 1, characterized in that, The screen pixel coordinates and design physical coordinates of the multiple solder balls are described using a two-dimensional affine transformation model, which includes: The screen pixel coordinates and design physical coordinates of each solder ball are treated as a coordinate pair. Based on multiple coordinate pairs, the optimal affine transformation matrix M is solved using the least squares method.

4. The method for obtaining logic information of chip solder balls according to claim 1, characterized in that, The process of converting the screen pixel coordinates of the target solder ball into design physical coordinates based on the affine transformation matrix M includes: ； Where (u, v) represents the screen pixel coordinates of the target solder ball, and (x, y) is the design physical coordinates of the target solder ball.

5. The method for obtaining logic information of chip solder balls according to claim 1, characterized in that, The step involves retrieving the target solder ball's logic information from a chip design information database based on its physical coordinates, including: Based on the design physical coordinates of the target solder ball, the pin name of the target solder ball is retrieved from the coordinate-pin lookup table; Based on the pin name of the target solder ball, the network relationship information of the target solder ball is found in the pin-network relationship lookup table; The pin names and network relationship information of the target solder ball constitute the logical information of the target solder ball.

6. The method for obtaining logic information of chip solder balls according to claim 1, characterized in that, The step of retrieving the logic information of the target solder ball from the chip design information database based on the design physical coordinates of the target solder ball, and then further includes: Draw a semi-transparent information box near the mouse click position in the video display area as an independent graphics layer, and render the pin name and signal network name of the target solder ball in the graphics layer; In the chip's global thumbnail navigation window, all pin positions contained in the global network pin member list in the target solder ball's network relationship information are highlighted to present the signal path of the target solder ball.

7. A logic information acquisition system for chip solder balls, characterized in that, include: The monitoring module is used to monitor and capture user mouse click events and screen pixel coordinates in the video display area. The video display area shows the entire chip, and the mouse click event refers to clicking on the target solder ball position on the chip. The coordinate mapping and calibration module is used to obtain the screen pixel coordinates of each solder ball by clicking on multiple solder balls in the video screen with the mouse, thus forming a set of screen pixel coordinates for multiple solder balls; Based on the pin name of each click location, the corresponding physical coordinates of the design are retrieved from the chip design information database to form a set of physical coordinates of multiple solder balls. Based on the screen pixel coordinates and physical coordinates of multiple solder balls, a two-dimensional affine transformation model is used to describe the transformation relationship between the screen pixel coordinates and the physical coordinates of the design, and the affine transformation matrix M from the screen pixel coordinates to the physical coordinates of the design is obtained. The transformation module is used to convert the screen pixel coordinates of the target tin ball into the design physical coordinates based on the affine transformation matrix M. The design data interface module is used to acquire standard chip design files, which include pinout diagram files and network connection table files. The pinout diagram files record the correspondence between the physical coordinates of each solder ball and the pin name, and the network connection table files record the network relationship information of each pin. The pinout diagram files and the network connection table files are parsed to construct coordinate-pin lookup tables and pin-network relationship lookup tables, which constitute a chip design information database. The retrieval module is used to retrieve the logic information of the target solder ball from the chip design information database based on the design physical coordinates of the target solder ball. The logic information of the target solder ball includes the pin name corresponding to the target solder ball and the network relationship information of the target solder ball. The network relationship information of the target solder ball includes the signal network to which the target solder ball belongs, the network electrical attributes, and the global network pin member list.

8. An electronic device, characterized in that, The device includes a memory and a processor, wherein the processor is used to execute computer management programs stored in the memory to implement the steps of the method for obtaining logical information of chip solder balls as described in any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, It stores a computer management program, which, when executed by a processor, implements the steps of the method for obtaining logic information of chip solder balls as described in any one of claims 1-6.

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