FeRAM-based parallel controller IP core system

Abstract

The invention discloses a system for parallel controller IP cores based on a FeRAM, relates to the technical field of controllers, and solves the technical problems that an existing FeRAM chip is limited in a data large-capacity storage scene, and the write-in error probability of data is caused by material fatigue failure and data transmission delay. The system comprises an AXI4-Full interface module, an AXI4-Lite interface module, an address mapping and data processing module, a controller configuration module, a read-write instruction control module, an error detection and correction module and a FeRAM driving module. The reliability and the efficiency of data transmission are ensured through an internal hierarchical interconnection mode of each functional module interface.

Description

Technical Field

[0001] This invention belongs to the field of controllers and relates to parallel controller IP core technology, specifically a system based on a FeRAM-based parallel controller IP core. Background Technology

[0002] With the rapid development of emerging fields such as communications, the Internet of Things, and autonomous driving, there is an urgent need to develop storage technologies that combine high read / write speeds, low power consumption, high durability, and non-volatility. FeRAM stores data based on the polarization reversal properties of ferroelectric materials, combining non-volatility and random access characteristics. Data is not lost after power failure, and it has nanosecond-level read / write speeds. FeRAM has write durability, which can be considered as an infinite number of write cycles. FeRAM has extremely low power consumption and does not require additional charge pump circuits. In battery-powered devices, it can significantly extend battery life and reduce heat generation. It is widely used in industrial automation, automotive electronic systems, smart grids, and other fields.

[0003] In existing FeRAM chips, the read / write process combines capacitive charge detection and electric field driving mechanisms. Under the driving force of the electric field, the central atom can move to two stable polarization states, corresponding to writing "1" and "0" respectively. Its polarization state can still be maintained after the electric field is removed, thus achieving non-volatility. When reading, an electric field is applied. If the atom position is in the same direction as the electric field, a small displacement current is generated; otherwise, the atom crosses the energy barrier and reverses polarization, generating a significant transient current. High-speed read / write operations can be achieved. However, the maximum capacity of existing FeRAM chips is limited to the Mb level, and the peak bandwidth of data access is also limited to below GB / s, which limits its application in large-capacity data storage scenarios. Furthermore, since the 1T1C structure of FeRAM chips is destructive readout, data needs to be rewritten each time it is read, which increases the probability of data writing errors caused by material fatigue failure and data transmission delay.

[0004] This invention provides a system based on a FeRAM-based parallel controller IP core to solve the above-mentioned technical problems. Summary of the Invention

[0005] This invention aims to solve at least one of the technical problems existing in the prior art; to this end, this invention proposes a system based on a FeRAM-based parallel controller IP core to solve two aspects of the technical problems: (1) The maximum capacity of existing FeRAM chips is limited to the Mb level, and the peak bandwidth for data access is also limited to below GB / s, which limits their application in large-capacity data storage scenarios; (2) Since the 1T1C structure of the FeRAM chip is destructive readout, the data needs to be rewritten each time it is read, which increases the probability of data writing errors caused by material fatigue failure and data transmission delay.

[0006] To achieve the above objectives, a first aspect of the present invention provides a system based on a FeRAM-based parallel controller IP core, comprising: an AXI4-Full interface module, an AXI4-Lite interface module, a controller configuration module, an address mapping and data processing module, an error detection and correction module, a read / write instruction control module, and a FeRAM driver module; The AXI4-Full interface module is responsible for controlling high-speed data exchange between the IP core and external systems; it integrates two data buffers, which are used for temporary storage of read and write data respectively. The AXI4-Lite interface module is responsible for the configuration management and status monitoring of the controller IP core; The controller configuration module is used to distribute the configuration parameters of the controller IP core during runtime to each functional module and to monitor the working status of each functional module. The address mapping and data processing module is responsible for the mapping and conversion between the AXI4-Full bus address space and the physical FeRAM address space, as well as the reorganization and distribution of read and write data. The error detection and correction module is responsible for monitoring abnormal situations during the data transmission process of the controller IP core. The read / write instruction control module is responsible for scheduling and controlling the controller IP core data access instructions; The FeRAM driver module is used to control and access the FeRAM chip that controls the IP core.

[0007] Preferably, the write operation of the AXI4-Full interface module includes: External write addresses and write data enter the AXI4-Full protocol processing submodule through the AXI4-Full bus handshake protocol; The AXI4-Full protocol processing submodule receives and latches the AXI4-Full write address sent from the outside, and generates a write request signal; it then outputs the write request signal to the read / write instruction control module. After the AXI4-Full protocol processing submodule finishes receiving external write data, it writes the write data into the write BUFFER module instantiated by the dual-port BUFFER submodule.

[0008] Preferably, the read operation of the AXI4-Full interface module includes: The external read address enters the AXI4-Full protocol processing submodule through the AXI4-Full bus handshake protocol; the AXI4-Full protocol processing submodule receives and latches the AXI4-Full read address sent from the outside, and generates a read request signal; The read request signal is input to the read / write instruction control module. After the IP core reads data from the FeRAM chip, the read data processed by the address mapping and data processing module is written into the read BUFFER module instantiated by the dual-port BUFFER submodule. The AXI4-Full protocol processing submodule manages the read operation latency using a read latency counter through a read latency management mechanism. When the data read bandwidth of the FeRAM chip matches the read data bandwidth of the AXI4-Full bus, the data in the read BUFFER module is read out sequentially and transmitted to the outside through the AXI4-Full bus.

[0009] Preferably, the AXI4-Full protocol processing submodule is further provided with a page mode working status detection function, which uses an internally configured register to record the page mode working status of the current AXI4-Full interface module in read / write mode; and outputs the value of the register to the controller configuration module.

[0010] Preferably, the dual-port BUFFER submodule is also used to support parameterizable pipeline design; when the number of pipeline stages is 0, the data temporarily stored in the BUFFER is directly output to the multi-stage pipeline read logic; The dual-port BUFFER submodule also has an optional byte write function; when the byte write is pulled high, the BUFFER is allowed to update a portion of the data. The dual-port BUFFER submodule also has a configurable BUFFER frame length. The external system writes the configured BUFFER effective frame length value to the corresponding configuration register through the AXI4-Lite interface module, and distributes the value of the register to the dual-port BUFFER submodule through the controller configuration module to configure the corresponding read / write BUFFER frame length.

[0011] Preferably, the AXI4-Lite interface module is also used to maintain a set of configuration registers and status registers; wherein, the configuration registers are used to support runtime parameter adjustment, transmission control, and user soft reset functions; and the status registers are used to support runtime status queries. The AXI4-Lite interface module also has an access protection mechanism that checks the validity of external system access addresses; these external system access addresses include external write addresses and external read addresses.

[0012] Preferably, the write operation of the AXI4-Lite interface module includes: External write addresses and write data enter the AXI4-Lite interface module through the AXI4-Lite bus handshake protocol; the AXI4-Lite interface module is used to check the validity of the external write address; Once the validity check of the external write address passes, the AXI4-Lite interface module updates the write data to the corresponding configuration register based on the external write address; and outputs the corresponding configuration command to the controller configuration module.

[0013] Preferably, the read operation of the AXI4-Lite interface module includes: External read addresses are accessed via the AXI4-Lite interface module through the AXI4-Lite bus handshake protocol; the validity of the external read address is checked using the AXI4-Lite interface module. Once the external read address passes the validity check, the AXI4-Lite interface module transmits the value of the corresponding register in the status register to the external system based on the read address.

[0014] Preferably, the controller configuration module is further configured to receive configuration instructions from the AXI4-Lite interface module, and after the validity of the parameters of the configuration instructions is verified, the configuration instructions are distributed to the corresponding functional modules. The controller configuration module is also used to receive status signals from the remaining functional modules other than the AXI4-Lite interface module, and input the status signals into the status register of the AXI4-Lite interface module.

[0015] Preferably, the address mapping and data processing module adopts a striped data distribution strategy. When the default configuration is selected during the instantiation of the top-level module, the address mapping and data processing module divides the 64-bit AXI4-Full data into four 16-bit data block stripes, and uses the error checking and correction module to generate two 16-bit misalignment check data block stripes; and maps the misalignment check data block stripes to different FeRAM chipsets respectively.

[0016] Preferably, the address mapping with the read / write operation address mapping of the data processing module includes: The address mapping and data processing module receives and latches valid read / write requests and read / write information from the read / write instruction control module. Each time an AXI4-Full data frame burst write is completed, the write address is incremented by 1 bit until the increment reaches the burst length. The write information includes the write address and the write burst length; the read information includes the read address and the read burst length; the burst length indicates the number of AXI4-Full data words read / written in this operation. The read / write operation address calculation is as follows: when the address mapping and data processing module responds to a valid read / write request from the read / write instruction control module, the read / write BUFFER address starts from 0 and increments according to the sequential addressing strategy based on different FeRAM chip data I / O bit width modes. The FeRAM chip address starts from the base address. When the falling edge of the channel ready signal of the FeRAM driver module is detected, the FeRAM chip address increments and the burst length counter decrements until the burst transmission is completed. The write operation data processing module reads 64-bit AXI4-Full data sequentially from the write BUFFER, divides the data into four 16-bit data blocks according to the address [4:3] bits in little-endian order, and calculates two 16-bit error check data blocks according to the ECC algorithm; finally, it uses a multi-channel parallel model to write the data into different FeRAM chipsets. The read operation data processing module reads data in parallel from 6 FeRAM channels, calculates the stripe rotation position based on the current FeRAM address, and dynamically determines the position of the parity check data stripe and the Galois domain parity data stripe in the stripe; and reassembles the read 96-bit striped data into a 64-bit AXI4-Full data word and two 16-bit parity data blocks.

[0017] Preferably, the error detection and correction module adopts a dual detection and correction mechanism based on parity check and Galois domain check, and implements the ECC scheme through independent disk redundant array configuration; During the write operation data processing phase, the error detection and correction module simultaneously reads 64-bit AXI4-Full data from the address mapping and data processing module and performs real-time RAID6 P+Q double parity calculation. Based on the current FeRAM address, it calculates the stripe rotation position and dynamically determines the storage locations of P and Q parities in the six FeRAM channels. Depending on the FeRAM chip's data I / O bit width mode, it calculates the corresponding P and Q parity values ​​for different bit widths. When a falling edge of the channel ready signal from the FeRAM driver module is detected, the write BUFFER address and FeRAM address increment synchronously, while the burst length counter decrements until the burst transmission is complete. Here, P parity is parity checking, and Q parity is Galois domain parity checking. During the read operation data processing phase, the error detection and correction module reads data in parallel from six FeRAM chipset channels. It calculates the stripe rotation position based on the current FeRAM address, dynamically determines the positions of P-parity and Q-parity checks within the stripe, and finally reassembles the read 96-bit stripe data into a 64-bit AXI4-Full data word and two 16-bit parity data words. It verifies data integrity by calculating the P-parity and Q-parity values ​​of the read data in real time and comparing them with the stored parity values. When a single-bit error is detected, the error location is precisely located and automatically corrected using P+Q parity check and Galois field check methods. When at most two FeRAM chipset failures occur, a stripe-by-strip data reconstruction algorithm is initiated to recover the correct data using P+Q parity check and Galois field check methods.

[0018] Preferably, the dual detection and correction mechanism based on parity check and Galois field check includes: The formula for calculating the parity check is as follows: ;in, Represents the XOR operation; , , , For data striping; The Galois field verification is based on mathematical operations using the finite field GF(2^8). In the primitive polynomial of GF(2^8), if... If the data exceeds the threshold boundary, the remainder will be taken; the primitive polynomial used is of type 0x11D, that is: ; The formula for calculating the Galois domain verification is as follows: Where g0=1, g1=2, g2=4, g3=8 are the constant coefficients corresponding to different data stripes.

[0019] Preferably, the read / write instruction control module is used to connect the address mapping and data processing module and the FeRAM driver module; to realize read / write mode switching through read / write request arbitration and processing mechanism; and to control page mode access; While the address mapping and data processing module is processing the current read / write operation, the read / write instruction control module arbitrates and latches subsequent new read / write requests from the AXI4-Full interface module; it caches read / write requests using the _lock signal and controls the timing of request validity using the _valid signal; finally, it performs an AND operation on the _lock signal of the read / write request.

[0020] Preferably, the FeRAM driver module manages the generation timing of all FeRAM chip control signals in a unified manner based on a 6-state state machine architecture and the timing signals input by the read / write instruction control module; it adopts a bidirectional data path control mechanism and supports multiple FeRAM data I / O bit width modes and chip specification configurations through intelligent parameterized design.

[0021] Compared with the prior art, the beneficial effects of the present invention are: 1. This invention divides the AXI4-Full data block into stripes and generates parity data stripes, which are then written in parallel into multiple FeRAM chipsets, thereby incrementally solving the capacity and bandwidth bottleneck problem of a single FeRAM chip. The AXI4-Full bus address space and the FeRAM chip physical address space are converted through a carefully designed address mapping scheme to ensure that the data is evenly distributed in multiple FeRAM groups, thereby achieving parallel access and improving the overall system capacity and bandwidth utilization.

[0022] 2. This invention employs a diversified parameter design strategy based on a hierarchical configuration architecture, including two levels: static compile-time parameters and dynamic runtime parameters. Static compile-time parameters are implemented through the Verilog parameter definition mechanism and are primarily used to determine the system's basic architecture and hardware resource allocation. Dynamic runtime parameters are implemented through configuration registers, supporting dynamic adjustments during system operation. It also utilizes a dual-redundancy error protection ECC scheme based on RAID 6 P+Q. This invention innovatively uses the RAID 6 P+Q scheme as the ECC scheme for the controller IP core for error detection and correction of the FeRAM chipset. Combined with parity checking (P-check) and Galois domain checking (Q-check), it achieves dual fault tolerance, enabling real-time detection and correction of single-bit errors. Even in the event of a dual-chip failure, it can still reconstruct the original data through distributed check data. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a top-level module architecture diagram of the present invention; Figure 2 This is a functional schematic diagram of the AXI4-Full interface module of the present invention; Figure 3 This is a functional schematic diagram of the AXI4-Lite interface module of the present invention; Figure 4This is a functional schematic diagram of the controller configuration module of the present invention; Figure 5 This is a schematic diagram illustrating the address mapping principle of the read / write operation of the address mapping and data processing module of the present invention. Figure 6 This is a schematic diagram illustrating the write operation data processing principle of the address mapping and data processing module of the present invention. Figure 7 This is a schematic diagram illustrating the read operation data processing principle of the address mapping and data processing module of the present invention. Figure 8 This is a functional schematic diagram of the error detection and correction module of the present invention; Figure 9 This is a functional schematic diagram of the read / write instruction control module of the present invention; Figure 10 This is a functional schematic diagram of the FeRAM driver module of the present invention. Detailed Implementation

[0025] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] Please see Figure 1 The first aspect of the present invention provides a system based on a FeRAM-based parallel controller IP core, comprising: an AXI4-Full interface module, an AXI4-Lite interface module, a controller configuration module, an address mapping and data processing module, an error detection and correction module, a read / write instruction control module, and a FeRAM driver module; The AXI4-Full interface module is responsible for controlling high-speed data exchange between the IP core and external systems; it integrates two data buffers, which are used for temporary storage of read and write data respectively. The AXI4-Lite interface module is responsible for the configuration management and status monitoring of the controller IP core; The controller configuration module is used to distribute the configuration parameters of the controller IP core during runtime to each functional module and to monitor the working status of each functional module. The address mapping and data processing module is responsible for the mapping and conversion between the AXI4-Full bus address space and the physical FeRAM address space, as well as the reorganization and distribution of read and write data. The error detection and correction module is responsible for monitoring abnormal situations during the data transmission process of the controller IP core. The read / write instruction control module is responsible for scheduling and controlling the controller IP core data access instructions; The FeRAM driver module is used to control and access the FeRAM chip that controls the IP core.

[0027] It should be noted that the global parameter definitions of the top-level module of the FeRAM parallel controller IP core system are shown in the following table:

[0028] Table 1 Global Parameter Definitions for Top-Level Modules

[0029] The digital interface definition of the top-level module of the FeRAM parallel controller IP core system is shown in the table below:

[0030] Table 2 Definition of Digital Interface for Top-Level Modules

[0031] Please see Figure 2 The AXI4-Full interface module is responsible for controlling high-speed data exchange between the IP core and external systems. It integrates two data buffers, which are used for temporary storage of read and write data. The write data buffer receives the data stream from the AXI4-Full bus and supports burst transmission mode. The read data buffer pre-buffers the data to be sent and responds to read requests from the AXI4-Full bus.

[0032] This invention solves the bandwidth matching problem between the AXI4-Full high-speed interface and asynchronous access of the FeRAM chip through a dual-buffer design, thereby improving data transmission efficiency.

[0033] For write operations of the AXI4-Full interface module, the external write address and write data enter the AXI4-Full protocol processing submodule through the AXI4-Full bus handshake protocol; the AXI4-Full protocol processing submodule receives and latches the external AXI4-Full write address and generates a write request signal; it outputs the write request signal to the read / write instruction control module; after the AXI4-Full protocol processing submodule has received the external write data, it writes the write data into the write BUFFER module instantiated by the dual-port BUFFER submodule.

[0034] For read operations of the AXI4-Full interface module, the external read address enters the AXI4-Full protocol processing submodule through the AXI4-Full bus handshake protocol. The AXI4-Full protocol processing submodule receives and latches the AXI4-Full read address sent from the outside and generates a read request signal. The read request signal is input to the read / write instruction control module. After the IP core reads data from the FeRAM chip, the address mapping and data processing module-processed read data are written into the read BUFFER module instantiated by the dual-port BUFFER submodule. The AXI4-Full protocol processing submodule manages the read operation delay through a read delay management mechanism using a read delay counter. When the data read bandwidth of the FeRAM chip matches the read data bandwidth of the AXI4-Full bus, the data in the read BUFFER module is read out sequentially and transmitted to the outside through the AXI4-Full bus.

[0035] The AXI4-Full protocol processing submodule also has a page mode operating status detection function, which uses internally configured registers to record the page mode operating status of the current AXI4-Full interface module in read / write mode; and outputs the value of the registers to the controller configuration module.

[0036] The dual-port BUFFER submodule also supports parameterized pipeline design; when the pipeline stage number is 0, the data temporarily stored in the BUFFER is directly output to the multi-stage pipeline read logic; the dual-port BUFFER submodule also has an optional byte write function; when the byte is written, it can be pulled high, allowing the BUFFER to update part of the data bytes; the dual-port BUFFER submodule also has a configurable BUFFER frame length. The external system writes the configured BUFFER effective frame length value to the corresponding configuration register through the AXI4-Lite interface module, and distributes the value of the register to the dual-port BUFFER submodule through the controller configuration module to configure the corresponding read / write BUFFER frame length.

[0037] Please see Figure 3 The AXI4-Lite interface module is responsible for the configuration management and status monitoring of the controller IP core. The AXI4-Lite interface module is also used to maintain a set of configuration registers and status registers. The AXI4-Lite interface module also has an access protection mechanism to check the validity of external system access addresses.

[0038] The configuration register is used to support runtime parameter adjustment, transmission control, and user soft reset functions; the status register is used to support runtime status queries; and the external system access addresses include external write addresses and external read addresses.

[0039] It should be noted that the AXI4-Lite interface module uses a simplified version of the AXI4 protocol, which reduces the complexity of the interface; by checking the validity of the external system access address, it ensures that the address is within the valid range, thereby guaranteeing the security of access operations.

[0040] The relevant register definitions maintained by the AXI4-Lite interface module are shown in the table below:

[0041] Table 3 Definitions of Register-Related Data

[0042] For write operations of the AXI4-Lite interface module, the external write address and write data enter the AXI4-Lite interface module through the AXI4-Lite bus handshake protocol; the AXI4-Lite interface module checks the validity of the external write address; when the validity check of the external write address passes, the AXI4-Lite interface module updates the write data to the corresponding configuration register according to the external write address; and outputs the corresponding configuration command to the controller configuration module.

[0043] For read operations of the AXI4-Lite interface module, the external read address is communicated to the AXI4-Lite interface module through the handshake protocol of the AXI4-Lite bus; the AXI4-Lite interface module checks the validity of the external read address; when the external read address passes the validity check, the AXI4-Lite interface module transmits the value of the corresponding register in the status register to the external system according to the read address.

[0044] Please see Figure 4 The controller configuration module is used to distribute the configuration parameters of the controller IP core to each functional module and monitor the working status of each functional module. The controller configuration module is also used to receive configuration instructions from the AXI4-Lite interface module. When the validity of the parameters of the configuration instruction is verified, the configuration instruction is distributed to the corresponding functional module. The controller configuration module is also used to receive the status signals of the remaining functional modules other than the AXI4-Lite interface module and input the status signals into the status register of the AXI4-Lite interface module.

[0045] Please see Figure 5 The address mapping and data processing module is responsible for mapping and converting the AXI4-Full bus address space to the physical FeRAM address space, as well as reassembling and distributing read and write data; and supports 16 / 8-bit FeRAM chip data I / O bit width and 6 / 12 / 18 / 24 FeRAM chip specifications.

[0046] The address mapping and data processing module adopts a striped data distribution strategy. When the default configuration is selected during the instantiation of the top-level module, the address mapping and data processing module divides the 64-bit AXI4-Full data into four 16-bit data block stripes and uses the error checking and correction module to generate two 16-bit misalignment check data block stripes. The misalignment check data block stripes are then mapped to different FeRAM chipsets.

[0047] It should be noted that the address mapping algorithm designed in the address mapping and data processing module ensures that data is evenly distributed across multiple FeRAM chips, thereby enabling parallel access and improving the overall system capacity and bandwidth utilization.

[0048] For read / write operation address mapping, the address mapping and data processing module receives and latches valid read / write requests and read / write information from the read / write instruction control module; each time an AXI4-Full data frame burst write is completed, the write address is incremented by 1 bit until the increment reaches the burst length; the write information includes the write address and the write burst length; the read information includes the read address and the read burst length; the burst length indicates the number of AXI4-Full data words read / written in this operation.

[0049] It should be noted that both read and write information are 40 bits. The write information includes the lower 32 bits of the write address and the higher 8 bits of the write burst length; the read information includes the lower 32 bits of the read address and the higher 8 bits of the read burst length. In the AXI4-Full bus, a 1-bit address offset corresponds to 1 byte of data, i.e., 8 bits. Taking a 64-bit word data frame as an example, the lower 3 bits of the address are used to align the data frame length; the 3rd and 4th address bits are used for selecting the data channel within the FeRAM chipset, including data channels A / B / C / D and parity channels E / F; the 5th and 6th bits are used for the FeRAM chip page address; and the 24th to 31st address bits are reserved.

[0050] For read / write operation address calculation, after the address mapping and data processing module responds to the valid read / write request from the read / write instruction control module, the read / write BUFFER address starts from 0 and increments according to the sequential addressing strategy based on different FeRAM chip data I / O bit width modes. The FeRAM chip address starts from the base address. When the falling edge of the channel ready signal of the FeRAM driver module is detected, the FeRAM chip address increments and the burst length counter decrements until the burst transmission is completed.

[0051] It should be noted that the address mapping and data processing module also supports adaptive processing for different FeRAM chip specifications: in 16-bit mode, the read / write BUFFER address and FeRAM address are synchronously incremented in a 1:1 ratio; in 8-bit mode, a 2:1 mapping strategy is adopted, that is, each AXI4-Full data word is transmitted twice, and the read / write BUFFER address is incremented once every two clock cycles, thereby achieving the optimal data transmission efficiency under different FeRAM chip specifications.

[0052] Please see Figure 6 For write operation data processing, the address mapping and data processing module reads 64-bit AXI4-Full data sequentially from the write BUFFER, divides the data into four 16-bit data blocks according to the address [4:3] bits in little-endian order, and calculates two 16-bit error check data blocks according to the ECC algorithm; finally, a multi-channel parallel model is used to write the data into different FeRAM chipsets.

[0053] Please see Figure 7 For read operation data processing, the address mapping and data processing module reads data in parallel from 6 FeRAM channels, calculates the stripe rotation position based on the current FeRAM address, and dynamically determines the position of the parity data stripe and the Galois field parity data stripe in the stripe; and reassembles the read 96-bit striped data into a 64-bit AXI4-Full data word and two 16-bit parity data blocks.

[0054] Please see Figure 8 The error detection and correction module is responsible for monitoring abnormal situations during the data transmission process of the controller IP core; it adopts a dual detection and correction mechanism based on parity check and Galois domain check, and implements the ECC scheme through independent disk redundant array configuration; During the write operation data processing phase, the error detection and correction module simultaneously reads 64-bit AXI4-Full data from the address mapping and data processing module and performs real-time RAID6 P+Q double parity calculation. Based on the current FeRAM address, it calculates the stripe rotation position and dynamically determines the storage locations of P and Q parities in the six FeRAM channels. Depending on the FeRAM chip's data I / O bit width mode, it calculates the corresponding P and Q parity values ​​for different bit widths. When a falling edge of the channel ready signal from the FeRAM driver module is detected, the write BUFFER address and FeRAM address increment synchronously, while the burst length counter decrements until the burst transmission is complete. Here, P parity is parity checking, and Q parity is Galois domain parity checking. During the read operation data processing phase, the error detection and correction module reads data in parallel from six FeRAM chipset channels. It calculates the stripe rotation position based on the current FeRAM address, dynamically determines the positions of P-parity and Q-parity checks within the stripe, and finally reassembles the read 96-bit stripe data into a 64-bit AXI4-Full data word and two 16-bit parity data words. It verifies data integrity by calculating the P-parity and Q-parity values ​​of the read data in real time and comparing them with the stored parity values. When a single-bit error is detected, the error location is precisely located and automatically corrected using P+Q parity check and Galois field check methods. When at most two FeRAM chipset failures occur, a stripe-by-strip data reconstruction algorithm is initiated to recover the correct data using P+Q parity check and Galois field check methods.

[0055] Please see Figure 9 The read / write instruction control module is responsible for scheduling and controlling the controller IP core data access instructions; it connects the address mapping and data processing module with the FeRAM driver module; it implements read / write mode switching through read / write request arbitration and processing mechanisms; and it controls page mode access. While the address mapping and data processing module is processing the current read / write operation, the read / write instruction control module arbitrates and latches subsequent new read / write requests from the AXI4-Full interface module; it caches read / write requests using the _lock signal and controls the timing of request validity using the _valid signal; finally, it performs an AND operation on the _lock signal of the read / write request.

[0056] Please see Figure 10 The FeRAM driver module is used to control and access the FeRAM chip of the control IP core. The FeRAM driver module is based on a 6-state state machine architecture and the timing signals input by the read and write instruction control module to uniformly manage the generation timing of all FeRAM chip control signals. It adopts a bidirectional data path control mechanism and supports multiple FeRAM data I / O bit width modes and chip specification configurations through intelligent parameterized design.

[0057] Some of the data in the above formula are calculated by removing dimensions and taking their numerical values. The formula is the closest to the real situation obtained by software simulation of a large amount of collected data. The preset parameters and preset thresholds in the formula are set by those skilled in the art according to the actual situation or obtained through simulation of a large amount of data.

[0058] The above embodiments are only used to illustrate the technical methods of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical methods of the present invention without departing from the spirit and scope of the technical methods of the present invention.

Claims

1. A system based on a FeRAM-based parallel controller IP core, characterized in that, include: The module consists of an AXI4-Full interface module, an AXI4-Lite interface module, a controller configuration module, an address mapping and data processing module, an error detection and correction module, a read / write instruction control module, and a FeRAM driver module. The AXI4-Full interface module is responsible for controlling high-speed data exchange between the IP core and external systems; it integrates two data buffers, which are used for temporary storage of read and write data respectively. The AXI4-Lite interface module is responsible for the configuration management and status monitoring of the controller IP core; The controller configuration module is used to distribute the configuration parameters of the controller IP core during runtime to each functional module and to monitor the working status of each functional module. The address mapping and data processing module is responsible for the mapping and conversion between the AXI4-Full bus address space and the physical FeRAM address space, as well as the reorganization and distribution of read and write data. The error detection and correction module is responsible for monitoring abnormal situations during the data transmission process of the controller IP core. The read / write instruction control module is responsible for scheduling and controlling the controller IP core data access instructions; The FeRAM driver module is used to control and access the FeRAM chip that controls the IP core.

2. The system based on FeRAM parallel controller IP core according to claim 1, characterized in that, The write operation of the AXI4-Full interface module includes: External write addresses and write data enter the AXI4-Full protocol processing submodule through the AXI4-Full bus handshake protocol; The AXI4-Full protocol processing submodule receives and latches the AXI4-Full write address sent from the outside, and generates a write request signal; it then outputs the write request signal to the read / write instruction control module. After the AXI4-Full protocol processing submodule finishes receiving external write data, it writes the write data into the write BUFFER module instantiated by the dual-port BUFFER submodule.

3. The system based on FeRAM parallel controller IP core according to claim 1, characterized in that, The read operation of the AXI4-Full interface module includes: The external read address enters the AXI4-Full protocol processing submodule through the AXI4-Full bus handshake protocol; the AXI4-Full protocol processing submodule receives and latches the AXI4-Full read address sent from the outside, and generates a read request signal; The read request signal is input to the read / write instruction control module. After the IP core reads data from the FeRAM chip, the read data processed by the address mapping and data processing module is written into the read BUFFER module instantiated by the dual-port BUFFER submodule. The AXI4-Full protocol processing submodule manages the read operation latency using a read latency counter through a read latency management mechanism. When the data read bandwidth of the FeRAM chip matches the read data bandwidth of the AXI4-Full bus, the data in the read BUFFER module is read out sequentially and transmitted to the outside through the AXI4-Full bus.

4. A system based on a FeRAM-based parallel controller IP core according to claim 2 or 3, characterized in that, The AXI4-Full protocol processing submodule is also equipped with a page mode working status detection function, which uses an internally configured register to record the page mode working status of the current AXI4-Full interface module in read / write mode; and outputs the value of the register to the controller configuration module.

5. A system based on a FeRAM-based parallel controller IP core according to claim 2, characterized in that, The dual-port BUFFER submodule is also used to support parameterizable pipeline design; when the number of pipeline stages is 0, the data temporarily stored in the BUFFER is directly output to the multi-stage pipeline read logic. The dual-port BUFFER submodule also has an optional byte write function; when the byte write is pulled high, the BUFFER is allowed to update a portion of the data. The dual-port BUFFER submodule also has a configurable BUFFER frame length. The external system writes the configured BUFFER effective frame length value to the corresponding configuration register through the AXI4-Lite interface module, and distributes the value of the register to the dual-port BUFFER submodule through the controller configuration module to configure the corresponding read / write BUFFER frame length.

6. The system based on FeRAM parallel controller IP core according to claim 1, characterized in that, The AXI4-Lite interface module is also used to maintain a set of configuration registers and status registers; wherein, the configuration registers are used to support runtime parameter adjustment, transmission control, and user soft reset functions; and the status registers are used to support runtime status queries. The AXI4-Lite interface module also has an access protection mechanism that checks the validity of external system access addresses; these external system access addresses include external write addresses and external read addresses.

7. The system based on FeRAM parallel controller IP core according to claim 6, characterized in that, The write operation of the AXI4-Lite interface module includes: External write addresses and write data enter the AXI4-Lite interface module through the AXI4-Lite bus handshake protocol; the AXI4-Lite interface module is used to check the validity of the external write address; Once the validity check of the external write address passes, the AXI4-Lite interface module updates the write data to the corresponding configuration register based on the external write address; and outputs the corresponding configuration command to the controller configuration module.

8. A system based on FeRAM parallel controller IP core according to claim 6, characterized in that, The read operation of the AXI4-Lite interface module includes: The external read address is communicated with the AXI4-Lite interface module via the AXI4-Lite bus handshake protocol; the validity of the external read address is checked using the AXI4-Lite interface module. Once the external read address passes the validity check, the AXI4-Lite interface module transmits the value of the corresponding register in the status register to the external system based on the read address.

9. A system based on FeRAM parallel controller IP core according to claim 1, characterized in that, The controller configuration module is also used to receive configuration instructions from the AXI4-Lite interface module. Once the validity of the parameters of the configuration instruction is verified, the configuration instruction is distributed to the corresponding functional module. The controller configuration module is also used to receive status signals from the remaining functional modules other than the AXI4-Lite interface module, and input the status signals into the status register of the AXI4-Lite interface module.

10. A system based on a FeRAM-based parallel controller IP core according to claim 1, characterized in that, The address mapping and data processing module adopts a striped data distribution strategy. When the default configuration is selected during the instantiation of the top-level module, the address mapping and data processing module divides the 64-bit AXI4-Full data into four 16-bit data block stripes and uses the error detection and correction module to generate two 16-bit misalignment detection data block stripes. The misalignment detection data block stripes are then mapped to different FeRAM chipsets.

11. A system based on a FeRAM-based parallel controller IP core according to claim 1, characterized in that, The address mapping and the read / write operation address mapping of the data processing module include: The address mapping and data processing module receives and latches valid read / write requests and read / write information from the read / write instruction control module. Each time an AXI4-Full data frame burst write is completed, the write address is incremented by 1 bit until the increment reaches the burst length. The write information includes the write address and the write burst length; the read information includes the read address and the read burst length; the burst length indicates the number of AXI4-Full data words read / written in this operation. The read / write operation address calculation is as follows: when the address mapping and data processing module responds to a valid read / write request from the read / write instruction control module, the read / write BUFFER address starts from 0 and increments according to the sequential addressing strategy based on different FeRAM chip data I / O bit width modes. The FeRAM chip address starts from the base address. When the falling edge of the channel ready signal of the FeRAM driver module is detected, the FeRAM chip address increments and the burst length counter decrements until the burst transmission is completed. The write operation data processing module reads 64-bit AXI4-Full data sequentially from the write BUFFER, divides the data into four 16-bit data blocks according to the address [4:3] bits in little-endian order, and calculates two 16-bit error check data blocks according to the ECC algorithm; finally, it uses a multi-channel parallel model to write the data into different FeRAM chipsets. The read operation data processing module reads data in parallel from 6 FeRAM channels, calculates the stripe rotation position based on the current FeRAM address, and dynamically determines the position of the parity check data stripe and the Galois domain parity data stripe in the stripe; and reassembles the read 96-bit striped data into a 64-bit AXI4-Full data word and two 16-bit parity data blocks.

12. The system of a parallel controller IP core based on FeRAM according to claim 1, characterized in that, The error detection and correction module adopts a dual detection and correction mechanism based on parity check and Galois domain check, and implements the ECC scheme through independent disk redundant array configuration; During the write operation data processing phase, the error detection and correction module simultaneously reads 64-bit AXI4-Full data from the address mapping and data processing module and performs real-time RAID6 P+Q double parity calculation. Based on the current FeRAM address, it calculates the stripe rotation position and dynamically determines the storage locations of P and Q parities in the six FeRAM channels. Depending on the FeRAM chip's data I / O bit width mode, it calculates the corresponding P and Q parity values ​​for different bit widths. When a falling edge of the channel ready signal from the FeRAM driver module is detected, the write BUFFER address and FeRAM address increment synchronously, while the burst length counter decrements until the burst transmission is complete. Here, P parity is parity checking, and Q parity is Galois domain parity checking. During the read operation data processing phase, the error detection and correction module reads data in parallel from six FeRAM chipset channels. It calculates the stripe rotation position based on the current FeRAM address, dynamically determines the positions of P-parity and Q-parity checks within the stripe, and finally reassembles the read 96-bit stripe data into a 64-bit AXI4-Full data word and two 16-bit parity data words. It verifies data integrity by calculating the P-parity and Q-parity values ​​of the read data in real time and comparing them with the stored parity values. When a single-bit error is detected, the error location is precisely located and automatically corrected using P+Q parity check and Galois field check methods. When at most two FeRAM chipset failures occur, a stripe-by-strip data reconstruction algorithm is initiated to recover the correct data using P+Q parity check and Galois field check methods.

13. The system of a parallel controller IP core based on FeRAM according to claim 12, characterized in that, The dual detection and correction mechanism based on parity check and Galois domain check includes: The formula for calculating the parity check is as follows: ;in, This represents the XOR operation; , , , For data striping; The Galois field verification is based on mathematical operations using the finite field GF(2^8). In the primitive polynomial of GF(2^8), if... If the data exceeds the threshold boundary, the remainder will be taken; the primitive polynomial used is of type 0x11D, that is: ; The formula for calculating the Galois domain verification is as follows: Where g0=1, g1=2, g2=4, g3=8 are the constant coefficients corresponding to different data stripes.

14. The system of a parallel controller IP core based on FeRAM according to claim 1, characterized in that, The read / write instruction control module is used to connect the address mapping and data processing module with the FeRAM driver module; Read / write mode switching is achieved through read / write request arbitration and processing mechanisms; and page mode access is controlled. While the address mapping and data processing module is processing the current read / write operation, the read / write instruction control module arbitrates and latches subsequent new read / write requests from the AXI4-Full interface module; it caches read / write requests using the _lock signal and controls the timing of request validity using the _valid signal; finally, it performs an AND operation on the _lock signal of the read / write request.

15. A system based on a FeRAM-based parallel controller IP core according to claim 1, characterized in that, The FeRAM driver module is based on a 6-state machine architecture and uses timing signals input from the read / write instruction control module to uniformly manage the generation timing of all FeRAM chip control signals. It adopts a bidirectional data path control mechanism and supports various FeRAM data I / O bit width modes and chip specification configurations through intelligent parameterized design.

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