Storage device

Abstract

A memory device includes: a non-volatile memory; and a memory controller configured to read read data from the non-volatile memory and write the read data to a memory device. The storage controller includes a management circuit configured to cache the read data in a cache memory in a host device by using a cache coherency protocol.

Description

Technical Field

[0001] The present invention relates to a storage device that caches read data in a cache memory in a host device by using a cache coherence protocol. Background Technology

[0002] Recently, storage devices, including non-volatile memory such as solid-state drives (SSDs), have been widely used. Storage devices are used to store or move large amounts of data.

[0003] When a storage device receives a read command from a host device, the storage device can read the corresponding read data from its internal non-volatile memory and provide the read data to the host device. At this time, various methods are being developed to quickly provide data from the storage device to the host device for rapid data processing. Summary of the Invention

[0004] The present invention relates to a storage device that allows a host device to obtain read data with low latency.

[0005] According to one aspect of the present invention, a storage device is provided, the storage device comprising: a non-volatile memory; and a storage controller configured to read read data from the non-volatile memory and write the read data to a storage device. The storage controller includes management circuitry configured to cache the read data in a cache memory in a host device using a cache coherence protocol.

[0006] According to another aspect of the present invention, a storage device is provided, the storage device comprising: a non-volatile memory; and a storage controller configured to process cache read commands issued by a host device and to write an indication of completion of processing the cache read commands to an external storage device. The storage controller includes management circuitry configured to cache the completion in a cache memory within the host device using a cache coherence protocol.

[0007] According to another aspect of the present invention, a storage device is provided, the storage device comprising: a non-volatile memory; a storage controller configured to read read data from the non-volatile memory; and a buffer memory including a data buffer to which the read data is written. The storage controller includes management circuitry configured to cache the read data in a cache memory in a host device using a cache coherence protocol. Attached Figure Description

[0008] The embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a block diagram illustrating an electronic device including a storage device according to an example embodiment; Figure 2 This is a block diagram illustrating the detailed structure of a storage device according to an example embodiment; Figure 3 This is a diagram illustrating an example of a read data transfer operation of a storage device according to an exemplary embodiment; Figure 4 This is a diagram illustrating an example of a storage device performing a transfer operation according to an exemplary embodiment; Figure 5 This is a diagram illustrating another example of a read data transfer operation of a storage device according to an example embodiment; Figure 6 This is a diagram illustrating another example of a storage device completing a transfer operation according to an example embodiment; Figure 7 This is a diagram illustrating an example of a cache read command received by a storage device according to an example embodiment; Figure 8 This is a diagram illustrating a method of using a storage device according to an example embodiment to cache at least a portion of read data based on a cache read command; Figure 9 This is a flowchart illustrating a method operated by a storage device according to the value of a flag field, based on an example embodiment; Figure 10 This is a flowchart illustrating a method of operating an electronic device including a storage device according to an example embodiment; and Figure 11 This is a diagram illustrating a system using a storage device according to an example embodiment. Detailed Implementation

[0009] In the following description, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. The same reference numerals refer to the same elements throughout.

[0010] Figure 1 This is a block diagram illustrating an electronic device 10 according to an embodiment.

[0011] refer to Figure 1 The electronic device 10 according to the embodiment may include a host device 100, a storage device 200 and a storage device 300.

[0012] In example embodiments, electronic device 10 can be implemented as a personal computer (PC), data server, ultra-mobile PC (UMPC), workstation, netbook, network attached storage (NAS), smart TV, Internet of Things (IoT) device, automotive, or portable electronic device. Portable electronic devices may include laptop computers, mobile phones, smartphones, tablet PCs, personal digital assistants (PDAs), enterprise digital assistants (EDAs), digital still cameras, digital video cameras, audio devices, portable multimedia players (PMPs), personal navigation devices (PNDs), MP3 players, handheld game consoles, e-readers, or wearable devices.

[0013] The host device 100 can control the overall operation of the electronic device 10. In embodiments, the host device 100 may include a processor core such as a central processing unit (CPU) or application processor (AP) configured to control the electronic device 10, or a computing node connected via a network.

[0014] The host device 100 can store data in the storage device 200, or can read data stored in the storage device 200. The host device 100 can generate write commands or read commands for the data.

[0015] In order to store data in storage device 200, host device 100 can write write data to storage device 300 to be written to storage device 200, and can write write commands to storage device 300 to indicate that data is to be written from storage device 300 to storage device 200.

[0016] In order to read data stored in storage device 200, host device 100 may write a read command indicating that data stored in storage device 200 should be read to storage device 300.

[0017] The host device 100 can read from the storage device 300 an indication of the completion of the processing result of the command.

[0018] The host device 100 can communicate with the storage device 200 through various interfaces. In this embodiment, the host device 100 can communicate with the storage device 200 through an interface that supports a cache coherence protocol. For example, the cache coherence protocol may include the Compute Fast Link (CXL) protocol.

[0019] Storage device 200 may include a storage medium that stores data according to commands from host device 100. Storage device 200 may be implemented as one of various types of devices. For example, storage device 200 may be implemented as one of various types of devices such as: eMMC, MMC, solid-state drive (SSD), universal flash memory (UFS), embedded UFS (eUFS), miniaturized multimedia card (RS-MMC), micro MMC format multimedia card, compact flash memory (CF) card, SD card, micro SD card, mini SD card, extreme digital (xD) card, smart media card, and memory stick.

[0020] Storage device 200 can perform operations corresponding to write commands or read commands generated by host device 100. Storage device 200 can obtain the write command or read command generated by host device 100 by reading it from storage device 300.

[0021] When the command received from storage device 300 is a write command, storage device 200 can obtain the write data generated by host device 100 by reading the write data corresponding to the write command from storage device 300. Storage device 200 can store the write data.

[0022] When the command obtained from the storage device 300 is a read command, the storage device 200 can internally search for read data corresponding to the read command and can write the read data to the storage device 300.

[0023] The storage device 200 can generate a completion corresponding to the command being executed, and can write the generated completion to the storage device 300.

[0024] In an embodiment, storage device 200 may include management circuitry 216. Management circuitry 216 may be implemented using hardware, firmware, software logic, or a combination thereof, through methods well known to those skilled in the art. Storage device 200 may cache read data in cache memory within host device 100 using a cache coherence protocol via management circuitry 216. Additionally, storage device 200 may cache completion data in cache memory within host device 100 via management circuitry 216 using a cache coherence protocol. In this way, because storage device 200 caches read data or completion data in cache memory within host device 100 using a cache coherence protocol, host device 100 can obtain read data with low latency. Reference will be made below. Figure 2 A more detailed description of the structure and operation of the host device 100 and the storage device 200 is provided.

[0025] Storage device 300 can store commands generated by host device 100. Additionally, storage device 300 can store data to be written to or read from storage device 200. Furthermore, storage device 300 can store commands to be sent from host device 100 to storage device 200. Additionally, storage device 300 can store completion information corresponding to the commands.

[0026] Storage device 300 may include volatile memory such as static random access memory (SRAM) or dynamic random access memory (DRAM). However, the inventive concept is not limited thereto, and storage device 300 may include any type of memory that can be accessed by host device 100, such as non-volatile memory such as flash memory, phase-change random access memory (PRAM), magnetic random access memory (MRAM), or ferroelectric random access memory (FeRAM).

[0027] Figure 2 This is a block diagram illustrating the detailed structure of a storage device 200 according to an example embodiment.

[0028] refer to Figure 2 The electronic device 10 according to the embodiment may include a host device 100 and a storage device 200. Additionally, although in Figure 2 The electronic device 10 according to the embodiment may also include a storage device 300, though it is not shown in the figure.

[0029] In this embodiment, the host device 100 may include a host controller 110 and a cache memory 120. The host controller 110 can control the overall operation of the host device 100.

[0030] The host controller 110 can generate write commands or read commands for data and store the generated write commands or read commands in the submission queue of the storage device 300. At this time, when the command generated by the host controller 110 is a write command, the host controller 110 can store the write data corresponding to the write command in the data buffer of the storage device 300.

[0031] The host controller 110 can read completions from the completion queue of the storage device 300. The host controller 110 can check the processing result of a write command or read command by checking the completion. At this time, the host controller 110 can perform pooling on the completion queue of the storage device 300 to check whether the completion corresponding to the write command or read command has been written to the completion queue.

[0032] When the completion corresponding to the read command is written to the completion queue of the storage device 300, the host controller 110 can obtain the read data from the data buffer of the storage device 300. At this time, because the host controller 110 must access the storage device 300 outside the host device 100 to obtain the completion and read data corresponding to the read command, a delay occurs when accessing the storage device 300 outside the host device 100.

[0033] The cache memory 120 can temporarily store data used by the host controller 110.

[0034] In this embodiment, the cache memory 120 can temporarily store read data generated by the storage controller 210 of the storage device 200. In this case, the management circuitry 216 included in the storage controller 210 can cache the read data in the cache memory 120 using a cache coherence protocol, thus enabling the read data to be temporarily stored in the cache memory 120.

[0035] In this embodiment, the cache memory 120 may temporarily store completions generated by the storage controller 210 of the storage device 200. In this case, the management circuitry 216 included in the storage controller 210 can cache the completions in the cache memory 120 using a cache coherence protocol, allowing read data to be temporarily stored in the cache memory 120.

[0036] The storage device 200 according to an embodiment may include a storage controller 210 and an NVM (non-volatile memory) 220. Additionally, the storage device 200 according to an embodiment may also include a buffer memory 230.

[0037] NVM 220 can store data, output stored data, or erase stored data under the control of storage controller 210. In embodiments, NVM 220 may include a two-dimensional (2D) or three-dimensional (3D) NAND flash memory device. However, the inventive concept is not limited thereto, and NVM 220 may include storage devices based on magnetic RAM (MRAM), spin-torque MRAM, conductive bridged RAM (CBRAM), ferroelectric RAM (FeRAM), phase-change RAM (PRAM), resistive RAM (RRAM), and various other types of memory.

[0038] Storage controller 210 can control the overall operation of storage device 200. Storage controller 210 can fetch commands written by host device 100 from the submission queue of storage device 300. Storage controller 210 can execute operations corresponding to the fetched commands and can write an indication of the completion of the processing result of the fetched commands to the completion queue of storage device 300.

[0039] In this embodiment, when the command obtained by the storage controller 210 is a write command, the storage controller 210 can obtain write data from the data buffer of the storage device 300 and store the obtained write data in the NVM 220. Next, the storage controller 210 can write an indication of completion of the processing result of the write command to the completion queue of the storage device 300.

[0040] In this embodiment, when the command obtained by the storage controller 210 is a read command, the storage controller 210 can read read data from the NVM 220 and write the read data to the data buffer of the storage device 300. Next, the storage controller 210 can write an indication of completion of the processing result of the read command to the completion queue of the storage device 300.

[0041] The storage controller 210 may include a host interface (I / F) 211, a memory interface 212, a CPU 213, a flash translation layer (FTL) 214, a packet manager 215, and management circuitry 216.

[0042] The host interface 211 can communicate with the host device 100 according to a predetermined interface protocol. In embodiments, the predetermined interface protocol may include at least one of various interface protocols such as: Advanced Technology Attachment (ATA) interface, Serial ATA (SATA) interface, External SATA (e-SATA) interface, Small Computer Small Interface (SCSI) interface, Serial Attached SCSI (SAS) interface, Peripheral Component Interconnect (PCI) interface, Fast PCI (PCIe) interface, Fast NVM (NVMe) interface, IEEE 1394, Universal Serial Bus (USB) interface, Secure Digital (SD) card interface, Multimedia Card (MMC) interface, eMMC interface, UFS interface, Embedded Universal Flash Memory (eUFS) interface, CF card interface, and network interface. The host interface 211 can receive signals from the host device 100 based on the predetermined interface protocol and can operate based on the received signals.

[0043] In this embodiment, the host interface 211 can communicate with the storage device 200 through an interface that supports a cache coherence protocol. For example, the cache coherence protocol may include the CXL protocol.

[0044] The memory interface 212 can communicate with the NVM 220 according to a predetermined interface protocol. In an embodiment, the predetermined interface protocol may include at least one of various interface protocols such as the toogle interface and the Open NAND Flash Interface (ONFI). In an embodiment, the memory interface 212 may communicate with the NVM 220 based on the toogle interface. In this case, the memory interface 212 may communicate with the NVM 220 through multiple channels. In an embodiment, each of the multiple channels may include multiple signal lines configured to transmit various control signals (e.g., / CE, CLE, ALE, / WE, / RE, and R / B), a data signal DQ, and a data strobe signal DQS.

[0045] CPU 213 can control the overall operation of storage controller 210. FTL 214 can perform various operations to efficiently utilize NVM 220. For example, FTL 214 can manage the address mapping between logical addresses from host device 100 and physical page addresses of storage device 200.

[0046] FTL 214 can perform wear leveling to prevent excessive degradation of specific blocks within an NVM 220 storage block (or block). Wear leveling by FTL 214 can increase the lifespan of the NVM 220. FTL 214 can also ensure free storage blocks by performing garbage collection on the NVM 220.

[0047] The packet manager 215 can generate packets according to the protocol of the interface negotiated with the host device 100, or it can parse various types of information from packets received from the host device 100.

[0048] The management circuit 216 can perform the operation of caching data or completion in the cache memory 120 of the host device 100 by using a cache coherence protocol.

[0049] In an embodiment, management circuitry 216 can cache read data in cache memory 120 in host device 100 by using a cache coherence protocol.

[0050] In this embodiment, management circuitry 216 may identify the address of the data buffer storing read data in storage device 300 immediately after initialization. Next, management circuitry 216 may cache the read data to be written to the data buffer in cache memory. For example, when storage controller 210 writes read data to storage device 300, management circuitry 216 may cache the read data in cache memory 120 using a cache coherence protocol.

[0051] In an embodiment, when the command obtained from the storage device 300 is a cache read command, the management circuit 216 can cache the read data in the cache memory 120 by using a cache coherence protocol.

[0052] Cache read commands may include commands similar to read commands or instructions to cache data and complete read commands in cache memory 120 using a cache coherence protocol. Management circuitry 216 may cache read data from NVM 220 in cache memory 120 based on the cache read command using the cache coherence protocol.

[0053] See below for reference. Figure 7 Describe examples of cache read commands and related operations.

[0054] In an embodiment, management circuitry 216 may use a cache coherence protocol to cache the completed data in cache memory 120 in host device 100.

[0055] In this embodiment, management circuitry 216 may identify the address of the completion queue stored in storage device 300 immediately after initialization. Next, management circuitry 216 may cache the completions to be written to the completion queue in cache memory. For example, when storage controller 210 writes a completion to storage device 300, management circuitry 216 may cache the completion in cache memory 120 using a cache coherence protocol.

[0056] In this embodiment, management circuitry 216 can process cache read commands and can cache the completion of processing results for cache read commands in cache memory 120 using a cache coherence protocol. Management circuitry 216 can cache read data in cache memory 120 according to cache read commands, and can then cache the completion of processing results for cache read commands in cache memory 120 using a cache coherence protocol.

[0057] As described above, when the management circuit 216 caches read data and completion data in the cache memory 120 within the host device 100 using a cache coherence protocol, the host controller 110 can obtain the completion and read data when accessing the cache memory 120. Compared to the host controller 110 accessing the storage device 300 external to the host device 100 to obtain the completion and read data, because the host controller 110 obtains the completion and read data within the host device 100, the read data and completion can be obtained with low latency. In this way, because the storage device 200 caches read data and completion data in the cache memory 120 within the host device 100 using a cache coherence protocol, the host device 100 can obtain the read data with low latency.

[0058] Buffer memory 230 can be used by host device 100 together with storage device 300. For example, buffer memory 230 may include host-managed device memory (HDM) of CXL. Buffer memory 230 is included in storage device 200, but can be used by host device 100 in the same manner as storage device 300.

[0059] The buffer memory 230 can store commands generated by the host device 100. Additionally, the buffer memory 230 can store data to be written to or read from the storage device 200. Furthermore, the buffer memory 230 can store commands to be sent from the host device 100 to the storage device 200. Additionally, the buffer memory 230 can store completions corresponding to the commands.

[0060] Buffer memory 230 may include a data buffer in which read data is stored. In an embodiment, management circuitry 216 may identify the address of the data buffer in buffer memory 230 and may cache read data to be written to the data buffer in cache memory 120.

[0061] Buffer memory 230 may include a completion queue stored therein. In an embodiment, management circuitry 216 may identify the address of the completion queue in buffer memory 230 and may cache read data to be written to the data buffer in cache memory 120.

[0062] In an embodiment, when the command obtained from the buffer memory 230 is a cache read command, the management circuit 216 can cache the read data in the cache memory 120 by using a cache coherence protocol, and can also cache the completion of the processing result of the cache read command in the cache memory 120 by using a cache coherence protocol.

[0063] As described above, when the buffer memory 230 is used by the host device 100 together with the storage device 300, the host device 100 can obtain data read and complete with low latency because the host device 100 obtains the data read and completes the data read.

[0064] Figure 3 This is a diagram illustrating an example of a read data transfer operation of a storage device according to an example embodiment.

[0065] refer to Figure 3 The movement of read data RD by storage device 200 can be checked according to the cache read command C_READ generated by host device 100.

[0066] First, storage device 200 can obtain the cache read command C_READ. At this time, storage device 200 can retrieve the cache read command C_READ from the commit queue of storage device 300.

[0067] The storage controller 210 of storage device 200 can read read data RD from NVM 220 according to the cache read command C_READ. For example, the storage controller 210 of storage device 200 can read read data RD from NVM 220 in response to the cache read command C_READ.

[0068] Next, the storage controller 210 can cache the read data RD in the cache memory 120 of the host device 100 via the management circuit 216. At this time, the management circuit 216 can cache the read data RD in the cache memory 120 using a cache coherence protocol. The cached read data RD in the cache memory 120 can then be sent from the cache memory 120 to the data buffer 310. For example, when other data is written to the space where the read data RD is stored in the cache memory 120, the cached read data RD can be evicted from the cache memory 120, and the evicted read data RD can be updated in the data buffer 310.

[0069] In this embodiment, the storage controller 210 may cache at least a portion of the read data RD in the cache memory 120 via the management circuit 216. In this case, the portion of the read data RD cached in the cache memory 120 may be determined based on the value of the offset field and the value of the line number field included in the cache read command C_READ, as described below.

[0070] At this time, the remaining portion of the read data RD that is not cached in the cache memory 120 can be stored in the data buffer 310. The memory controller 210 can write the read data RD to the data buffer 310 via the management circuit 216 in a direct memory access (DMA) manner.

[0071] In one example, management circuitry 216 may write only the remaining portion of the read data RD that is not cached in cache memory 120 to data buffer 310. In another example, management circuitry 216 may write the entire read data RD, including the remaining portion of the read data RD that is not cached in cache memory 120, to data buffer 310.

[0072] In this way, the read data RD is cached in the cache memory 120 in the host device 100 via the management circuit 216, thereby reducing the access latency of the host device 100 to the read data RD.

[0073] Figure 4 This is a diagram illustrating an example of a storage device completing a transfer operation according to an example embodiment.

[0074] refer to Figure 4 , can follow as Figure 3 The cache read command C_READ is received, and the read data RD is cached in cache memory 120. The COM move is then checked to complete.

[0075] The storage controller 210 can cache the read data RD in the cache memory 120, and can then generate a completion COM indicating the processing result of the cache read command C_READ.

[0076] Next, the storage controller 210 can cache the completion COM in the cache memory 120 of the host device 100 via the management circuit 216. At this time, the management circuit 216 can cache the completion COM in the cache memory 120 using a cache coherence protocol. The cached completion COM in the cache memory 120 can then be sent from the cache memory 120 to the completion queue 320. For example, when other data is written to the space where the completion COM is stored in the cache memory 120, the cached completion COM can be evicted from the cache memory 120, and the evicted completion COM can be updated in the completion queue 320.

[0077] In this way, the completion COM is cached in the cache memory 120 in the host device 100 via the management circuit 216, thereby reducing the latency of the host device 100 accessing the completion COM.

[0078] Figure 5 This is a diagram illustrating another example of a read data transfer operation of a storage device according to an example embodiment.

[0079] refer to Figure 5 , and in Figure 3 Unlike other devices, when the host device 100 uses the buffer memory 230 and the storage device 300, it can check the movement of the read data RD by the storage device 200 according to the cache read command C_READ generated by the host device 100.

[0080] With Figure 3 Unlike other storage devices, storage controller 210 can write read data RD to buffer memory 230 in storage device 200.

[0081] At this time, the storage controller 210 can be as follows: Figure 3 The read data RD is cached in the cache memory 120 of the host device 100 by the management circuit 216. At this time, the management circuit 216 can cache the read data RD in the cache memory 120 by using a cache coherence protocol.

[0082] Therefore, even when the host device 100 uses the buffer memory 230 and the storage device 300, the access latency of the host device 100 to read the data RD can be reduced.

[0083] Figure 6 This is a diagram illustrating another example of a storage device completing a transfer operation according to an embodiment.

[0084] refer to Figure 6 , and in Figure 4 Unlike other methods, when the host device 100 uses the buffer memory 230 and the storage device 300, it can check the completion of the COM movement after the read data RD is cached in the cache memory 120 upon receiving the cache read command C_READ.

[0085] At this time, the storage controller 210 can be as follows: Figure 4 The management circuit 216 caches the completed COM in the cache memory 120 of the host device 100. At this time, the management circuit 216 can cache the completed COM in the cache memory 120 using a cache coherence protocol.

[0086] However, with Figure 4Unlike other memory controllers, storage controller 210 can write the completed COM to buffer memory 230 in storage device 200.

[0087] Therefore, even when the host device 100 uses the buffer memory 230 and the storage device 300, the latency of the host device 100 to complete COM access can be reduced.

[0088] Figure 7 This is a diagram illustrating an example of a cache read command received by a storage device according to an example embodiment.

[0089] refer to Figure 7 According to an embodiment, the cache read command C_READ received by the storage device 200 may include a logical block address (LBA) field, a type field, a size field, an offset field, and a line number field. Additionally, the cache read command C_READ received by the storage device 200 according to an embodiment may also include a flag field.

[0090] The LBA field can indicate the LBA in the NVM 220 of storage device 200 where the read data to be read according to the cache read command C_READ is stored.

[0091] The type field can indicate whether the command received from host device 100 is a cache read command C_READ.

[0092] The size field can indicate the size of the data to be read by the cache read command C_READ.

[0093] In an embodiment, when the storage device 200 determines from the host device 100 that the command received is a cache read command C_READ based on the type field, the storage device 200 can read the read data from the NVM 220 of the storage device 200 based on the LBA field and the size field.

[0094] The offset field can indicate the starting point of the portion of the read data read according to the cache read command C_READ to be stored in the cache memory 120 of the host device 100.

[0095] The line number field can indicate the line number of the data to be stored in the cache memory 120 of the host device 100, starting from the starting point indicated by the offset field, in the read data read according to the cache read command C_READ.

[0096] In an embodiment, when the management circuit 216 of the storage device 200 determines that the command received from the host device 100 is a cache read command C_READ, it can select the data to be cached in the cache memory 120 from the read data based on the value of the offset field and the value of the row number field included in the cache read command C_READ.

[0097] exist Figure 3 and Figure 5 In the above embodiments, when the read data RD is cached in the cache memory 120, the management circuit 216 can cache at least a portion of the read data RD in the cache memory 120 based on the value of the offset field and the value of the row number field. In this way, only a portion of the read data RD is cached in the cache memory 120 according to the value of the offset field and the value of the row number field, thereby reducing the time spent caching the read data RD in the cache memory 120.

[0098] The flag field can indicate the point in time when the storage controller 210 will complete COM caching in cache memory 120. More specifically, the flag field can indicate whether the point in time when COM is completed caching in cache memory 120 is after the entire read data RD has been stored in cache memory 230 or after at least a portion of the read data RD, set based on the offset field and row number field, has been cached in cache memory 120.

[0099] When the flag field indicates that the completion COM is cached in cache memory 120 after at least a portion of the read data RD has been cached in cache memory 120, the storage controller 210 can cache the completion COM in cache memory 120 after at least a portion of the read data RD has been cached in cache memory 120. At this time, because the host device 100 can receive the completion COM with only at least a portion of the read data RD set based on the offset field and row number field, rather than the entire read data RD, cached in cache memory 120, at least a portion of the necessary read data RD can be obtained more quickly.

[0100] See below for reference. Figure 9 This describes an example of how management circuit 126 operates based on the value of the flag field.

[0101] Figure 8 This is a diagram illustrating a method by which a storage device, according to an example embodiment, caches at least a portion of read data based on a cache read command.

[0102] refer to Figure 8You can check examples of read data read according to the cache read command.

[0103] Data can be read in the size field of the cache read command, starting from the LBA field indicated by the LBA field of the cache read command.

[0104] In one embodiment, at least a portion, but not all, of the read data can be cached in cache memory 120 based on the values ​​of the offset field and the row number field. Figure 8 In one embodiment, management circuit 126 may cache only the portion of the data read from the LBA that corresponds to the row number indicated by the row number field of the cache read command (starting from the offset value indicated by the offset field of the cache read command). Figure 8 (The gray shading indicates the area).

[0105] Figure 9 This is a flowchart illustrating a method by which a storage device operates based on the value of a flag field according to an example embodiment.

[0106] refer to Figure 9 The flowchart shown illustrates how the management circuit 126 operates based on the value of the flag field.

[0107] In operation S910, the management circuit 216 of the storage device 200 can check whether the value of the flag field is the first value (e.g., logic 1).

[0108] When the value of the flag field is the first value (S910, Yes), the process proceeds to operation S920, and the management circuit 216 can cache the completion COM in the cache memory 120 after at least a portion of the read data RD has been cached in the cache memory 120. That is, the management circuit 216 can cache at least a portion of the read data selected based on the value of the offset field and the value of the line number field included in the cache read command in the cache memory 120 by using a cache coherence protocol, and can then cache the completion COM in the cache memory 120.

[0109] Conversely, when the value of the flag field is not the first value but the second value (e.g., logic 0) (S910, no), the process proceeds to operation S930, and the management circuit 216 can cache the completed COM into the cache memory 120 after the entire read data RD has been stored in the buffer memory 230.

[0110] Figure 10 This is a flowchart illustrating a method of operating an electronic device including a storage device according to an example embodiment.

[0111] refer to Figure 10 It can check the operation between the main controller 110, cache memory 120, storage device 200 and storage device 300 when a cache read command is received.

[0112] In operation S1010, storage device 200 can send read data to storage device 300. At this time, storage device 200 can write the read data to data buffer 310 of storage device 300.

[0113] Simultaneously with operation S1010, in operation S1020, the storage device 200 may send read data to the cache memory 120. At this time, the storage device 200 can cache the read data in the cache memory 120. Since at least a portion of the read data can be cached in the cache memory 120 based on the value of the offset field and the value of the row number field of the cache read command, operation S1020 can complete faster than operation S1010.

[0114] After operation S1020 ends, in operation S1030, storage device 200 can cache the completion result of the processing of the cache read command in cache memory 120.

[0115] At this time, the host controller 110 can perform a completion queue (CQ) polling operation to check whether the completion is cached in the cache memory 120, as in operation S1040. In this case, the host controller 110 checks whether the completion is cached in the cache memory 120 inside the host device 100, thereby reducing latency compared to checking whether the completion is written to the external storage device 300 of the host device 100.

[0116] When it is determined in operation S1040 that caching is complete, in operation S1050, the host controller 110 can notify the cache memory 120 that caching is complete by performing a completion queue write operation.

[0117] Next, in operation S1060, the host controller 110 can notify the storage device 200 that caching has been completed by performing a completion queue head bell operation.

[0118] Finally, in operation S1070, the host controller 110 can access cached read data in the cache memory 120. At this time, the host controller 110 accesses cached read data in the cache memory 120 inside the host device 100, thereby reducing latency compared to accessing read data written to the storage device 300 outside the host device 100.

[0119] Figure 11 This is a diagram illustrating a system using a storage device according to an example embodiment.

[0120] Figure 11 The system 1000 can essentially be a mobile system such as a mobile phone, smartphone, tablet PC, wearable device, healthcare device, or Internet of Things (IoT) device. However, Figure 11 The system 1000 is not necessarily limited to mobile systems and may include automotive devices such as PCs, laptops, servers, media players, or navigation systems.

[0121] refer to Figure 11 The system 1000 may include a main processor 1100, memories 1200a and 1200b and storage devices 1300a and 1300b, and may also include one or more of an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470 and a connection interface 1480.

[0122] The main processor 1100 can control the overall operation of the system 1000, and more specifically, can control the operation of other components constituting the system 1000. The main processor 1100 can be implemented as a general-purpose processor, a special-purpose processor, or an application processor (AP).

[0123] The main processor 1100 may include one or more CPU cores 1110, and may also include a controller 1120 for controlling memories 1200a and 1200b and / or storage devices 1300a and 1300b. According to an embodiment, the main processor 1100 may also include an accelerator 1130 as dedicated circuitry for high-speed data computation, such as artificial intelligence (AI) data computation. The accelerator 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and may be implemented as a separate chip physically independent of other components of the main processor 1100.

[0124] Memory 1200a and 1200b can be used as the main memory device of system 1000 and can include volatile memory such as SRAM and / or DRAM, but can also include non-volatile memory such as flash memory, PRAM and / or RRAM. Memory 1200a and 1200b can also be implemented in the same package as main processor 1100.

[0125] Storage devices 1300a and 1300b can be used as non-volatile storage devices that store data regardless of power supply, and can have a relatively large storage capacity compared to memories 1200a and 1200b. Storage devices 1300a and 1300b may include storage controllers 1310a and 1310b and NVMs 1320a and 1320b that store data under the control of storage controllers 1310a and 1310b. NVMs 1320a and 1320b may include flash memory with a 2D structure or a 3D vertical NAND (V-NAND) structure, but may include other types of non-volatile memory such as PRAM and / or RRAM.

[0126] Storage devices 1300a and 1300b can be included in system 1000 either physically separate from main processor 1100 or implemented in the same package as main processor 1100. Furthermore, storage devices 1300a and 1300b can both take the form of solid-state drives (SSDs) or memory cards and can be detachably connected to other components of system 1000 via interfaces such as connection interface 1480, which will be described below. Storage devices 1300a and 1300b may include, but are not limited to, devices employing standard protocols such as UFS, eMMC, or NVMe fast non-volatile memory.

[0127] Figure 11 The main processor 1100 of system 1000 may be included in the above reference. Figures 1 to 10 The described host device 100. Additionally... Figure 11 The memory 1200a and 1200b of system 1000 may be included in the above reference. Figures 1 to 10 The described storage device 300. Additionally... Figure 11 The storage devices 1300a and 1300b of system 1000 may be included in the above reference. Figures 1 to 10 The storage device 200 is described.

[0128] The image capture device 1410 can capture still images or moving images and may include a camera, video camera and / or webcam.

[0129] User input device 1420 can receive various types of data input from the user of system 1000, and may include, for example, a touchpad, keypad, keyboard, mouse and / or microphone.

[0130] Sensor 1430 can detect various types of physical quantities that can be obtained from outside the system 1000 and can convert the sensed physical quantities into electrical signals. Sensor 1430 may include temperature sensors, pressure sensors, illuminance sensors, position sensors, acceleration sensors, biosensors, and / or gyroscope sensors.

[0131] The communication device 1440 can transmit signals to and receive signals from other devices outside the system 1000 according to various communication protocols. The communication device 1440 may include an antenna, a transceiver, and / or a modem.

[0132] The display 1450 and the speaker 1460 can be used as output devices to output visual and auditory information to the user of the system 1000, respectively.

[0133] The power supply unit 1470 can appropriately convert power supplied from a battery (not shown) built into the system 1000 and / or an external power source, and can supply the converted power to each component of the system 1000.

[0134] The connection interface 1480 provides a connection between the system 1000 and external devices connected to the system 1000 for exchanging data with the system 1000. The connection interface 1480 can be implemented in various interface methods such as: ATA interface, SATA interface, e-SATA interface, SCSI interface, SAS interface, PCI interface, PCIe interface, NVMe interface, IEEE 1394, USB interface, SD card interface, MMC interface, eMMC interface, UFS interface, eUFS interface, and CF card interface.

[0135] According to an aspect of the present invention, the management circuit identifies the address of the data buffer in the buffer memory and caches the read data to be written to the data buffer in the cache memory.

[0136] According to an aspect of the present invention, the management circuit selects data to be cached in the cache memory from the read data based on the value of the offset field and the value of the row number field included in the cache read command.

[0137] According to an aspect of the present invention, the management circuit identifies the address of the completed completion queue stored in the buffer memory, and the completed cache to be written to the completed queue is stored in the cache memory.

[0138] According to another aspect of the present invention, a storage device is provided, the storage device comprising: a non-volatile memory; a storage controller configured to process cache read commands issued by a host device; and a buffer memory including a completion queue indicating to which completion of processing results of the cache read commands is written. The storage controller includes management circuitry configured to cache the completions in the cache memory of the host device using a cache coherence protocol.

[0139] According to another aspect of the invention, the management circuit identifies the address of the completion queue in the buffer memory and caches the completion cache to be written to the completion queue in the cache memory.

[0140] According to another aspect of the present invention, the management circuit caches read data read from the non-volatile memory according to the cache read command in the cache memory by using the cache coherence protocol.

[0141] According to another aspect of the present invention, the management circuit identifies the address of the data buffer in the buffer memory that stores the read data, and caches the read data to be written to the data buffer in the cache memory.

[0142] According to another aspect of the present invention, the cache read command includes a logical block address (LBA) field, a type field, a size field, an offset field, and a line number field.

[0143] According to another aspect of the present invention, the management circuit selects data to be cached in the cache memory from the read data based on the value of the offset field and the value of the row number field included in the cache read command.

[0144] According to another aspect of the present invention, the cache read command further includes a flag field, and when the value of the flag field is a first value, the management circuit caches at least a portion of the read data selected based on the value of the offset field and the value of the row number field included in the cache read command in the cache memory by using the cache coherence protocol, and then caches a completion indication of the processing result of the cache read command in the cache memory by using the cache coherence protocol.

[0145] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A storage device, the storage device comprising: Non-volatile memory; as well as A storage controller configured to read data from the non-volatile memory and write the read data to a storage device. The storage controller includes a management circuit configured to cache the read data in a cache memory in the host device using a cache coherence protocol.

2. The storage device according to claim 1, wherein, The management circuit identifies the address of the data buffer in the storage device that stores the read data, and caches the read data to be written to the data buffer in the cache memory.

3. The storage device according to claim 1, wherein, When the command obtained from the storage device is a cache read command, the management circuit caches the read data in the cache memory by using the cache coherence protocol.

4. The storage device according to claim 3, wherein, The cache read command includes a logical block address field, a type field, a size field, an offset field, and a row number field.

5. The storage device according to claim 4, wherein, The management circuit selects data to be cached in the cache memory from the read data based on the value of the offset field and the value of the row number field included in the cache read command.

6. The storage device according to claim 3, wherein, The management circuit responds to the cache read command by caching the read data in the cache memory, and then caches the completion of the processing result of the cache read command in the cache memory by using the cache coherence protocol.

7. The storage device according to claim 6, wherein, The management circuit identifies the address of the completed queue stored in the storage device and stores the completed cache to be written to the completed queue in the cache memory.

8. The storage device according to claim 1, wherein, The cache coherence protocol includes a compute fast link protocol.

9. A storage device, the storage device comprising: Non-volatile memory; as well as A storage controller configured to process cache read commands issued by a host device and to write an indication of completion of processing the cache read commands to an external storage device. The storage controller includes a management circuit configured to cache the completed data in a cache memory in the host device using a cache coherence protocol.

10. The storage device according to claim 9, wherein, The management circuit identifies the address of the completed queue stored in the external storage device and stores the completed cache to be written to the completed queue in the cache memory.

11. The storage device according to claim 9, wherein, The management circuit uses the cache coherency protocol to cache read data read from the non-volatile memory according to the cache read command in the cache memory.

12. The storage device according to claim 11, wherein, The management circuit identifies the address of the data buffer in the external storage device that stores the read data, and caches the read data to be written to the data buffer in the cache memory.

13. The storage device according to claim 11, wherein, The cache read command includes a logical block address field, a type field, a size field, an offset field, and a row number field.

14. The storage device according to claim 13, wherein, The management circuit selects data to be cached in the cache memory from the read data based on the value of the offset field and the value of the row number field included in the cache read command.

15. The storage device according to claim 9, wherein, The cache coherence protocol includes a compute fast link protocol.

16. A storage device, the storage device comprising: Non-volatile memory; A storage controller configured to read data from the non-volatile memory; as well as A buffer memory, comprising a data buffer to which the read data is written. The storage controller includes a management circuit configured to cache the read data in a cache memory in the host device using a cache coherence protocol.

17. The storage device according to claim 16, wherein, When the command obtained from the buffer memory is a cache read command, the management circuit caches the read data in the cache memory by using the cache coherence protocol.

18. The storage device according to claim 17, wherein, The cache read command includes a logical block address field, a type field, a size field, an offset field, and a row number field.

19. The storage device according to claim 18, in, The cache read command also includes a flag field, and When the value of the flag field is a first value, the management circuit caches at least a portion of the read data selected based on the value of the offset field and the value of the row number field included in the cache read command in the cache memory by using the cache coherence protocol, and then caches the completion of the processing result of the cache read command in the cache memory by using the cache coherence protocol.

20. The storage device according to claim 17, wherein, The management circuit responds to the cache read command by caching the read data in the cache memory, and then caches the completion of the processing result of the cache read command in the cache memory by using the cache coherence protocol.

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