Area and power efficient partial word features in embedded memory

Abstract

The invention relates to area and power efficient partial word features in embedded memory. A static random access memory (SRAM) device with enhanced flexibility and power efficiency includes two memory cores having different bit widths and a control section that receives part of word signals. The signal allows each memory core to be independently controlled, selectively enabled or disabled. The SRAM device also includes a decoder circuit and a plurality of word line drivers that may be independently enabled or disabled for each memory core based on the partial word signal. The wordline drivers are organized into two groups, each group coupled to a wordline of a respective memory core. The power control circuit selectively provides power to each group of drivers according to the partial word signal. This architecture allows for more granular control of memory access and power consumption, potentially improving the overall efficiency and performance of the device in applications that require variable memory access modes.

Description

[0001] Related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 697,789, filed September 23, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of integrated circuit design, and more particularly to static random access memory (SRAM) architecture. More specifically, this disclosure relates to power-efficient SRAM designs with selective memory bank activation capability for use in system-on-a-chip (SoC) applications. Background Technology

[0004] System-on-a-Chip (SoC) designs often include multiple instances of Static Random Access Memory (SRAM) circuitry. These SRAM circuits typically include components such as decoders, control circuitry, and input / output (I / O) circuitry. In traditional designs, SRAM memory circuitry of different sizes, such as 16-bit, 32-bit, and 64-bit configurations, are often found within a single SoC.

[0005] Part of the principle behind implementing SRAM circuits of different sizes stems from power consumption considerations. Larger memory arrays, especially those with more columns, consume more power during read and write operations. Therefore, it can be advantageous to perform certain operations specifically on smaller memory units to optimize power efficiency.

[0006] However, this traditional approach presents several challenges. The need to connect multiple wires to different SRAM memory circuits consumes a significant amount of chip area. This increased routing complexity leads to inefficient layout and potential signal integrity issues. Furthermore, each SRAM memory circuit typically requires its own decoder, control circuitry, and I / O components. This redundancy in hardware resources hinders the realization of potential power savings that could be achieved through shared circuitry.

[0007] These limitations in traditional SRAM implementations within a SoC highlight the need for further development in memory architecture design. Issues such as wiring complexity, circuit redundancy, area efficiency, and power optimization require solutions. Summary of the Invention

[0008] In one embodiment, a static random access memory (SRAM) device with enhanced flexibility and power efficiency includes two memory cores with different bit widths and a control section that receives partial word signals. These signals allow for independent control of each memory core, selectively enabling or disabling them. The SRAM device also includes decoder circuitry and multiple word line drivers that can be independently enabled or disabled for each memory core based on the partial word signals. The word line drivers are organized into two groups, each coupled to the word lines of a corresponding memory core. Power control circuitry selectively supplies power to each group of drivers based on the partial word signals. This architecture allows for more granular control over memory access and power consumption, potentially improving the overall efficiency and performance of the device in applications requiring variable memory access modes. Attached Figure Description

[0009] Figure 1A It is a block diagram of a static random access memory (SRAM) with an equal-width memory bank and a half-word select mechanism.

[0010] Figure 1B It is a block diagram of an innovative static random access memory (SRAM) with a non-uniform memory bank and a partial word selection mechanism.

[0011] Figure 2 It is shown that it is used for Figure 1B A schematic diagram of the SRAM decoder circuit and word line driver;

[0012] Figure 3 This is a schematic diagram showing a portion of the control section responsible for generating certain control signals for SRAM.

[0013] Figure 4 This is a schematic diagram showing the detailed structure of the memory core and its associated bit line control circuitry.

[0014] Figure 5A It shows Figure 1A A power consumption curve for a complete SRAM design.

[0015] Figure 5B It shows Figure 1A A graph showing the power consumption of an SRAM design operating in half-word mode.

[0016] Figure 6A This is a graph showing the power consumption of the complete SRAM design in Figure 1B.

[0017] Figure 6B It is shown Figure 1B A graph showing the power consumption of an SRAM design operating in partial word mode. Detailed Implementation

[0018] The following disclosure enables those skilled in the art to make and use the subject matter described herein. The general principles outlined in this disclosure can be applied to embodiments and applications beyond those detailed above without departing from the spirit and scope of this disclosure. This disclosure is not intended to be limited to the embodiments shown, but rather is to be given the widest scope consistent with the principles and features disclosed or suggested herein.

[0019] Figure 1A A block diagram of a static random access memory (SRAM) 10 used in a system-on-a-chip (SoC) is shown. The SRAM 10 is designed to allow selective activation of memory banks, improving power efficiency. The SRAM 10 comprises two memory banks: a left memory core (MEM core L) 12L and a right memory core (MEM core R) 12R, each 16 bits wide, for a total memory width of 32 bits.

[0020] The row decoder (ROWDEC) 13 selects a specific row within the two memory cores 12L and 12R based on the provided address input. The input / output (I / O) module 18 facilitates data transfer with the memory cores 12L and 12R. The SRAM 10 includes a total of 32 data pins, labeled Q0 through Q31. Pins Q0 through Q15 are used for the left memory group (memory core 12L), while pins Q16 through Q31 are used for the right memory group (memory core 12R). The dummy column (DCOL) 14 helps resolve process variations and thus maintains consistent and stable performance during read and write operations performed on the memory cores 12L and 12R. The dummy row decoder 11 performs a similar function to the row decoder 13, but is used for the dummy column 14 instead of the left and right memory cores 12L and 12R.

[0021] Control circuitry 16 receives and manages various signals, including address inputs and functional commands (e.g., enable write, chip select), coordinating the activities of various components. The SRAM implements a half-word selection mechanism controlled by the HW<0:1> signal. This allows the circuitry to selectively activate the left memory bank 12L, the right memory bank 12R, or both memory banks simultaneously, achieving power savings by driving only the memory banks required for a given operation.

[0022] The half-word mechanism operates as follows: when the signal HW<0:1> is set to select only the left memory bank, the SRAM activates only memory core 12L and its associated circuitry, while memory core 12R remains inactive. Similarly, when set to select only memory core 12R, it activates memory core 12R while inactively deactivating memory core 12L. When both memory banks are selected, the SRAM operates as a full 32-bit memory. This selective activation results in significant power savings during operations that do not require the full memory bit width.

[0023] This design offers power efficiency advantages through selective memory bank activation. However, the SRAM 10 design architecture requires the left memory core 12L and right memory core 12R to have equal bit widths. This requirement is inherent to the functionality of the half-word mechanism, as it employs symmetrical memory banks for correct operation. The requirement for equal-width memory banks ensures that it can handle the same data width when either memory bank is selected individually, maintaining consistency in memory operation regardless of which memory bank is active. Therefore, the SRAM 10 design does not allow the use of asymmetric memory banks, such as 8-bit and 24-bit wide memory banks, which limits its flexibility in certain applications that may require variable memory widths.

[0024] Figure 1B A block diagram of an innovative static random access memory (SRAM) 10' is shown, which is designed to allow for memory banks of non-uniform width, solving... Figure 1A The limitations of the design shown. Figure 1A The designs shown differ, and these memory cores (MEM cores) 12L and 12R can have different bit widths. In this example, the left memory core 12L is 8 bits wide, while the right memory core 12R is 24 bits wide, resulting in a total memory width of 32 bits. Here, pins Q0 to Q7 are used for the left memory group (memory core 12L), while pins Q8 to Q31 are used for the right memory group (memory core 12R), reflecting the asymmetric nature of the memory groups.

[0025] SRAM 10' implements a partial word feature that provides independent control over the left and right memory stores. This feature is managed via the PW<0:1> signal, which is located on two pins—PW... <0> and PW <1> —Two signals received on the upper part. These pins allow for dynamic and static power savings by selectively enabling or disabling memory banks 12L and 12R. Control section 16 receives PW <0> and PW <1> Signals interpret these inputs to manage the activation of the memory core accordingly.

[0026] The PW<0:1> signal functions as follows: When PW <1> and PW <0> When both are 0, both left memory core 12L and right memory core 12R are enabled, allowing full access to the entire 32-bit memory width. If PW <1> =0 and PW <0> If the value is 1, memory core 12L is disabled, while memory core 12R remains enabled, providing only access to memory core 12R (24-bit in this example), and reducing power consumption by disabling memory core 12L. Conversely, when PW <1> =1 and PW <0> When PW is 0, memory core 12L is enabled while memory core 12R is disabled, providing only access to memory core 12L (8 bits in this example) and achieving power savings by disabling the larger memory core 12R. Finally, if PW <1> and PW <0> If both are 1, then both memory cores 12L and 12R are disabled. This state can be used to keep the overall chip running even when the entire SRAM is powered down.

[0027] Figure 2 A decoder circuit and word line driver 13 for generating word line signals for SRAM 10' are shown.

[0028] The circuit includes a PMOS transistor MPL0, whose source is connected to VDDMA, and whose drain is connected to the drain of an NMOS transistor MNL0. VDDMA represents the memory array supply voltage, while VDDMP represents the memory peripheral supply voltage. The RTAM (Retention Test Array Mode) signal controls the retention mode operation of the memory core.

[0029] The source of transistor MNL0 is grounded. The gates of both transistors MPL0 and MNL0 are coupled to receive the ASLEEP_WLDRV_L signal.

[0030] Similarly, the source of the PMOS transistor MPR0 is connected to VDDMA, and its drain is connected to the drain of the NMOS transistor MNR0. The source of transistor MNR0 is grounded. The gates of both transistors MPR0 and MNR0 are coupled to receive the ASLEEP_WLDRV_R signal.

[0031] This circuit contains 256 decoding circuits, labeled 21. <0> Up to 21 <255> Each decoding circuit 21 receives an address input and generates decoding signals for both the left and right memory cores. The output of each decoding circuit 21 is connected to a pair of inverters: an inverter 22L for the left memory core 12L and an inverter 22R for the right memory core 12R. There are 256 inverters 22L, labeled 22L. <0> Up to 22L <255> And 256 inverters 22R, labeled 22R <0> Up to 22R <255> .

[0032] Each inverter 22L is powered between the voltage at the common drain of transistors MPL0 / MNL0 and ground. The output of each inverter 22L drives the word line WL_L for the left memory core 12L. <x>, where x ranges from 0 to 255.

[0033] Similarly, each inverter 22R is powered between the voltage at the common drain of transistors MPR0 / MNR0 and ground. The output of each inverter 22R drives the word line WL_R for the right memory core 12R. <x>, where x ranges from 0 to 255.

[0034] NMOS transistor MNL1 <0> To MNL1 <255> The drains are respectively connected to inverter 22L <0> Up to 22L <255> The outputs are grounded. Their gates are controlled by the ASLEEP_WLDRV_L signal.

[0035] NMOS transistor MNR1 <0> To MNR1 <255> The drains of the two electrodes are respectively connected to inverter 22R. <0> Up to 22R <255> The outputs of these devices have their sources connected to ground. Their gates are controlled by the ASLEEP_WLDRV_R signal.

[0036] The circuit operates as follows: When ASLEEP_WLDRV_L is asserted (high) to disable memory core 12L, transistor MPL0 is turned off and transistor MNL0 is turned on, effectively grounding the power supply to all inverters 22L. This disables the word line driver for the left memory core 12L. Simultaneously, transistor MNL1... <0> To MNL1 <255> Ensure all word lines WL_L are connected. <x>It was pulled to the ground to prevent any accidental activation of memory cells in the left core.

[0037] Conversely, when ASLEEP_WLDRV_L is deasserted (low) to enable memory core 12L, transistor MPL0 turns on and transistor MNL0 turns off, connecting inverter 22L to VDDMA. This allows inverter 22L to drive word line WL_L based on the output of decoding circuit 21. <x>In this state, transistor MNL1 <0> To MNL1 <255> Off, allowing word lines to be driven high or low as needed.

[0038] The same principle applies to ASLEEP_WLDRV_R and its counterparts MPR0, MNR0, inverter 22R, and transistor MNR1. <0> To MNR1 <255> Controls are used to activate or deactivate the right memory core 12R.

[0039] This design allows for independent control of the word lines of each memory core, enabling partial word functionality and energy efficiency in SRAM 10'. By selectively asserting or deasserting ASLEEP_WLDRV_L and ASLEEP_WLDRV_R, the circuitry can independently activate or deactivate each memory core, supporting the previously described partial word operations.

[0040] Figure 3 The portion of control section 16 responsible for generating the ASLEEP_WLDRV_L and ASLEEP_WLDRV_R signals is shown. This circuit controls the activation and deactivation of the word line drivers for the left and right memory cores of SRAM 10'.

[0041] The circuit that generates the ASLEEP_WLDRV_L signal includes a PW receiver. <0> The signal is used as input level converter (LS) 251. This level converter will convert the PW signal into a signal level. <0> The signal is converted from its original voltage level to a VDDMA level to ensure compatibility with the memory array's power supply voltage. The output of level shifter 25L is fed into the first input of NOR gate 26L, which also receives the SLEEP signal as its second input. The output generated from NOR gate 26L then passes through inverter 27L to produce the final ASLEEP_WLDRV_L signal.

[0042] The circuitry that generates ASLEEP_WLDRV_R mirrors this structure. It includes a level shifter 25R that receives PW <1> The signal is converted to a VDDMA level. The converted signal then enters NOR gate 26R at its first input, which also uses the ASLEEP signal as its second input. Inverter 27R processes the output of NOR gate 26R to produce the ASLEEP_WLDRV_R signal.

[0043] When the SLEEP signal is asserted (high), NOR gates 26L and 26R output a low signal regardless of the PW input. Therefore, ASLEEP_WLDRV_L and ASLEEP_WLDRV_R are asserted (high) after passing through their respective inverters, effectively disabling both memory cores. This feature puts the entire SRAM into a low-power sleep mode.

[0044] When the SLEEP signal is deasserted (low), the circuit responds with a separate PW signal. If PW <0> If it is low, then ASLEEP_WLDRV_L will be deasserted (low), enabling left memory core 12L. Conversely, if PW <0> If ASLEEP_WLDRV_L is high, then ASLEEP_WLDRV_L will be asserted (high), disabling the left memory kernel. The same principle applies to PW. <1> And its control over ASLEEP_WLDRV_R used for right memory core 12R.

[0045] Figure 4 The detailed structure of memory cores 12L and 12R and their associated bit line control circuitry are shown.

[0046] In memory core 12L, the source of PMOS transistor TL0 is connected to VDDMA, and its gate is connected to PW. <0> Control. The drain of transistor TL0 is directly connected to the m×n-bit cell array of the memory core 12L. PMOS transistors TL1 and TL2 are connected in series. The source of transistor TL1 is connected to VDDMA, and its gate is controlled by RTAM. <0> Control. The drain of transistor TL1 is connected to the source of transistor TL2. The gate and drain of transistor TL2 are connected together (diode connection configuration), and it is also connected to the bit cell array. Similarly, PMOS transistors TL3 and TL4 are also connected in series. The source of transistor TL3 is connected to VDDMA, and its gate is controlled by RTAM. <1> Control. The drain of transistor TL3 is connected to the source of transistor TL4. The gate of transistor TL4 is connected to the drain of transistor TL4, and the drain of transistor TL4 is also connected to the bit cell array. Transistors TL0-TL4 together provide a virtual power supply voltage to the bit cells of memory core 12L.

[0047] A similar structure was implemented in memory core 12R. The source of the PMOS transistor TR0 is connected to VDDMA, and its gate is connected to PW. <1> Control. The drain of transistor TR0 is directly connected to the p×q bit cell array of the memory core 12R. PMOS transistors TR1 and TR2 are connected in series, the source of transistor TR1 is connected to VDDMA, and the gate of transistor TR1 is controlled by RTAM. <0> Control. The source of transistor TR2 is connected to the drain of transistor TR1, and the gate of transistor TR2 is connected to the drain of transistor TR2. The drain of transistor TR2 is connected to the bit cell array. Similarly, PMOS transistors TR3 and TR4 form another series connection, with the source of transistor TR3 connected to VDDMA and the gate of transistor TR3 connected to RTAM. <1> Control. The source of transistor TR4 is connected to the drain of transistor TR3, and the gate and drain of transistor TR4 are connected to each other and also to the bit cell array. Similar to the left core, transistors TR0-TR4 provide virtual power supply voltage to the bit cells of memory core 12R.

[0048] The operation of the virtual power supply voltage circuits in each memory core 12L and 12R is as follows.

[0049] In normal operating mode, PW is low, while RTAM is low. <0> and RTAM <1> High. In this normal operating mode, when PW (for 12L, PW is high). <0> For 12R, PW <1> When the voltage is low, transistors TL0 / TR0 are turned on, providing a direct connection from the VDDMA to the cell array. This provides full voltage and current supply during normal read and write operations. In this mode, transistors TL1-TL4 (or transistors TR1-TR4) are turned off, and the supply voltage is not affected.

[0050] In power-down mode (PW high), transistors TL0 / TR0 are turned off, disconnecting the direct VDDMA power supply from the corresponding bit cell array. This reduces power consumption by cutting off the main power supply path. In this state, memory contents are not necessarily retained unless the RTAM signal is activated; if they are not activated, a complete power-down of the memory is performed. In retention mode (PW high and RTAM...),... <0> or RTAM <1> When (or both) are low, they activate one or both of the series-connected transistor pairs (transistors TL1-TL2 and TL3-TL4, or transistors TR1-TR2 and TR3-TR4). These series-connected transistors act as a high-resistance path between the VDDMA and the bit cell array. The diode connection configuration of transistors TL2 / TL4 (or TR2 / TR4) provides a voltage drop, providing a lower voltage to the bit cell array—enough to hold data, but not enough for normal read / write operations.

[0051] By having two separate RTAM signals (RTAM) <0> and RTAM <1> This allows for fine-grained control over the holding mode. This can be used to provide different levels of holding current or for redundancy.

[0052] Below each bit cell array, the circuitry includes bit line control circuitry, labeled 18 for memory core 12L. <0> up to 18 <m>The marking for memory core 12R is 19. <0> up to 19 For memory core 12L, the circuit is replicated m+1 times (from 0 to m), as 18<0>,..., 18 <m> As shown, for memory core 12R, it is copied p+1 times (from 0 to p), as in 19. <0> , ..., 19< / m> As shown.

[0053] In the bit line control circuit 18 used for memory core 12L <0> up to 18 <m>In the middle, PMOS transistor PL3 <0> Up to PL3 <m>The source is connected to VDDMP, and its gate is made of PW. <0> Control. Transistor PL3 <0> Up to PL3 <m>The drain of the transistor is connected to a node labeled Nint1. PMOS transistor PL1 <0> To PL1 <m>and PL2<0> to PL2 <m>The source of transistor PL1 is connected to node Nint1. <0> To PL1 <m>The drain of the transistor PL2<0> to PL2 <m>The drain of the transistor PL1<0> to PL1 <m>and transistors PL2<0> to PL2 <m>The gate of the PMOS transistor is controlled by the precharge signal PCH_L. (PL4) <0> Up to PL4 <m>are connected between the bit lines BLTL_0 to BLTL_m and BLFL_0 to BLFL_m.

[0054] The bit line control circuits for the memory core 12R follow the same pattern. In the bit line control circuits 19<0> to 19< / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> In the middle, PMOS transistor PR3 <0> To PR3 The source is connected to VDDMP, and its gate is made of PW. <1> Control. Transistor PR3 <0> To PR3 The drain of the transistor is connected to a node labeled Nint2. PMOS transistor PR1 <0> To PR1 and PR2 <0> To PR2 The source of transistor PR1 is connected to node Nint2. <0> The drain of PR1 is connected to bit lines BLTR_0 to BLTR_p, and transistor PR2... <0> To PR2 The drain of transistor PR1 is connected to the padding lines BLFR_0 to BLFR_p. <0> To PR1 and transistor PR2 <0> To PR2 The gate of the PMOS transistor PR4 is controlled by the precharge signal PCH_R. <0> To PR4 are connected between bit lines BLTR_0 to BLTR_p and BLFR_0 to BLFR_p.

[0055] The bit line control circuit allows for individual control of bit line pre-charge and access for each memory core, supporting partial word functionality of the SRAM. The PW<0> and PW<1> signals control the activation of the bit line pre-charge circuit for the left and right memory cores, respectively, enabling power savings when a particular core is not in use.

[0056] The pre-charge signals PCH_L and PCH_R control the equalization of the bit lines prior to a read or write operation. When asserted, these signals turn on the PL1, PL2, PR1, and PR2 transistors, connecting the bit lines to the pre-charge voltage at nodes Nint1 and Nint2.

[0057] Transistors PL4 and PR4 act as equalization transistors, ensuring that the true and complement bit lines (BLTL and BLFL for the left core, BLTR and BLFR for the right core) are at the same potential prior to the start of an operation.

[0058] The asymmetric design of the memory cores (m x n for 12L and p x q for 12R) is reflected in the different number of bit line control circuits for each core, allowing for flexible memory configuration while maintaining individual core control. This design enables the SRAM to efficiently support partial word operations, activating only the necessary parts of the memory array and associated control circuitry based on the current operational requirements.

[0059] Figure 5A depicts Figure 1A the power dissipation profile of the complete SRAM design shown. This graph shows several distinct peaks of varying heights, representing different power dissipation levels during various operations. The dashed oval highlights a region of particular interest, where a cluster of high power dissipation peaks can be observed. These peaks correspond to periods of full memory access, where both the left and right memory banks are simultaneously active.

[0060] Figure 5B shows the power dissipation of the same SRAM design Figure 1A running in half-word mode. In this mode, only one of the two equally-sized memory banks is active at a time. This graph shows a similar overall pattern as Figure 5A but with significant differences in the highlighted region. Compared to Figure 5A the power dissipation peaks within the dashed oval appear lower in magnitude, indicating a reduction in power dissipation. This reduction is consistent with the expected behavior of half-word mode, where only half of the memory is active at any given time.

[0061] Figure 6A shows Figure 1B The power consumption curve for the full SRAM design shown. The graph shows a pattern similar to Figure 5A

[0062] Figure 6B depicts the power consumption of the SRAM design in Figure 1B running in partial word mode. This mode allows for the selection of activating the 8-bit memory bank, the 24-bit memory bank, or both. The graph shows a significant difference in the highlighted area compared to Figure 6A Figure 5B

[0063] The partial word functionality provides several advantages, including: dynamic power savings by allowing selective activation of memory banks based on immediate system needs, static power savings in scenarios where only a portion of the memory is needed for extended periods of time, flexibility in effectively using the asymmetric memory design for various modes of operation within a SOC, and fine control for precise management of the active memory portion through the two-bit PW signal. Thus, the asymmetric SRAM design described herein achieves enhanced efficiency and versatility, accommodating different operational requirements within a SOC while minimizing power usage.

[0064] It is clear that modifications and changes can be made to what has been described and shown herein without departing from the scope of the present disclosure.

[0065] While the present disclosure has been described with respect to a limited number of embodiments, those skilled in the art, having the benefit of this disclosure, can conceive of other embodiments without departing from the scope of what is disclosed. Furthermore, those skilled in the art can conceive of embodiments representing various combinations of the embodiments disclosed herein in various ways.​​​ < / m> < / x> < / x> < / x> < / x>

Claims

1. A static random access memory (SRAM) device, comprising: The first memory core has a first bit width; The second memory core has a second bit width that is different from the first bit width; The control section is configured to receive partial word signals and selectively enable or disable each of the first memory core and the second memory core based on the partial word signals, thereby allowing independent control of the first memory core and the second memory core.

2. The SRAM device according to claim 1, further comprising: The decoder circuit is coupled to the first memory core and the second memory core; and Multiple word line drivers are coupled to the decoder circuit, wherein the word line drivers are configured to be selectively enabled or disabled for each of the first and second memory cores based on the partial word signals; The word line driver includes: The first set of drivers is coupled to the word lines of the first memory core; The second set of drivers is coupled to the word lines of the second memory core; A first power control circuit is configured to selectively provide power to the first set of drivers based on the partial word signal; and A second power control circuit is configured to selectively provide power to the second set of drivers based on the partial word signal.

3. The SRAM device according to claim 1, wherein the control section comprises: A first level converter is configured to receive the first bit of the partial word signal; A second level converter is configured to receive the second bit of the partial word signal; A first logic circuit is coupled to the output of the first level converter and configured to generate a first sleep signal for the first memory core. and A second logic circuit is coupled to the output of the second level converter and is configured to generate a second sleep signal for the second memory core.

4. The SRAM device of claim 3, wherein the first logic circuit includes a NOR gate and an inverter, and wherein the second logic circuit includes a NOR gate and an inverter.

5. The SRAM device according to claim 1, further comprising: The first virtual power supply voltage circuit is coupled to the first memory core; and The second virtual power supply voltage circuit is coupled to the second memory core; in, Each of the first virtual power supply voltage circuit and the second virtual power supply voltage circuit is configured to selectively supply one of the full operating voltage and the data holding voltage to its respective memory core based on the partial word signal.

6. The SRAM device according to claim 5, wherein, Each of the first virtual power supply voltage circuit and the second virtual power supply voltage circuit includes: A first transistor is coupled between the supply voltage and the corresponding memory core, and the first transistor is controlled by the partial word signal; The first pair of transistors connected in series are coupled between the supply voltage and the corresponding memory core; and The second pair of transistors connected in series are coupled between the supply voltage and the corresponding memory core; The first pair of series-connected transistors and the second pair of series-connected transistors are controlled by a hold-mode signal.

7. The SRAM device according to claim 1, further comprising: The first set of bit line control circuits is coupled to the first memory core; and The second set of bit line control circuits is coupled to the second memory core; Each set of bit line control circuits is configured to be selectively enabled or disabled based on the partial word signal.

8. The SRAM device of claim 1, wherein the partial word signal comprises at least two bits.

9. A method for operating a static random access memory (SRAM) device, the method comprising: Receive partial word signals; and Based on the aforementioned partial word signals, each of the first memory core and the second memory core can be selectively enabled or disabled, thereby allowing independent control of the first memory core and the second memory core. The first memory core has a first bit width, and the second memory core has a second bit width that is different from the first bit width.

10. The method of claim 9, further comprising: Based on the partial word signals, the first set of word line drivers coupled to the first memory core are selectively enabled or disabled; and Based on the aforementioned partial word signals, the second set of word line drivers coupled to the second memory core are selectively enabled or disabled; in: Selectively enabling or disabling the first set of word line drivers includes controlling a first power control circuit to selectively provide power to a first set of inverters coupled to the word lines of the first memory core; and Selectively enabling or disabling the second set of word line drivers includes controlling a second power control circuit to selectively provide power to a second set of inverters coupled to the word lines of the second memory core.

11. The method of claim 9, further comprising: The first bit of the partial word signal is level-shifted; Level conversion is performed on the second bit of the partial word signal; Based on the first bit of the level shift, a first sleep signal is generated for the first memory core; and Based on the second bit of the level shift, a second sleep signal is generated for the second memory core.

12. The method according to claim 9, wherein: Generating the first sleep signal includes performing a NOR operation on the first bit of the level shift and the sleep signal, followed by an inversion operation; and Generating the second sleep signal includes performing a NOR operation on the second bit of the level shift and the sleep signal, followed by an inversion operation.

13. The method of claim 9, further comprising: Based on the partial word signal, one of the full operating voltage and the data holding voltage is selectively provided to the first memory core; and Based on the partial word signal, one of the full operating voltage and the data holding voltage is selectively provided to the second memory core.

14. The method of claim 9, further comprising: Based on the aforementioned partial word signals, the first set of bit line control circuits coupled to the first memory core are selectively enabled or disabled; and Based on the partial word signals, the second set of bit line control circuits coupled to the second memory core are selectively enabled or disabled.

15. The method of claim 9, further comprising: The SRAM device is operated in full-power mode by enabling the first memory core and the second memory core. The SRAM device is operated in a first partial power mode by enabling the first memory core and disabling the second memory core. The SRAM device is operated in a second partial power mode by enabling the second memory core and disabling the first memory core. and The SRAM device operates in low-power mode by disabling both the first and second memory cores.

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