Three-dimensional capacitor based on multistage tree-shaped interdigital structure
By employing a multi-level tree-like interdigitated three-dimensional capacitor in integrated circuits, the non-uniformity problem of fractal curve structures in photolithography and etching processes is solved, realizing a high-density and high-reliability capacitor design suitable for modular integration.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-19
- Publication Date
- 2026-03-24
AI Technical Summary
In the prior art, capacitors with fractal curve structures have non-uniformity issues in photolithography and etching processes, which leads to loss of control over critical dimensions and electric field concentration, affecting device reliability and service life.
A three-dimensional capacitor employing a multi-level tree-like interdigitated structure, including main interdigitates, sub-interdigitates, and third-level interdigitates, forms a regular interdigitated structure. Interdigitate gaps are formed on the surface of a silicon substrate using a dry etching process, and conductive and dielectric layers are covered at the interdigitate gaps to form a high-density capacitor array.
It achieves exponential growth in electrode area, obtains ultra-high capacitance density and high reliability, solves the problems of electric field concentration and process inhomogeneity, and is suitable for modular integration.
Smart Images
Figure CN121728784A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of microelectronics technology, and specifically relates to a high-density, high-reliability three-dimensional capacitor structure for use in integrated circuits and its manufacturing method. Background Technology
[0002] In integrated circuits and advanced packaging, capacitor performance directly impacts signal integrity and system stability. As chip feature sizes continue to shrink, higher demands are placed on capacitor density, reliability, and high-frequency characteristics. In existing technologies, fractal curve structures (such as FASS curves) are used in capacitor design to achieve longer electrode perimeters within a limited area. However, these structures have serious drawbacks in practical applications. Fractal structures are irregular patterns across an entire surface; their complexity and irregularity challenge the uniformity of photolithography and etching processes. Uneven etching rates for trenches with different orientations and curvatures can easily lead to loss of control over critical dimensions and inconsistent structural depths. Furthermore, the irregular image of fractal curves results in numerous abrupt changes in curvature radius. These locations generate electric field concentration effects, significantly reducing the breakdown voltage of the capacitor's dielectric layer and affecting device reliability and lifespan.
[0003] Therefore, considering the aforementioned technical problems, it is necessary to provide a new technical solution. Summary of the Invention
[0004] To at least address one of the technical problems existing in the prior art, the present invention aims to provide a three-dimensional capacitor based on a high-density multi-level tree-like interdigitated structure, the specific technical solution of which is as follows: This invention discloses a three-dimensional capacitor comprising a silicon substrate; A silicon trench is formed on the surface of the silicon substrate. At least a first electrode layer, a second electrode layer, and a dielectric layer separating the first electrode layer and the second electrode layer are provided on the inner surface of the silicon trench and the adjacent surface of the silicon substrate. The first electrode layer, the second electrode layer, and the dielectric layer form a deep trench structure. Multiple main interdigitates are formed on a silicon substrate, wherein the multiple main interdigitates are spaced apart from each other; Multiple sub-forks are formed on a silicon substrate, wherein the sub-forks are interleaved and connected to the main fork, and the main fork and the sub-forks have a certain angle, the angle being less than 90°. Both the main fork and the sub-forks are forks formed by etching silicon trenches on the surface of the silicon substrate.
[0005] As a preferred embodiment of the three-dimensional capacitor described in this invention, the main interdigitated finger and the sub-interdigitated finger form a multi-level tree-like interdigitated finger structure, which is a two-level structure.
[0006] As a preferred embodiment of the three-dimensional capacitor of the present invention, at least the main interdigitated fingers and the sub-interdigitated fingers form a multi-level tree-like interdigitated finger structure, and the multi-level tree-like interdigitated finger structure constitutes a standard unit.
[0007] As a preferred embodiment of the three-dimensional capacitor described in this invention, the plurality of main interdigitated fingers are arranged in parallel to each other to form a coplanar interdigitated finger structure.
[0008] As a preferred embodiment of the three-dimensional capacitor of the present invention, a plurality of sub-forked fingers are interleaved and connected to the main forked finger, and the main forked finger and the sub-forked fingers constitute a coplanar forked finger structure.
[0009] The sub-interdigital finger and the main interdigital finger connected thereto have a certain included angle, the included angle being between 20° and 80°.
[0010] In a preferred embodiment of the three-dimensional capacitor described in this invention, both the main interdigitated finger and the sub-interdigitated finger are columnar interdigitated fingers.
[0011] As a preferred embodiment of the three-dimensional capacitor described in this invention, the deep trench structure on the surface of the silicon substrate further forms a third-level interdigitated finger, which is connected to the sub-interdigitated finger; the main interdigitated finger, the sub-interdigitated finger and the third-level interdigitated finger form a multi-level tree-like interdigitated finger structure, which is a three-level structure.
[0012] As a preferred embodiment of the three-dimensional capacitor described in this invention, a plurality of third-level interdigitated fingers are interleaved and connected to the sub-interdigitated fingers to form a coplanar interdigitated finger structure.
[0013] As a preferred embodiment of the three-dimensional capacitor of the present invention, the third-level interdigitated finger and the sub-interdigitated finger connected thereto have a certain included angle, the included angle being from 20° to 80°.
[0014] As a preferred embodiment of the three-dimensional capacitor described in this invention, the third-stage interdigitated fingers are columnar interdigitated fingers.
[0015] As a preferred embodiment of the three-dimensional capacitor described in this invention, the main forked finger, the sub-forked finger, and the third-level forked finger are collectively referred to as forked fingers.
[0016] Preferably, the width of the interdigitated fingers ranges from 0.1 μm to 2 μm.
[0017] Preferably, the spacing between adjacent interdigitated fingers ranges from 0.1 μm to 2 μm.
[0018] As a preferred embodiment of the three-dimensional capacitor described in this invention, the standard cell has a size of n μm × n μm, where n ≥ 10.
[0019] As a preferred embodiment of the three-dimensional capacitor described in this invention, the standard unit size is modularly repeated and spliced to form a large-scale capacitor array.
[0020] As a preferred embodiment of the three-dimensional capacitor described in this invention, the silicon trench is formed at the interdigital gaps on the surface of the silicon substrate by a dry etching process.
[0021] In a preferred embodiment of the three-dimensional capacitor described in this invention, the silicon trench depth is 10 μm to 60 μm.
[0022] In a preferred embodiment of the three-dimensional capacitor described in this invention, the inner surface of the silicon trench and the adjacent surface of the silicon substrate are sequentially covered with a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer, and a third conductive layer, and the silicon trench is filled. The first electrode layer includes a first conductive layer and a third conductive layer, which are electrically connected to form the first electrode. The second electrode layer includes a second conductive layer, which forms the second electrode. The dielectric layer includes a first dielectric layer and a second dielectric layer.
[0023] Compared with the prior art, the technical solution of the present invention has at least one or more of the following beneficial effects: This invention employs a regular and controllable three-dimensional interdigitated structure, eliminating the problems of electric field concentration and process inhomogeneity caused by fractal curves. The invention creatively proposes a multi-level tree-like interdigitated structure of "main interdigitated finger - sub-interdigitated finger - third-level interdigitated finger." This structure maximizes the effective surface area of the electrodes in three-dimensional space, achieving exponential growth of the electrode area within a limited space through multi-level branching. This results in a capacitance density far exceeding that of traditional interdigitated capacitors, achieving ultra-high capacitance density, high reliability, and excellent electrical performance. Simultaneously, the use of a fixed n μm x n μm (n≥10µm) standard cell size facilitates modular, repetitive layout and splicing during the chip design phase, forming large-scale capacitor arrays and enabling modular integration.
[0024] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description
[0025] To more clearly illustrate the technical solution of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0026] Figure 1 This is a top view of a standard cell in an embodiment of the three-dimensional capacitor described in this invention. Figure 2 This is a top view of a standard cell of another embodiment of the three-dimensional capacitor described in this invention. Figure 3 This is a top view of the capacitor array structure of the three-dimensional capacitor described in this invention; Figure 4 This is a cross-sectional schematic diagram of the deep silicon trench structure of the three-dimensional capacitor described in this invention.
[0027] Wherein, 1-silicon substrate, 11-silicon trench, 12-main interdigitated finger, 13-sub-interdigitated finger, 14-third-level interdigitated finger, 15-frame finger, 111-first conductive layer, 112-first dielectric layer, 113-second conductive layer, 114-second dielectric layer, 115-third conductive layer, 116-first electrode lead-out layer, 117-second electrode lead-out layer. Detailed Implementation
[0028] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.
[0029] In the description of this invention, it should be understood that the terms "upper," "lower," "top," "bottom," "inner," "outer," "front end," "rear end," "both ends," "one end," and "the other end," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0030] In the description of this invention, unless otherwise explicitly specified and limited, the terms "provided with," "equipped with," "connected," "installed," "sleeved," "opened," and "fixed," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances. Example
[0031] Please see Figure 1-4 ,like Figure 1-4 As shown, the present invention provides a three-dimensional capacitor, which includes a silicon substrate 1; The silicon substrate 1 has a silicon trench 11. At least a first electrode layer, a second electrode layer and a dielectric layer separating the first electrode layer and the second electrode layer are provided on the inner surface of the silicon trench and the adjacent surface of the silicon substrate 1. The first electrode layer, the second electrode layer and the dielectric layer form a deep trench structure. A plurality of main interdigitated fingers 12 are formed on the surface of the silicon substrate 1, wherein the plurality of main interdigitated fingers 12 are arranged at intervals. A plurality of sub-forks 13 are formed on the surface of the silicon substrate 1, wherein the sub-forks 13 are interleaved and connected to the main fork 12, and the main fork 12 and the sub-forks 13 have a certain angle, the angle being less than 90°. On the silicon substrate, both the main fork 12 and the sub-forks 13 are forks formed by etching silicon trenches 11 on the surface of the silicon substrate.
[0032] The main interdigitated finger 12 and the sub-interdigitated finger 13 form a multi-level tree-like interdigitated finger structure, which constitutes a standard unit. In this example, the multi-level tree-like interdigitated finger structure is constructed using a sacrificial layer process.
[0033] The sub-forked fingers 13 are arranged alternately on the main forked fingers 12. This can be because the sub-forked fingers 13 are arranged alternately on the main forked fingers 12 where they are located, or the sub-forked fingers 13 on the main forked fingers 12 are arranged alternately with the sub-forked fingers 13 on the adjacent main forked fingers 12, or both of the above situations exist simultaneously, depending on the specific layout required by the design.
[0034] In the example, the main interdigitated finger 12 and the sub-interdigitated finger 13 form a multi-level tree-like interdigitated finger structure, which is a two-level structure.
[0035] Preferably, each standard unit further includes a frame finger 15, and the main fork finger 12 is provided with a frame finger 15 at its end along the length direction, with the main fork finger 12 connected to the frame finger 15. Preferably, both ends of the main fork finger 12 are provided with frame fingers 15 along the length direction, and multiple main fork fingers 12 are sequentially and alternately connected to the frame fingers 15 at both ends. The sequential and alternate connection of multiple main fork fingers 12 to the frame fingers 15 at both ends means, for example, one main fork finger 12 is connected to the frame finger 15 on the left, the next adjacent main fork finger 12 is connected to the frame finger 15 on the right, the next adjacent main fork finger 12 is connected to the frame finger 15 on the left, and so on... etc. Of course, this patent is not limited to this, and other connection methods can be used according to actual needs. In the example, the frame finger and the main fork finger 12 are arranged perpendicularly. Preferably, the frame finger between two adjacent standard units is a shared frame finger for the two standard units. In the example, the width of the frame finger 15 is the same as the width of the main fork finger 12. In the example, the frame finger is set perpendicular to the main fork finger 12.
[0036] Preferably, the plurality of main interdigitated fingers 12 are arranged in parallel to each other to form a coplanar interdigitated finger structure.
[0037] Preferably, the plurality of sub-forks 13 are staggered and connected to the main fork 12, and the main fork 12 and the sub-forks 13 form a coplanar fork structure. More preferably, the sub-forks 13 and the main fork 12 connected to them have a certain angle, the angle ranging from 20° to 80°. In the example, the plurality of sub-forks 13 are arranged in parallel.
[0038] Preferably, the standard unit has a size of n μm × n μm, where n ≥ 10.
[0039] Preferably, the standard unit size is formed into a large-scale capacitor array through modular repeating layout and splicing.
[0040] Preferably, the silicon trench 11 is formed at the interdigital gaps on the surface of the silicon substrate 1 by a dry etching process.
[0041] In a preferred embodiment, the deep trench structure on the surface of the silicon substrate 1 further forms a third-level interdigitated finger 14, which is connected to the sub-interdigitated finger 13; the main interdigitated finger 12, the sub-interdigitated finger 13 and the third-level interdigitated finger 14 form a multi-level tree-like interdigitated finger structure, which is a three-level structure.
[0042] Preferably, multiple third-level interdigitated fingers 14 are staggered on the sub-interdigitated fingers 13 to form a coplanar interdigitated finger structure.
[0043] Preferably, the third-level interdigitated finger 14 and the sub-interdigitated finger 13 connected thereto have a certain included angle, the included angle being between 20° and 80°.
[0044] In a preferred embodiment, the main interdigitated finger 12, the sub-interdigitated finger 13, and the third-level interdigitated finger 14 are collectively referred to as interdigitated fingers.
[0045] Preferably, the width of the interdigitated fingers ranges from 0.1 μm to 2 μm. More preferably, the width of the interdigitated fingers is not less than 0.2 μm. Preferably, the spacing between adjacent interdigitated fingers ranges from 0.1 μm to 2 μm. More preferably, the spacing between adjacent interdigitated fingers is not less than 0.2 μm.
[0046] Further preferably, the aspect ratio of the silicon trench is no greater than 30:1.
[0047] In a preferred embodiment, the inner surface of the silicon trench 11 and the adjacent surface of the silicon substrate 1 are sequentially covered with a first conductive layer 111, a first dielectric layer 112, a second conductive layer 113, a second dielectric layer 114, and a third conductive layer 115, and the silicon trench 11 is filled. The first electrode layer includes a first conductive layer 111 and a third conductive layer 115, which are electrically connected to form the first electrode. The second electrode layer includes a second conductive layer 113, which forms the second electrode. The dielectric layer includes a first dielectric layer 112 and a second dielectric layer 114.
[0048] In the example, the dielectric layer covers the interdigital surface.
[0049] In the example, the first conductive layer 111, the first dielectric layer 112, the second conductive layer 113, the second dielectric layer 114, and the third conductive layer 115 form a high-density three-dimensional capacitor.
[0050] Preferably, the second dielectric layer 114 has a first conductive channel that sequentially penetrates the second dielectric layer 114, the second conductive layer 113, and the first dielectric layer 112 to the first conductive layer 111. When the third conductive layer 115 is covered, the conductive material of the third conductive layer 115 fills the first conductive channel, connecting the third conductive layer 115 and the first conductive layer 111. A first insulating interlayer is provided on the inner wall of the first conductive channel at a position corresponding to the second conductive layer 113. The first insulating interlayer prevents the first conductive layer 111 and the third conductive layer 115 from being electrically connected to the second conductive layer 113. In this example, the second conductive layer 113 is also connected to a first electrode lead-out layer 116 for connection to the outside.
[0051] Preferably, a second conductive channel is formed on the surface of the third conductive layer 115, the second conductive channel penetrating the second dielectric layer to the second conductive layer 113, and a second insulating interlayer is also provided on the inner wall of the second conductive channel, the second insulating interlayer separating the second conductive layer 113 and the third conductive layer 115. In the example, the second conductive channel is filled with a conductive material, and the conductive material is connected to a second electrode lead-out layer 117 for connection to the outside. The first electrode lead-out layer and the second electrode lead-out layer are not connected.
[0052] Example 1 See Figure 1 and Figure 3-4 This embodiment provides a three-dimensional capacitor with a two-dimensional interdigitated tree structure, which uses a standard unit size of 10μm × 10μm. The three-dimensional capacitor includes a silicon substrate 1, and a silicon trench 11 is formed on the surface of the silicon substrate. The inner surface of the silicon trench 11 and the adjacent surface of the silicon substrate 1 are sequentially covered with a first conductive layer 111, a first dielectric layer 112, a second conductive layer 113, a second dielectric layer 114 and a third conductive layer 115. The first conductive layer 111 and the third conductive layer 115 are electrically connected to form a first electrode. The specific electrical connection method will not be repeated. The second conductive layer 113 forms a second electrode. The first conductive layer 111, the first dielectric layer 112, the second conductive layer 113, the second dielectric layer 114 and the third conductive layer 115 form a deep silicon trench structure to form a high-density three-dimensional capacitor. The deep trench structure on the silicon substrate 1 forms multiple main interdigitates 12 and multiple sub-interdigitates 13. The sub-interdigitates 13 are connected to the main interdigitates 12, forming a two-level tree-like interdigitate structure of main interdigitates and sub-interdigitates. In the example, the multiple main interdigitates are arranged in parallel to each other, forming a coplanar interdigitate structure. In the example, the included angle between the sub-interdigitate 13 and the main interdigitate 12 connected to it is 45°, forming a coplanar interdigitate structure. In the example, the width of the interdigitates and the spacing between adjacent interdigitates are both in the range of 0.1μm to 2μm. In this embodiment, the standard cell size is modularly repeated and spliced to form a 5x5 standard cell capacitor array. In the example, silicon trenches 11 are formed on the surface of the silicon substrate 1 at the interdigitate gaps using a dry etching process, and the depth of the silicon trenches 11 is 10μm to 60μm.
[0053] Example 2 See Figure 2 and Figure 4This embodiment provides a three-dimensional capacitor with a two-level tree-like interdigitated structure, which uses a standard unit size of 10μm × 10μm. The three-dimensional capacitor includes a silicon substrate 1, and a silicon trench 11 is formed on the surface of the silicon substrate. The inner surface of the silicon trench 11 and the adjacent surface of the silicon substrate 1 are sequentially covered with a first conductive layer 111, a first dielectric layer 112, a second conductive layer 113, a second dielectric layer 114 and a third conductive layer 115. The first conductive layer 111 and the third conductive layer 115 are electrically connected to form a first electrode. The specific electrical connection method will not be repeated. The second conductive layer 113 forms a second electrode. The first conductive layer 111, the first dielectric layer 112, the second conductive layer 113, the second dielectric layer 114 and the third conductive layer 115 form a deep silicon trench structure to form a high-density three-dimensional capacitor. The deep trench structure on the silicon substrate 1 forms multiple main interdigitates 12, multiple sub-interdigitates 13 and multiple third-level interdigitates 14. The sub-interdigitates 13 are connected to the main interdigitates 12, and the third-level interdigitates 14 are connected to the sub-interdigitates 13, forming a three-level tree-like interdigitate structure of main interdigitates-sub-interdigitates-third-level interdigitates.
[0054] In the example, multiple main interdigitated fingers are arranged parallel to each other, forming a coplanar interdigitated structure. In the example, the angle between the main interdigitated fingers and the sub-interdigitated fingers is 45°, forming a coplanar interdigitated structure. In the example, the angle between the sub-interdigitated fingers and the third-level interdigitated finger 14 is 45°, forming a coplanar interdigitated structure. In the example, the width of the interdigitated fingers and the spacing between adjacent interdigitated fingers range from 0.1 μm to 2 μm. In the example, standard cell sizes are modularly repeated and spliced to form a 5x5 standard cell capacitor array. In the example, silicon trenches 11 are formed on the surface of the silicon substrate 1 at the interdigitated gaps using a dry etching process, and the depth of the silicon trenches 11 is 10 μm to 60 μm.
[0055] It should be noted that, unless otherwise specified, all features in the above embodiments or embodiments described herein can be freely combined.
[0056] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "preferred embodiments," "other embodiments," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.
[0057] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications and variations to the above embodiments within the scope of the present invention.
Claims
1. A three-dimensional capacitor, characterized in that, Including silicon substrate (1); The silicon substrate (1) has a silicon trench (11) formed on its surface. The inner surface of the silicon trench (11) and the adjacent surface of the silicon substrate (1) are provided with at least a first electrode layer, a second electrode layer and a dielectric layer that separates the first electrode layer and the second electrode layer. The first electrode layer, the second electrode layer and the dielectric layer form a deep trench structure. A plurality of main interdigitated fingers (12) are formed on a silicon substrate (1), wherein the plurality of main interdigitated fingers (12) are arranged at intervals; Multiple sub-forks (13) are formed on a silicon substrate (1), wherein the sub-forks (13) are interleaved and connected to the main fork (12), and the main fork (12) and the sub-forks (13) have a certain angle, the angle being less than 90°. Both the main fork (12) and the sub-forks (13) are forks formed by etching silicon trenches (11) on the surface of the silicon substrate.
2. The three-dimensional capacitor according to claim 1, characterized in that, The main interdigitated finger (12) and the sub-interdigitated finger (13) form a multi-level tree-like interdigitated finger structure, which is a two-level structure; and / or Multiple main interdigitated fingers (12) are arranged in parallel to each other to form a coplanar interdigitated finger structure.
3. The three-dimensional capacitor according to claim 1 or 2, characterized in that, Multiple sub-interdigitates (13) are interleaved and connected to the main interdigitate (12), and the main interdigitate (12) and the sub-interdigitates (13) form a coplanar interdigitate structure; and / or The sub-interdigital finger (13) and the main interdigital finger (12) connected thereto have a certain included angle, the included angle being between 20° and 80°.
4. The three-dimensional capacitor according to claim 1, characterized in that, The deep trench structure on the surface of the silicon substrate (1) also forms a third-level interdigitated finger (14), which is connected to the sub-interdigitated finger (13); the main interdigitated finger (12), the sub-interdigitated finger (13) and the third-level interdigitated finger (14) form a multi-level tree-like interdigitated finger structure, which is a three-level structure.
5. The three-dimensional capacitor according to claim 2 or 4, characterized in that, The multi-level tree-like interdigitated structure constitutes a standard unit.
6. The three-dimensional capacitor according to claim 1, characterized in that, The standard units are modularly repeated and spliced to form a large-scale capacitor array; and / or The standard unit has a size of n μm × n μm, where n ≥ 10.
7. The three-dimensional capacitor according to claim 4, characterized in that, Multiple third-level interdigitated fingers (14) are interleaved and connected to the sub-interdigitated fingers (13) to form a coplanar interdigitated finger structure; and / or The third-level interdigitated finger (14) and the sub-interdigitated finger (13) connected thereto have a certain included angle, the included angle ranging from 20° to 80°; and / or Both the main interdigital finger (12) and the subinterdigital finger (13) are columnar interdigital fingers.
8. The three-dimensional capacitor according to claim 4, characterized in that, The main interdigitated finger (12), the sub-interdigitated finger (13), and the third-level interdigitated finger (14) are collectively referred to as interdigitated fingers; The width of the interdigitated fingers ranges from 0.1 μm to 2 μm; and / or The spacing between adjacent interdigitates ranges from 0.1 μm to 2 μm.
9. The three-dimensional capacitor according to claim 1, characterized in that, The silicon trench (11) is formed at the interdigital gaps on the surface of the silicon substrate (1) by a dry etching process; and / or The depth of the silicon trench (11) is 10 μm to 60 μm.
10. The high-density three-dimensional capacitor according to claim 1, characterized in that, The inner surface of the silicon trench (11) and the adjacent surface of the silicon substrate (1) are sequentially covered with a first conductive layer (111), a first dielectric layer (112), a second conductive layer (113), a second dielectric layer (114) and a third conductive layer (115), and the silicon trench (11) is filled. The first electrode layer includes a first conductive layer (111) and a third conductive layer (115), which are electrically connected to form the first electrode. The second electrode layer includes a second conductive layer (113), which forms the second electrode. The dielectric layer includes a first dielectric layer (112) and a second dielectric layer (114).