Etching method
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-31
- Publication Date
- 2026-03-24
AI Technical Summary
In existing technologies, the etching selectivity of the dielectric layer is relatively low compared to that of the photoresist, which leads to premature consumption of the photoresist when etching high aspect ratio holes/trenches, resulting in problems such as developer residue or pattern collapse.
Before etching, the photoresist mask is hardened by forming a plasma using a mixture of SF6 and inert gas to form a dense hardened layer on the surface of the photoresist mask. Subsequently, a mixed gas plasma of CHF3, Ar and CF4 is used to etch the dielectric layer.
This improves the etching selectivity of the dielectric layer relative to the photoresist mask, ensuring that the photoresist mask is less likely to fail prematurely during the etching process. It also enhances the etching rate of the dielectric layer and the controllability of the etching process, avoiding developer residue or pattern collapse caused by premature consumption of the photoresist mask.
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Figure CN121728987A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure belongs to the technical field of semiconductor technology, and particularly relates to an etching method. BACKGROUND
[0002] High aspect ratio (HAR) dielectric etching hole / trench is a key technology in advanced semiconductor manufacturing and advanced packaging. For example, a very deep via hole (depth up to tens to hundreds of microns) is etched on a silicon substrate, and then a metal (such as copper) is filled to realize vertical conduction. Or a very dense and deep (also in the micron level) trench array is etched on a silicon wafer, and then a dielectric layer and a conductor layer are deposited to form a capacitor.
[0003] In the related art, in order to form a HAR dielectric etching hole / trench, a dielectric layer is generally deposited on a substrate, and a photoresist (PR) is spin-coated, and then a target pattern (such as a small hole or a via array) is formed on the photoresist by exposure and development. Subsequently, using the photoresist as a mask, a target pattern is transferred to the dielectric layer using a plasma etching process to obtain a HAR dielectric etching hole.
[0004] However, since the etching selectivity ratio of the dielectric layer relative to the photoresist (i.e., the ratio of the dielectric etching rate to the photoresist etching rate) is low (usually about 2), in order to avoid etching process failure caused by premature complete consumption of the mask (photoresist), the thickness of the photoresist is often increased. However, when the etching hole critical dimension (CD) is small and the photoresist thickness is increased, it is easy to cause development liquid residue or pattern collapse. SUMMARY
[0005] The etching method provided by the embodiments of the present disclosure can improve the etching selectivity ratio of the dielectric layer relative to the photoresist mask. The technical solutions are as follows:
[0006] The etching method provided by the embodiments of the present disclosure can improve the etching selectivity ratio of the dielectric layer relative to the photoresist mask. The technical solutions are as follows:
[0007] A substrate structure is provided, which includes a substrate and a dielectric layer deposited on the substrate; a patterned photoresist mask is formed on the dielectric layer; a hardening treatment is performed on the photoresist mask; and a dry etching is performed on the dielectric layer under the cover of the treated photoresist mask to form a hollow structure in the dielectric layer.
[0008] In another implementation manner of the present disclosure, the hardening treatment on the photoresist mask includes: using a first plasma formed by a mixed gas of SF6 and an inert gas to react with the photoresist mask to form a dense hardening layer on the surface of the photoresist mask.
[0009] In yet another implementation manner of the present disclosure, in the process that the first plasma formed by the mixed gas of SF6 and inert gas reacts with the photoresist mask to form a dense hardened layer on the surface of the photoresist mask, the flow rate of the SF6 gas is 60-150 sccm, the flow rate of the inert gas is 60-150 sccm, and the operation time of the first plasma is 10-30 s.
[0010] In yet another implementation manner of the present disclosure, in the process that the first plasma formed by the mixed gas of SF6 and inert gas reacts with the photoresist mask to form a dense hardened layer on the surface of the photoresist mask, the pressure of the reaction chamber in which the SF6 and the inert gas are located is 100-150 mTorr.
[0011] In yet another implementation manner of the present disclosure, the dry etching of the medium layer under the mask of the processed photoresist mask to form a hollow structure in the medium layer comprises:
[0012] The second plasma formed by the mixed gas of CHF3, Ar and CF4 is used to etch the medium layer under the mask of the processed photoresist mask.
[0013] In yet another implementation manner of the present disclosure, the etching time of the second plasma to the medium layer is 800-900 s, and the etching pressure is 220-280 mTorr.
[0014] In yet another implementation manner of the present disclosure, in the process that the second plasma formed by the mixed gas of CHF3, Ar and CF4 etches the medium layer, the flow rate of the CHF3 gas is 20-80 sccm, the flow rate of the Ar gas is 100-200 sccm, and the flow rate of the CF4 gas is 20-100 sccm.
[0015] In yet another implementation manner of the present disclosure, the thickness of the medium layer is 3.4-4.5 μm.
[0016] In yet another implementation manner of the present disclosure, the medium layer is SiO2.
[0017] In yet another implementation manner of the present disclosure, the etching selectivity ratio of the medium layer to the processed photoresist mask is greater than 5.
[0018] The technical scheme provided by the embodiments of the present disclosure has the beneficial effects that:
[0019] When HAR dielectric etched holes are achieved using the etching method provided in this embodiment, the photoresist mask is hardened before etching the dielectric layer. Since the cross-linking density of the hardened photoresist mask increases significantly, the etching rate of the hardened photoresist mask decreases significantly under the same etching conditions. This improves the etching selectivity of the dielectric layer relative to the photoresist mask, ultimately resulting in HAR dielectric etched holes / trenches.
[0020] In other words, because a hardened photoresist mask is more resistant to physical bombardment and chemical erosion, its consumption rate will be lower under the same etching conditions. Furthermore, hardening the photoresist mask allows it to withstand more demanding etching conditions in subsequent etching processes. Therefore, the etching intensity can be increased to improve the etching rate of the dielectric layer without worrying about premature photoresist mask failure. This also allows for increasing the etching rate of the dielectric layer by changing the etching conditions, thereby improving the etching selectivity of the dielectric layer relative to the photoresist mask. Attached Figure Description
[0021] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0022] Figure 1 This is a flowchart of an etching method provided in an embodiment of this disclosure;
[0023] Figure 2 This is a flowchart of another etching method provided in this embodiment of the disclosure;
[0024] Figure 3 This is a schematic diagram of the film structure of the substrate before etching provided in an embodiment of this disclosure;
[0025] Figure 4 This is a schematic diagram of the film structure of the dielectric etched hole obtained after etching according to an embodiment of this disclosure.
[0026] The symbols in the diagram represent the following meanings:
[0027] 100. Base structure;
[0028] 101. Substrate;
[0029] 102, dielectric layer; 1020, dielectric etching via;
[0030] 103. Photoresist mask; 1030. Target window. Detailed Implementation
[0031] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.
[0032] This disclosure provides an etching method, such as... Figure 1 As shown, the etching methods include:
[0033] S101: Provides a substrate structure.
[0034] The substrate structure includes the substrate and the dielectric layer deposited on the substrate.
[0035] The substrate is used to provide a deposition base for the dielectric layer.
[0036] S102: Form a patterned photoresist mask on the dielectric layer.
[0037] S103: Harden the photoresist mask.
[0038] S104: Dry etching is performed on the dielectric layer under the cover of the processed photoresist mask to form a hollow structure in the dielectric layer.
[0039] When HAR dielectric etched holes are achieved using the etching method provided in this embodiment, the photoresist mask is first hardened before etching the dielectric layer using a hardened photoresist mask via a second plasma. Since the cross-linking density of the hardened photoresist mask increases significantly, the etching rate of the hardened photoresist mask decreases significantly under the same etching conditions. This improves the etching selectivity of the dielectric layer relative to the photoresist mask, ultimately resulting in HAR dielectric etched holes / trenches.
[0040] In other words, because a hardened photoresist mask is more resistant to physical bombardment and chemical erosion, its consumption rate will be lower under the same etching conditions. Furthermore, hardening the photoresist mask allows it to withstand more demanding etching conditions in subsequent etching processes. Therefore, the etching intensity can be increased to improve the etching rate of the dielectric layer without worrying about premature photoresist mask failure. This also allows for increasing the etching rate of the dielectric layer by changing the etching conditions, thereby improving the etching selectivity of the dielectric layer relative to the photoresist mask.
[0041] In this embodiment of the disclosure, hardening the photoresist mask enables it to form a denser and more robust three-dimensional network structure, thereby increasing its crosslinking density.
[0042] On the other hand, embodiments of this disclosure also provide another etching method, such as Figure 2 As shown, the etching method includes:
[0043] S201: Provide a base structure.
[0044] The substrate structure includes a substrate and a dielectric layer deposited on the substrate.
[0045] Alternatively, the substrate may include any one of sapphire, SiC, Si, and GaN.
[0046] These substrates have stable crystal structures and high mechanical strength, making them suitable for the epitaxial growth of GaN-based optoelectronic devices and effectively reducing defect density.
[0047] In other examples, the substrate can also be any known semiconductor material, such as silicon, silicon-germanium, silicon-on-insulator, or silicon-on-sapphire substrates. Alternatively, the substrate can be a substrate that has already undergone front-end integrated circuit processes (e.g., manufacturing electronic components such as transistors, capacitors, resistors, diodes, etc.) and some back-end processes (e.g., bottom-level contact holes and bottom-level metal wiring, etc.).
[0048] In this embodiment, the substrate is a Si substrate. This can significantly reduce costs.
[0049] Alternatively, when depositing the dielectric layer on the substrate, any film deposition process can be used to deposit the dielectric layer on the substrate.
[0050] Optionally, the dielectric layer is a Si-containing dielectric layer.
[0051] In this embodiment of the disclosure, the thickness of the dielectric layer is 3.4-4.5 μm, and the dielectric layer is SiO2. For example, the thickness of the SiO2 dielectric layer is 4 μm.
[0052] For example, when depositing an SiO2 dielectric layer on a substrate, plasma-enhanced chemical vapor deposition (PECVD) can be used. That is, the dielectric layer is formed using a PECVD device.
[0053] During the operation, the substrate is first placed in a wet cleaning tank in front of the PECVD equipment and rinsed with standard RCA cleaning solution or dilute hydrofluoric acid (DHF), then dried with high-purity nitrogen or by spin drying. A clean surface ensures good adhesion and uniformity of the deposited film.
[0054] The RCA cleaning solution includes SC-1 (solution 1) and SC-2 (solution 2). SC-1's main components are ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and deionized water (H2O), with a typical volume ratio of 1:1:5 to 1:2:7. Its function includes removing particulate matter, organic contaminants, and some metallic impurities from the silicon wafer surface. The cleaning effect is achieved through the oxidation of H2O2 and the complexation of NH4OH, while simultaneously forming a hydrophilic silica protective film.
[0055] SC-2 (solution No. 2) is composed of hydrochloric acid (HCl), H2O2, and deionized water, with a typical ratio of HCl to H2O2 of 1:1:6 to 1:2:8. It is mainly used to remove residual metal ions (such as sodium, iron, and magnesium) by converting metallic contaminants into soluble substances through the dissolving power of HCl and the oxidizing effect of H2O2.
[0056] Next, the cleaned substrate is removed and precisely placed onto the base within the process chamber of the PECVD equipment. The chamber is then closed, and the vacuum pump begins operation, evacuating the chamber to a high vacuum (the base vacuum is typically up to 10). -6 (Torque level) to remove impurities such as oxygen and water vapor from the air and prevent them from contaminating the membrane.
[0057] The base begins heating, raising the substrate to the preset process temperature. Once the temperature stabilizes, an inert gas (such as N2) is introduced into the chamber, and a vacuum is continuously pumped out to "purge" the chamber and ensure a stable and pure environment.
[0058] Then comes the deposition process, in which reactive gases (such as SiH4 and N2O) are introduced into the chamber, and the chamber pressure is maintained at a stable and appropriate level to form a dielectric layer.
[0059] S202: Forming a patterned photoresist mask on the dielectric layer.
[0060] Optionally, step S202 includes the following steps:
[0061] 2021: Spin coating, uniformly spin coating a layer of photoresist (PR) onto the surface of the deposited dielectric layer.
[0062] The purpose of this step is to form a uniform, defect-free, smooth polymer film.
[0063] 2022: Soft baking, which involves heating the photoresist to evaporate most of the solvent in the photoresist, thus solidifying and stabilizing it.
[0064] 2023: Exposure, using a lithography machine, allows ultraviolet light to pass through a mask etched with the target pattern, selectively irradiating the photoresist.
[0065] The areas exposed to light will undergo a chemical reaction and will be dissolved during subsequent development.
[0066] The purpose of exposure is to transfer the pattern on the photomask to the photoresist in the form of a latent image.
[0067] 2023: Development involves immersing the exposed substrate structure in the developer. For positive photoresist, the photoresist in the exposed areas is dissolved, exposing windows of the dielectric layer; the photoresist in the unexposed areas remains. At this point, a patterned photoresist mask is formed.
[0068] 2024: Hard bake, the substrate structure is heated again to further harden the photoresist mask, improve its adhesion to the dielectric layer and its resistance to etching in subsequent etching processes.
[0069] In this embodiment, the thickness of the photoresist mask is 1.5-2.0 μm. This thickness range meets the requirements of high-resolution photolithography while providing sufficient etching resistance to prevent structural collapse or sidewall drilling during subsequent plasma etching due to excessive thinness. Moreover, a thickness of 1.5-2.0 μm can reduce development defects (such as residue or over-etching) caused by uneven developer penetration, thereby improving pattern fidelity.
[0070] For example, the photoresist mask has a thickness of 1.7 μm. This thickness can reduce development defects.
[0071] S203: Harden the photoresist mask.
[0072] Optionally, step S203 includes the following steps:
[0073] A first plasma, formed using a mixture of SF6 and inert gas, reacts with a photoresist mask to form a dense, hardened layer on the surface of the photoresist mask.
[0074] This process is typically performed on a reactive ion etching (RIE) machine or a dedicated plasma stripping / processing machine.
[0075] In actual operation, a substrate with a patterned photoresist mask is placed into the reaction chamber of the RIE.
[0076] Then, a mixture of SF6 and inert gas is introduced to generate the first plasma.
[0077] The generation process of the first plasma: During reactive ion etching, a mixture of SF6 and He gas is introduced into the reaction chamber, and then a high-frequency electric field greater than the gas breakdown critical value is applied. Under the action of the strong electric field, stray electrons accelerated by the high-frequency electric field randomly collide with gas molecules or atoms. When the electron energy is large enough, secondary electron emission occurs, which in turn continuously excites or ionizes gas molecules, forming the first plasma.
[0078] The role of SF6: SF6 decomposes in plasma to produce fluorine atoms (F). Fluorine atoms have strong chemical reactivity and can react with organic polymers in the photoresist mask, breaking the polymer chains of the photoresist mask and changing its structure. This results in the formation of a dense hardened layer on the surface of the photoresist mask, thus hardening the photoresist mask.
[0079] The inert gas is helium (He). He mainly serves to dilute SF6 gas, regulate plasma properties, and improve etching uniformity in the gas mixture. The presence of He makes the ion energy distribution in the first plasma more uniform, reducing etching inconsistencies caused by uneven ion energy on the photoresist mask surface, thus contributing to a more stable and uniform photoresist curing effect.
[0080] In other words, by introducing a mixture of SF6 and He gas into the reaction chamber, a dense hardened layer can be formed on the surface of the photoresist mask under extremely low power, short time, and non-etching conditions, thereby achieving the purpose of hardening the photoresist mask.
[0081] In other words, in this embodiment, hardening the photoresist mask refers to treating the surface of the photoresist mask with a first plasma formed by a mixture of SF6 and inert gas to densify the surface of the photoresist mask and enhance its resistance to etching.
[0082] In other examples, the inert gas is also Ar or another.
[0083] Optionally, during the process of reacting a first plasma formed using a mixture of SF6 and inert gas with a photoresist mask to form a dense hardened layer on the surface of the photoresist mask, the SF6 gas flow rate is 60-150 sccm (150 standard cubic centimeters per minute), the inert gas flow rate is 60-150 sccm, and the working time of the first plasma is 10-30 s.
[0084] Moreover, during the process of reacting the first plasma formed using a mixture of SF6 and inert gas with the photoresist mask to form a dense hardened layer on the surface of the photoresist mask, the pressure of the reaction chamber containing the SF6 and inert gas is 100-150 millitor.
[0085] In this embodiment, during the reaction of a first plasma formed using a mixture of SF6 and inert gas with a photoresist mask to form a dense hardened layer on the surface of the photoresist mask, the SF6 gas flow rate is 1000 sccm, the He gas flow rate is 100 sccm, and the working time of the first plasma is 20 s. The pressure in the reaction chamber is 125 mTorr. The source power (the radio frequency power that excites the plasma in the reaction chamber) is 100 W.
[0086] In this way, fluorine radicals (F) in the first plasma formed by SF6 can react with the photoresist mask (such as polymethyl methacrylate, PMMA) to replace the CH bonds with a stronger, more inert, and denser carbon-fluorine bond structure, thereby forming a dense hardened layer on the surface of the photoresist mask through a densification effect.
[0087] S204: Dry etching is performed on the dielectric layer under the cover of the processed photoresist mask to form a hollow structure in the dielectric layer.
[0088] Optionally, S204 includes:
[0089] Under the cover of the processed photoresist mask, the dielectric layer is etched using a second plasma formed by a mixture of CHF3, Ar and CF4 gases.
[0090] The etching time of the second plasma on the dielectric layer is 800-900s, and the etching pressure is 220-280 millitor.
[0091] Furthermore, during the etching of the dielectric layer using a second plasma formed by a mixture of CHF3, Ar, and CF4 gases, the CHF3 gas flow rate is 20-80 sccm, the Ar gas flow rate is 100-200 sccm, and the CF4 gas flow rate is 20-100 sccm.
[0092] In this embodiment, during the etching of the dielectric layer using a second plasma formed by a mixture of CHF3, Ar, and CF4 gases, the CHF3 gas flow rate is 50 sccm, the Ar gas flow rate is 150 sccm, and the CF4 gas flow rate is 60 sccm. The etching time is 857 s, and the etching pressure is 250 mTorr.
[0093] The F radicals generated from the decomposition of CHF3 react with the dielectric layer (such as SiO2) to generate volatile products (such as SiF4), while the physical bombardment effect of Ar enhances anisotropic etching. The addition of CF4 promotes the deposition of CFx polymers on the sidewalls and bottom of the photoresist mask, forming a protective layer, significantly improving the etching selectivity of the photoresist mask and preventing premature failure of the photoresist mask.
[0094] The high flow rate of Ar (150 sccm) reduces sidewall roughness through ion bombardment, while suppressing the micromask effect, ensuring etching uniformity on large-size wafers.
[0095] The pressure range (220-280 mTorr) balances the mean free path of ions with the concentration of reactive gases, avoiding a decrease in etching rate due to excessive pressure or uneven polymer deposition due to excessively low pressure.
[0096] Moreover, this gas ratio (CHF3:Ar4:CF4≈1:3:1.2) can stably remove the dielectric layer within an etching time of 800-900s, while ensuring complete penetration without damaging the substrate structure through etching control.
[0097] As can be seen, the above process is suitable for etching contact holes with high aspect ratios.
[0098] In this embodiment, the etching selectivity ratio between the dielectric layer and the processed photoresist mask is greater than 5. This allows the above process to be applied to high aspect ratio contact hole etching, where the aspect ratio can reach greater than 4.
[0099] S205: Remove the photoresist mask.
[0100] After etching is complete, the photoresist mask is removed by dry or wet methods, and the surface oxides are removed.
[0101] In this embodiment of the disclosure, the photoresist mask is hardened using SF6 and He gases. Since the photoresist mask itself is a polymer, in the atmosphere of He inert gas, SF6 plasma makes the internal components of the polymer cross-link more tightly, thereby hardening the photoresist mask and increasing the dielectric selectivity ratio (PR) of the photoresist mask from 2.5 to greater than 5 (which can be 5.1).
[0102] The embodiments of this disclosure are applied to specific examples.
[0103] Figure 3 This is a schematic diagram of the film structure of the substrate before etching provided in the embodiments of this disclosure, as shown below. Figure 3 As shown, the substrate structure 100 before etching includes a substrate 101, a dielectric layer 102 deposited on the substrate 101, and a photoresist mask 103 spin-coated on the dielectric layer 102.
[0104] The photoresist mask 103 has a target window 1030.
[0105] Figure 4 This is a schematic diagram of the film structure of the dielectric etched hole obtained after etching according to an embodiment of this disclosure, as shown below. Figure 4 As shown, the method described above is used to... Figure 3 After etching the structure, you can obtain Figure 4The corresponding medium etching hole is 1020.
[0106] By comparison, without adding step S203 (i.e., without hardening the photoresist mask before etching), directly etching through S204 after step S202 results in a significantly smaller hole depth in the dielectric layer SiO2 formed by the dielectric etching process. Figure 4 The depth of the dielectric etching holes formed in the SiO2 dielectric layer in the middle.
[0107] Furthermore, by measuring the film thickness of the photoresist mask and the dielectric layer before and after etching using a film thickness gauge, the etching rates of the photoresist mask and the dielectric layer are obtained. Calculations show that, without adding step S203, when etching is performed directly through S204 after step S202, the etching rate (EtchRate, ER) of the dielectric layer is: (per minute, ); while photoresist mask PR The etching selectivity ratio (SiO2 / PR selectivity ratio) of the dielectric layer to the photoresist mask is 2.5.
[0108] After adding step S203, the ER of the dielectric layer SiO2 is 3800 A / min; the ER of the photoresist mask is 745 A / min; and the SiO2 / PR selectivity ratio is 5.1.
[0109] As can be seen, the above method can significantly improve the etching selectivity of the dielectric layer relative to the photoresist mask. This method is applicable to normally off and normally on gallium nitride high electron mobility transistor devices, as well as dry etching with SiN as the dielectric layer, and dry etching of deep holes (aspect ratio > 5).
[0110] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” “top,” and “bottom,” etc., are used only to indicate relative positional relationships; when the absolute position of the described objects changes, the relative positional relationship may also change accordingly.
[0111] The above is not intended to limit this disclosure in any way. Although this disclosure has been disclosed above through embodiments, it is not intended to limit this disclosure. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this disclosure. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this disclosure without departing from the content of the technical solution of this disclosure shall still fall within the scope of the technical solution of this disclosure.
Claims
1. An etching method, characterized in that, The etching method includes: A substrate structure is provided, the substrate structure including a substrate and a dielectric layer deposited on the substrate; A patterned photoresist mask is formed on the dielectric layer; The photoresist mask is hardened. Under the cover of the processed photoresist mask, the dielectric layer is dry etched to form a hollow structure in the dielectric layer.
2. The etching method according to claim 1, characterized in that, The hardening process of the photoresist mask includes: A first plasma, formed using a mixture of SF6 and an inert gas, reacts with the photoresist mask to form a dense, hardened layer on the surface of the photoresist mask.
3. The etching method according to claim 2, characterized in that, During the process of reacting the first plasma formed using a mixture of SF6 and inert gas with the photoresist mask to form a dense hardened layer on the surface of the photoresist mask, the SF6 gas flow rate is 60-150 sccm, the inert gas flow rate is 60-150 sccm, and the working time of the first plasma is 10-30 s.
4. The etching method according to claim 3, characterized in that, During the process of reacting the first plasma formed using a mixture of SF6 and inert gas with the photoresist mask to form a dense hardened layer on the surface of the photoresist mask, the pressure of the reaction chamber containing the SF6 and the inert gas is 100-150 mTorr.
5. The etching method according to claim 1, characterized in that, The step of dry etching the dielectric layer under the cover of the processed photoresist mask to form a hollow structure in the dielectric layer includes: Under the cover of the processed photoresist mask, the dielectric layer is etched using a second plasma formed by a mixture of CHF3, Ar and CF4 gases.
6. The etching method according to claim 5, characterized in that, The etching time of the second plasma on the dielectric layer is 800-900s, and the etching pressure is 220-280 millitor.
7. The etching method according to claim 5, characterized in that, During the etching of the dielectric layer using a second plasma formed by a mixture of CHF3, Ar, and CF4 gases, the CHF3 gas flow rate is 20-80 sccm, the Ar gas flow rate is 100-200 sccm, and the CF4 gas flow rate is 20-100 sccm.
8. The etching method according to any one of claims 1-7, characterized in that, The thickness of the dielectric layer is 3.4-4.5 μm.
9. The etching method according to claim 8, characterized in that, The dielectric layer is SiO2.
10. The etching method according to any one of claims 1-7, characterized in that, The etching selectivity ratio between the dielectric layer and the processed photoresist mask is greater than 5.