DRAM (Dynamic Random Access Memory) double-stacked chip packaging structure and packaging process
By improving the redistribution layer and bump structure design, combined with flip-chip technology, the problems of heat dissipation difficulties and excessive thickness in DRAM dual-chip stacked packaging have been solved, achieving efficient heat dissipation and ultra-thin packaging.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-17
- Publication Date
- 2026-03-24
AI Technical Summary
In existing DRAM dual-chip stacked packaging solutions, heat cannot be dissipated in time, leading to performance degradation, and the packaging thickness is difficult to meet the requirements for ultra-thin packaging.
An improved redistribution layer and bump structure design is adopted, combined with flip-chip technology, to achieve electrical connection between bare chips through Sn-Ag-Cu alloy bumps, and the heat sink is directly contacted on the back of the second bare chip. The molding layer material is optimized to reduce the package thickness.
It significantly improves heat dissipation performance, reduces package thickness, enhances structural stability and circuit connection reliability, and meets the requirements of high performance and ultra-thin packaging.
Smart Images
Figure CN121729074A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of memory chip packaging technology, specifically to a DRAM dual-stacked chip packaging structure and packaging process. Background Technology
[0002] With the rapid development of artificial intelligence, 5G communication, and IoT technologies, the demand for memory capacity and data rate in consumer electronics products is growing exponentially. When PCB layout space or physical structure is limited, the traditional method of increasing the number of memory chips is no longer feasible, and increasing the storage density of a single memory chip becomes an inevitable choice.
[0003] The mainstream chip stacking packaging technology in the industry increases the capacity of a single memory chip by stacking at least two bare chips. However, while increasing capacity, the stacking structure also significantly increases the power density per unit volume. When the chip is running at high frequency of read and write, the power dissipation will be converted into a large amount of heat. If it is not dissipated in time, it will reduce the chip's operating frequency and weaken the performance potential of high-speed interfaces. Therefore, the requirements for heat dissipation technology of miniaturized, high-performance stacked chips are increasing.
[0004] In existing DRAM dual-chip stacked packaging solutions, the bonding pads of the original bare dies are all located in the center. The pads must first be guided to the edge of the bare die via a redistribution layer (RDL), and then connected to the packaging substrate via bonding wires. The two bare dies are then bonded together using a wire overlay film (FOW), and finally molded into a single chip using epoxy molding compound (EMC). To meet heat dissipation requirements, a heat sink is usually additionally attached to the molded surface of the chip.
[0005] The existing technology has obvious drawbacks: On the one hand, the bare chip above is between EMC with a thermal conductivity of only 1-3 W / m·k and FOW with a thermal conductivity of about 0.3 W / m·k. Heat cannot be transferred to the external environment in time, which not only affects the chip access speed and signal integrity, but also triggers the temperature control protection mechanism, restricting high bandwidth and high speed read and write performance. On the other hand, the dielectric layer and metal wiring layer of RDL will increase the thickness of the bare chip before packaging, the arc height of the bonding wire and the required reserved thickness of the molding material, further increasing the overall height of the package, making it difficult to adapt to the requirements of ultra-thin packaging.
[0006] Therefore, we propose a DRAM dual-stacked chip packaging structure and packaging process. Summary of the Invention
[0007] The purpose of this invention is to provide a DRAM dual-stacked chip packaging structure and packaging process, which solves the problems mentioned in the background art.
[0008] To achieve the above objectives, the present invention provides the following technical solution: a DRAM dual-stacked chip packaging structure, comprising a substrate, a first bare chip, a second bare chip, a bump structure, and a molding layer; the first bare chip is mounted on the substrate and connected to the substrate circuitry via bonding wires; a first redistribution layer is provided on the surface of the first bare chip, which extends the original center pad of the first bare chip to the edge, forming An-WB bonding pads, Bn-WB bonding pads, multiple An-FC pads, multiple Bn-FC pads, and multiple support pads; the An-FC pads and Bn-FC pads are respectively connected to the original An pad and original Bn pad of the first bare chip via wiring, while the support pads are not connected to the circuitry; the second bare chip has a second redistribution layer and the bump structure on its surface. The second redistribution layer leads the original center pad of the second bare chip to the side via interlaced lines. The bump structure includes multiple An-BP bumps, multiple Bn-BP bumps, and multiple support bumps. The An-BP bumps and Bn-BP bumps are connected to the original Anpad and original Bnpad circuits of the second bare chip, respectively, while the support bumps are not connected to any circuit. The second bare chip is mounted upside down on top of the first bare chip, with the An-BP bumps aligned with the An-FCpad, the Bn-BP bumps aligned with the Bn-FCpad, and the support bumps aligned with the support pad, forming a circuit connection. The molding layer encapsulates the first bare chip, the second bare chip, and the bump structure, with the back of the second bare chip exposed outside the molding layer.
[0009] In a preferred embodiment of the present invention, the bump structure includes An-BP bumps, Bn-BP bumps and supporting bumps, all of which are made of Sn-Ag-Cu alloy.
[0010] In a preferred embodiment of the present invention, the An-FCpad, Bn-FCpad and support pad are evenly distributed on the upper surface of the first bare chip; the number of An-BP bumps, Bn-BP bumps and support bumps are the same as the number of An-FCpad, Bn-FCpad and support pad.
[0011] In a preferred embodiment of the present invention, the positional deviations between the An-BP bump and the An-FCpad, the Bn-BP bump and the Bn-FCpad, and the support bump and the support pad are controlled within a preset accuracy range.
[0012] In a preferred embodiment of the present invention, the molding layer is made of epoxy molding compound, and the back of the second bare chip exposed outside the molding layer is polished.
[0013] This invention also relates to a DRAM dual-stacked chip packaging process, comprising the following process steps:
[0014] S1: Fabrication of the first bare chip. The first bare chip is designed using RDL. The first redistribution layer is formed through photolithography and electroplating processes. The original center pad of the first bare chip is led out to the edge to form An-WB bonding pad, Bn-WB bonding pad, multiple An-FC pads, multiple Bn-FC pads and multiple support pads. It is ensured that the An-FC pads and Bn-FC pads are connected to the original An pads and original Bn pads of the first bare chip through wiring, respectively, while the support pads are not connected to the circuit.
[0015] S2: Fabrication of the second bare chip. The second bare chip adopts an RDL+Bump design. First, a second wiring layer is formed through photolithography and electroplating. The original center pad of the second bare chip is led out to the side through circuit cross-connection. Then, a bump structure is formed using a bumping process to obtain multiple An-BP bumps, multiple Bn-BP bumps, and multiple supporting bump bumps. It is ensured that the An-BP bumps and Bn-BP bumps are connected to the original Anpad and original Bnpad circuits of the second bare chip, respectively, while the supporting bump bumps are not connected to the circuit.
[0016] S3: Position matching design, using CAD design software to ensure that the An-BP bump of the second bare chip is consistent with the An-FCpad of the first bare chip, the Bn-BP bump is consistent with the Bn-FCpad, and the support bump bump is consistent with the support pad.
[0017] S4: First bare chip mounting and bonding. The first bare chip prepared in S1 is mounted on the substrate through an adhesive film. After curing, a bonding process is used to connect the An-WB bonding pad and the Bn-WB bonding pad to the corresponding pads on the substrate through bonding wires.
[0018] S5: Second bare chip flip mounting, the second bare chip prepared in S2 is flipped, and the corresponding pad of the first bare chip is aligned by flip bonding equipment. The circuit connection between An-BP bump and An-FCpad and Bn-BP bump and Bn-FCpad is achieved by reflow soldering, and the support bump is attached to the support pad.
[0019] S6: Molding and polishing. The compression molding process is used to mold the overall structure consisting of the substrate, the first bare chip, the second bare chip and the bump structure to form a molding layer. Then, the back of the second bare chip exposed outside the molding layer is polished.
[0020] In a preferred embodiment of the present invention, in S4, the first bare chip is mounted on the substrate by an adhesive film and then cured; the bonding process uses gold wire bonding, and the An-WB bonding pad and Bn-WB bonding pad are connected to the corresponding pads on the substrate by bonding wires.
[0021] In a preferred embodiment of the present invention, in S5, the reflow soldering is performed in a nitrogen atmosphere to ensure a reliable connection between the An-BP bump and the An-FCpad, and between the Bn-BP bump and the Bn-FCpad; in S6, a molding process is used to form a molding layer that encapsulates the first bare chip, the second bare chip, and the bump structure.
[0022] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0023] The invention significantly improves heat dissipation performance: after the second bare chip is stacked, the back of the crystal is directly exposed, which can directly contact the external heat sink. The heat dissipation coefficient of silicon is 150W / (m·K), which is much higher than EMC and FOW, greatly enhancing the heat dissipation efficiency and avoiding performance degradation caused by heat accumulation.
[0024] Effective reduction in package thickness: The chip top molding area required for bonding wires in conventional products has been eliminated, and the structural matching of RDL and bumps has been optimized, significantly reducing the overall thickness of the chip and meeting the requirements of ultra-thin packaging;
[0025] Strong structural stability: The precise alignment and cooperation between the support pad and the support bump enhances the structural stability of the stacked dual chips and ensures the reliability of the circuit connection. Attached Figure Description
[0026] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:
[0027] Figure 1 This is a planar and cross-sectional view of the first bare chip of the present invention;
[0028] Figure 2 This is a planar and cross-sectional view of the second bare chip of the present invention;
[0029] Figure 3 This is a schematic diagram of the first bare chip surface bonding of the present invention;
[0030] Figure 4This is a flip-chip and cross-sectional view of the second bare chip of the present invention;
[0031] Figure 5 This is a schematic diagram of the second bare chip flip-chip mounting of the present invention;
[0032] Figure 6 This is a schematic diagram of the flip-chip assembly of the present invention;
[0033] Figure 7 This is a schematic diagram of the molding process of the present invention. Detailed Implementation
[0034] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below in conjunction with specific embodiments.
[0035] like Figure 1-7 As shown, a DRAM dual-stacked chip packaging structure is as follows:
[0036] First bare chip and second bare chip: both are DRAM bare chips of the same specifications, with the original bonding pad located in the center area of the chip;
[0037] Bump structure: including An-BP bump, Bn-BP bump, and support bump, used to realize the interconnection between the first bare chip and the second bare chip;
[0038] The pad structure on the first bare chip: An-FCpad, Bn-FCpad, and support pad are all led out from the original central pad through the first wiring layer;
[0039] Encapsulation layer: Utilizes epoxy molding compound to protect the chip and interconnect structure;
[0040] Bonding wire: Gold wire is used to achieve electrical connection between the first bare chip and the substrate.
[0041] Specific implementation steps of DRAM dual-stacked chip packaging process:
[0042] The packaging process of this embodiment is based on the above structural design and consists of 6 core steps. The operational details of each step are as follows:
[0043] Step S1: Fabrication of the first bare die
[0044] Cleaning: Place the bare DRAM chip into a plasma cleaner to remove surface oil and oxide layer;
[0045] Dielectric layer coating: Polyimide resin is coated on the chip surface using a spin-coat process to form a uniform dielectric layer, which is then pre-baked.
[0046] Photolithography and development: The photoresist is applied, and the RDL pattern is transferred to the photoresist through ultraviolet exposure. After development, the wiring windows are exposed.
[0047] Copper plating layer: Copper is electroplated in the window area to form a wiring layer, and then the remaining photoresist is stripped off;
[0048] Pad formation: The excess copper layer is removed by etching, leaving the An-WB bonding pad, Bn-WB bonding pad, An-FC pad, Bn-FC pad, and support pad, thus completing the fabrication of the first bare chip.
[0049] Step S2: Fabrication of the second bare chip
[0050] RDL fabrication: Repeat steps 1-5 of S1 to fabricate a second wiring layer on the surface of the second bare chip. The wiring path is designed as "staggered" to ensure that the lead-out position is aligned with the pad of the first bare chip.
[0051] Ball preparation: Growing copper pillars and printing solder paste at the RDL lead-out position of the second bare chip;
[0052] Bump forming: The chip is placed in a reflow oven, heated and held in a nitrogen atmosphere, and then cooled. The solder paste melts and forms An-BP bumps, Bn-BP bumps, and support bumps, completing the fabrication of the second bare chip.
[0053] Step S3: Location Matching Design
[0054] A 3D model is created using CAD design software. The pad coordinates (based on chip center positioning) of the first bare chip and the bump coordinates of the second bare chip are imported. The bump positions are adjusted through the coordinate calibration function to ensure that the positional deviations of the An-BP bump and An-FCpad, the Bn-BP bump and Bn-FCpad, and the support bump and support pad meet the process requirements. The final RDL and bump layout files are generated to guide the process fabrication of S1 and S2.
[0055] Step S4: First bare die mounting and bonding
[0056] Chip preparation: An adhesive film is applied to the back of the wafer, which is then cut into individual chips using a wafer dicing machine;
[0057] Chip mounting: The first bare chip is aligned with the target position and mounted using a pick and place machine. Pressure is applied and held for a certain period of time to ensure that the adhesive film adheres evenly to the substrate.
[0058] Curing: The mounted substrate is placed in an oven for curing to fully cure the adhesive film and achieve reliable bonding between the chip and the substrate;
[0059] Gold wire bonding: A fully automatic bonding machine is used to bond one end of the gold wire to the An-WB bonding pad and the Bn-WB bonding pad, and the other end to the corresponding pad on the substrate. The arc height of the gold wire is controlled (to avoid interference with subsequent flip-chip bonding).
[0060] Step S5: Flip-mounting of the second bare die
[0061] Flip-chip positioning: The second bare chip is placed into the nozzle (vacuum adsorption) of the flip-chip bonding equipment. The equipment's vision positioning system captures the bumps on the chip and the pads on the first bare chip, and the chip orientation is adjusted to align the two.
[0062] Reflow soldering: The aligned structure is sent into a reflow oven and reflowed according to a preset curve under a nitrogen atmosphere, so that the Sn-Ag-Cu bumps melt and form an intermetallic compound with the pad, completing the electrical connection; after reflow, it is naturally cooled to room temperature, and the support bumps and support pads are tightly attached to form mechanical support.
[0063] Step S6: Molding and polishing are performed using the Compression Molding process;
[0064] Mold preparation: Place the flip-chip structure into the mold (the upper cavity reserves the exposed space for the back of the second bare chip), and the mold is preheated;
[0065] Molding material injection: The epoxy molding material in the material tank is evenly distributed in the substrate molding area through the flow channel system, and then fed into the mold cavity. Pressure is maintained and cured so that the epoxy molding material completely fills the cavity and wraps the first bare chip, the second bare chip and the bump structure to form a molding layer.
[0066] Demolding and post-curing: After opening the mold and removing the encapsulated part, place it in an oven for post-curing to improve the bonding strength and temperature resistance of the epoxy molding compound;
[0067] Crystal back grinding: The package is fixed on the chuck of the grinding machine, and the exposed crystal back of the second bare chip is ground with a diamond grinding wheel to control the overall thickness of the package. Then the crystal back is polished with a grinding wheel to remove grinding scratches and increase the heat dissipation contact area.
[0068] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or basic characteristics. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within the present invention.
[0069] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.
Claims
1. A DRAM dual-stacked chip packaging structure, characterized in that: The system includes a substrate (1), a first bare chip (2), a second bare chip (3), a bump structure, and a molding layer (10). The first bare chip (2) is mounted on the substrate (1) and is connected to the substrate (1) via bonding wires (11). The surface of the first bare chip (2) is provided with a first redistribution layer, which leads the original center pad of the first bare chip (2) to the edge to form an An-WB bonding pad, a Bn-WB bonding pad, multiple An-FC pads (7), multiple Bn-FC pads (8), and multiple support pads (9). The An-FC pads (7) and Bn-FC pads (8) are respectively connected to the original An pad and the original Bn pad of the first bare chip (2) via wiring. The support pads (9) are not connected to the circuit. The surface of the second bare chip (3) is provided with a second redistribution layer and the bump structure. The second redistribution layer leads the original center pad of the second bare chip (3) to the edge to form an An-WB bonding pad, a Bn-WB bonding pad, multiple An-FC pads (7), multiple Bn-FC pads (8), and multiple support pads (9). The central pad is led out to the side through a circuit. The bump structure includes multiple An-BP bumps (4), multiple Bn-BP bumps (5) and multiple support bumps (6). The An-BP bumps (4) and Bn-BP bumps (5) are connected to the original Anpad and original Bnpad circuits of the second bare chip (3), respectively. The support bumps (6) are not connected to the circuit. The second bare chip (3) is mounted upside down on top of the first bare chip (2). The An-BP bumps (4) are aligned with the An-FCpad (7), the Bn-BP bumps (5) are aligned with the Bn-FCpad (8), and the support bumps (6) are aligned with the support pad (9) to form a circuit connection. The molded layer (10) wraps the first bare chip (2), the second bare chip (3) and the bump structure. The crystal back of the second bare chip (3) is exposed outside the molded layer (10).
2. The DRAM dual-stacked chip packaging structure according to claim 1, characterized in that: The bump structure includes An-BP bump (4), Bn-BP bump (5) and support bump (6), all of which are made of Sn-Ag-Cu alloy.
3. The DRAM dual-stacked chip packaging structure according to claim 1, characterized in that: The An-FCpad (7), Bn-FCpad (8) and support pad (9) are evenly distributed on the upper surface of the first bare chip (2); the number of An-BP bump (4), Bn-BP bump (5) and support bump (6) are the same as the number of An-FCpad (7), Bn-FCpad (8) and support pad (9).
4. The DRAM dual-stacked chip packaging structure according to claim 1, characterized in that: The positional deviations of the An-BP bump (4) and the An-FCpad (7), the Bn-BP bump (5) and the Bn-FCpad (8), and the support bump (6) and the support pad (9) are controlled within a preset accuracy range.
5. A DRAM dual-stacked chip packaging structure according to claim 1, characterized in that: The molding layer (10) is made of epoxy molding compound, and the back of the second bare chip (3) exposed outside the molding layer (10) is polished.
6. A DRAM dual-stacked chip packaging process, applicable to the DRAM dual-stacked chip packaging structure according to any one of claims 1-5, characterized in that: The process includes the following steps: S1: First bare chip fabrication. The first bare chip (2) is designed using RDL. The first redistribution layer is formed by photolithography and electroplating. The original center pad of the first bare chip (2) is led out to the edge to form An-WB bonding pad, Bn-WB bonding pad, multiple An-FC pads (7), multiple Bn-FC pads (8) and multiple support pads (9). It is ensured that the An-FC pads (7) and Bn-FC pads (8) are connected to the original An pads and original Bn pads of the first bare chip (2) through wiring, and the support pads (9) are not connected to the circuit. S2: Fabrication of the second bare chip. The second bare chip (3) adopts RDL+Bump design. First, the second wiring layer is formed by photolithography and electroplating. The original center pad of the second bare chip (3) is led out to the side by the line crossover. Then, the bump structure is formed by the bumping process to obtain multiple An-BP bumps (4), multiple Bn-BP bumps (5) and multiple support bump bumps (6). Ensure that the An-BP bumps (4) and Bn-BP bumps (5) are connected to the original Anpad and original Bnpad circuits of the second bare chip (3) respectively, and the support bump bumps (6) are not connected to the circuit. S3: Position matching design, using CAD design software to ensure that the An-BP bump (4) of the second bare chip (3) is consistent with the An-FCpad (7), Bn-BP bump (5) and Bn-FCpad (8), and the support bump (6) and support pad (9) of the first bare chip (2); S4: First bare chip mounting and bonding. The first bare chip (2) prepared in S1 is mounted on the substrate (1) through an adhesive film. After curing, the bonding process is used to connect the An-WB bonding pad and the Bn-WB bonding pad to the corresponding pads of the substrate (1) through bonding wires (11). S5: Second bare chip flip mounting, the second bare chip (3) prepared in S2 is flipped, and the corresponding pads of the first bare chip (2) are aligned by flip bonding equipment. The circuit connection between An-BP bump (4) and An-FCpad (7) and Bn-BP bump (5) and Bn-FCpad (8) is achieved by reflow soldering, and the support bump (6) is attached to the support pad (9). S6: Molding and polishing. The overall structure consisting of substrate (1), first bare chip (2), second bare chip (3) and bump structure is molded using the Compression Molding process to form a molding layer (10). Then, the crystal back of the second bare chip (3) exposed outside the molding layer (10) is polished.
7. The DRAM dual-stacked chip packaging structure and packaging process according to claim 1, characterized in that: In S4, the first bare chip (2) is attached to the substrate (1) by an adhesive film and then cured. The bonding process uses gold wire bonding, and the An-WB bonding pad and Bn-WB bonding pad are connected to the corresponding pads of the substrate (1) by bonding wires (11).
8. The DRAM dual-stacked chip packaging structure and packaging process according to claim 1, characterized in that: In S5, reflow soldering is performed in a nitrogen atmosphere to ensure reliable connection between An-BP bump (4) and An-FCpad (7), and between Bn-BP bump (5) and Bn-FCpad (8); in S6, a molding layer (10) is formed by molding process to encapsulate the first bare chip (2), the second bare chip (3) and the bump structure.