Semiconductor package and method of manufacturing the same
By using an etching method to mark the frame and spacers, the problem of controlling the laser marking depth was solved, enabling the manufacturing of thin packages and preventing warping, thus improving the integration and reliability of the packages.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-04
- Publication Date
- 2026-03-24
AI Technical Summary
In existing technologies, it is difficult to control the marking depth of laser marking processes to a shallow level, which leads to increased thickness of the package and difficulty in improving warping issues. Furthermore, when the laser marking depth is too deep, it can easily cause cracks in the package.
By employing an etched marking frame method, marking patterns are constructed using adhesive layers and spacers, reducing the thickness of the marking frame and leaving space in the molding layer to form a thin and non-warping semiconductor package.
It enables the manufacturing of thin packages, reduces package thickness, and improves device integration and reliability, while also providing the ability to shield against electromagnetic interference.
Smart Images
Figure CN121729079A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor packaging, and more particularly to semiconductor packages and methods for manufacturing the same. Background Technology
[0002] Typically, semiconductor packages that have undergone the packaging process need to be marked to indicate product information such as performance parameters. The traditional marking process involves directly etching marks onto the encapsulation layer using laser ablation, a method known as laser marking. After laser marking, conductive media can be used to electrically interconnect the chips and between the chips and the substrate. Then, the encapsulation material is filled and cured using the packaging process, resulting in a highly reliable system-in-package (SIP).
[0003] However, in existing marking processes, due to the use of laser ablation, it is difficult to control the marking depth to a shallow level. Laser marking is generally quite deep (maximum depth of 50μm), making it difficult to form thin encapsulations, and the overall warping problem of the encapsulation is difficult to improve. Summary of the Invention
[0004] To address the aforementioned technical problems, exemplary embodiments of this disclosure provide a semiconductor package with a shallow marking depth and a method for manufacturing the same.
[0005] In addition, exemplary embodiments of this disclosure also provide a semiconductor package having a thin thickness and being resistant to warping, and a method for manufacturing the same.
[0006] In addition, exemplary embodiments of this disclosure also provide a semiconductor package with electromagnetic interference (EMI) shielding capability and a method for manufacturing the same.
[0007] According to one aspect of an exemplary embodiment of the present disclosure, a semiconductor package includes: a substrate; a semiconductor chip located on the substrate; a molding layer covering the semiconductor chip; an adhesive layer on an upper surface of the molding layer; a marking frame on the adhesive layer, wherein the marking frame exposes a portion of the adhesive layer, the exposed portion of the adhesive layer forming a marking pattern; and a spacer on a lower surface of the adhesive layer and spaced horizontally from the semiconductor chip, wherein the spacer is spaced from the substrate.
[0008] Furthermore, the spacer may be a first spacer, and the semiconductor package may also include a second spacer spaced apart from the semiconductor chip in the horizontal direction, and the first spacer and the second spacer may be located on two opposite sides of the semiconductor chip in the horizontal direction.
[0009] Further, the semiconductor chip can be electrically connected to the chip pad of the base via the bonding wire and a bonding point of the bonding wire and the chip pad can be superposed with the spacer along the vertical direction.
[0010] Further, the bonding wire can extend from the bonding point through a space between the spacer and the base and a space between the spacer and the semiconductor chip to be connected to an upper surface of the semiconductor chip.
[0011] Further, an upper surface of the marking frame and an upper surface of the marking pattern can be coplanar.
[0012] Further, a thickness of the marking pattern and a thickness of the marking frame can be the same.
[0013] Further, the thickness of the marking frame can be less than 8 µm.
[0014] Further, the marking frame can include a metallic material.
[0015] Further, the marking frame can include copper.
[0016] Further, side surfaces of the molding layer, side surfaces of the adhesive layer, and side surfaces of the marking frame can be aligned in the vertical direction.
[0017] Further, the adhesive layer can include a portion located between the marking frame and the molding layer.
[0018] According to another aspect of example embodiments of the present disclosure, a method of manufacturing a semiconductor package includes removing a portion of a preliminary marking frame on a separation carrier to form a marking region, the portion of the preliminary marking frame being removed at the marking region, wherein a remaining portion of the preliminary marking frame forms a marking frame; covering the marking frame with an adhesive layer such that the adhesive layer includes a body portion and a marking pattern disposed on the body portion, the marking pattern filling the marking region; disposing a spacer on the adhesive layer; forming a molding layer on the adhesive layer and covering a semiconductor chip, wherein the semiconductor chip is on a base and between the base and the adhesive layer; and removing the separation carrier to expose an upper surface of the marking frame and an upper surface of the marking pattern, wherein the spacer is spaced apart from the base.
[0019] Further, the spacer can be a first spacer, the semiconductor package can further include a second spacer spaced apart from the semiconductor chip in a horizontal direction, and the first spacer and the second spacer can be located at two opposite sides of the semiconductor chip in the horizontal direction.
[0020] Further, the semiconductor chip can be electrically connected to the chip pad of the base via the bonding wire and a bonding point of the bonding wire and the chip pad can be superposed with the spacer along the vertical direction.
[0021] Furthermore, bonding leads can extend from the bonding point through the space between the spacer and the substrate and the spacer and the semiconductor chip to connect to the upper surface of the semiconductor chip.
[0022] Furthermore, the upper surface of the marking frame and the upper surface of the marking pattern can be coplanar.
[0023] Furthermore, the thickness of the marking pattern can be the same as the thickness of the marking frame.
[0024] Furthermore, the thickness of the marker frame can be less than 8 μm.
[0025] Furthermore, the marking frame may include a metallic material.
[0026] Furthermore, the marker frame may include copper.
[0027] Furthermore, the side surfaces of the molding layer, the side surfaces of the main body, and the side surfaces of the marking frame can be aligned in the vertical direction.
[0028] Furthermore, the step of forming the molding layer may include: placing the separation carrier in the lower cavity of the mold with the spacer and the main body facing upwards, and placing the substrate and the semiconductor chip in the upper cavity of the mold with the semiconductor chip facing downwards; closing the mold and injecting encapsulation material into the mold; and cooling and curing the encapsulation material between the substrate and the main body to form the molding layer, wherein, after closing the mold, the upper surface of the spacer may be vertically spaced from the surface of the substrate facing the spacer.
[0029] Furthermore, the separation carrier can be placed on the release film in the lower cavity of the mold. Attached Figure Description
[0030] The features and advantages of this disclosure above and in other aspects will become more apparent from the following detailed description of embodiments of this disclosure in conjunction with the accompanying drawings. In the drawings, the same reference numerals will consistently indicate the same elements.
[0031] Figure 1 This is a schematic diagram of a semiconductor package based on related technologies.
[0032] Figure 2 This is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present disclosure.
[0033] Figure 3 This is a flowchart of a method for manufacturing a semiconductor package according to an exemplary embodiment of the present disclosure.
[0034] Figure 4 , Figure 5 and Figure 6This is a cross-sectional view of an intermediate step in a method for manufacturing a semiconductor package according to an exemplary embodiment of the present disclosure.
[0035] Figure 7 This is a flowchart of a molding process for a method of manufacturing a semiconductor package according to an exemplary embodiment of the present disclosure.
[0036] Figure 8 This is a cross-sectional view of an intermediate step in a method for manufacturing a semiconductor package according to an exemplary embodiment of the present disclosure.
[0037] Figure 9 This is a perspective view of a semiconductor package according to an exemplary embodiment of the present disclosure. Detailed Implementation
[0038] In the following description, various embodiments of the present disclosure will be described more fully with reference to the accompanying drawings, in which some embodiments are illustrated. However, the present disclosure may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein.
[0039] For ease of description, spatial relative terms such as “below,” “under,” “below,” “above,” and “above” may be used herein to describe the relationship of an element as shown in the accompanying drawings to other elements. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are also intended to include different orientations of the device during use or operation. For example, if the device in the drawings is flipped, an element previously described as “below” or “under” other elements will subsequently be oriented “above” said other elements. Thus, the term “below” can include both “above” and “below” orientations.
[0040] Figure 1 This is a schematic diagram of a semiconductor package based on related technologies.
[0041] Reference Figure 1 The semiconductor package includes a substrate 1, a chip 2, spacers 3, and an encapsulation layer 4. The chip 2 is disposed on the upper surface of the substrate 1 and electrically connected to the substrate 1 via bonding leads. The spacers 3 are horizontally disposed on both sides of the chip 2 on the upper surface of the substrate 1 and spaced apart from the chip 2 by a certain distance. For example, the spacers 3 may be located on two opposite sides of the chip 2. The bonding leads may extend in the region between the chip 2 and the spacers 3. The encapsulation layer 4 covers the chip 2 and the spacers 3 on the upper surface of the substrate 1.
[0042] Typically, a mark M is engraved on the upper surface of the encapsulation layer 4 using laser ablation. The mark M may include patterns representing performance parameters of the semiconductor package, product information, etc. In some cases, due to limitations of laser ablation, the mark M must be formed relatively deep. In such cases, if the encapsulation layer 4 is thin, the depth DP of the mark M can easily cause cracks in the semiconductor package, reducing device yield and reliability. Therefore, the thickness of the encapsulation layer 4 needs to be sufficiently large to ensure that the depth DP of the mark M does not cause cracks in the semiconductor package. In laser marking processes, the depth DP of the mark M can be controlled below 50 μm, for example, from 10 μm to 50 μm. However, because laser marking processes cannot form a smaller depth DP of the mark M (e.g., below 10 μm), it is impossible to reduce the thickness of the encapsulation layer 4, thus making it difficult to reduce the overall thickness of the semiconductor package.
[0043] Furthermore, due to the differences in the coefficients of thermal expansion among the various parts of the semiconductor package, warping is prone to occur during manufacturing. Spacer 3 is used to control the warping of the semiconductor package, but spacer 3 occupies space for arranging bonding leads, making it difficult to increase the integration density.
[0044] Figure 2 This is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present disclosure.
[0045] Reference Figure 2 A semiconductor package according to an example embodiment of the present disclosure includes a substrate 110, a semiconductor chip 120, a molding layer 130, an adhesive layer 140, a marking frame 150, and a spacer S.
[0046] Semiconductor chip 120 is located on substrate 110. For example, semiconductor chip 120 may be located on the upper surface of substrate 110. For example, semiconductor chip 120 may be located in the central region of the upper surface of substrate 110. For example, semiconductor chip 120 may be a memory chip or a controller chip. Semiconductor chip 120 may be a bare die. Substrate 110 may be a package substrate such as a printed circuit board and may include multiple layers stacked in a vertical direction. Each layer in the multiple layers may include lines or traces. Adjacent layers in the multiple layers may be electrically connected to each other via vias.
[0047] A molding layer 130 covers the semiconductor chip 120 on the substrate 110. For example, the molding layer 130 may cover the upper surface 120T and side surfaces 120S of the semiconductor chip 120, and the lower surface BS, inner surface IS, and outer surface OS of the spacer S. The lower surface 120B of the semiconductor chip 120 may be disposed on the upper surface of the substrate 110, so as not to be covered by or in contact with the molding layer 130. The upper surface TS of the spacer S may be configured to contact the lower surface of the adhesive layer 140, so as not to be covered by or in contact with the molding layer 130. For example, the molding layer 130 may be formed of a molding material such as epoxy resin (EMC).
[0048] Adhesive layer 140 covers the upper surface of molding layer 130. Adhesive layer 140 may include a portion located between marking frame 150 and molding layer 130. The portion of adhesive layer 140 located between marking frame 150 and molding layer 130 may be a body portion 141. In this case, adhesive layer 140 may include body portion 141 and marking pattern 145 disposed on body portion 141. Marking frame 150 may expose a portion of adhesive layer 140. The portion of adhesive layer 140 exposed by marking frame 150 may form marking pattern 145. For example, adhesive layer 140 may contact the upper surface TS of spacer S. Adhesive layer 140 may be a bare film attachment (DAF).
[0049] The marking frame 150 is on the main body 141 of the adhesive layer 140. A portion of the marking frame 150 is removed to form a marking area 150R. For example, when viewed in cross-sectional view, the marking frame 150 may include multiple portions arranged horizontally and spaced apart from each other. The horizontal width of each of the multiple portions may, but does not necessarily, differ from each other. The marking pattern 145 of the adhesive layer 140 may be disposed between adjacent portions of the multiple portions of the marking frame 150.
[0050] Spacers S are disposed on the lower surface of the adhesive layer 140 in the edge region and located on both sides of the semiconductor chip 120 in the horizontal direction. For example, a portion of the spacers S may be disposed on two horizontally opposite sides of the semiconductor chip 120 and spaced apart from the semiconductor chip 120. Marking patterns 145 are located in marking regions 150R (e.g., filling marking regions 150R) and connected to the body portion 141. For example, the remaining portion of the marking frame 150 that has not been removed may be located in the horizontal direction between adjacent marking patterns 145, such that the adhesive layer 140 includes recesses 140R. In other words, the marking frame 150 may be embedded in the recesses 140R of the adhesive layer 140.
[0051] The spacer S may not contact the substrate 110. For example, the spacer S may be a dummy chip that does not have electrical function.
[0052] Unlike laser ablation, the marking information of a semiconductor package according to an exemplary embodiment of this disclosure can be defined by a pattern obtained by etching a marking frame. The outline of the pattern can be defined by the marking area of the marking frame, and the body of the pattern can be formed by the marking pattern of the adhesive layer. Since the marking frame can be easily formed to have a small thickness, the overall thickness of the semiconductor package can be reduced by reducing the thickness of the molding layer, while preventing cracks from appearing in the semiconductor package.
[0053] Furthermore, the presence of spacers and the space between the spacers and the substrate allows for improved layout margins for interconnect components such as bonding leads, thereby enhancing device integration and reliability while preventing warping of the semiconductor package.
[0054] In the example embodiment, still refer to Figure 2 The lower surface BS of the spacer S can be spaced apart from the upper surface of the substrate 110 by a first distance D1, and the inner surface IS of the spacer S and the outer surface 120S of the semiconductor chip 120 can be spaced apart from each other by a second distance D2.
[0055] In this example embodiment, the first distance D1 may be less than the second distance D2, but this disclosure is not limited thereto. In other example embodiments, depending on the density of the wiring layout, the plurality of spacers S disposed on both sides of the semiconductor chip 120 may have different values of the first distance D1, which can significantly improve the wiring freedom of the semiconductor package.
[0056] In an example embodiment, the semiconductor chip 120 can be electrically connected to a chip pad on the substrate 110 via a bonding lead W, and the bonding point J1 between the bonding lead W and the chip pad can be positioned vertically below the spacer S (e.g., it can be stacked vertically with the spacer S). For example, the chip pad can be disposed on the upper surface of the substrate 110. The chip pad can be a lead finger or a lead pad on the substrate.
[0057] In this example embodiment, the bonding lead W can extend from the bonding point J1 through the space between the spacer S and the substrate 110 and the space between the spacer S and the semiconductor chip 120 to connect to the upper surface 120T of the semiconductor chip 120. For example, the bonding lead W can be formed of a metal such as gold (Au) and can be electrically connected to the chip pad of the substrate 110 via a wire bonding process. For example, the bonding lead W can be spaced apart from the spacer S and the semiconductor chip 120 by being wrapped with a molding layer 130 to electrically insulate them.
[0058] In this example embodiment, the upper surface 120T of the semiconductor chip 120 can be an active surface, while the lower surface 120B can be a passive surface. The bonding lead W can be electrically connected to interconnect elements located on the active surface of the semiconductor chip 120 via the bonding point J2. For example, the arcuate portion of the bonding lead W may not contact the lower surface 140B of the adhesive layer 140.
[0059] In an example embodiment, the upper surface 150T of the marking frame 150 and the upper surface 145T of the marking pattern 145 may be coplanar. In this example embodiment, the vertical thickness of the marking pattern 145 may be the same as the vertical thickness T of the marking frame 150. For example, the thickness of the marking pattern 145 may be 5 μm, for example, 5 μm ± 2 μm. In an example embodiment, the thickness of the marking pattern 145 and / or the thickness T of the marking frame 150 may be less than 10 μm, less than 9 μm, or less than 8 μm. Compared to the minimum marking depth DP of 10 μm formed by laser ablation, the thickness T of the marking frame can be significantly reduced.
[0060] In an example embodiment, the marker frame 150 may include a metallic material. For example, the marker frame 150 may include a material that can be used in an etching process, such as copper. When the marker frame 150 is formed of a metallic material, it may also have the function of shielding electromagnetic interference (EMI), thereby improving the reliability of the semiconductor package.
[0061] In example embodiments, such as Figure 2 As shown, the side surfaces 110S of the substrate 110, the side surfaces 130S of the molding layer 130, the side surfaces 140S of the main body 141 of the adhesive layer 140, and the side surfaces 150S of the marking frame 150 can be aligned in the vertical direction. When the marking frame 150 is formed of a metallic material and its side surfaces 150S are aligned with the side surfaces of the respective underlying elements, the rigidity of the marking frame 150 itself can serve as an aid to the spacers S, further reducing the overall warpage of the semiconductor package.
[0062] The following will refer to Figures 3 to 8 Describe in detail the manufacturing method of semiconductor packages. Figure 3 This is a flowchart of a method for manufacturing a semiconductor package according to an exemplary embodiment of the present disclosure. Figure 4 , Figure 5 and Figure 6 This is a cross-sectional view of an intermediate step in a method for manufacturing a semiconductor package according to an exemplary embodiment of the present disclosure. Figure 7 This is a flowchart of a molding process for a method of manufacturing a semiconductor package according to an exemplary embodiment of the present disclosure. Figure 8This is a cross-sectional view of an intermediate step in a method for manufacturing a semiconductor package according to an exemplary embodiment of the present disclosure.
[0063] Reference Figure 3 and Figure 4 A method for manufacturing a semiconductor package according to an exemplary embodiment of the present disclosure includes the following steps: S100, providing a marking unit, the marking unit including a preliminary marking frame 150PRE and a separation carrier 160 disposed below the preliminary marking frame 150PRE. In the exemplary embodiment, the preliminary marking frame 150PRE may have a plate shape.
[0064] S200, a portion of the preliminary marking frame 150PRE is removed to form the marking region 150R, and the remaining portion of the preliminary marking frame 150PRE forms the marking frame 150. In an example embodiment, an exposure and development process can be performed on the preliminary marking frame 150PRE using a mask MSK including a predetermined pattern to transfer the predetermined pattern to the marking region 150R. For example, the predetermined pattern may include a pattern representing identification information such as performance parameters of a semiconductor package, product information, etc. Figure 4 As shown, the mask MSK is displayed from a top-view perspective. Photolithography performed using the mask MSK can transfer the pattern PTRN onto the marking area 150R. For example, the pattern PTRN can be represented by the area exposed by the mask MSK, which can correspond to the area where the preliminary marking frame 150PRE has been removed. The area where the preliminary marking frame 150PRE has been removed can represent the pattern PTRN. For example, the area where the preliminary marking frame 150PRE has been removed can form numbers, letters, and / or symbols, etc., to provide identification information.
[0065] Reference Figure 3 and Figure 5 In step S300, the marking frame 150 is covered by an adhesive layer 140, such that the adhesive layer 140 includes a main body 141 and a marking pattern 145 disposed on the main body 141. The marking pattern 145 fills the marking area 150R and is connected to the main body 141. The marking pattern 145 can fill the marking area 150R from which the initial marking frame 150PRE has been removed, such that the marking pattern 145 can represent the pattern PTRN. For example, the marking pattern 145 of the adhesive layer 140 can form numbers, letters, and / or symbols, etc., to provide identification information.
[0066] S400, spacers S are provided on the adhesive layer 140. The spacers S are arranged in the edge region on the lower surface 140B of the adhesive layer 140. For example, multiple spacers S can be provided. Multiple spacers S can be arranged along the outer periphery of the lower surface 140B of the adhesive layer 140.
[0067] Reference Figure 3and Figure 6 S500, a chip unit is provided, the chip unit including a substrate 110 and a semiconductor chip 120 located on the substrate 110. In an example embodiment, the semiconductor chip 120 may be electrically connected to a chip pad of the substrate 110 via bonding leads W.
[0068] S600, a molding process is performed on the marking cells and chip cells to form a molding layer 130. The spacers S are located on both sides of the semiconductor chip 120 in the horizontal direction and do not contact the substrate 110 during the molding process. In an example embodiment, the molding process may be performed in a mold 200. Although Figure 6 Only the lower cavity of mold 200 is shown, but mold 200 may also include an upper cavity.
[0069] Reference Figure 7 In an example embodiment, the molding process may include: S610, placing a marking unit in the lower cavity of the mold 200 with the marking area 150R facing upwards, and placing a chip unit in the upper cavity of the mold 200 with the semiconductor chip 120 facing downwards. For example, the main body 141 may be located between the marking area 150R / marking pattern 145 and the semiconductor chip 120.
[0070] In this example embodiment, the release film RF can be disposed in the lower cavity of the mold 200. The release film RF can facilitate the removal of the semiconductor package from the mold 200 after cooling. In this case, the separation carrier 160 of the marking unit can be placed on the release film RF in the lower cavity of the mold 200.
[0071] S620, close mold 200 and inject encapsulating material (such as EMC).
[0072] S630, cool and solidify the encapsulating material to form the molding layer 130.
[0073] In this example embodiment, after the mold 200 is closed, the upper surface of the spacer S can be vertically spaced apart from the upper surface of the substrate 110 by a first distance D1. Simultaneously, the inner surface IS of the spacer S and the outer surface 120S of the semiconductor chip 120 can be horizontally spaced apart from each other by a second distance D2.
[0074] Reference Figure 3 and Figure 8 The semiconductor package is removed from the mold 200. Next, the following steps are performed: S700, the separation carrier 160 is removed to expose the upper surface 150T of the marking frame 150 and the upper surface 145T of the marking pattern 145.
[0075] In an example embodiment, the separation carrier 160 may be formed of a material such as a photosensitive material or a thermosensitive material. When the separation carrier 160 is subjected to ultraviolet light irradiation or heating, the adhesiveness of the separation carrier 160 may be reduced so that it can be peeled off from the marking frame 150.
[0076] Figure 9 This is a perspective view of a semiconductor package according to an exemplary embodiment of the present disclosure.
[0077] Reference Figure 9 The release carrier 160 can be formed of a transparent material. The release carrier 160 can protect the marker frame 150 and the marker pattern 145 from damage during various process steps in the manufacture of the semiconductor package. For example, after the release carrier 160 is peeled off, the upper surface 150T of the marker frame 150 and the upper surface 145T of the marker pattern 145 can both be smooth.
[0078] A semiconductor package according to an example embodiment of the present disclosure may include a body structure formed by a marking frame 150, an adhesive layer 140, and a molding layer 130, wherein a marking pattern 145 of the adhesive layer 140 fills a marking area 150R of the marking frame 150 to form a pattern displaying identification information of the semiconductor package. For example, where there is no marking frame 150, the adhesive layer 140 may be exposed to form the marking pattern 145.
[0079] In summary and recap, the identification information of the semiconductor package according to the exemplary embodiments of this disclosure can be defined by a pattern obtained by etching a marking frame. Since the marking frame can be easily formed to have a small thickness, the overall thickness of the semiconductor package can be reduced by decreasing the thickness of the molding layer, while preventing cracks from appearing in the semiconductor package.
[0080] Furthermore, the presence of spacers and the space between the spacers and the substrate allows for improved layout margins for interconnect components such as bonding leads, thereby enhancing device integration and reliability while preventing warping of the semiconductor package.
[0081] Although this disclosure contains numerous specific implementation details, it should not be construed as limiting the scope of the claims. Certain features described in this disclosure as independent embodiments may also be implemented in combinations of single embodiments. Conversely, multiple features described in a single embodiment may be implemented separately in multiple embodiments, or presented in any suitable sub-combination. Furthermore, while the foregoing features may be described as acting in a specific combination, in some cases one or more features may be removed from the combination, which may refer to a sub-combination or a variation thereof. The order of operations shown in the accompanying drawings may differ from that illustrated.
[0082] Although several examples have been shown, it should be understood that various modifications can be made to the form and details without departing from the spirit and scope of this disclosure.
Claims
1. A semiconductor package, comprising: Base; Semiconductor chips are located on a substrate; Molded layer, covering the semiconductor chip; An adhesive layer is located on the upper surface of the molding layer; A marking frame is placed on an adhesive layer, wherein the marking frame exposes a portion of the adhesive layer, and the exposed portion of the adhesive layer forms a marking pattern; and Spacers are located on the lower surface of the adhesive layer and are spaced apart from the semiconductor chip in the horizontal direction. The spacer is spaced apart from the substrate.
2. The semiconductor package according to claim 1, wherein, The spacer is the first spacer. The semiconductor package further includes a second spacer spaced horizontally from the semiconductor chip, and The first spacer and the second spacer are located on two opposite sides of the semiconductor chip in the horizontal direction.
3. The semiconductor package according to claim 1, wherein, The semiconductor chip is electrically connected to the chip pad of the substrate via bonding leads, and The bonding points between the bonding leads and the chip pads are stacked vertically with the spacers.
4. The semiconductor package according to claim 3, wherein, The bonding leads extend from the bonding point through the space between the spacer and the substrate and the spacer and the semiconductor chip to connect to the upper surface of the semiconductor chip.
5. The semiconductor package according to claim 1, wherein, The upper surface of the marking frame and the upper surface of the marking pattern are coplanar.
6. A method for manufacturing a semiconductor package, comprising: A portion of the initial marker frame on the separation carrier is removed to form a marker region, wherein the portion of the initial marker frame is removed at the marker region, and the remaining portion of the initial marker frame forms the marker frame. An adhesive layer is used to cover the marking frame, such that the adhesive layer includes a main body and a marking pattern disposed on the main body, with the marking pattern filling the marking area; Spacers are placed on the adhesive layer; A molding layer formed on an adhesive layer and covering a semiconductor chip, wherein the semiconductor chip is on a substrate and located between the substrate and the adhesive layer; and Remove the separation carrier to expose the upper surface of the marker frame and the upper surface of the marker pattern. The spacer is spaced apart from the substrate.
7. The method according to claim 6, wherein, The spacer is the first spacer. The semiconductor package further includes a second spacer spaced horizontally from the semiconductor chip, and The first spacer and the second spacer are located on two opposite sides of the semiconductor chip in the horizontal direction.
8. The method according to claim 6, wherein, The semiconductor chip is electrically connected to the chip pad of the substrate via bonding leads, and The bonding points between the bonding leads and the chip pads are stacked vertically with the spacers.
9. The method according to claim 8, wherein, The bonding leads extend from the bonding point through the space between the spacer and the substrate and the spacer and the semiconductor chip to connect to the upper surface of the semiconductor chip.
10. The method according to claim 6, wherein, The upper surface of the marking frame and the upper surface of the marking pattern are coplanar.